Packaging structure based on silicon-based silicon carbide intermediate layer and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor devices, and particularly relates to a CoWoS packaging structure based on a silicon-based silicon carbide intermediate layer and a preparation method of the CoWoS packaging structure, the silicon-based silicon carbide intermediate layer comprises a monocrystalline silicon substrate, the two surfaces of the monocrystalline silicon substrate are polished, a 3C-SiC heat dissipation layer is epitaxially grown on one surface of the monocrystalline silicon substrate, and silicon through holes are fully distributed in the monocrystalline silicon substrate. According to the CoWoS packaging structure, through the innovative structural design of the double-polished silicon-based 3C-SiC intermediate layer, after 3C-SiC epitaxial growth is completed, device preparation can be directly carried out on the polished back face of the silicon substrate, the preparation method is highly compatible with an existing silicon-based semiconductor technology, large-size wafer growth is supported, the technology can be simplified, and the production efficiency is improved. Therefore, the necessary, complex and high-precision bonding link of the interposer and the device in the traditional scheme is fundamentally omitted, the process flow is shortened, the technical complexity and potential yield loss are reduced, the manufacturing cost is remarkably reduced, and the manufacturing method has the advantages of process compatibility and cost.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a CoWoS packaging structure based on a silicon-based silicon carbide interposer and its preparation method. Background Technology

[0002] Currently, high-performance GPU chips commonly employ CoWoS (Chip-on-Wafer-on-Substrate) packaging technology. This technology achieves high-density, low-latency heterogeneous integration by densely stacking and integrating multiple chips (such as processors and memory) into a single package structure, which is then packaged onto a substrate. This not only significantly reduces package size but also greatly improves the overall system performance and energy efficiency.

[0003] The CoWoS package structure mainly consists of: a computing chip (such as a GPU / CPU) and high-bandwidth memory (HBM) at the top, a core interconnect layer called the "interposer" in the middle, and a packaging substrate at the bottom. Its core idea is to integrate multiple chips in a high-density, side-by-side arrangement on the interposer, which then connects them to the underlying substrate. The interposer is the core of the CoWoS package, responsible for high-speed interconnection between chips and assisting in heat dissipation and mitigating thermal stress. Currently, mainstream interposer materials include silicon, organic materials, glass, and ceramics, with silicon interposers being the dominant solution in the current high-performance computing field.

[0004] However, with the exponential growth in demand for AI computing power, the power density of GPU chips is constantly approaching physical limits, and heat dissipation has become a key bottleneck restricting the industry's development. Traditional silicon-based interposers have low thermal conductivity, making it difficult to meet the heat dissipation requirements of high-power chips. This leads to performance throttling and reliability degradation due to overheating, severely affecting the continuous and stable output of AI computing power.

[0005] In recent years, silicon carbide (SiC) materials have attracted widespread attention due to their excellent thermal conductivity, reaching as high as 490 W / (m·K). Currently, researchers in the industry are using high-thermal-conductivity 4H-SiC wafers to replace traditional silicon interposers in an attempt to improve overall performance. A schematic diagram of the resulting CoWoS packaging structure is shown below. Figure 1 As shown, the silicon interposer that the 4H-SiC wafer replaces is one of the core components of the CoWoS packaging platform. It has a large area and many interconnects are set inside the silicon interposer through silicon vias and wiring. It is responsible for connecting the small chips integrated on the interposer to each other and to the packaging substrate.

[0006] Despite the advantages of 4H-SiC in terms of thermal conductivity, it still faces several challenges in practical applications. First, large-size 4H-SiC wafers are not only expensive, but their dicing, grinding, and polishing processes are not yet mature, limiting their large-scale application in the interposer field. Second, when using 4H-SiC as an interposer, devices must be bonded to the 4H-SiC wafer, and then the wafer must be bonded to the packaging substrate, resulting in a complex and costly process. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to address the above-mentioned deficiencies in the prior art by providing a packaging structure based on a silicon-based silicon carbide interposer and its preparation method. The silicon-based interposer and CoWoS packaging structure covered with a 3C-SiC heat dissipation layer are prepared by using 3C-SiC, which can be directly epitaxially grown on a silicon substrate. The silicon-based interposer and CoWoS packaging structure with a relatively simple structure, support for large-size wafer growth, and excellent heat dissipation performance are cleverly designed.

[0008] The first aspect of the present invention provides a silicon-based silicon carbide interposer, the interposer comprising a monocrystalline silicon substrate, the monocrystalline silicon substrate being polished on both sides and having a 3C-SiC heat dissipation layer epitaxially grown on one side, and having through silicon vias (TSVs) distributed on the monocrystalline silicon substrate.

[0009] According to the above scheme, the single-crystal silicon substrate is <100> Crystal orientation of silicon wafers or <111> The silicon wafers are oriented in a specific crystal direction and are 6 inches, 8 inches, or 12 inches in size. The largest standard wafer size currently used in the semiconductor industry is 12 inches, and the single-crystal silicon substrate selected in this invention is compatible with current semiconductor processes.

[0010] According to the above scheme, the thickness of the 3C-SiC heat dissipation layer is 50-100μm.

[0011] According to the above scheme, the method for epitaxially growing a 3C-SiC heat dissipation layer on one side of a single-crystal silicon substrate is to prepare it using chemical vapor deposition. This process effectively suppresses the thermal stress caused by the mismatch between the thermal expansion coefficients of silicon and silicon carbide, thereby preparing a 3C-SiC interposer layer with high crystal quality and low internal stress. Moreover, the 3C-SiC material used itself has a higher theoretical thermal conductivity than 4H-SiC.

[0012] A second aspect of the present invention provides a packaging structure based on the above-described silicon-based silicon carbide interposer, comprising: Silicon-based silicon carbide interlayer; Device layers mounted via wiring on the polished surface of a silicon-based silicon carbide interposer.

[0013] The third aspect of the present invention provides a method for preparing the above-mentioned packaging structure, the specific steps of which are as follows: a 3C-SiC heat dissipation layer is epitaxially grown on one surface of a double-sided polished single-crystal silicon substrate to obtain a silicon wafer covered with the 3C-SiC heat dissipation layer; then, through-silicon vias are prepared on the silicon wafer covered with the 3C-SiC heat dissipation layer using conventional methods in the art to obtain a silicon-based silicon carbide interposer; and then, a device layer is prepared on the side of the silicon-based silicon carbide interposer that is not covered with the 3C-SiC heat dissipation layer by wiring to obtain a CoWoS packaging structure based on the silicon-based silicon carbide interposer.

[0014] According to the above scheme, the double-sided polished single-crystal silicon substrate is a commercially available double-sided polished single-crystal silicon substrate, or the single-crystal silicon substrate is double-sided polished to obtain an ultra-smooth surface (surface roughness less than 0.2nm) that meets the requirements of 3C-SiC epitaxial growth.

[0015] According to the above scheme, the method for epitaxially growing a 3C-SiC heat dissipation layer on one surface of a double-sided polished monocrystalline silicon substrate is as follows: using H2 as a carrier gas and ethylene as a carbon source, carbonization is carried out at 1200℃ for 5 minutes. Subsequently, while introducing H2 and ethylene, trichlorosilane is also introduced as a silicon source. The reaction is carried out at a deposition temperature of 1300℃ and a deposition pressure of 100mbar for 40 minutes. A 3C-SiC heat dissipation layer with excellent crystal quality and a thickness of 40μm is deposited on the surface of the monocrystalline silicon substrate.

[0016] According to the above scheme, the H2 is introduced into the process chamber by bubbling, the H2 flow rate is 20 sccm, and the ethylene flow rate is 7 sccm.

[0017] According to the above scheme, the flow rate of trichlorosilane is 15 sccm.

[0018] 3C-SiC material has a thermal conductivity of 500 W / (m·K), which is better than 4H-SiC, and has better heat dissipation potential. Moreover, 3C-SiC is the only silicon carbide crystal form that can be directly epitaxially grown on a silicon substrate. This invention utilizes the characteristics of 3C-SiC to directly epitaxially grow 3C-SiC on one side of a single crystal silicon wafer, and then mount semiconductor devices on a polished layer on the other side. This avoids the difficult problem of fabricating large-size 4H-SiC wafers, which are expensive and have low maturity. It also supports smooth expansion to large-size wafers such as 8 inches and even 12 inches, and avoids complex interlayer and device bonding processes, greatly simplifying the manufacturing process of CoWoS packaging structure and significantly reducing raw material and manufacturing costs.

[0019] The beneficial effects of this invention are as follows: 1. The silicon-based interposer with a 3C-SiC heat dissipation layer provided by this invention has higher thermal conductivity than traditional silicon wafers and 4H-SiC wafers, and is easy to prepare in large areas and batches using chemical vapor deposition. This provides a more promising material platform and performance upgrade space to address the heat dissipation challenges brought about by the higher power density of future AI computing chips. 2. The CoWoS packaging structure of this invention, through its innovative "dual-polished silicon-based 3C-SiC interposer" structural design, allows for direct device fabrication on the polished back side of the silicon substrate after 3C-SiC epitaxial growth. The fabrication method is highly compatible with existing silicon-based semiconductor processes, supports large-size wafer growth, simplifies the process, and fundamentally eliminates the necessary, complex, and high-precision interposer and device bonding steps required in traditional solutions. This shortens the process flow, reduces technical complexity and potential yield losses, significantly reduces manufacturing costs, and offers process compatibility and cost advantages. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the CoWoS packaging structure in the prior art; Figure 2 A comparative diagram showing the fabrication process of the 4H-SiC interposer (left) and the silicon-based 3C-SiC interposer (right) from Example 1; Figure 3 This is a comparison chart of the average specific heat capacity of Si and 3C-SiC. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0022] Example 1 A silicon-based silicon carbide interposer is prepared as follows: A commercially available double-sided polished 6-inch... <100> A monocrystalline silicon substrate with a specific crystal orientation was placed in a chemical vapor deposition (CVD) apparatus for epitaxial growth of a 3C-SiC heat dissipation layer. H2 was used as the carrier gas and introduced into the process chamber via a bubbling method at a flow rate of 20 sccm. Ethylene was used as the carbon source at a flow rate of 7 sccm. The reaction was carried out at 1200°C for 5 minutes for carbonization. Subsequently, while introducing H2 and ethylene, trichlorosilane was also introduced as the silicon source at a flow rate of 15 sccm. The reaction was carried out at a deposition temperature of 1300°C and a deposition pressure of 100 mbar for 40 minutes. A 3C-SiC heat dissipation layer with excellent crystal quality and a thickness of 40 μm was deposited on one surface of the monocrystalline silicon substrate. The monocrystalline silicon substrate covered with the 3C-SiC heat dissipation layer was then removed, and through-silicon vias were fabricated on the monocrystalline silicon substrate using conventional techniques in the art to obtain a silicon-based silicon carbide interlayer.

[0023] A CoWoS package structure was fabricated based on the aforementioned silicon-based silicon carbide interposer. The specific fabrication method is as follows: A device layer is mounted on the side of the silicon-based silicon carbide interposer that does not cover the 3C-SiC heat dissipation layer via wiring, resulting in a CoWoS package structure based on the silicon-based silicon carbide interposer. A schematic diagram of the specific fabrication process is shown below. Figure 2 As shown on the right.

[0024] and Figure 2 The diagram on the left illustrates the fabrication process of a CoWoS package structure using 4H-SiC wafers instead of the traditional silicon interposer. First, the device layer needs to be mounted onto a single-crystal silicon substrate via wiring. Then, the 4H-SiC wafers are bonded to the single-crystal silicon substrate. To improve the interface mismatch between the single-crystal silicon substrate and the 4H-SiC, thus achieving heterogeneous bonding of 4H-SiC, the 4H-SiC wafers require cutting, grinding, chemical mechanical polishing, surface activation treatment (SAB), and post-annealing. This process is complex and costly. High-quality bonding requires extremely high alignment precision (submicron level), ultra-high flatness, a strictly clean environment, and high-temperature, high-pressure processes, resulting in huge equipment investment and a narrow process window. Furthermore, the polycrystalline / amorphous structure at the heterogeneous bonding interface leads to phonon scattering, reducing the overall thermal conductivity from the interposer to the heat sink.

[0025] The commercially available double-sided polished 6-inch wafer used in this embodiment was tested using a microcalorimeter. <100> The specific heat capacity of crystal-oriented single-crystal silicon substrates and commercially available 3C-SiC, such as Figure 3 The image shown is a commercially available double-sided polished 6-inch screen used in this embodiment. <100> A comparison of the specific heat capacity of monocrystalline silicon substrates with different crystal orientations and commercially available 3C-SiC is shown in the figure. As can be seen from the figure, the average specific heat capacity of the monocrystalline silicon substrate is 0.772 J·g. -1 ·K -1 The average specific heat capacity of commercially available 3C-SiC is 0.903 J·g. -1 ·K -1 The thermal diffusivity was measured to be 82.7 mm using a laser thermal conductivity meter. 2 / s and 41.1mm 2 / s. Density was calculated by measuring mass and volume, and was 0.00163 g / mm³. 3 and 0.00366g / mm 3 According to the thermal conductivity calculation formula (thermal conductivity = thermal diffusivity × specific heat capacity × density), the thermal conductivity of the monocrystalline silicon substrate is 103.96 W / m·K, while the thermal conductivity of commercially available 3C-SiC is 135.91 W / m·K. The results show that 3C-SiC has an advantage in heat dissipation compared to monocrystalline silicon substrates.

[0026] Existing solutions using 4H-SiC wafers as interposers require complex wafer bonding processes to connect to device wafers or carriers, introducing additional bonding interfaces. These interfaces are weak points in thermal resistance and mechanical reliability, potentially containing microvoids and interface defects that affect heat conduction efficiency and long-term reliability. Furthermore, the processes are complex and time-consuming. In this invention, the interposer is directly epitaxially grown from 3C-SiC on a silicon substrate, resulting in a natural monolithic integrated structure of "silicon substrate / 3C-SiC epitaxial layer." This structure has no bonding interfaces, providing a more direct and lower impedance path for heat and electricity transfer, and higher structural integrity, fundamentally improving heat dissipation efficiency and reliability. This heterogeneous integrated structure with an integrated silicon-based 3C-SiC interposer perfectly meets the core needs of advanced packaging for higher integration, stronger heat dissipation capabilities, and lower costs.

[0027] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A silicon-based silicon carbide interposer, characterized in that, The intermediate layer includes a monocrystalline silicon substrate, which is polished on both sides and has a 3C-SiC heat dissipation layer epitaxially grown on one side. The monocrystalline silicon substrate is covered with through-silicon vias.

2. The silicon-based silicon carbide interposer according to claim 1, characterized in that, The single-crystal silicon substrate is <100> Crystal orientation of silicon wafers or <111> Crystal-oriented silicon wafers, which are 6 inches, 8 inches or 12 inches in size.

3. The silicon-based silicon carbide interposer according to claim 1, characterized in that, The thickness of the 3C-SiC heat dissipation layer is 50-100μm.

4. The silicon-based silicon carbide interposer according to claim 1, characterized in that, The method for epitaxially growing a 3C-SiC heat dissipation layer on one side of a single-crystal silicon substrate is to prepare it using chemical vapor deposition.

5. A packaging structure based on the silicon-based silicon carbide interposer as described in any one of claims 1-4, characterized in that, It includes: Silicon-based silicon carbide interlayer; Device layers mounted via wiring on the polished surface of a silicon-based silicon carbide interposer.

6. A method for fabricating a packaging structure based on a silicon-based silicon carbide interposer as described in claim 5, characterized in that, The specific steps are as follows: a 3C-SiC heat dissipation layer is epitaxially grown on one surface of a double-sided polished single-crystal silicon substrate to obtain a silicon wafer covered with the 3C-SiC heat dissipation layer. Then, through-silicon vias are fabricated on the silicon wafer covered with the 3C-SiC heat dissipation layer using conventional methods in the art to obtain a silicon-based silicon carbide interposer. Then, a device layer is fabricated on the side of the silicon-based silicon carbide interposer that is not covered with the 3C-SiC heat dissipation layer by wiring to obtain a CoWoS packaging structure based on the silicon-based silicon carbide interposer.

7. The method for fabricating a packaging structure based on a silicon-based silicon carbide interposer according to claim 6, characterized in that, The double-sided polished monocrystalline silicon substrate is a commercially available double-sided polished monocrystalline silicon substrate, or the monocrystalline silicon substrate is double-sided polished to obtain an ultra-smooth surface that meets the requirements for 3C-SiC epitaxial growth.

8. The method for fabricating a packaging structure based on a silicon-based silicon carbide interposer according to claim 6, characterized in that, The method for epitaxially growing a 3C-SiC heat dissipation layer on one surface of a double-sided polished monocrystalline silicon substrate is as follows: using H2 as a carrier gas and ethylene as a carbon source, carbonization is carried out at 1200℃ for 5 minutes. Subsequently, while introducing H2 and ethylene, trichlorosilane is also introduced as a silicon source. The reaction is carried out at a deposition temperature of 1300℃ and a deposition pressure of 100mbar for 40 minutes. A 3C-SiC heat dissipation layer with excellent crystal quality and a thickness of 40μm is deposited on the surface of the monocrystalline silicon substrate.

9. The method for preparing a packaging structure based on a silicon-based silicon carbide interposer according to claim 8, characterized in that, The H2 is introduced into the process chamber by bubbling, with a flow rate of 20 sccm and an ethylene flow rate of 7 sccm.

10. The method for preparing a packaging structure based on a silicon-based silicon carbide interposer according to claim 8, characterized in that, The flow rate of the trichlorosilane is 15 sccm.

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