Display substrate

Abstract

A display substrate (10) comprises a substrate (11), the substrate (11) comprises a plurality of sub-pixel areas, at least one sub-pixel area comprises a first electrode (15) and a second electrode (16) which are arranged on the substrate (11), the second electrode (16) is located on the side, away from the substrate (11), of the first electrode (15), and the second electrode (16) and the first electrode (15) are insulated from each other; each second electrode (16) comprises a plurality of electrode strips (161) arranged in parallel in the first direction, and a first slit (16s) is formed between every two adjacent electrode strips (161) in the same second electrode (16). In the first direction, the width (W) of the electrode strips (161) is smaller than the width of the sub-pixel area, and the sub-pixel area comprises at least three electrode strips (161); the ratio of the width (W) of at least one electrode strip (161) to the width of the corresponding sub-pixel region is 0.06-0.3; wherein one of the first electrode (15) and the second electrode (16) is a pixel electrode, and the other one is a common electrode.

Description

Display substrate Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate. Background Art

[0002] Liquid crystal display devices can reduce power consumption during use by lowering their operating frequency, thereby extending their display life. However, when the image on some LCD panels changes with frequency, the flexoelectric properties of the liquid crystal molecules cause differences in transmittance when their polarity reverses, resulting in image flicker and reduced display quality.

[0003] Summary of the Invention

[0004] The present disclosure provides a display substrate, comprising a substrate, the substrate comprising a plurality of sub-pixel regions, wherein at least one of the sub-pixel regions comprises: a first electrode and a second electrode disposed on the substrate, the second electrode being located on a side of the first electrode away from the substrate and insulated from the first electrode;

[0005] The second electrode includes a plurality of electrode strips arranged in parallel along a first direction, a first slit being defined between two adjacent electrode strips in the same second electrode; a width of the electrode strip along the first direction is smaller than a width of the sub-pixel region, and the sub-pixel region includes at least three electrode strips; and a ratio of a width of at least one electrode strip to a width of the corresponding sub-pixel region is between 0.06 and 0.3;

[0006] One of the first electrode and the second electrode is a pixel electrode, and the other is a common electrode.

[0007] In some embodiments, along the first direction, a ratio of a width of at least one of the electrode strips to a width of the first slit on an adjacent side is between 0.4 and 1.3.

[0008] In some embodiments, along the first direction, 750 to 900 sub-pixel areas are passed through per inch, and the width of the electrode strip is between 1.8 μm and 4 μm.

[0009] In some embodiments, the change in transmittance of the display substrate between two adjacent frames and the width of the electrode strips satisfy the following relationship: A = (-0.0228W + 0.1348) * k

[0010] Wherein, W is the width of the electrode strip, A is the transmittance change value of the display substrate in two adjacent frames, k is the error coefficient, and 0<k<3.

[0011] In some embodiments, the display substrate further comprises:

[0012] a plurality of grid lines, wherein the grid lines are arranged along a second direction, and the second direction is the same as or different from the first direction;

[0013] A plurality of thin film transistors, each of the plurality of thin film transistors is electrically connected to a pixel electrode of the sub-pixel region and to one of the gate lines.

[0014] In some embodiments, the plurality of thin film transistors include a plurality of first thin film transistors and a plurality of second thin film transistors, and a width of a gate of the first thin film transistor in the second direction is greater than a width of the second thin film transistor in the second direction;

[0015] A plurality of first support portions are located on a side of the gate of the first thin film transistor away from the substrate, and an orthographic projection of each of the plurality of first support portions on the substrate overlaps with an orthographic projection of the gate of one of the first thin film transistors on the substrate.

[0016] In some embodiments, the first supporting portion is provided in the same layer as the source and drain electrodes of the plurality of thin film transistors.

[0017] In some embodiments, a difference in width between the gate of the first thin film transistor and the gate of the second thin film transistor in the second direction is between 6 μm and 10 μm.

[0018] In some embodiments, the display substrate further comprises:

[0019] a plurality of second supporting portions, wherein an orthographic projection of each of the plurality of second supporting portions on the substrate overlaps with an orthographic projection of one of the first supporting portions on the substrate;

[0020] Wherein, the second supporting portion is provided in the same layer as the active layer of the thin film transistor.

[0021] In some embodiments, an orthographic projection of at least a portion of the gate line on the substrate does not overlap with an orthographic projection of the first electrode on the substrate.

[0022] In some embodiments, the display substrate further comprises:

[0023] a plurality of data lines, each of the plurality of data lines extending along a third direction, the third direction intersecting the second direction;

[0024] In which, the orthographic projection of each data line on the substrate overlaps with the orthographic projections of the gates of multiple thin film transistors on the substrate; at least one edge of the data line has a recessed portion, and the orthographic projection of the recessed portion on the substrate is located within the range of the orthographic projection of the gates of the thin film transistors on the substrate.

[0025] In some embodiments, the depth of the recessed portion is less than or equal to half the width of the data line.

[0026] In some embodiments, the display substrate further comprises:

[0027] A plurality of touch signal lines are provided in the same layer as the source electrodes and the drain electrodes of the plurality of thin film transistors; each of the plurality of touch signal lines extends along the third direction;

[0028] The first electrode is multiplexed as a touch electrode and is electrically connected to the touch signal line.

[0029] In some embodiments, the width of the touch signal line is 1.5 to 3 times the width of the data line.

[0030] In some embodiments, the first electrodes of the plurality of sub-pixel regions constitute a first electrode layer, the first electrode layer comprising: a plurality of first sub-electrodes, the plurality of first sub-electrodes being arranged in an array along the second direction and the third direction;

[0031] A second slit is provided between two adjacent first sub-electrodes arranged in the second direction, and an orthographic projection of the second slit on the base substrate overlaps with an orthographic projection of the touch signal line on the base substrate.

[0032] In some embodiments, the width of the second slit is greater than or equal to the width of the touch signal line.

[0033] In some embodiments, the display substrate further comprises:

[0034] a plurality of third supporting portions, disposed in the same layer as the gate line, wherein an orthographic projection of each of the plurality of third supporting portions on the substrate overlaps with an orthographic projection of one of the touch signal lines on the substrate;

[0035] A plurality of fourth support portions are arranged in the same layer as the active layer of the thin film transistor; each of the plurality of fourth support portions corresponds to one of the third support portions, and the orthographic projection of the fourth support portion on the substrate overlaps with the orthographic projection of one of the third support portions.

[0036] In some embodiments, the orthographic projection of the first sub-electrode on the substrate overlaps with the orthographic projection of the second sub-electrode on the substrate;

[0037] The first sub-electrode and a second electrode overlapping with the orthographic projection of the first sub-electrode constitute an electrode unit. In the same electrode unit, the first sub-electrode includes a first edge and a second edge arranged opposite to each other in the third direction, the first edge is adjacent to the thin film transistor connected to the second electrode, and the first edge has a bent portion, which is opposite to the drain of the adjacent thin film transistor and bends away from the thin film transistor.

[0038] In some embodiments, the second electrode further includes a connecting portion connected to the plurality of electrode strips, an orthographic projection of at least part of the connecting portion on the substrate is located outside an orthographic projection of the first electrode on the substrate, and the connecting portion is connected to the drain of the thin film transistor through a first via hole;

[0039] An orthographic projection of the first via hole on the substrate is outside an orthographic projection of the first electrode on the substrate.

[0040] In some embodiments, when the driving frequency of the display substrate is 60 Hz and the polarities of the driving voltages in each sub-pixel region are opposite in two adjacent frames, the flicker value of the display substrate is less than -30 dB.

[0041] In some embodiments, the display substrate further comprises:

[0042] A plurality of thin film transistors are arranged between the layer where the first electrode is located and the substrate;

[0043] a first passivation layer, disposed between the plurality of thin film transistors and the layer where the first electrode is located;

[0044] a second passivation layer, disposed between the layer where the first electrode is located and the layer where the second electrode is located;

[0045] A plurality of touch signal lines are provided in the same layer as the source and the drain of each of the plurality of thin film transistors;

[0046] A plurality of transfer electrodes are provided on the same layer as the second electrode;

[0047] The second electrode is connected to the drain electrode of the thin film transistor through a first via hole penetrating the first passivation layer and the second passivation layer;

[0048] The transfer electrode is electrically connected to the first electrode through a second via hole penetrating the second passivation layer, and is connected to the touch signal line through a third via hole penetrating the first passivation layer and the second passivation layer.

[0049] In some embodiments, the second via hole corresponding to the same switching electrode is connected to the third via hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0051] FIG. 1 is a schematic diagram of area division of a display substrate provided in some embodiments.

[0052] FIG. 2 is a cross-sectional view of a display panel provided in some embodiments.

[0053] FIG3 and FIG4 are potential diagrams of a sub-pixel region in two adjacent frames, respectively.

[0054] FIG5 is a cross-sectional view of a display substrate provided in some embodiments of the present disclosure.

[0055] FIG. 6 is a curve showing the relationship between the transmittance change of the substrate and the width of the electrode strips in two adjacent frames.

[0056] FIG. 7 is a transmittance curve diagram corresponding to positive and negative frames in a sub-pixel region when W=2.5 μm and S=4.0 μm.

[0057] FIG8 is a transmittance curve diagram of a sub-pixel region corresponding to a positive frame and a negative frame when W=3.5 and S=4.0 μm.

[0058] FIG9 is a schematic diagram of a gate metal layer provided in some embodiments of the present disclosure.

[0059] FIG. 10 is a schematic diagram of a semiconductor layer provided in some embodiments of the present disclosure.

[0060] FIG11 is a schematic diagram of a source / drain metal layer provided in some embodiments of the present disclosure.

[0061] FIG12 is a schematic diagram of the superposition of a gate metal layer, a semiconductor layer, and a source / drain metal layer provided in some embodiments of the present disclosure.

[0062] FIG13 is a schematic diagram of a first transparent conductive layer provided in some embodiments of the present disclosure.

[0063] FIG14 is a schematic diagram of the superposition of a gate metal layer, a semiconductor layer, a source / drain metal layer, and a first transparent conductive layer provided in some embodiments of the present disclosure.

[0064] FIG15 is a schematic diagram of a second transparent conductive layer provided in some embodiments of the present disclosure.

[0065] 16 is a schematic diagram of the superposition of a gate metal layer, a semiconductor layer, a source / drain metal layer, a first transparent conductive layer, and a second transparent conductive layer provided in some embodiments of the present disclosure.

[0066] FIG17 is a cross-sectional view taken along line AA' in FIG16.

[0067] FIG18 is a cross-sectional view taken along line BB' in FIG16.

[0068] FIG19 is a cross-sectional view of a display panel provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0069] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0070] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0071] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0072] As used herein, "parallel" and "perpendicular" include the conditions described and conditions similar to the conditions described, and the range of the similar conditions is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism can be, for example, a deviation within 10°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 10°.

[0073] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0074] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0075] FIG1 is a schematic diagram illustrating the regional division of a display substrate provided in some embodiments, and FIG2 is a cross-sectional view of a display panel provided in some embodiments. As shown in FIG1 and FIG2 , the display panel includes: a display substrate 10 and a color filter substrate 20 disposed opposite each other, and a liquid crystal layer disposed therebetween. The display substrate 10 includes a substrate 11, on which are disposed a plurality of gate lines GL, a plurality of data lines DL, a plurality of thin-film transistors 12, a plurality of pixel electrodes 13, and a common electrode 14. The plurality of gate lines GL and the plurality of data lines DL are intersectingly disposed, thereby dividing the display area into a plurality of sub-pixel regions P. Each sub-pixel region P is provided with a pixel electrode 13, and each sub-pixel region P corresponds to a thin-film transistor 12. The gate of the thin-film transistor 12 is connected to the gate line GL, the source of the thin-film transistor 12 is connected to the data line DL, and the drain of the thin-film transistor 12 is connected to the pixel electrode 13. The common electrode 14 is arranged on the side of the layer where the pixel electrode 13 is located away from the substrate 11. The part of the common electrode 14 corresponding to the sub-pixel area P includes a plurality of electrode strips 141. Slits 14s are provided between adjacent electrode strips 141, so that a horizontal electric field is formed between the common electrode 14 and the pixel electrode 13 to drive the liquid crystal molecules in the sub-pixel area P to deflect.

[0076] To prevent liquid crystal polarization, polarity inversion is typically used to drive the display substrate when driving the display panel. That is, the polarity of the pixel electrodes loaded on the pixel electrodes in the same sub-pixel area in two adjacent display cycles is opposite. In addition, when driving the display panel, the operating frequency is generally reduced to reduce power consumption during use to increase the usage time. However, the display panel may produce a difference in transmittance due to the flexoelectric effect when the liquid crystal molecules are reversed in polarity, which may cause image flickering and reduce the display quality.

[0077] The flexoelectric effect of liquid crystals refers to the electric polarization caused by the bending and curvature of liquid crystals. It is a common phenomenon, especially in wedge-shaped and banana-shaped nematic liquid crystals with permanent dipole moments. The vector expression of the flexoelectric polarization intensity is P = e 11 n(▽·n)+e 33 (▽×n)×n, where n is the liquid crystal director, e 11 and e 33 They correspond to the flexural and bending flexoelectric coefficients respectively. The interaction between flexoelectric polarization and an external electric field can cause a change in the liquid crystal director, which is the flexoelectric effect. This effect is easily masked by the dielectric effect and the anchoring effect of the substrate, but is more obvious under low frequencies (for example, less than 20 Hz) and DC voltage signals. The response of the permanent dipole moment of the liquid crystal molecules to the electric field leads to the enhancement and weakening of the external electric field, which causes the liquid crystal molecules in the positive and negative frames to rotate at different angles under the electric field, resulting in a difference in the transmittance of the positive and negative frames. At low frequencies, the difference in the transmittance of the positive and negative frames manifests as flickering and is recognizable by the human eye.

[0078] Figures 3 and 4 are potential diagrams of the sub-pixel area in two adjacent frames, respectively. As shown in Figures 3 and 4, the electric field is strongest at the position corresponding to the electrode strip 141, that is, the flexoelectric phenomenon of the liquid crystal at the electrode strip 141 is the strongest, and the transmittance difference in the area where the electrode strip 141 is located in the two adjacent frames is the largest.

[0079] Embodiments of the present disclosure provide a display substrate. FIG5 is a cross-sectional view of a display substrate provided in some embodiments of the present disclosure. As shown in FIG5 , the display substrate includes a substrate 11, which includes multiple sub-pixel regions. For example, multiple gate lines and multiple data lines are provided on the substrate 11. The multiple gate lines and multiple data lines are intersecting and insulated from each other, thereby defining multiple sub-pixel regions. At least one sub-pixel region includes: a first electrode 15 and a second electrode 16 provided on the substrate 11. The second electrode 16 is located on a side of the first electrode 15 away from the substrate 11 and is insulated from the first electrode 15.

[0080] One of the first electrode 15 and the second electrode 16 is a pixel electrode, and the other is a common electrode. The first electrode 15 and the second electrode 16 are both made of a transparent conductive material. The materials of the first electrode 15 and the second electrode 16 can be the same or different. The transparent conductive material can be indium tin oxide (ITO), indium zinc oxide (IZO), aluminum tin oxide (ATO), aluminum zinc oxide (AZO), or other suitable metal oxides. The first electrode 15 and the second electrode 16 can both be a single layer or a stack of multiple layers.

[0081] The second electrode 16 includes a plurality of electrode strips 161 arranged in parallel along a first direction. A first slit 16s is defined between adjacent electrode strips 161 within the same second electrode 16. Along the first direction, the width W of the electrode strips 161 is smaller than the width of the sub-pixel region. In some embodiments, the ratio of the width W of at least one electrode strip 161 to the width of the corresponding sub-pixel region is between 0.06 and 0.3.

[0082] The width W of the electrode strip 161 refers to the dimension of the electrode strip 161 perpendicular to the extending direction thereof.

[0083] The inventors have discovered that when the width W of electrode strips 161 is larger, the area occupied by electrode strips 161 is larger, and the flexoelectric effect of liquid crystal molecules in the area occupied by electrode strips 161 is relatively reduced, thereby further improving image flicker. In the disclosed embodiment, setting the ratio of the width W of at least one electrode strip 161 to the width of the corresponding sub-pixel area between 0.06 and 0.3 is beneficial for improving image flicker.

[0084] In some embodiments, the ratio of the width W of each electrode strip 161 to the width of the corresponding sub-pixel region can be set between 0.06 and 0.3.

[0085] In some embodiments, a plurality of sub-pixel regions arranged along a first direction constitute a pixel. For example, three or four sub-pixel regions arranged along the first direction constitute a pixel region. The multiple sub-pixels in a pixel region are used to display multiple colors, such as red, green, and blue. In some embodiments, the pixel density of the display substrate is 250 PPI to 300 PPI, that is, there are 250 to 300 pixel regions per inch of length along the first direction. In one example, each pixel region includes three sub-pixel regions, that is, there are 750 to 900 sub-pixel regions per inch of length along the first direction. The width of the electrode strips 161 is between 1.8 μm and 4 μm.

[0086] In one example, the pixel density is 270PPI, and the width W of the electrode strip 161 is 1.8μm; or, W is 2μm; or, W is 2μm; or, W is 2.4μm; or, W is 2.5μm; or, W is 3μm; or, W is 3μm; or, W is 3μm; or, W is 3.5μm; or, W is 3.8μm; or, W is 4μm.

[0087] In some embodiments, the relationship between the transmittance change value A of the display substrate in two adjacent frames and the width W of the electrode strips satisfies the following equation: A=(-0.0228W+0.1348)*k

[0088] Here, k is an error coefficient, 0<k<3; for example, k is 1, or 1.1, or 1.5, or 2.

[0089] It should be noted that the driving voltage in the same sub-pixel region has opposite polarity in two adjacent display cycles. For example, the voltage applied to the common electrode remains unchanged, but the polarity of the pixel electrodes in the same sub-pixel region is opposite in two adjacent display cycles. Therefore, the transmittance change value of the display substrate in two adjacent frames refers to the ratio of the difference in transmittance of the display substrate in the two adjacent display cycles to the sum of the transmittance of the display substrate in the two adjacent display cycles.

[0090] During actual testing, when the display substrate displays a test image, the brightness at the center of the display substrate can be collected by an optical instrument, so as to determine the difference in transmittance between two adjacent display periods of the display substrate based on the brightness at the center of the display substrate.

[0091] 6 is a curve showing the relationship between the transmittance change value of the substrate and the electrode strip width in two adjacent frames. The curve satisfies the above relationship. The k value corresponding to FIG6 is 1.

[0092] After comprehensively considering factors such as the width and transmittance of the electrode strips 161, the inventors have found that for display substrates with a pixel density of 250 PPI to 300 PPI, by setting the width of the electrode strips 161 to between 1.8 μm and 4 μm, and providing 2 to 6 electrode strips 161 in each sub-pixel area, the change in transmittance of the display substrate between two adjacent frames is reduced, thereby reducing the flicker value of the display substrate. When the drive frequency of the display substrate is 60 Hz, the flicker value is less than or equal to -30 dB. The flicker value is a parameter used to indicate the degree of image flicker. A larger flicker value indicates a higher degree of flicker, and a smaller flicker value indicates a lower degree of flicker.

[0093] In some embodiments, along the first direction, the ratio of the width W of at least one electrode strip 161 to the width S of the adjacent first slit 16s is between 0.4 and 1.3. Considering that a larger W / S ratio (i.e., larger W and smaller S) results in lower transmittance in the sub-pixel region, in the disclosed embodiments, the ratio of the width of the electrode strip 161 to the width of the first slit 16s is set between 0.4 and 1.3. This can improve image flicker while maintaining the transmittance of the sub-pixel region.

[0094] For example, the ratio of the width W of at least one electrode strip 161 to the width S of the first slit 16s is 0.4, or 0.5, or 0.55, or 0.6, or 0.63, or 0.75, or 0.8, or 0.85, or 0.88, or 1, or 1.3.

[0095] The width S of the first slit 16s refers to the dimension of the first slit 16s perpendicular to the extending direction thereof.

[0096] In one example, the pixel density is 270PPI, the width W of the electrode strip 161 is 1.8μm, and the width S of the first slit 16s is 4μm; or, W is 2μm and S is 4.8μm; or, W is 2μm and S is 4μm; or, W is 2.4μm and S is 4.4μm; or, W is 2.5μm and S is 4μm; or, W is 3μm and S is 3.5μm; or, W is 3μm and S is 3μm; or, W is 3μm and S is 3μm; or, W is 3μm and S is 4μm; or, W is 3.5μm and S is 4μm; or, W is 3.8μm and S is 3μm; or, W is 4μm and S is 4μm.

[0097] Table 1 shows the A values ​​corresponding to different W / S (i.e., the transmittance change value of the display substrate in two adjacent frames). Figure 7 shows the transmittance curves of the sub-pixel area corresponding to positive and negative frames when W=2.5μm and S=4.0μm; Figure 8 shows the transmittance curves of the sub-pixel area corresponding to positive and negative frames when W=3.5 and S=4.0μm. Among them, the positive frame means that the driving voltage on the pixel electrode is greater than the voltage on the common electrode; the negative frame means that the driving voltage on the pixel electrode is less than the voltage on the common electrode; the horizontal axis in Figures 7 and 8 represents the position, and the vertical axis represents the transmittance. Table 1, Figures 7 and 8 are the results of simulations under the conditions of a pixel density of 270PPI, a driving frequency of 10Hz, and a driving voltage of -2.1V and 2.1V in two adjacent frames, respectively. The transmittances in Table 1 are expressed based on the transmittance when W=2.4μm and S=4.4μm. It can be seen from Table 1, FIG7 and FIG8 that when the width of the electrode strip 161 is between 2 μm and 3.8 μm and the width of the first slit 16s is between 3 μm and 4.8 μm, a lower A value can be achieved while ensuring transmittance.

[0098] Table 1

[0099] Figure 9 is a schematic diagram of a gate metal layer provided in some embodiments of the present disclosure, Figure 10 is a schematic diagram of a semiconductor layer provided in some embodiments of the present disclosure, Figure 11 is a schematic diagram of a source-drain metal layer provided in some embodiments of the present disclosure, Figure 12 is a schematic diagram of the superposition of a gate metal layer, a semiconductor layer, and a source-drain metal layer provided in some embodiments of the present disclosure, Figure 13 is a schematic diagram of a first transparent conductive layer provided in some embodiments of the present disclosure, Figure 14 is a schematic diagram of the superposition of a gate metal layer, a semiconductor layer, a source-drain metal layer, and a first transparent conductive layer provided in some embodiments of the present disclosure, Figure 15 is a schematic diagram of a second transparent conductive layer provided in some embodiments of the present disclosure, Figure 16 is a schematic diagram of the superposition of a gate metal layer, a semiconductor layer, a source-drain metal layer, a first transparent conductive layer, and a second transparent conductive layer provided in some embodiments of the present disclosure, Figure 17 is a cross-sectional view along line A-A' in Figure 16, and Figure 18 is a cross-sectional view along line BB' in Figure 16.

[0100] As shown in Figures 9 to 18, the display substrate also includes a plurality of thin film transistors 12, each sub-pixel area corresponds to a thin film transistor 12, the drain of each thin film transistor 12 is electrically connected to the pixel electrode of a sub-pixel area, and the gate 12g of each thin film transistor 12 is electrically connected to a gate line GL. The gate 12g of the thin film transistor 12 and the gate line GL are both located in the gate metal layer G1. Among them, the gate 12g of the thin film transistor 12 can be connected to the gate line GL as an integral structure, and the gate line GL extends along the second direction, and the second direction is the same as or different from the first direction. In the embodiment of the present disclosure, the first direction and the second direction are the same as an example for explanation. However, in other embodiments, there may also be a certain angle between the first direction and the second direction. The material of the gate metal layer may include, for example, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the gate metal layer may include one or more of gold (Au), gold alloys, silver (Ag), silver alloys, aluminum (Al), aluminum alloys, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloys, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloys, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), molybdenum niobium (MoNb), and molybdenum niobium titanium (MTD), and the gate metal layer may have a single-layer or multi-layer structure.

[0101] The gate insulating layer GI is provided on a side of the gate metal layer away from the substrate 11. The gate insulating layer GI may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The gate insulating layer GI may be formed as a single layer or multiple layers.

[0102] The semiconductor layer ACT is arranged on the side of the gate insulating layer GI away from the substrate 11, and the semiconductor layer ACT includes an active layer 12a of each thin film transistor 12. The active layer 12a may include, for example, an inorganic semiconductor material (for example, polycrystalline silicon, amorphous silicon, etc.), an organic semiconductor material, or an oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor 12 may be an oxide thin film transistor 12, and the active layer 12a is an oxide semiconductor layer, which is beneficial to reducing the leakage current of the thin film transistor 12. The active layer 12a may include a channel region arranged opposite to the gate 12g and a source region and a drain region respectively located on both sides of the channel region. Both the source region and the drain region may include impurities with a higher impurity concentration than that of the channel region. The impurities may include N-type impurities or P-type impurities.

[0103] The source-drain metal layer SD is disposed on the side of the semiconductor layer ACT away from the substrate 11. The source-drain metal layer SD includes multiple data lines DL, and the source 12s and drain 12d of each thin-film transistor 12. The source 12s of the thin-film transistor 12 is electrically connected to the source region of the active layer 12a, and the drain 12d of the thin-film transistor 12 is electrically connected to the drain region of the active layer 12a. Furthermore, the display substrate in the disclosed embodiments may also have a touch function. Accordingly, the display substrate also includes multiple touch signal lines TL. In some embodiments, the touch signal lines TL are disposed in the same layer as the data lines DL and the source 12s and drain 12d of the thin-film transistor 12, thereby simplifying the patterning process. The source / drain metal layer may include one or more of gold (Au), gold alloy, silver (Ag), silver alloy, aluminum (Al), aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), molybdenum niobium (MoNb), and molybdenum niobium titanium (MTD). The source / drain metal layer may have a single-layer or multi-layer structure.

[0104] Both the touch signal line TL and the data line DL can extend along a third direction. It should be noted that the touch signal line TL (or data line DL) extending along the third direction means that the touch signal line TL (or data line DL) as a whole extends along the third direction. The touch signal line TL (or data line DL) can be a straight line or have some bends, but the overall trend is to extend along the third direction. The second direction intersects the third direction, for example, the second direction is perpendicular to the third direction.

[0105] The first passivation layer PVX1 is provided on a side of the thin film transistor 12 away from the substrate 11. The first passivation layer PVX1 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The first passivation layer PVX1 may be formed as a single layer or multiple layers.

[0106] The first transparent conductive layer TC1 is disposed on a side of the first passivation layer PVX1 away from the substrate 11. The first transparent conductive layer TC1 may include a first electrode 15. In the embodiment of the present disclosure, the first electrode 15 may be a common electrode.

[0107] In some embodiments, the first electrodes 15 of multiple sub-pixel regions constitute a first electrode layer. The first electrode layer includes multiple first sub-electrodes 151 arranged in an array along the second and third directions. The orthographic projection of each first sub-electrode 151 on the substrate 11 may overlap with one or more sub-pixel regions. In other words, the portion of the first sub-electrode 151 located in a sub-pixel region serves as the first electrode.

[0108] Among them, there is a second slit 15s between two adjacent first sub-electrodes 151 arranged in the second direction; the orthographic projection of the second slit 15s on the substrate 11 overlaps with the orthographic projection of the touch signal line TL on the substrate 11, so as to reduce the overlapping area between the touch signal line TL and the first electrode layer, thereby reducing the parasitic capacitance between the touch signal line TL and the first electrode layer, and reducing or preventing the parasitic capacitance from affecting the signal on the touch signal line TL.

[0109] As shown in FIG11 , the touch signal line TL may be a meander line, including first line segments TL1 and second line segments TL2 alternately arranged and connected in a third direction, with the first line segments TL1 and the second line segments TL2 extending in different directions. Each second slit 15s corresponds to a first line segment TL1 or a second line segment TL2, and the extension direction of each second slit 15s is the same as the extension direction of the corresponding first line segment TL1 or second line segment TL2. Furthermore, the orthographic projection of each second slit 15s on the substrate 11 overlaps with the orthographic projection of the corresponding first line segment TL1 or second line segment TL2 on the substrate 11.

[0110] In some embodiments, the width of the second slit 15s may be greater than or equal to the width of the touch signal line TL, and two opposite sides of the touch signal line TL are partially exposed by the second slit 15s, thereby further reducing the overlapping area between the touch signal line TL and the first electrode layer.

[0111] The orthographic projection of the touch signal line TL on the substrate 11 does not overlap with the orthographic projection of the data line DL on the substrate 11 .

[0112] In some embodiments, the width of the touch signal line TL is greater than the width of the data line DL, which is beneficial to reducing the resistance of the touch signal line and further beneficial to improving touch sensitivity.

[0113] In some embodiments, the width of the touch signal line TL is 1.5 to 3 times the width of the data line DL. In one example, the width of the touch signal line TL is between 4.5 μm and 7 μm, and the width of the data line DL is between 1.5 μm and 3.5 μm. For example, the width of the touch signal line TL is 4.5 μm, and the width of the data line DL is 1.5 μm; for another example, the width of the touch signal line TL is 5 μm, and the width of the data line DL is 2 μm; for another example, the width of the touch signal line TL is 5.8 μm, and the width of the data line DL is 2.8 μm.

[0114] In some embodiments, a third slit 18s is defined between two adjacent first sub-electrodes 151 arranged in the third direction. The third slit 18s may extend along the second direction, and the third slit 18s exposes at least a portion of the gate line GL and the drain electrode 12d of the thin-film transistor 12. That is, the orthographic projection of at least a portion of the gate line GL on the substrate 11 does not overlap with the orthographic projection of the first electrode 15 on the substrate 11, and the orthographic projection of the drain electrode 12d of the thin-film transistor 12 on the substrate 11 does not overlap with the orthographic projection of the first electrode 15 on the substrate 11. This reduces parasitic capacitance between the first electrode 15 and the gate line GL, and reduces parasitic capacitance between the first electrode 15 and the drain electrode 12d of the thin-film transistor 12.

[0115] In some embodiments, the orthographic projection of each first sub-electrode 151 on the substrate 11 overlaps with one or more sub-pixel areas. For example, the orthographic projection of each first sub-electrode 151 on the substrate 11 overlaps with 2, 3, 4, or 5 sub-pixel areas. In addition, the multiple first sub-electrodes 151 can be divided into multiple electrode groups 15g, each electrode group 15g can include multiple first sub-electrodes 151 arranged along the second direction and connected in sequence, and the two adjacent first sub-electrodes 151 in the same electrode group 15g can be connected by two sub-electrode connecting portions 152, and the two adjacent first sub-electrodes 151 and the two sub-electrode connecting portions 152 between them form a second slit 15s. The sub-electrode connecting portion 152 and the first sub-electrode 151 can form an integral structure. Each electrode group 15g can be connected to a touch signal line TL, and different electrode groups 15g are connected to different touch signal lines TL.

[0116] As shown in Figures 17 and 18, the second passivation layer PVX2 is provided on the side of the layer where the first electrode 15 is located away from the substrate 11. The second passivation layer PVX2 is provided on the side of the thin film transistor 12 away from the substrate 11. The first passivation layer PVX1 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The second passivation layer PVX2 can be formed as a single layer or multiple layers.

[0117] The second transparent conductive layer TC2 is disposed on a side of the second passivation layer PVX2 away from the substrate 11. The second transparent conductive layer TC2 may include a plurality of second electrodes 16. The second electrodes 16 are pixel electrodes, each corresponding to a sub-pixel region. The second electrodes 16 include a plurality of electrode strips 161 and a connecting portion 162. The connecting portion 162 is connected to each electrode strip 161 and is connected to the drain electrode 12d of the thin-film transistor 12 via a first via hole V1 that penetrates the first passivation layer PVX1 and the second passivation layer PVX2.

[0118] In some embodiments, as shown in FIG11 , the drain electrode 12d of each thin-film transistor 12 includes a drain body portion 12d1 and a drain connection portion 12d2. The drain connection portion 12d2 is connected to the active layer, and the orthographic projection of the drain body portion 12d1 on the substrate 11 is located outside the orthographic projection of the active layer on the substrate 11. In one example, the second electrode 16 is electrically connected to the drain body portion 12d1, and the orthographic projection of the second electrode 16 on the substrate 11 completely covers the orthographic projection of the drain body portion 12d1 on the substrate 11, thereby ensuring a reliable connection between the second electrode 16 and the thin-film transistor.

[0119] In the embodiment of the present disclosure, the first electrode 15 serves as a common electrode in the display stage; in the touch stage, it is reused as a touch electrode and electrically connected to the touch signal line TL to receive the touch signal on the touch signal line TL. This arrangement can simplify the structure of the display substrate. Specifically, the first electrode 15 can be connected to the touch signal line TL through the transfer electrode 17. Specifically, the transfer electrode 17 is arranged on the same layer as the second electrode 16, and the transfer electrode 17 is electrically connected to the first electrode 15 through the second via V2 penetrating the second passivation layer PVX2, and is connected to the touch signal line TL through the third via V3 penetrating the first passivation layer PVX1 and the second passivation layer PVX2.

[0120] Among them, the second via V2 and the third via V3 can be connected. At this time, the transfer electrode 17 not only contacts the surface of the first electrode 15 away from the substrate 11, but also contacts the side surface of the first electrode 15, thereby improving the connection stability between the transfer electrode 17 and the first electrode 15.

[0121] It is understandable that if the first electrode 15 is used as a pixel electrode and the second electrode 16 is used as a common electrode, the vias for connecting the pixel electrode and the thin film transistor 12, and the vias for connecting the common electrode and the touch signal line TL require different patterning processes to be made separately. In the embodiment of the present disclosure, the advantage of using the first electrode 15 as the common electrode and the second electrode 16 as the pixel electrode (i.e., the common electrode is at the bottom and the pixel electrode is at the top) is that: after the thin film transistor 12 is made, the first passivation layer PVX1, the first electrode 15, and the second passivation layer PVX2 can be formed in sequence; then, the first via V1, the second via V2, and the third via V3 are formed simultaneously through the same patterning process; finally, the second electrode 16 and the transfer electrode 17 are formed simultaneously through the same patterning process. That is, the vias for connecting the pixel electrode and the thin film transistor 12, and the vias for connecting the common electrode and the touch signal line TL, can be made through the same patterning process, thereby simplifying the manufacturing process and reducing production costs.

[0122] In the embodiment of the present disclosure, the display substrate may further include a common voltage line (not shown), and each first sub-electrode 151 is electrically connected to the common voltage line. The common voltage line is used to provide a common voltage signal to the first sub-electrodes 151 during the display phase. In one example, the common voltage line can be provided on the same layer as the gate line GL, and each first sub-electrode 151 is electrically connected to the common voltage line through a via.

[0123] In some embodiments, as shown in FIG9 , the plurality of thin film transistors 12 may include a plurality of first thin film transistors 121 and a plurality of second thin film transistors 122. That is, some of the thin film transistors 12 in the display substrate may function as first thin film transistors 121, and another portion of the thin film transistors 12 may function as second thin film transistors 122. In one example, each gate line GL may connect the plurality of first thin film transistors 121 and the plurality of second thin film transistors 122.

[0124] The width of the gate electrode 121 g of the first thin film transistor 121 in the second direction is greater than the width of the second thin film transistor 122 in the second direction.

[0125] In some embodiments, the difference in width between the gate 121g of the first thin film transistor 121 and the gate 122g of the second thin film transistor 122 in the second direction is between 6 μm and 10 μm, for example, 6 μm, 8 μm, or 10 μm.

[0126] As shown in FIG11 , the display substrate further includes a plurality of first support portions 81. The plurality of first support portions 81 are located on a side of the gate electrode 121g of the first thin-film transistor 121 away from the substrate 11. The orthographic projection of each first support portion 81 on the substrate 11 overlaps with the orthographic projection of the gate electrode 121g of a first thin-film transistor 121 on the substrate 11. In one example, the width of the first support portion 81 in the third direction can be the same as or similar to the width of the gate electrode 121g of the first thin-film transistor 121 in the third direction.

[0127] In one example, multiple first support portions 81 can be located in the source-drain metal layer SD, that is, multiple first support portions 81 are arranged in the same layer as the source and drain electrodes 12d of multiple thin film transistors 12, and the data lines DL, so that the first support portions 81, the source electrodes, the drain electrodes 12d, and the data lines DL of each thin film transistor 12 can be simultaneously manufactured through the same patterning process to simplify the preparation process.

[0128] In one example, the orthographic projection of the first support portion 81 on the substrate 11 may be an ellipse, a polygon, etc. For example, the orthographic projection of the first support portion 81 on the substrate 11 may be a rectangle, a hexagon, etc.

[0129] In an example, the first supporting portion 81 is floating, that is, the first supporting portion 81 is insulated from the data line DL and the thin film transistor 12 .

[0130] In some embodiments, at least one edge of the data line DL has a recessed portion DLa, where the orthographic projection of the recessed portion DLa on the substrate 11 is within the orthographic projection of the gate electrode of the thin film transistor on the substrate 11. The edge of the data line DL refers to the edge of the data line DL extending along its length. The recessed portion DLa can reduce the width of the overlap between the data line DL and the gate metal layer G1, thereby reducing parasitic capacitance between the data line DL and the gate metal layer G1.

[0131] In some embodiments, the depth of the recessed portion DLa is less than or equal to half the width of the data line DL, thereby reducing the parasitic capacitance between the data line DL and the gate metal layer G1 while ensuring signal transmission efficiency of the data line DL. The depth of the recessed portion DLa refers to its dimension in the second direction. In one example, the width of the data line DL is 2-3 μm, and the depth of the recessed portion DLa is less than or equal to 1 μm.

[0132] In some embodiments, each first support portion 81 is adjacent to a data line DL. It should be noted that "a first support portion 81 adjacent to a data line DL" means that no other structure is disposed between the first support portion 81 and the data line DL. In some embodiments, the edge of the data line DL adjacent to the first support portion 81 near the first support portion 81 has the aforementioned recessed portion DLa, which curves away from the first support portion 81. For example, a first support portion 81 is adjacent to a data line DL to its right, and the left edge of the data line DL has a recessed portion DLa that opposes the first support portion 81 and curves to the right.

[0133] In some embodiments, as shown in FIG10 , the display substrate further includes a plurality of second support portions 82 . The second support portions 82 are disposed on the same layer as the active layer 12 a of the thin film transistor 12 . The orthographic projection of each second support portion 82 on the substrate 11 overlaps with the orthographic projection of one first support portion 81 on the substrate 11 . For example, the orthographic projection of each second support portion 82 on the substrate 11 substantially coincides with the orthographic projection of one first support portion 81 on the substrate 11 .

[0134] In some embodiments, as shown in Figures 9 and 10, the display substrate may further include: a plurality of third support portions 83 and a plurality of fourth support portions 84. The third support portions 83 are disposed on the same layer as the gate lines GL, and the orthographic projection of each third support portion 83 on the substrate 11 overlaps with the orthographic projection of a touch signal line TL on the substrate 11. The fourth support portions 84 are disposed on the same layer as the active layer 12a of the thin film transistor 12. Each fourth support portion 84 corresponds to a third support portion 83, and the orthographic projection of the fourth support portion 84 on the substrate 11 overlaps with the orthographic projection of a third support portion 83 on the substrate 11.

[0135] In an example, the orthographic projection of the third support portion 83 on the substrate 11 may overlap with the orthographic projection of a touch signal line TL on the substrate 11 ; the orthographic projection of the fourth support portion 84 on the substrate 11 overlaps with the orthographic projection of a touch signal line TL on the substrate 11 .

[0136] When the display substrate disclosed herein is used in a display panel, multiple spacers can be provided between the display substrate and the color filter substrate to provide support for the display panel. A first support portion 81, a second support portion 82 corresponding to the first support portion 81, and a portion of the gate metal layer G1 corresponding to the first support portion 81 form a first support group; a third support portion 83, a fourth support portion 84 corresponding to the third support portion 83, and a portion of the source / drain metal layer SD corresponding to the third support portion 83 form a second support group. Each first support group and each second support group is used to correspond to the position of a spacer. The provision of the first support portion 81, the second support portion 82, the third support portion 83, and the fourth support portion 84 can improve the support stability of the spacer.

[0137] In one example, each sub-pixel area corresponds to a spacer, and each spacer is arranged opposite to a first support group or a second support group.

[0138] In some embodiments, the orthographic projection of the first sub-electrode 151 on the substrate 11 overlaps with the orthographic projection of the second electrode 16 on the substrate 11. The first sub-electrode 151 and the second electrode 16 whose orthographic projection overlaps with the first sub-electrode 151 constitute an electrode unit. In the same electrode unit, the first sub-electrode 151 includes a first edge E1 and a second edge E2 arranged opposite each other in the third direction. The first edge E1 is adjacent to the thin film transistor 12 connected to the second electrode 16. The first edge E1 has a bent portion 15b. The bent portion 15b is opposite to the drain 12d of the adjacent thin film transistor 12 and bends away from the drain 12d of the thin film transistor 12 to prevent parasitic capacitance from being generated between the first sub-electrode 151 and the drain 12d.

[0139] FIG19 is a cross-sectional view of a display panel provided in some embodiments of the present disclosure. As shown in FIG19 , the display panel includes: the above-mentioned display substrate 10, a color filter substrate 20 arranged opposite to the display substrate 10, and a liquid crystal layer 30 located therebetween.

[0140] The color filter substrate 20 includes a substrate 21, a color filter layer, and a black matrix BM. The color filter layer and black matrix BM are disposed on the side of the substrate 21 facing the display substrate 10. The color filter layer includes multiple color filter sections 22a, for example, multiple red filter sections, multiple blue filter sections, and multiple green filter sections. The orthographic projection of each color filter section 22a on the display substrate overlaps with a sub-pixel area, and the orthographic projections of different color filter sections 22a on the display substrate 10 overlap with different sub-pixel areas. The orthographic projection of the black matrix BM on the substrate 11 of the display substrate 10 overlaps the orthographic projections of the gate lines GL, data lines DL, and touch signal lines TL on the substrate 11 of the display substrate 10.

[0141] A covering layer 20 is further provided on the side of the color filter layer away from the substrate 21 . The covering layer 20 may be made of an organic material, such as optical adhesive.

[0142] Alignment layers may be provided on both the side of the color filter substrate 20 facing the display substrate 10 and the side of the display substrate 10 facing the color filter substrate 20 , for aligning liquid crystal molecules in the liquid crystal layer 30 .

[0143] The display panel may further include a plurality of spacers 31, which are located between the color filter substrate 20 and the array substrate 10 to support the display panel and maintain the thickness of the display panel. The plurality of spacers 31 may include a plurality of main spacers and a plurality of auxiliary spacers, and the height of the main spacers may be greater than the height of the auxiliary spacers.

[0144] The present disclosure also provides a display device, including the display panel in the above embodiment. The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0145] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a substrate, wherein the substrate comprises a plurality of sub-pixel regions, wherein: At least one of the sub-pixel regions comprises: a first electrode and a second electrode disposed on the substrate, wherein the second electrode is located on a side of the first electrode away from the substrate and is insulated from the first electrode; The second electrode comprises a plurality of electrode strips arranged in parallel along a first direction, and a first slit is provided between two adjacent electrode strips in the same second electrode; along the first direction, the width of the electrode strip is smaller than the width of the sub-pixel region, and the sub-pixel region comprises at least three electrode strips; and the ratio of the width of at least one of the electrode strips to the width of the corresponding sub-pixel region is between 0.06 and 0.3; One of the first electrode and the second electrode is a pixel electrode, and the other is a common electrode.

2. The display substrate according to claim 1, wherein: Along the first direction, a ratio of a width of at least one of the electrode strips to a width of the first slit on an adjacent side is between 0.4 and 1.

3.

3. The display substrate according to claim 1, wherein: Along the first direction, 750 to 900 sub-pixel areas are passed through per inch, and the width of the electrode strip is between 1.8 μm and 4 μm.

4. The display substrate according to any one of claims 1 to 3, wherein: The change in transmittance of the display substrate between two adjacent frames and the width of the electrode strips satisfy the following relationship: A = (-0.0228W + 0.1348) * k Wherein, W is the width of the electrode strip, A is the transmittance change value of the display substrate in two adjacent frames, k is the error coefficient, and 0<k<3.

5. The display substrate according to any one of claims 1 to 4, wherein: The display substrate further comprises: A plurality of grid lines, wherein the grid lines are arranged along a second direction, and the second direction is the same as or different from the first direction; A plurality of thin film transistors, each of the plurality of thin film transistors is electrically connected to a pixel electrode of the sub-pixel region and to one of the gate lines.

6. The display substrate according to claim 5, wherein: The plurality of thin film transistors include a plurality of first thin film transistors and a plurality of second thin film transistors, and the width of the gate of the first thin film transistor in the second direction is greater than the width of the second thin film transistor in the second direction; A plurality of first support portions are located on a side of the gate of the first thin film transistor away from the substrate, and an orthographic projection of each of the plurality of first support portions on the substrate overlaps with an orthographic projection of the gate of the first thin film transistor on the substrate.

7. The display substrate according to claim 6, wherein: The first supporting portion is arranged in the same layer as the source electrodes and the drain electrodes of the plurality of thin film transistors.

8. The display substrate according to claim 6, wherein: A difference between the widths of the gate of the first thin film transistor and the gate of the second thin film transistor in the second direction is between 6 μm and 10 μm.

9. The display substrate according to claim 6, wherein: The display substrate further comprises: a plurality of second supporting portions, wherein an orthographic projection of each of the plurality of second supporting portions on the substrate overlaps with an orthographic projection of one of the first supporting portions on the substrate; Wherein, the second supporting portion is arranged at the same layer as the active layer of the thin film transistor.

10. The display substrate according to claim 5, wherein: An orthographic projection of at least a portion of the gate line on the substrate does not overlap with an orthographic projection of the first electrode on the substrate.

11. The display substrate according to claim 5, wherein: The display substrate further comprises: a plurality of data lines, each of the plurality of data lines extending along a third direction, the third direction intersecting the second direction; Among them, the orthographic projection of each data line on the substrate overlaps with the orthographic projections of the gates of the plurality of thin film transistors on the substrate; at least one edge of the data line has a recessed portion, and the orthographic projection of the recessed portion on the substrate is within the range of the orthographic projection of the gate of the thin film transistor on the substrate.

12. The display substrate according to claim 11, wherein: The depth of the recessed portion is less than or equal to half of the width of the data line.

13. The display substrate according to claim 11, wherein: The display substrate further comprises: A plurality of touch signal lines are arranged in the same layer as the source electrodes and the drain electrodes of the plurality of thin film transistors; each of the plurality of touch signal lines extends along the third direction; The first electrode is multiplexed as a touch electrode and is electrically connected to the touch signal line.

14. The display substrate according to claim 13, wherein: The width of the touch signal line is 1.5 to 3 times the width of the data line.

15. The display substrate according to claim 13, wherein: The first electrodes of the plurality of sub-pixel regions constitute a first electrode layer, wherein the first electrode layer comprises: a plurality of first sub-electrodes, and the plurality of first sub-electrodes are arranged in an array along the second direction and the third direction; A second slit is provided between two adjacent first sub-electrodes arranged in the second direction, and an orthographic projection of the second slit on the base substrate overlaps with an orthographic projection of the touch signal line on the base substrate.

16. The display substrate according to claim 15, wherein: The width of the second slit is greater than or equal to the width of the touch signal line.

17. The display substrate according to claim 13, wherein: The display substrate further comprises: A plurality of third support portions are arranged in the same layer as the gate line, and an orthographic projection of each of the plurality of third support portions on the substrate overlaps with an orthographic projection of one of the touch signal lines on the substrate; A plurality of fourth support portions are arranged in the same layer as the active layer of the thin film transistor; each of the plurality of fourth support portions corresponds to one of the third support portions, and an orthographic projection of the fourth support portion on the substrate overlaps with an orthographic projection of one of the third support portions.

18. The display substrate according to claim 5, wherein: The orthographic projection of the first sub-electrode on the substrate overlaps with the orthographic projection of the second electrode on the substrate; The first sub-electrode and a second electrode overlapping with the orthographic projection of the first sub-electrode constitute an electrode unit. In the same electrode unit, the first sub-electrode includes a first edge and a second edge arranged opposite to each other in the third direction, the first edge is adjacent to the thin film transistor connected to the second electrode, and the first edge has a bent portion, which is opposite to the drain of the adjacent thin film transistor and bends away from the thin film transistor.

19. The display substrate according to claim 5, wherein: The second electrode further comprises a connecting portion connected to the plurality of electrode strips, an orthographic projection of at least part of the connecting portion on the substrate is located outside an orthographic projection of the first electrode on the substrate, and the connecting portion is connected to the drain of the thin film transistor through a first via hole; An orthographic projection of the first via hole on the substrate is outside an orthographic projection of the first electrode on the substrate.

20. The display substrate according to any one of claims 1 to 19, wherein: When the driving frequency of the display substrate is 60 Hz and the polarities of the driving voltages in each sub-pixel region are opposite in two adjacent frames, the flicker value of the display substrate is less than -30 dB.

21. The display substrate according to any one of claims 1 to 20, wherein: The display substrate further comprises: A plurality of thin film transistors are arranged between the layer where the first electrode is located and the substrate; A first passivation layer is disposed between the plurality of thin film transistors and a layer where the first electrode is located; A second passivation layer is provided between the layer where the first electrode is located and the layer where the second electrode is located; A plurality of touch signal lines are arranged in the same layer as the source and the drain of each of the plurality of thin film transistors; A plurality of switching electrodes are arranged in the same layer as the second electrode; Wherein, the second electrode is connected to the drain electrode of the thin film transistor through a first via hole penetrating the first passivation layer and the second passivation layer; The transfer electrode is electrically connected to the first electrode through a second via hole penetrating the second passivation layer, and is connected to the touch signal line through a third via hole penetrating the first passivation layer and the second passivation layer.

22. The display substrate according to claim 21, wherein: The second via hole corresponding to the same switching electrode is connected to the third via hole.

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