Semiconductor device

Abstract

The technical problem of the present invention is to effectively suppress the concentration of an electric field generated when a reverse voltage is applied in a semiconductor device having a structure in which an outer peripheral trench is provided in a drift layer. A semiconductor device (1) is provided with a semiconductor substrate (20), a drift layer (30) provided on the semiconductor substrate (20), an anode electrode (40) in contact with the drift layer (30), and a cathode electrode (50) in contact with the semiconductor substrate (20). The drift layer (30) has: an outer peripheral trench (61) provided along an outer edge (41) of the anode electrode (40) so as to overlap the outer edge (41) in plan view; an outer peripheral groove (62) that is adjacent to the outer peripheral groove (61) and is provided on the outside of the outer peripheral groove (61) so as to surround the outer peripheral groove (61) in plan view; and a boss region (311) located between the outer peripheral groove (61) and the outer peripheral groove (62). The width (Wm1) of the boss region (311) is narrower than the width (Wt1) of the outer peripheral groove (61).

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to semiconductor devices having a structure in which peripheral trenches are provided in the drift layer. Background Technology

[0002] Patent Document 1 discloses a semiconductor device comprising: a first electrode layer connected to the surface of an n-type gallium oxide semiconductor layer, a second electrode layer connected to the back surface of the n-type gallium oxide semiconductor layer, and a p-type nickel oxide semiconductor layer embedded in trenches disposed in the n-type gallium oxide semiconductor layer. In Patent Document 1, by providing multiple trenches into which the p-type nickel oxide semiconductor layer is embedded, the concentration of the electric field generated when a reverse voltage is applied is suppressed.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2023-010539 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] However, in the structure disclosed in Patent Document 1, the effect of suppressing the concentration of the electric field generated when the reverse voltage is applied to the trench portion such as the bottom of the trench in the drift layer is not sufficient.

[0008] This disclosure describes a technique for effectively suppressing the concentration of electric field generated when a reverse voltage is applied in a semiconductor device having a structure in which an outer peripheral trench is provided in the drift layer.

[0009] Technical means to solve the problem

[0010] A semiconductor device according to one aspect of this disclosure includes: a semiconductor substrate, a drift layer disposed on the semiconductor substrate, a first electrode in contact with the drift layer, and a second electrode in contact with the semiconductor substrate. The drift layer has: a plurality of peripheral trenches, including: a first peripheral trench disposed along its outer edge such that it overlaps with the outer edge of the first electrode when viewed from above; a second peripheral trench adjacent to the first peripheral trench and disposed outside the first peripheral trench such that it surrounds the first peripheral trench when viewed from above; and a first boss region located between the first peripheral trench and the second peripheral trench, the width of the first boss region being narrower than the width of the first peripheral trench.

[0011] The effects of the invention

[0012] According to this disclosure, a technique is provided for effectively suppressing the concentration of electric field generated when a reverse voltage is applied in a semiconductor device having a structure in which an outer peripheral trench is provided in the drift layer. Attached Figure Description

[0013] Figure 1 (a) is a schematic top view illustrating the structure of a semiconductor device 1 according to a first embodiment of the technology disclosed herein. Furthermore, Figure 1 (b) is along Figure 1 The approximate cross-sectional view of line AA shown in (a).

[0014] Figure 2 (a) is a schematic cross-sectional view used to illustrate the construction of a first modified example of semiconductor device 1. Figure 2 (b) is a schematic cross-sectional view illustrating the construction of a second modified example of semiconductor device 1. Figure 2 (c) is a schematic cross-sectional view illustrating the construction of a third modified example of semiconductor device 1. Figure 2 (d) is a schematic cross-sectional view used to illustrate the construction of the fourth modified example of semiconductor device 1.

[0015] Figure 3 (a) is a schematic cross-sectional view illustrating the construction of a fifth modified example of semiconductor device 1. Figure 3 (b) is a schematic cross-sectional view used to illustrate the construction of the sixth modified example of semiconductor device 1. Figure 3 (c) is a schematic cross-sectional view used to illustrate the construction of the seventh modified example of semiconductor device 1. Figure 3 (d) is a schematic cross-sectional view used to illustrate the construction of the eighth modified example of semiconductor device 1.

[0016] Figure 4 (a) is a schematic cross-sectional view used to illustrate the construction of the ninth modified example of semiconductor device 1. Figure 4 (b) is a schematic cross-sectional view used to illustrate the construction of the tenth modified example of semiconductor device 1.

[0017] Figure 5 (a) is a schematic top view illustrating the structure of a semiconductor device 2 according to a second embodiment of the technology disclosed herein. Furthermore, Figure 5 (b) is along Figure 5 The approximate cross-sectional view of line AA shown in (a).

[0018] Figure 6 This is a schematic cross-sectional view used to illustrate the construction of a first modified example of semiconductor device 2.

[0019] Figure 7 This is a schematic cross-sectional view used to illustrate the construction of a second modified example of semiconductor device 2.

[0020] Figure 8 This is a schematic cross-sectional view used to illustrate the structure of a third modified example of semiconductor device 2.

[0021] Figure 9 This is a schematic cross-sectional view used to illustrate the structure of the fourth modified example of semiconductor device 2.

[0022] Figure 10 This is a schematic cross-sectional view used to illustrate the structure of the fifth modified example of semiconductor device 2.

[0023] Figure 11 (a) is a schematic top view illustrating the structure of a semiconductor device 3 according to a third embodiment of the technology disclosed herein. Furthermore, Figure 11 (b) is along Figure 11 The approximate cross-sectional view of line AA shown in (a).

[0024] Figure 12 This is a schematic cross-sectional view used to illustrate the construction of a modified example of semiconductor device 3. Detailed Implementation

[0025] Hereinafter, with reference to the accompanying drawings, embodiments of the technology disclosed herein will be described in detail.

[0026] <First Implementation>

[0027] Figure 1 (a) is a schematic top view illustrating the structure of a semiconductor device 1 according to a first embodiment of the technology disclosed herein. Furthermore, Figure 1 (b) is along Figure 1 The approximate cross-sectional view of line AA shown in (a).

[0028] Figure 1 The semiconductor device 1 shown is a Schottky barrier diode, comprising a semiconductor substrate 20 and a drift layer 30, both made of gallium oxide (β-Ga₂O₃). Silicon (Si) or tin (Sn) is introduced into the semiconductor substrate 20 and the drift layer 30 as n-type impurities. The concentration of impurities is higher in the semiconductor substrate 20 than in the drift layer 30; therefore, the semiconductor substrate 20 acts as an n-type impurity. + The layer performs its function, with drift layer 30 acting as n. - The layer performs its function. For example, the impurity concentration of the semiconductor substrate 20 is 1×10⁻⁶. 18 cm -3 The impurity concentration in drift layer 30 is 1×10⁻⁶. 16 cm -3 .

[0029] The semiconductor substrate 20 is formed by cutting a bulk crystal that has been formed using a melt growth method or similar process, and its thickness is approximately 250 μm. The planar dimensions of the semiconductor substrate 20 are not particularly limited, but are generally selected based on the amount of current flowing through the device. If the maximum forward current is approximately 20 A, then it can be set to approximately 2.4 mm × 2.4 mm when viewed from above.

[0030] The semiconductor substrate 20 has an upper surface 21 located on the upper side during mounting, and a back surface 22 located on the opposite side of the upper surface 21, i.e., on the lower side during mounting. A drift layer 30 is formed on the entire surface of the upper surface 21. The drift layer 30 is a thin film of gallium oxide epitaxially grown on the upper surface 21 of the semiconductor substrate 20 using reactive sputtering, PLD, MBE, MOCVD, HVPE, or other methods. The thickness of the drift layer 30 is not particularly limited, but it is generally selected based on the reverse breakdown voltage of the device. To ensure a breakdown voltage of around 600V, for example, a thickness of around 15μm is sufficient.

[0031] An anode electrode 40, in Schottky contact with the drift layer 30, is formed on the upper surface 31 of the drift layer 30. The anode electrode 40 functions as the first electrode of the semiconductor device 1. The anode electrode 40 is made of metals such as platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), molybdenum (Mo), and copper (Cu). The anode electrode 40 can be a multilayer structure with different metal films stacked, such as Pt / Au, Pt / Al, Pd / Au, Pd / Al, Pt / Ti / Au, or Pd / Ti / Au. On the other hand, a cathode electrode 50, in ohmic contact with the semiconductor substrate 20, is provided on the back side 22 of the semiconductor substrate 20. The cathode electrode 50 functions as the second electrode of the semiconductor device 1. The cathode electrode 50 is made of metals such as titanium (Ti). The cathode electrode 50 can be a multilayer structure with different metal films stacked, such as Ti / Au or Ti / Al. In this case, Ti is in contact with the semiconductor substrate 20.

[0032] In this embodiment, peripheral trenches 61 and 62 are provided in the drift layer 30. The peripheral trench 61 is provided along the outer edge 41 of the anode electrode 40, overlapping it when viewed from above. The peripheral trench 62 is provided outside the peripheral trench 61, surrounding it when viewed from above. The peripheral trenches 61 and 62 are adjacent to each other. Inside the peripheral trenches 61 and 62, p-type semiconductor components 71 and 72, having a conductivity type opposite to that of the drift layer 30, are respectively embedded. Each p-type semiconductor component 71 and 72 forms a pn junction with the drift layer 30. The p-type semiconductor components 71 and 72 can be made of materials such as Si, GaAs, GaN, SiC, Ge, ZnSe, CdS, InP, SiGe, AlN, BN, AlGaN, NiO, Cu2O, Ir2O3, and Ag2O.

[0033] like Figure 1As shown in (b), a portion of the surface of the p-type semiconductor component 71 embedded in the peripheral trench 61 is connected to the anode electrode 40. Thus, the p-type semiconductor component 71 and the anode electrode 40 are at the same potential. The p-type semiconductor component 72 embedded in the peripheral trench 62 is not connected to the anode electrode 40.

[0034] The region located between the outer peripheral grooves 61 and 62 on the upper surface 31 of the drift layer 30 forms a boss region 311. The boss region 311 is not in contact with the anode electrode 40. Here, when the width of the outer peripheral groove 61 is set to Wt1, the width of the outer peripheral groove 62 is set to Wt2, and the width of the boss region 311 is set to Wm1, in Figure 1 In the example shown in (b), Wm1 < Wt1 = Wt2. That is, the width of the boss region 311 is narrower than the width of the peripheral groove 61. In addition, the widths Wt1 of the peripheral groove 61 and Wt2 of the peripheral groove 62 do not need to be the same; for example, the width Wt2 of the peripheral groove 62 can be narrower than the width Wt1 of the peripheral groove 61.

[0035] Therefore, when a reverse voltage is applied to the semiconductor device 1, the potential difference between the outer peripheral trench 61 and the outer peripheral trench 62 is small. Consequently, because the electric field applied to the outer peripheral trench 61 is dispersed over a wide range, the electric field gradient becomes gentler. As a result, because the electric field applied to the outer peripheral trench 61... Figure 1 In (b), the electric field strength at the bottom of the peripheral trench 61, represented by the symbol B, is reduced, thus improving the reliability of the semiconductor device 1.

[0036] As an example, when the thickness of the drift layer 30 is 15 μm, the depth of the peripheral trenches 61 and 62 is 2 μm, the p-type semiconductor components 71 and 72 are made of NiO, the anode electrode 40 is made of Ni, and the cathode electrode 50 is made of a Ti / Au laminate, when a reverse voltage of 2000V is applied, the electric field strength applied to the bottom of the peripheral trench 61 (represented by the symbol B) is 6.7 MV / cm when designed as Wt1 = Wt2 = Wm1 = 3 μm. In contrast, when designed as Wt1 = Wt2 = 4 μm and Wm1 = 3 μm, it is reduced to 6.2 MV / cm.

[0037] Figure 2 (a) is a schematic cross-sectional view used to illustrate the construction of a first modified example of semiconductor device 1. Figure 2 The first variation shown in (a) is similar to Figure 1 The difference in semiconductor device 1 shown in (b) is that the peripheral trenches 61 and 62 are not completely embedded by p-type semiconductor components 71 and 72, respectively, but are only provided on the inner walls of the peripheral trenches 61 and 62. Even with this structure, the same effect as the semiconductor device 1 described above can be obtained.

[0038] Figure 2 (b) is a schematic cross-sectional view illustrating the construction of a second modified example of semiconductor device 1. Figure 2 The second variation shown in (b) is similar to Figure 2 The difference in the first variation of the semiconductor device 1 shown in (a) is that the peripheral trench 61 is embedded by the anode electrode 40 via the p-type semiconductor member 71. Even with this configuration, the same effect as the semiconductor device 1 described above can be achieved.

[0039] Figure 2 (c) is a schematic cross-sectional view illustrating the construction of a third modified example of semiconductor device 1. Figure 2 The third variation shown in (c) is similar to Figure 1 The difference in semiconductor device 1 shown in (b) is that p-type semiconductor components 71 and 72 are provided only on the bottom surface and the corner portion that forms the boundary between the bottom surface and the side surface in the inner walls of the outer peripheral trenches 61 and 62; a portion of the anode electrode 40 is embedded in the outer peripheral trench 61. Even with this structure, the same effect as the semiconductor device 1 described above can be obtained.

[0040] Figure 2 (d) is a schematic cross-sectional view used to illustrate the construction of the fourth modified example of semiconductor device 1. Figure 2 The fourth variation shown in (d) is similar to Figure 2 The difference in the first variation of the semiconductor device 1 shown in (a) is that the inner walls of the peripheral trenches 61, 62 and a portion of the upper surface 31 of the drift layer 30 located theren are covered by p-type semiconductor components 71, 72. Even with this configuration, the same effect as the semiconductor device 1 described above can be achieved.

[0041] Figure 3 (a) is a schematic cross-sectional view illustrating the construction of a fifth modified example of semiconductor device 1. Figure 3 The fifth variation shown in (a) is similar to Figure 2 The difference in the first variation of the semiconductor device 1 shown in (a) is that the surfaces of the p-type semiconductor components 71 and 72 are covered by an insulating film 81. Even with this construction, the same effect as the semiconductor device 1 described above can be obtained.

[0042] Figure 3 (b) is a schematic cross-sectional view used to illustrate the construction of the sixth modified example of semiconductor device 1. Figure 3 The sixth variation shown in (b) is similar to Figure 3The fifth variation of the semiconductor device 1 shown in (a) differs in that the peripheral trench 61 is embedded by the anode electrode 40 via the insulating film 81 and the p-type semiconductor member 71. Even with this configuration, the same effect as the semiconductor device 1 described above can be achieved.

[0043] Figure 3 (c) is a schematic cross-sectional view used to illustrate the construction of the seventh modified example of semiconductor device 1. Figure 3 The seventh variation shown in (c) is similar to Figure 3 The fifth variation of the semiconductor device 1 shown in (a) differs in that the peripheral trenches 61 and 62 are embedded in the insulating film 81 via p-type semiconductor components 71 and 72, respectively. Even with this configuration, the same effect as the semiconductor device 1 described above can be achieved.

[0044] Figure 3 (d) is a schematic cross-sectional view used to illustrate the construction of the eighth modified example of semiconductor device 1. Figure 3 The eighth variation shown in (d) is similar to Figure 3 The seventh variation of the semiconductor device 1 shown in (c) differs in that the upper surface 31 of the drift layer 30 exposed from the anode electrode 40 and the outer periphery of the anode electrode 40 are covered by an insulating film 81. Even with this configuration, the same effect as the semiconductor device 1 described above can be obtained.

[0045] Figure 4 (a) is a schematic cross-sectional view used to illustrate the construction of the ninth modified example of semiconductor device 1. Figure 4 The ninth variation shown in (a) is similar to Figure 3 The seventh variation of the semiconductor device 1 shown in (c) differs in that the upper surface 31 of the drift layer 30 exposed from the anode electrode 40 and the outer periphery of the anode electrode 40 are covered by an insulating film 82 that is different from the insulating film 81. Even with this configuration, the same effect as the semiconductor device 1 described above can be obtained.

[0046] Figure 4 (b) is a schematic cross-sectional view used to illustrate the construction of the tenth modified example of semiconductor device 1. Figure 4 The tenth variation shown in (b) is similar to Figure 3 The seventh variation of the semiconductor device 1 shown in (b) differs in that the upper surface 31 of the drift layer 30 exposed from the anode electrode 40, the outer periphery of the anode electrode 40, and the interior of the outer peripheral trench 62 are covered by an insulating film 82 that is different from the insulating film 81. Even with this configuration, the same effect as the semiconductor device 1 described above can be obtained.

[0047] <Second Implementation>

[0048] Figure 5 (a) is a schematic top view illustrating the structure of a semiconductor device 2 according to a second embodiment of the technology disclosed herein. Furthermore, Figure 5 (b) is along Figure 5 The approximate cross-sectional view of line AA shown in (a).

[0049] The semiconductor device 2 of the second embodiment differs from the semiconductor device 1 of the first embodiment in that: peripheral trenches 63-65 are further provided in the drift layer 30, and p-type semiconductor components 73-75 are embedded in the peripheral trenches 63-65 respectively. The other basic structures are the same as those of the semiconductor device 1 of the first embodiment, therefore the same elements are given the same symbols, and repeated descriptions are omitted.

[0050] A peripheral trench 63 is provided outside the peripheral trench 62 in a top view, surrounding it. A peripheral trench 64 is provided outside the peripheral trench 63 in a top view, surrounding it. A peripheral trench 65 is provided outside the peripheral trench 64 in a top view, surrounding it. The peripheral trench 65 constitutes the outermost peripheral trench. Furthermore, the p-type semiconductor component 71 embedded in the peripheral trench 61 is connected to the anode electrode 40, while the p-type semiconductor components 72 to 75 embedded in the peripheral trenches 62 to 65 are not connected to the anode electrode 40.

[0051] The region on the upper surface 31 of the drift layer 30 between the outer peripheral grooves 62 and 63 forms a boss region 312. The region on the upper surface 31 of the drift layer 30 between the outer peripheral grooves 63 and 64 forms a boss region 313. The region on the upper surface 31 of the drift layer 30 between the outer peripheral grooves 64 and 65 forms a boss region 314. Similar to boss region 311, boss regions 312 to 314 are not in contact with the anode electrode 40.

[0052] Here, when the widths of the outer peripheral grooves 61-65 are set to Wt1-Wt5 respectively, and the widths of the boss areas 311-314 are set to Wm1-Wm4 respectively, in Figure 5 In the example shown, Wm1 < Wt1 = Wt2 = Wt3 = Wt4 = Wt5, and Wm1 < Wm2 = Wm3 = Wm4. That is, the width of the boss region 311 is narrower than the width of the outer peripheral grooves 61-65, and narrower than the width of the boss region 314. Figure 5 In the example shown, the width of the outer peripheral boss region in two adjacent boss regions is wider than the width of the inner peripheral boss region, or the same as the width of the inner peripheral boss region. That is, the width of the outer peripheral boss region in two adjacent boss regions is greater than the width of the inner peripheral boss region.

[0053] Thus, if three or more peripheral trenches are provided in the drift layer 30, the electric field gradient when a reverse voltage is applied to the semiconductor device 2 becomes gentler, thereby mitigating the maximum electric field applied to the drift layer 30. Furthermore, since the width of the boss region 311 is reduced compared to the widths of the other boss regions 312-314, the potential difference between the peripheral trenches 61 and 62 is reduced, further mitigating the maximum electric field applied to the drift layer 30. As a result, the reliability of the semiconductor device 2 is further improved.

[0054] As an example, in the semiconductor device 1 of the first embodiment, with a drift layer 30 thickness of 15 μm, peripheral trenches 61 and 62 depth of 2 μm, p-type semiconductor components 71 and 72 made of NiO, anode electrode 40 made of Ni, and cathode electrode 50 made of a Ti / Au laminate, the maximum electric field strength applied to the drift layer 30 when a reverse voltage of 2000V is applied is 7.9 MV / cm, designed with Wt1 = Wt2 = 4 μm and Wm1 = 3 μm. In contrast, in the semiconductor device 1 of the second embodiment... In conductor device 2, with the drift layer 30 having a thickness of 15 μm, the outer peripheral trenches 61-65 having a depth of 2 μm, the p-type semiconductor components 71-75 being made of NiO, the anode electrode 40 being made of Ni, and the cathode electrode 50 being made of a Ti / Au laminate, the maximum electric field strength applied to the drift layer 30 when a reverse voltage of 2000V is applied is mitigated to 7.0 MV / cm when designed as Wt1=Wt2=Wt3=Wt4=Wt5=4μm, Wm1=1μm, and Wm2=Wm3=Wm4=4μm.

[0055] Figure 6 This is a schematic cross-sectional view used to illustrate the construction of a first modified example of semiconductor device 2. Figure 6 The first variant shown is... Figure 5 The difference in semiconductor device 2 shown in (b) is that: Figure 2 As in the first variation of semiconductor device 1 shown in (a), the peripheral trenches 61-65 are not completely embedded by p-type semiconductor components 71-75, but are only provided on the inner walls of the peripheral trenches 61-65. Even with this structure, the same effect as the semiconductor device 2 described above can be obtained.

[0056] Furthermore, in the semiconductor device 2 of the second embodiment, it is possible to... Figure 2 As in the second variation of the semiconductor device 1 shown in (b), the anode electrode 40 is embedded in the peripheral trench 61 via the p-type semiconductor member 71, which can be used as... Figure 2As in the third variation of the semiconductor device 1 shown in (c), p-type semiconductor members 71-75 are provided only on the bottom surface of the inner wall of the outer peripheral trenches 61-65 and at the corners that form the boundary between the bottom and side surfaces. Alternatively, as shown in [example], [further details are needed]. Figure 2 As in the fourth variation of the semiconductor device 1 shown in (d), the inner walls of the peripheral trenches 61-65 and a portion of the upper surface 31 of the drift layer 30 located nearby are covered by p-type semiconductor components 71-75, respectively.

[0057] Furthermore, in the semiconductor device 2 of the second embodiment, it is possible to... Figure 3 As in the fifth modification of the semiconductor device 1 shown in (a), the surfaces of the p-type semiconductor components 71-75 are covered by an insulating film 81, which allows for... Figure 3 As in the sixth modification of the semiconductor device 1 shown in (b), the anode electrode 40 is embedded in the peripheral trench 61 via the insulating film 81 and the p-type semiconductor component 71, and can be used as... Figure 3 As in the seventh modification of the semiconductor device 1 shown in (c), the outer peripheral trenches 61-65 are embedded by the insulating film 81 via p-type semiconductor components 71-75, and can also be as follows: Figure 3 As in the eighth variation of the semiconductor device 1 shown in (d), the upper surface 31 of the drift layer 30 exposed from the anode electrode 40 and the outer periphery of the anode electrode 40 are covered by an insulating film 81.

[0058] Furthermore, in the semiconductor device 2 of the second embodiment, it is possible to... Figure 4 As in the ninth modification of the semiconductor device 1 shown in (a), the outer peripheral trenches 61-65 are embedded by the insulating film 81 via p-type semiconductor components 71-75, and the upper surface 31 of the drift layer 30 exposed from the anode electrode 40 and the outer periphery of the anode electrode 40 are covered by an insulating film 82 different from the insulating film 81. Figure 4 As in the tenth variation of the semiconductor device 1 shown in (b), the surface of the p-type semiconductor components 71-75 is covered by an insulating film 81, and the anode electrode 40 is embedded in the peripheral trench 61 via the insulating film 81 and the p-type semiconductor components 71. The upper surface 31 of the drift layer 30 exposed from the anode electrode 40, the outer periphery of the anode electrode 40, and the interior of the peripheral trench 62-65 are covered by an insulating film 82 that is different from the insulating film 81.

[0059] Figure 7 This is a schematic cross-sectional view used to illustrate the construction of a second modified example of semiconductor device 2. Figure 7 The second variation shown is the same as Figure 5The difference in semiconductor device 2 shown in (b) is that Wm1 < Wm2 < Wm3 < Wm4. That is, the width of the outer peripheral protrusion region in two adjacent protrusion regions is wider than the width of the inner peripheral protrusion region. As a result, the potential difference between two adjacent outer peripheral trenches decreases towards the inner peripheral side, thus further mitigating the maximum electric field applied to the drift layer 30.

[0060] As an example, with a drift layer 30 thickness of 15 μm, outer peripheral trenches 61-65 depth of 2 μm, p-type semiconductor components 71-75 made of NiO, anode electrode 40 made of Ni, and cathode electrode 50 made of a Ti / Au laminate, the maximum electric field strength applied to the drift layer 30 when a reverse voltage of 2000V is applied, with the design Wt1=Wt2=Wt3=Wt4=Wt5=4μm, Wm1=1μm, Wm2=3μm, Wm3=4μm, and Wm4=5μm, is reduced to 6.3MV / cm. In the above example, the width of the outermost boss region 314 is larger than the width of the outer peripheral trenches 61-65. Furthermore, the width of the second outermost boss region 313 is the same as the width of the outer peripheral trenches 61-65. Thus, the innermost boss area 311 can be designed to be narrower than the outer peripheral grooves 61-65, and the outermost boss area 314 can be designed to be wider than the outer peripheral grooves 61-65.

[0061] Figure 8 This is a schematic cross-sectional view used to illustrate the structure of a third modified example of semiconductor device 2. Figure 8 The third variation shown is the same as Figure 7 The difference in the second variation of the semiconductor device 2 shown is that Wm1 < Wm2 < Wm3 ≦ Wm4 < Wt4. That is, the width of the outermost protrusion region 314 is narrower than the width of the outermost trench 64 adjacent to the outermost trench 65. Therefore, the maximum electric field applied to the drift layer 30 is further mitigated. Furthermore, in Figure 8 In the example shown, the width of the outer peripheral boss region in two adjacent boss regions is greater than the width of the inner peripheral boss region.

[0062] As an example, when the thickness of the drift layer 30 is 15 μm, the depth of the peripheral trenches 61-65 is 2 μm, the p-type semiconductor components 71-75 are made of NiO, the anode electrode 40 is made of Ni, and the cathode electrode 50 is made of a Ti / Au laminate, the maximum electric field strength applied to the drift layer 30 when a reverse voltage of 2000V is applied is reduced to 6.1 MV / cm when designed as Wt1=Wt2=Wt3=Wt4=Wt5=4μm, Wm1=1μm, Wm2=2μm, and Wm3=Wm4=3μm.

[0063] Figure 9 This is a schematic cross-sectional view used to illustrate the structure of the fourth modified example of semiconductor device 2. Figure 9 The fourth variation shown is the same as Figure 5 The difference in semiconductor device 2 shown in (b) is that Wt1 = Wt2 = Wt3 = Wt4 > Wt5. That is, the width of the outermost peripheral trench 65 is narrower than the width of the first peripheral trench 61. Therefore, it is possible to ensure... Figure 5 While achieving the same effect as the semiconductor device 2 shown in (b), it also miniaturizes the chip size. Furthermore, in Figure 9 In the example shown, the width of the peripheral groove on the outer periphery side of two adjacent peripheral grooves is narrower than the width of the peripheral groove on the inner periphery side, or the same as the width of the peripheral groove on the inner periphery side. That is, the width of the peripheral groove on the outer periphery side of two adjacent peripheral grooves is less than the width of the peripheral groove on the inner periphery side.

[0064] As an example, with a drift layer 30 thickness of 15 μm, peripheral trenches 61-65 depth of 2 μm, p-type semiconductor components 71-75 made of NiO, anode electrode 40 made of Ni, and cathode electrode 50 made of a Ti / Au laminate, the maximum electric field strength applied to the drift layer 30 when a reverse voltage of 2000V is applied, with the design parameters Wt1=Wt2=Wt3=Wt4=4μm, Wt5=3μm, Wm1=1μm, and Wm2=Wm3=Wm4=4μm, is 7.0 MV / cm. This is comparable to the result when Wt1=Wt2=Wt3=Wt4=Wt5=4μm. Figure 5 The semiconductor device 2 shown in (b) has the same effect.

[0065] Figure 10 This is a schematic cross-sectional view used to illustrate the structure of the fifth modified example of semiconductor device 2. Figure 10 The fifth variation shown is the same as Figure 5The difference in semiconductor device 2 shown in (b) is that Wt1 > Wt2 > Wt3 > Wt4 > Wt5. That is, the width of the outer peripheral trench on the outer peripheral side in two adjacent outer peripheral trenches is narrower than the width of the outer peripheral trench on the inner peripheral side. Therefore, it is possible to ensure... Figure 5 While achieving the same effect as the semiconductor device 2 shown in (b), it further miniaturizes the chip size.

[0066] As an example, with a drift layer 30 thickness of 15 μm, peripheral trenches 61-65 depth of 2 μm, p-type semiconductor components 71-75 made of NiO, anode electrode 40 made of Ni, and cathode electrode 50 made of a Ti / Au laminate, the maximum electric field strength applied to the drift layer 30 when a reverse voltage of 2000V is applied, with the following parameters: Wt1 = 4 μm, Wt2 = 3.5 μm, Wt3 = 3 μm, Wt4 = 2.5 μm, Wt5 = 2 μm, Wm1 = 1 μm, and Wm2 = Wm3 = Wm4 = 4 μm, is 7.0 MV / cm. This is comparable to the result when Wt1 = Wt2 = Wt3 = Wt4 = Wt5 = 4 μm. Figure 5 The semiconductor device 2 shown in (b) has the same effect.

[0067] <Third Implementation Method>

[0068] Figure 11 (a) is a schematic top view illustrating the structure of a semiconductor device 3 according to a third embodiment of the technology disclosed herein. Furthermore, Figure 11 (b) is along Figure 11 The approximate cross-sectional view of line AA shown in (a).

[0069] The semiconductor device 3 of the third embodiment differs from the semiconductor device 2 of the second embodiment in that a plurality of central trenches 90 are provided in the drift layer 30, and an anode electrode 40 is provided in the central trenches 90 via an insulating film 83. The other basic structures are the same as those of the semiconductor device 2 of the second embodiment; therefore, the same reference numerals are used for the same elements, and repeated descriptions are omitted.

[0070] Unlike the peripheral grooves 61-65, the multiple central grooves 90 all overlap with the anode electrode 40 when viewed from above. In contrast, at least a portion of the peripheral grooves 61-65 does not overlap with the anode electrode 40 when viewed from above. Specifically, for peripheral groove 61, a portion overlaps with the anode electrode 40 when viewed from above, while the remaining portion does not overlap with the anode electrode 40 when viewed from above; for peripheral grooves 62-65, all of them do not overlap with the anode electrode 40 when viewed from above.

[0071] The anode electrodes 40 disposed in the multiple central trenches 90 and the anode electrodes 40 disposed on the upper surface 31 of the drift layer 30 can be made of the same material or different materials. The depths of the multiple central trenches 90 and the peripheral trenches 61-65 can be the same or different. For example, the depths of the multiple central trenches 90 and the peripheral trenches 61-65 can all be set to approximately 2 μm.

[0072] The area sandwiched between two central trenches 90 in the upper surface 31 of the drift layer 30 forms a boss region 310. When a reverse voltage is applied between the anode electrode 40 and the cathode electrode 50, the boss region 310 becomes a depletion layer. As a result, the channel region of the drift layer 30 is interrupted, thus significantly suppressing leakage current when a reverse voltage is applied.

[0073] Thus, in the third embodiment, the semiconductor device 3 has multiple central trenches 90 at positions overlapping with the anode electrode 40 when viewed from above, thereby reducing leakage current. Furthermore, by providing multiple central trenches 90, the leakage current applied to the... Figure 11 The electric field strength at the bottom of the outer peripheral groove 61, represented by the symbol B in (b), is also reduced.

[0074] As an example, when the thickness of the drift layer 30 is 15 μm, the depth of the peripheral trenches 61-65 and the central trench 90 is 2 μm, the p-type semiconductor components 71-75 are made of NiO, the anode electrode 40 is made of Ni, and the cathode electrode 50 is made of a Ti / Au laminate, when a reverse voltage of 2000V is applied, the electric field strength applied to the bottom of the peripheral trench 61 (represented by the symbol B) is 6.1 MV / cm when the central trench 90 is absent, provided that Wt1=Wt2=Wt3=Wt4=Wt5=4μm, Wm1=1μm, Wm2=2μm, and Wm3=Wm4=3μm. In contrast, when multiple central trenches 90 are provided, the field strength is reduced to 4.7 MV / cm.

[0075] Furthermore, in the semiconductor device 1 of the first embodiment or the semiconductor device 2 of the second embodiment, a [further details can be provided]. Figure 11 (a) and Figure 11 The central trench 90 is shown in (b). That is, in the semiconductor device 1 of the first embodiment and the semiconductor device 2 of the second embodiment, a plurality of central trenches 90 may be provided in the drift layer 30, and an anode electrode 40 may be provided in the central trenches 90 via an insulating film 83.

[0076] Figure 12 This is a schematic cross-sectional view used to illustrate the construction of a modified example of semiconductor device 3. Figure 12 The variations shown are similar to Figure 11The difference in semiconductor device 3 shown in (b) is that a p-type semiconductor component 79 with a conductivity type opposite to that of the drift layer 30 is provided in multiple central trenches 90. The drift layer 30 and the p-type semiconductor component 79 form a pn junction. Accordingly, a so-called junction barrier Schottky diode is constructed. Furthermore, similar to semiconductor device 3, since the channel region between the boss regions 310 is clamped when a reverse voltage is applied between the anode electrode 40 and the cathode electrode 50, the leakage current when a reverse voltage is applied is significantly suppressed. Moreover, by providing p-type semiconductor components 79 in multiple central trenches 90, the leakage current when a reverse voltage is applied between the anode electrode 40 and the cathode electrode 50 is significantly suppressed. Figure 12 The electric field strength at the bottom of the outer peripheral groove 61, represented by the symbol B, decreases.

[0077] As an example, when the thickness of the drift layer 30 is 15 μm, the depth of the peripheral trenches 61-65 and the central trench 90 is 2 μm, the p-type semiconductor components 71-75 and 79 are made of NiO, the anode electrode 40 is made of Ni, and the cathode electrode 50 is made of a Ti / Au laminate, when a reverse voltage of 2000V is applied, the electric field strength applied to the bottom of the peripheral trench 61 (represented by the symbol B) is 6.1 MV / cm when there is no central trench 90, provided that Wt1=Wt2=Wt3=Wt4=Wt5=4μm, Wm1=1μm, Wm2=2μm, and Wm3=Wm4=3μm. In contrast, when multiple central trenches 90 with p-type semiconductor components 79 are provided, the field strength is reduced to 4.8 MV / cm.

[0078] Furthermore, in the semiconductor device 1 of the first embodiment or the semiconductor device 2 of the second embodiment, a [further details can be provided]. Figure 12 The central trench 90 is shown. That is, in the semiconductor device 1 of the first embodiment or the semiconductor device 2 of the second embodiment, a plurality of central trenches 90 may be provided in the drift layer 30, and a p-type semiconductor member 79 having a conductivity type opposite to that of the drift layer 30 may be provided in the central trenches 90.

[0079] The above describes the implementation of the technology disclosed herein. However, the technology disclosed herein is not limited to the above implementation. Various modifications can be made without departing from its spirit, and these modifications are of course included within the scope of the technology disclosed herein.

[0080] For example, in the embodiments described above, gallium oxide is used as the material for the semiconductor substrate 20 and the drift layer 30. However, the material for the semiconductor substrate 20 and the drift layer 30 is not limited to gallium oxide; materials such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), diamond (C), silicon (Si), germanium (Ge), silicon-germanium (SiGe), and gallium arsenide (GaAs) can be used. Even when using these materials as the materials for the semiconductor substrate 20 and the drift layer 30, the same effect can be obtained based on the same principle as when gallium oxide is used.

[0081] The technology disclosed herein includes the following configuration examples, but is not limited thereto.

[0082] A semiconductor device according to one aspect of this disclosure includes: a semiconductor substrate; a drift layer disposed on the semiconductor substrate; a first electrode in contact with the drift layer; and a second electrode in contact with the semiconductor substrate. The drift layer has: a plurality of peripheral trenches, including: a first peripheral trench disposed along its outer edge such that it overlaps with the outer edge of the first electrode when viewed from above; a second peripheral trench adjacent to the first peripheral trench and disposed outside the first peripheral trench such that it surrounds the first peripheral trench when viewed from above; and a first boss region located between the first peripheral trench and the second peripheral trench, the width of the first boss region being narrower than the width of the first peripheral trench. As a result, the electric field strength applied to the bottom of the first peripheral trench is mitigated.

[0083] In the aforementioned semiconductor device, the plurality of peripheral trenches may include an outermost peripheral trench located at the outermost periphery, and the drift layer may further have a second protrusion region located between the outermost peripheral trench and the peripheral trench adjacent to the outermost peripheral trench, wherein the width of the first protrusion region is narrower than the width of the second protrusion region. Accordingly, since the electric field gradient becomes gentler, the maximum electric field applied to the drift layer is mitigated.

[0084] In the aforementioned semiconductor device, the drift layer may have multiple protrusion regions including a first protrusion region and a second protrusion region, wherein the width of the protrusion region located on the outer peripheral side of two adjacent protrusion regions is greater than the width of the protrusion region located on the inner peripheral side. Accordingly, the potential difference between two adjacent outer peripheral trenches decreases towards the inner peripheral side, thus further mitigating the maximum electric field applied to the drift layer.

[0085] In the aforementioned semiconductor device, the width of the second protrusion region can be narrower than the width of the outermost peripheral trench adjacent to it. This further mitigates the maximum electric field applied to the drift layer.

[0086] In the aforementioned semiconductor device, the width of the outermost peripheral trench among a plurality of peripheral trenches can be narrower than the width of the first peripheral trench. This enables miniaturization of the chip size.

[0087] In the aforementioned semiconductor device, there may be a plurality of peripheral trenches, including at least three peripheral trenches, wherein the width of the peripheral trench located on the outer peripheral side in two adjacent peripheral trenches is less than or equal to the width of the peripheral trench located on the inner peripheral side. Accordingly, the chip size can be further miniaturized.

[0088] In the aforementioned semiconductor device, the drift layer may further have a plurality of central trenches disposed at positions overlapping with the first electrode when viewed from above, and the first electrode is disposed in the plurality of central trenches via an insulating film. Accordingly, the electric field intensity applied to the bottom of the first peripheral trench can be mitigated while the leakage current is reduced.

[0089] In the aforementioned semiconductor device, the drift layer may further have a plurality of central trenches disposed at positions overlapping with the first electrode when viewed from above, and semiconductor components having a conductivity type opposite to that of the drift layer are disposed in the plurality of central trenches. Accordingly, the electric field strength applied to the bottom of the first peripheral trench can be mitigated while reducing leakage current.

[0090] In the aforementioned semiconductor device, the first electrode can be an anode electrode, and the second electrode can be a cathode electrode. Accordingly, a diode can be constructed.

[0091] In the aforementioned semiconductor device, the first electrode may be in Schottky contact with the drift layer, and the second electrode may be in ohmic contact with the semiconductor substrate. Accordingly, a Schottky barrier diode can be constructed.

[0092] In the above-mentioned semiconductor device, it may be that: a plurality of peripheral trenches are provided with semiconductor components of the opposite conductivity type to the drift layer, the semiconductor component provided in the first peripheral trench is connected to the first electrode, and the semiconductor components provided in the peripheral trenches other than the first peripheral trench are not connected to the first electrode.

[0093] This application claims the benefit of Japanese Patent Application No. 2023-156320, filed on September 21, 2023, the entire disclosure of which is incorporated herein by reference.

[0094] Explanation of symbols

[0095] 1-3 Semiconductor devices

[0096] 20 Semiconductor substrates

[0097] 21. Top surface of semiconductor substrate

[0098] 22. Back side of semiconductor substrate

[0099] 30 Drift Layers

[0100] 31. Upper surface of the drift layer

[0101] 40 Anode electrode

[0102] 41. Outer edge of the anode electrode

[0103] 50 Cathode Electrode

[0104] 61-65 Peripheral grooves

[0105] 71-75, 79 p-type semiconductor components

[0106] 81-83 Insulating film

[0107] 90 Center Groove

[0108] 310-314 convex area.

Claims

1. A semiconductor device, characterized in that, have: Semiconductor substrate; A drift layer disposed on the semiconductor substrate; The first electrode in contact with the drift layer; and The second electrode that is in contact with the semiconductor substrate. The drift layer has: A plurality of peripheral grooves, comprising: a first peripheral groove disposed along the outer edge of the first electrode such that it overlaps with the outer edge of the first electrode in a top view; and a second peripheral groove adjacent to the first peripheral groove and disposed outside the first peripheral groove such that it surrounds the first peripheral groove in a top view; and The first boss area is located between the first peripheral groove and the second peripheral groove. The width of the first boss area is narrower than the width of the first peripheral groove.

2. The semiconductor device as claimed in claim 1, characterized in that, The plurality of peripheral grooves also includes the outermost peripheral groove located on the outermost periphery. The drift layer also has a second protrusion region located between the outermost peripheral groove and the peripheral groove adjacent to the outermost peripheral groove. The width of the first boss region is narrower than the width of the second boss region.

3. The semiconductor device as claimed in claim 2, characterized in that, The drift layer has multiple protrusion regions including the first protrusion region and the second protrusion region. In two adjacent boss regions, the width of the boss region located on the outer periphery is greater than the width of the boss region located on the inner periphery.

4. The semiconductor device as claimed in claim 2, characterized in that, The width of the second boss region is narrower than the width of the outermost peripheral groove adjacent to the outermost peripheral groove.

5. The semiconductor device as claimed in claim 1, characterized in that, The outermost peripheral groove among the plurality of peripheral grooves is narrower than the width of the first peripheral groove.

6. The semiconductor device as claimed in claim 5, characterized in that, The plurality of peripheral grooves includes at least three peripheral grooves. The width of the peripheral groove on the outer periphery side in two adjacent peripheral grooves is less than the width of the peripheral groove on the inner periphery side.

7. The semiconductor device as claimed in claim 1, characterized in that, The drift layer also has multiple central grooves disposed at positions that overlap with the first electrode when viewed from above. The first electrode is disposed in the plurality of central trenches via an insulating film.

8. The semiconductor device as claimed in claim 1, characterized in that, The drift layer also has multiple central grooves disposed at positions that overlap with the first electrode when viewed from above. Semiconductor components having a conductivity type opposite to that of the drift layer are provided in the plurality of central trenches.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The first electrode is the anode electrode, and the second electrode is the cathode electrode.

10. The semiconductor device as claimed in claim 9, characterized in that, The first electrode is in contact with the Schottky drift layer. The second electrode is in ohmic contact with the semiconductor substrate.

11. The semiconductor device as claimed in claim 1, characterized in that, Semiconductor components with a conductivity type opposite to that of the drift layer are disposed in the plurality of peripheral trenches. The semiconductor component disposed in the first peripheral trench is connected to the first electrode. The semiconductor component disposed in the peripheral trench other than the first peripheral trench among the plurality of peripheral trenches is not connected to the first electrode.

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