Chip retention time violation repairing method and device, electronic equipment and storage medium

Abstract

The invention provides a chip retention time violation repairing method and device, electronic equipment and a storage medium, and the method comprises the steps: building a delay scale factor of cross-process corner calculation based on the repairing unit delay information, and carrying out the statistical analysis of a retention time violation report, so as to locate a to-be-repaired time sequence node set; on this basis, calculating the minimum establishment time margin under the reference process corner and taking the minimum establishment time margin as a constraint condition, then selecting a repair unit combination to determine the actually increased delay under the bidirectional constraint of the retention time repair demand and the establishment time margin, and dynamically updating the margin and the violation measurement until the repair condition is met; and finally, an executable engineering change instruction file is generated, so that the consistency of multiple process corners is higher, the introduction of automatic retention time repair of newly established violations is avoided, the manual screening and repeated iteration cost is reduced, and the overall time sequence convergence efficiency and repair stability are improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design automation technology, and more specifically, to a method, apparatus, electronic device, and storage medium for chip hold-time violation repair. Background Technology

[0002] In the digital integrated circuit design flow, to ensure the correctness of data sampling by timing units such as flip-flops / latches, setup and hold time constraints must typically be met. A hold time violation occurs when, within a hold window after the clock's effective edge, the data path changes too rapidly, causing instability in the sampling unit within the hold window, thus leading to functional errors or potential metastability risks. With increasing process variations, larger chip sizes, and stricter verification requirements across voltage and temperature angles at advanced process nodes, locating and correcting hold time violations has become a crucial step in back-end timing closure.

[0003] Current hold-time correction methods typically involve inserting delays into the data path, such as inserting buffers, delay cells, or making engineering changes (ECOs) to the existing gate-level architecture. However, in practical engineering, hold-time correction and setup-time constraints are inherently coupled. Arbitrary delay insertions may introduce new setup-time violations on other paths, leading to repeated iterations of timing convergence and low efficiency. Furthermore, cell delays and timing margins vary significantly across different process corners of the chip, and traditional methods can easily result in insufficient or excessive correction, affecting timing margins. Summary of the Invention

[0004] This disclosure provides at least one chip hold-time violation repair method, apparatus, electronic device, and storage medium. It constructs a delay ratio factor calculated across process corners based on repair unit delay information, and performs statistical analysis on hold-time violation reports to locate the set of timing nodes to be repaired. Based on this, it calculates the minimum setup time margin under a baseline process corner and uses it as a constraint. Then, under the dual constraints of hold-time repair requirements and setup time margin, it selects a combination of repair units to determine the actual increase in delay, dynamically updates the margin and violation metric until the repair conditions are met, and finally generates an executable engineering change instruction file. This achieves more consistent hold-time repair across multiple process corners, avoids introducing new setup violations, reduces manual screening and iterative costs, and improves overall timing convergence efficiency and repair stability.

[0005] This disclosure provides a method for repairing chip hold-time violations, including: Obtain the repair unit delay information required for holding time repair, and determine the delay ratio factor required across process corners based on the repair unit delay information; Parse and statistically analyze hold-time violation reports to determine the set of time-series nodes to be repaired and their corresponding violation metrics. Obtain the setup time margin and calculate the minimum setup time margin under the reference process angle based on the delay ratio factor; For the set of time-series nodes, under the dual constraints of the hold-time repair requirement and the minimum setup time margin, a repair unit combination is selected to determine the actual increase in delay, and the setup time margin and hold-time violation metric are updated during the repair process until the preset repair conditions are met. Based on the repair results, generate an engineering change order document for repairing retention time violations.

[0006] In one optional implementation, the delay information of the repair unit required for holding time repair is obtained, and the delay ratio factor required for cross-process corner calculation is determined based on the delay information of the repair unit, specifically including: Extract the initial delay information of the buffer or delay unit used for time-repair from the process library; By combining the on-chip deviation data built into the process library, the initial delay information is corrected using the Gaussian distribution principle to eliminate systematic deviations; The delay ratio factor is obtained by fitting the delay ratio of multiple process corners based on the corrected delay information.

[0007] In one optional implementation, the hold-time violation reports are parsed and statistically analyzed to determine the set of time-series nodes to be repaired and their corresponding violation metrics, specifically including: Extract the path identifier, timing node identifier, and violation value from the hold-time violation report; Statistical analysis of time-series nodes is performed to obtain the number of occurrences, maximum violation value, and cumulative violation value; Generate an EDA script file for obtaining setup time margin; The extraction results of the time-keeping violation report are integrated with the statistical results of the time-series nodes to generate a traversal data table containing the path identifier, the time-series node identifier, the violation value, the occurrence count, the maximum violation value, and the cumulative violation value.

[0008] In one optional implementation, obtaining the setup time margin and calculating the minimum setup time margin under the reference process angle based on the delay ratio factor specifically includes: Using the EDA script file, obtain the establishment time margin of each of the time-series nodes under at least one signature establishment angle; The set-up time margin is converted to a reference process angle based on the delay ratio factor, and the minimum value of the conversion result is taken as the minimum set-up time margin.

[0009] In one optional implementation, under the dual constraints of the hold-up time repair requirement and the minimum setup time margin, a combination of repair units is selected to determine the actual increase in delay, specifically including: Within the current path, time-series nodes are sorted according to their occurrence frequency or cumulative violation value to determine repair priority; The delay value that can be increased is calculated for the current time sequence node. The delay value that can be increased is determined by the current hold time repair requirement and the minimum setup time margin. Based on the principle of proximity priority, a combination of repair units is selected from the repair units so that the actual increase in delay is close to the increase in delay value.

[0010] In one optional implementation, the setup time margin and hold time violation metric are updated during the repair process until a preset repair condition is met, specifically including: Record the timing nodes and the corresponding actual increased delay, and update the minimum setup time margin based on the actual increased delay; After updating the minimum setup time margin, the next time-series node on the same path continues to be processed to calculate the increase in delay value and update the minimum setup time margin based on the actual increase in delay, until the hold time violation metric meets the preset repair condition or the path traversal ends.

[0011] In one optional implementation, an engineering change order file for fixing retention time violations is generated based on the repair results, specifically including: The updated timing nodes and corresponding repair unit combination information are converted into engineering change instructions that can be executed by the EDA tool to generate the engineering change instruction file.

[0012] This disclosure also provides a chip hold-time violation repair device, including: The delay information processing module is used to acquire the repair unit delay information required for holding time repair, and determine the delay ratio factor required for cross-process corner calculation based on the repair unit delay information; The violation report parsing module is used to parse hold time violation reports and perform statistical analysis to determine the set of time-series nodes to be repaired and their corresponding violation measurement information; The time margin calculation module is used to obtain the setup time margin and calculate the minimum setup time margin under the reference process angle based on the delay ratio factor. The timing path repair module is used to select a combination of repair units to determine the actual increase in delay for the set of timing nodes under the bidirectional constraints of the hold-time repair requirement and the minimum setup time margin, and to update the setup time margin and hold-time violation metric during the repair process until the preset repair conditions are met. The file generation module is used to generate engineering change instruction files for fixing retention time violations based on the repair results.

[0013] This disclosure also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they perform steps of the above-described chip hold-time violation repair method, or any possible implementation of the above-described chip hold-time violation repair method.

[0014] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the above-described chip hold-time violation repair method, or any possible implementation thereof.

[0015] This disclosure also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implements the above-described chip hold-time violation repair method, or the steps in any possible implementation of the above-described chip hold-time violation repair method.

[0016] This disclosure provides a chip hold-time violation repair method, apparatus, electronic device, and storage medium. It constructs a delay ratio factor calculated across process corners based on repair unit delay information, and performs statistical analysis on hold-time violation reports to locate the set of timing nodes to be repaired. Based on this, it calculates the minimum setup time margin under a baseline process corner and uses it as a constraint. Then, under the dual constraints of hold-time repair requirements and setup time margin, it selects a combination of repair units to determine the actual increase in delay, dynamically updates the margin and violation metric until the repair conditions are met, and finally generates an executable engineering change instruction file. This achieves more consistent hold-time repair across multiple process corners, avoids introducing new setup violations, reduces manual screening and iterative costs, and improves overall timing convergence efficiency and repair stability.

[0017] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to this disclosure and, together with the specification, serve to explain the technical solutions of this disclosure. It should be understood that the following drawings only show some embodiments of this disclosure and should not be considered as limiting the scope. Those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0019] Figure 1 A flowchart of a chip hold-time violation repair method provided by an embodiment of this disclosure is shown; Figure 2 A flowchart of another chip hold-time violation repair method provided by an embodiment of this disclosure is shown; Figure 3 A schematic diagram of a chip hold-time violation repair apparatus provided in an embodiment of this disclosure is shown; Figure 4 A schematic diagram of an electronic device provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0022] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0023] Research has revealed that existing hold-time correction methods typically involve inserting delays into the data path, such as inserting buffers, delay cells, or making engineering changes (ECOs) to the existing gate-level architecture. However, in practical engineering, hold-time correction and setup-time constraints are inherently coupled. Arbitrary delay insertions may introduce new setup-time violations on other paths, leading to repeated iterations of timing convergence and low efficiency. Furthermore, cell delays and timing margins vary significantly across different process corners, making traditional methods prone to under-correction or over-correction, thus affecting timing margins.

[0024] Based on the above research, this disclosure provides a chip hold time violation repair method, apparatus, electronic device, and storage medium. It constructs a delay ratio factor calculated across process corners based on the delay information of the repair units, and performs statistical analysis on hold time violation reports to locate the set of timing nodes to be repaired. Based on this, it calculates the minimum setup time margin under the baseline process corner and uses it as a constraint. Then, under the dual constraints of hold time repair requirements and setup time margin, it selects a combination of repair units to determine the actual increase in delay, dynamically updates the margin and violation metric until the repair conditions are met, and finally generates an executable engineering change instruction file. This achieves more consistent hold time repair across multiple process corners, avoids introducing new setup violations, reduces manual screening and iterative costs, and improves overall timing convergence efficiency and repair stability.

[0025] To facilitate understanding of this embodiment, a detailed description of the chip hold-time violation repair method disclosed in this disclosure is provided first. The execution entity of the chip hold-time violation repair method provided in this disclosure is generally a computer device with certain computing capabilities. This computer device may include, for example, a terminal device, a server, or other processing devices. The terminal device may be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. In some possible implementations, the chip hold-time violation repair method can be implemented by the processor calling computer-readable instructions stored in memory.

[0026] See Figure 1 The diagram shows a flowchart of a chip hold-time violation repair method provided in this embodiment of the present disclosure. The method includes steps S101 to S105, wherein: S101. Obtain the repair unit delay information required for holding time repair, and determine the delay ratio factor required for cross-process angle calculation based on the repair unit delay information.

[0027] In practical implementation, in order to achieve cross-process corner estimation of time margin without having to repeatedly build a complete timing environment for each process corner, this invention first structurally acquires and statistically corrects the delay information of commonly used repair units for hold-time repair, and constructs the delay scaling factor (also known as process corner scaling factor) required for cross-process corner estimation based on this. The repair unit may include buffers, delay cells, etc., used for hold-time repair.

[0028] Specifically, regarding delay information acquisition, this invention can extract a set of repair units related to hold-time repair from a process library (e.g., timing library files of a standard cell library) and read the initial delay information of each repair unit under multiple process corners. The initial delay information can be the key timing arc delay parameters of the repair unit, including but not limited to: rise / fall delay, lookup table delay values ​​under different input conversion rates and different output load conditions, or representative delay values ​​corresponding to the target repair scenario (e.g., using the delay corresponding to typical input conversion / typical load as a representative value).

[0029] The above method ensures that subsequent cross-process angle calculations are based on the same repair unit and the same type of delay aperture, avoiding proportional distortion caused by inconsistent apertures.

[0030] Furthermore, considering that on-chip variation (OCV) in advanced processes can introduce systematic pessimism, and that the degree of pessimism may not be consistent across different process corners, this invention, after extracting the initial delay information, further combines the on-chip variation data built into the process library to perform statistical correction processing on the initial delay information.

[0031] Specifically, the delay samples can be corrected based on the Gaussian distribution principle to eliminate or reduce systematic biases under pessimistic scenarios, making the obtained delay information closer to the statistically equivalent delay that can be used for estimation. For example, the given bias parameters in the library can be mapped to the mean / variance or confidence interval of the delay distribution, and the original delay values ​​can be corrected accordingly to obtain the corrected delay information. Through this correction step, the cross-process angle scaling factor is no longer directly and strongly influenced by the single-angle pessimistic configuration, thereby improving the stability and consistency of the estimation.

[0032] Here, in determining the delay ratio factor, the present invention fits the delay ratio between multiple process corners based on the corrected delay information, thereby obtaining the delay ratio factor required for cross-process corner calculation.

[0033] Specifically, a baseline process angle (e.g., corner1) can be pre-selected as a unified calculation benchmark, and the scaling relationship between the baseline process angle and the remaining process angles (corner2…cornerN) can be calculated separately. As one implementation method, the correction delay of each repair unit under different process angles can be compared to obtain the unit-level ratio. Then, the set of repair units can be statistically summarized (e.g., by taking the mean, weighted mean, or robust statistics) to obtain the scaling factor of that process angle relative to the baseline process angle.

[0034] One implementation method is to simplify and fit the relationship between delay and process angle, directly outputting the mapping ratio from each process angle to the reference process angle. Regardless of the fitting method used, the delay ratio factor can characterize the scaling law of the repair unit delay as the process angle changes between different process angles, which can be used later when converting the establishment time margin from non-reference process angles to the reference process angle.

[0035] Optionally, to improve the generalization ability of the scaling factor, the present invention can also perform quality control on the extracted delay samples, such as removing outlier samples, fitting scaling factors according to the type of repair unit (buffer type, delay cell type), or weighting the samples according to the frequency of use of the repair unit in the target design, so that the obtained scaling factor is more consistent with the real repair scenario.

[0036] S102. Analyze the hold-time violation reports and perform statistical analysis to determine the set of time-series nodes to be repaired and their corresponding violation measurement information.

[0037] In practical implementation, to quickly locate the time-series nodes that contribute the most to repair and are most worthy of priority processing among a large number of time-keeping violation paths, this invention performs parsing and statistical analysis on the time-keeping violation reports, structuring the scattered information in the reports into a traversable dataset, thereby obtaining a set of time-series nodes to be repaired and their corresponding violation measurement information. The violation measurement information may include at least: the violation value (slack) at the single-path level, and the occurrence count (#path), maximum violation value (wns), and cumulative violation value (tns) at the node level, for subsequent traversal sorting and repair decisions.

[0038] Specifically, the hold-time violation reports are first parsed to extract the path ID, timing point, and violation value (slack) for each hold-time violation path. In implementation, the text can be scanned line by line and segmented based on fixed fields, delimiters, or keywords in the EDA tool's report format. For different tools or report templates, rule-based regular expression matching can also be used to extract the above information.

[0039] This parsing step transforms the original report from text output that cannot be directly statistically analyzed into structured records, and generates a first table for subsequent statistical processing. The record granularity of this first table is preferably at the path-node level, that is, each record is associated with at least one path ID, one timing point, and a corresponding slack.

[0040] After obtaining the first table, this invention further aggregates and statistically analyzes the time-series node dimensions to form violation measurement information at the node level. Specifically, this includes: counting the number of times each time-series node appears in all violation paths (#path), which reflects the coverage breadth of the node in the violation set; counting the maximum violation value (wns) corresponding to the time-series node, which reflects the most severe hold time risk in the relevant paths of the node; and counting the cumulative violation value (tns) corresponding to the time-series node, which reflects the degree of contribution of the node to the total number of violations.

[0041] Here, a second table is generated based on the above statistical results, so that each timing point is associated with its node-level metrics such as #path, wns, and tns, providing a quantitative basis for determining the repair priority and calculating the repair strategy.

[0042] Meanwhile, in order to automate the acquisition of setup time margins in subsequent steps, this invention also generates a script file (such as a tcl file or other tool command file) for execution by EDA tools during the generation of the second table. This script file is used to batch query or export the setup time margins of the timing node set under a specified process corner.

[0043] Furthermore, to unify the violation values ​​at the path level and the statistical metrics at the node level into the same traversal data structure, this invention integrates the extraction results of the first table with the statistical results of the second table to form a third table for subsequent traversal repair. The third table may contain at least the fields "path id, timing point, slack, wns, tns, #path", where slack characterizes the current hold-time violation severity of a specific path, and wns, tns, and #path characterize the node-level importance and global impact of the timing point. This allows the subsequent repair process to address both individual path compliance and prioritize the repair of bottleneck nodes that are more critical to global convergence.

[0044] S103. Obtain the setup time margin and calculate the minimum setup time margin under the reference process angle based on the delay ratio factor.

[0045] In specific implementation, in order to avoid introducing new setup time violations due to insertion delay during the time-maintenance repair process, after determining the set of timing nodes to be repaired, this invention further obtains the setup time slack of the timing nodes at at least one process angle, and combines it with the aforementioned determined delay ratio factor to uniformly convert the setup time slack to the reference process angle, thereby obtaining the minimum setup time slack under the reference process angle.

[0046] Here, the minimum setup time margin serves as a key constraint boundary for subsequent selection of combinations of delay calculation and repair units, limiting the upper limit of the delay increase for time-maintaining repair and reducing the risk of setup time being compromised.

[0047] Specifically, the present invention utilizes the aforementioned generated EDA script file to perform batch queries on the timing node set to obtain the setup time margin of each timing node at at least one process corner.

[0048] Here, the process angle can be one of the typical angle, the slowest angle, the worst-case setup angle, or the approval angle specified in the design process; the query object is preferably a timing node related to the hold time repair (e.g., a critical capture end or intermediate node on the violation path) so that subsequent constraint calculations can directly cover the actual repair location.

[0049] In this way, by using a scripted batch query method, the time slack can be output in the form of structured data (such as tables or database records) and correspond one-to-one with the time sequence node identifier, avoiding the inefficiency and inconsistency caused by manual querying.

[0050] Furthermore, after obtaining the setup time margin under the non-reference process angle, the present invention further performs cross-process angle conversion on the setup time margin based on the delay ratio factor to estimate the equivalent setup time margin under the reference process angle.

[0051] Specifically, for a non-reference process angle, the delay ratio factor of the process angle relative to the reference process angle is read, and the setup time margin obtained under the process angle is mapped to the reference process angle according to the preset conversion rule.

[0052] For example, in one implementation, the setup time margin can be considered as an acceptable space for increased latency, and scaled according to a scale consistent with the changes in data path latency, thereby obtaining the estimated setup time margin of the node under the baseline process angle. Through this conversion, the margin data from different process angles have a unified scale, which facilitates subsequent constraint comparisons and decisions based on the same benchmark.

[0053] It should be noted that, to ensure the safety of subsequent repair strategies across multiple process corners, this invention takes the minimum setup time margin calculated to the baseline process corner as the minimum setup time margin under the baseline process corner. In other words, when the time sequence node set obtains setup time margins in multiple non-baseline process corners, conversions can be performed separately, and the minimum value can be taken in the node dimension or path dimension to obtain the most conservative constraint boundary that best reflects the setup time bottleneck; when setup time margins are obtained only in one non-baseline process corner, the converted margin is directly used as a candidate value, and the minimum value within the set is taken as the minimum setup time margin for the global or current path.

[0054] In this way, by taking the minimum after conversion, the present invention introduces the establishment time constraint into the hold-time repair process in the form of a quantifiable boundary, so that the decision on the insertion of repair units and the increase of delay is always controlled by the establishment time safety margin.

[0055] Optionally, to enhance the stability of the calculation results, the present invention may also introduce tolerance or safety factors in the conversion and minimum process. For example, the preset margin may be further deducted from the converted setup time margin to resist fluctuations caused by model errors, changes in wire network delay, or subsequent optimization; or the minimum setup time margin may be maintained for different types of time-series nodes to achieve more refined constraint control.

[0056] By obtaining the setup time margin and calculating the minimum setup time margin of the reference process angle, this invention provides a clear and directly calculable upper bound condition for the selection of repair unit combinations under the bidirectional constraint of setup time constraint for subsequent hold time repair requirements, thereby improving the success rate and first-time convergence efficiency of hold time repair.

[0057] S104. For the set of time-series nodes, under the dual constraints of the hold-time repair requirement and the minimum setup time margin, select a combination of repair units to determine the actual increase in delay, and update the setup time margin and hold-time violation metric during the repair process until the preset repair conditions are met.

[0058] In practical implementation, after obtaining the set of timing nodes to be repaired, the corresponding hold time violation metric information, and the minimum setup time margin under the baseline process angle, this invention selects a combination of repair units for each location to be repaired under the bidirectional constraints of hold time repair requirements and the minimum setup time margin, determines the actual increase in delay, and continuously updates the setup time margin and hold time violation metric during the repair process. This process enables the hold time repair to be optimized by controlled delay increase within the setup time safety boundary, thereby reducing the risk of introducing new setup time violations and improving the first convergence rate.

[0059] In practice, based on the aforementioned statistical analysis results, a traversal order is first established along both the time-keeping violation path and time-series node dimensions. As an optional implementation, nodes within the current time-keeping violation path can be sorted according to the frequency of occurrence or cumulative violation value to determine the repair priority.

[0060] Here, the occurrence count reflects the coverage of a node across multiple violation paths, while the cumulative violation value reflects the node's contribution to the total number of global violations. By prioritizing the repair of nodes with high coverage or high contribution, the scale of violations can be reduced more quickly under the same repair budget, and ineffective iterations can be reduced.

[0061] In terms of traversal granularity, the present invention can repair each path one by one by traversing the nodes within the path, or repair the key global nodes first by traversing the nodes globally. In a preferred implementation, the path with the most serious violation or the largest cumulative violation can be selected as the current path in the path dimension, and then repair can be attempted in sequence according to the node priority in the path, so as to balance the achievement of single path and the overall convergence efficiency.

[0062] Furthermore, after determining the current timing node to be repaired, this invention calculates the increaseable delay value at that node as the target constraint range for selecting the repair unit combination. The increaseable delay value is subject to at least two types of constraints simultaneously: one is the hold time repair requirement, which is the minimum increase delay requirement required to make the current hold time violation metric meet a preset threshold; the other is the setup time constraint, which is the maximum increaseable delay space limited by the minimum setup time margin under the reference process angle.

[0063] In other words, the minimum amount of time required to fix the hold-up time violation and the maximum amount allowed to be added to the minimum setup time margin together constitute a two-way constraint boundary, ensuring that subsequent decisions can effectively fix hold-up time violations without exceeding the setup time safety margin.

[0064] In one implementation, the allowable delay can be set to an upper bound that does not exceed the minimum setup time margin, and a lower bound that meets the maintenance time repair requirements. When the lower bound is greater than the upper bound, it can be determined that the repair at that node cannot be completed under the current constraints, and then switch to the next node in the path or adjust the repair strategy (e.g., select different repair positions, change the repair unit granularity, etc.) to avoid meaningless over-insertion.

[0065] Furthermore, after obtaining the potential increase in delay value, the present invention selects a combination of repair units from the set of repair units to determine the actual increase in delay. The combination of repair units can be a single repair unit or a series combination of multiple repair units; for each candidate combination, it can be evaluated based on the degree of matching between its equivalent increase in delay at the reference process angle (or the equivalent increase in delay converted by the delay scaling factor) and the potential increase in delay.

[0066] As a preferred strategy, this invention adopts the proximity priority principle: under the premise of not exceeding the upper bound of the setup time, priority is given to selecting the combination of repair units that makes the actual increase in delay closest to the value of the increase in delay, thereby achieving the hold-time repair target with the fewest possible number of unit insertions and reducing disturbances to other timing paths. For cases with multiple equivalent candidates, additional criteria can be introduced for selection, such as prioritizing combinations with fewer units, prioritizing combinations with lower power consumption / area overhead, or prioritizing combinations with less wiring impact, to improve engineering feasibility.

[0067] Here, after executing a repair decision, the invention does not stop, but enters the measurement update and iteration phase to form a closed-loop repair. Specifically, this includes: updating the minimum setup time margin based on the actual increase in delay of the current node, that is, subtracting the introduced increase in delay from the available setup time margin to obtain the updated setup time safety boundary; at the same time, updating the hold-time violation metric of the current path based on the actual increase in delay to reflect the improvement effect of the repair action on the degree of violation.

[0068] After the update is completed, the present invention continues to perform an iterative process of calculating the increase in delay, selecting the combination of repair units, determining the actual increase in delay, and updating the metric for the next timing node on the same path, until the preset repair conditions are met or the path traversal ends. The preset repair conditions may include, but are not limited to: the current path hold-time violation metric reaching a preset threshold (e.g., slack is no longer negative or not less than the target threshold), the current path having no repairable nodes, or the global violation metric (e.g., global WNS / TNS) reaching the target range. If the preset repair conditions are not met at the end of the path traversal, a corresponding prompt message can be output or the path can be marked as an abnormal path requiring further engineering processing, so that higher-level strategies (e.g., adjusting constraints, modifying the logical structure, or rearranging the routing) can be used for subsequent processing.

[0069] As one possible implementation method, see Figure 2 The diagram shows a flowchart of a chip hold-time violation repair method provided in this embodiment of the present disclosure. The method includes steps S1041 to S1045, wherein: S1041. Sort the time sequence nodes in the current path according to the number of occurrences or the cumulative violation value to determine the repair priority.

[0070] S1042. Calculate the possible increase delay value for the current timing node. The possible increase delay value is determined by the current hold time repair requirement and the minimum setup time margin.

[0071] S1043. Select a combination of repair units from the repair units according to the principle of proximity priority, so that the actual increase in delay is close to the increase in delay value.

[0072] S1044. Record the timing nodes and the corresponding actual increased delay, and update the minimum setup time margin based on the actual increased delay.

[0073] S1045. After updating the minimum setup time margin, continue to perform the step of calculating the increaseable delay value to update the minimum setup time margin based on the actual increase in delay for the next time sequence node of the same path, until the hold time violation metric meets the preset repair condition or the path traversal ends.

[0074] In this embodiment, in order to achieve efficient and controllable repair within a single hold-time violation path, the present invention determines the repair priority according to statistical indicators within the path, and calculates the possible increase in delay under the bidirectional constraint of hold-time repair requirement and minimum setup time margin. Then, based on the proximity priority principle, the repair unit combination is selected to determine the actual increase in delay. Subsequently, the repair decision is solidified and recorded, and the minimum setup time margin is dynamically updated with the actual increase in delay to ensure that the repair of subsequent nodes is always within the setup time safety boundary until the path meets the standard or the traversal is completed.

[0075] First, within the current time violation path, all time-series nodes associated with that path are extracted. These time-series nodes are then sorted based on their occurrence count or cumulative violation value in the global violation set to determine repair priority. The occurrence count reflects the number of violation paths covered by the node, while the cumulative violation value reflects the node's contribution to the total number of violations; higher occurrence counts or larger cumulative violation values ​​result in higher priority.

[0076] After determining the current highest priority timing node, this invention calculates the possible increase in delay value for that current timing node. The possible increase in delay value is constrained by two directions: on the one hand, the hold time repair requirement is determined based on the current hold time violation metric to obtain the amount of delay increase required to make the violation meet a preset threshold; on the other hand, the maximum allowable increase in delay space is limited by using the minimum setup time margin under the reference process angle as the upper bound.

[0077] After obtaining the potential increase in delay value, this invention selects a combination of repair units from the set of repair units based on the principle of proximity priority, so that the actual increase in delay is as close as possible to the potential increase in delay value. Specifically, candidate units and their combinations in the set of repair units can be enumerated or retrieved, and the equivalent increase in delay corresponding to each candidate combination can be calculated. Under the premise of not exceeding the minimum setup time margin, the candidate combination with the smallest deviation from the potential increase in delay value is selected as the target repair unit combination.

[0078] After determining the combination of repair units, this invention records the timing nodes and the corresponding actual increased delays, and updates the minimum setup time margin based on the actual increased delays. The update method can be to include the actual increased delays in the setup time margin consumption, thereby obtaining the updated minimum setup time margin. This ensures that subsequent calculations of the increase in delay for other timing nodes within the same path can reflect the impact of the performed repair actions on the setup time safety boundary.

[0079] After updating the minimum setup time margin, the present invention continues to execute the above process on the next time-series node of the same path until the hold-time violation metric meets the preset repair condition or the path traversal ends. The preset repair condition can be set to the current path hold-time violation metric reaching a target threshold (e.g., hold-time slack is not less than zero or not less than a preset safety margin), or set to stop when traversing to the end of the path and still unable to continue adding delay within the setup time constraint, and output the corresponding non-compliance flag for subsequent processing using other strategies.

[0080] S105. Generate an engineering change order document for maintaining time violation repair based on the repair results.

[0081] In specific implementation, the present invention further converts the repair results into an Engineering Change Order (ECO) file that can be directly executed by EDA tools, so that the hold-time violation repair can be implemented in the gate-level netlist and physical implementation.

[0082] Specifically, the present invention first structures the repair results to form a repair list for ECO generation. The repair list includes at least: the target timing node identifier (e.g., gate / flip-flop pin / network name), the corresponding repair unit type and instance information (e.g., the inserted buffer or delay unit model), the number or combination structure of repair units, and the target value or equivalent delay value for the actual increase in delay.

[0083] Subsequently, the present invention generates engineering change instructions based on the repair list, the engineering change instructions conforming to the syntax and execution constraints of the target EDA tool. As one implementation, a set of instructions for logical-level ECO can be generated, including but not limited to: inserting repair unit instances on a specified network, disconnecting the original connection and reconnecting to a new network, setting the attributes of the newly added instances (such as library unit type, drive capability, naming rules), etc. As another implementation, physical ECO instructions recognizable during the placement and routing phase can also be generated simultaneously to guide the tool in incremental placement, validation, and incremental routing, ensuring that the newly added repair units can be physically implemented and meet design rules.

[0084] The above scheme will now be described in conjunction with specific implementation methods.

[0085] First, the initial delay information of cells commonly used for repairing hold time (such as buffers and delay cells) in the process library is extracted. Combined with on-chip offset data built into the process library, the delay is corrected using the Gaussian distribution principle (eliminating systematic biases in pessimistic scenarios). Based on the extracted delay information, a simple scale factor for delays across multiple process corners is fitted, which is used to subsequently establish time margins for cross-process corner calculations.

[0086] Next, the time violation reports are parsed to extract the path ID, timing point, and violation value (slack), generating the first table for subsequent statistics. The occurrence count (#path), maximum violation value (wns), and cumulative violation value (tns) of each timing point are calculated, generating the second table. An EDAtcl (toolcommandlanguage) file is also generated to obtain the setup time margin. The data from the two tables are then integrated to form a third table containing "pathid, timing point, slack, wns, tns, #path" (for subsequent traversal).

[0087] Next, using the setup time margin file, the setup time margin for each timing node at at least one process corner (corner2…N) is obtained. Based on the delay scaling factor, the minimum margin for the baseline process corner (corner1) is calculated using the formula: Vcorner1_margin = min(Vcorner2_margin * Scorner1_factor / Scorner2_factor, …, VcornerN_margin * Scorner1_factor / ScornerN_factor). Where Vcorner1_margin represents the minimum setup time margin at the baseline process corner; Vcornereri_margin represents the setup time margin at the i-th process corner (cornereri); and Scornereri_factor represents the delay scaling factor at the i-th process corner (cornereri).

[0088] Furthermore, within the current timing path, timing nodes are sorted by their occurrence count (#path) or cumulative violation value (tns) and analyzed sequentially. The delay value that can be added to the timing node is calculated as min(abs(wns), Vcorner1_margin) (a two-way constraint to avoid new violations). Repair unit combinations are selected according to the "proximity priority" principle, and the actual added delay (real_add_delay) is calculated. The timing node, actual added delay value, and setup time margin (Vcorner1_margin – real_add_delay), repair unit combinations, and other information are recorded. The path repair is checked to see if it meets the criteria (slack – real_add_delay > 0): if it does, proceed to the next path; otherwise, continue iterating. If it still doesn't meet the criteria after traversing all timing nodes, a prompt message is output. Before analyzing the next path, the delay and setup time margin of the added timing nodes are updated, and the violation value of the timing path is updated. If it meets the criteria, it is skipped directly; otherwise, the above process is repeated.

[0089] Finally, based on the timing path traversal and repair, an Engineering Change File (ECO) for maintaining timing violations is generated in the EDA tool format.

[0090] This disclosure provides a chip hold-time violation repair method. It constructs a delay ratio factor calculated across process corners based on repair unit delay information, and performs statistical analysis on hold-time violation reports to locate the set of timing nodes to be repaired. Based on this, it calculates the minimum setup time margin under a baseline process corner and uses it as a constraint. Then, under the dual constraints of hold-time repair requirements and setup time margin, it selects a combination of repair units to determine the actual increase in delay, dynamically updates the margin and violation metric until the repair conditions are met, and finally generates an executable engineering change instruction file. This achieves more consistent hold-time repair across multiple process corners, avoids introducing new setup violations, reduces manual screening and iterative costs, and improves overall timing convergence efficiency and repair stability.

[0091] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0092] Based on the same inventive concept, this disclosure also provides a chip hold time violation repair device corresponding to the chip hold time violation repair method. Since the principle of the device in this disclosure for solving the problem is similar to the chip hold time violation repair method described above in this disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0093] Please see Figure 3, Figure 3 This is a schematic diagram of a chip hold-time violation repair device provided in an embodiment of this disclosure. Figure 3 As shown in the figure, the chip hold time violation repair apparatus 300 provided in this embodiment includes: The delay information processing module 310 is used to obtain the repair unit delay information required for holding time repair, and to determine the delay ratio factor required for cross-process angle calculation based on the repair unit delay information.

[0094] The violation report parsing module 320 is used to parse hold time violation reports and perform statistical analysis to determine the set of time-series nodes to be repaired and their corresponding violation measurement information.

[0095] The time margin calculation module 330 is used to obtain the setup time margin and calculate the minimum setup time margin under the reference process angle based on the delay ratio factor.

[0096] The timing path repair module 340 is used to select a combination of repair units to determine the actual increase in delay for the set of timing nodes under the bidirectional constraints of the hold-time repair requirement and the minimum setup time margin, and to update the setup time margin and hold-time violation metric during the repair process until the preset repair conditions are met.

[0097] The document generation module 350 is used to generate an engineering change instruction file for fixing retention time violations based on the repair results.

[0098] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0099] This disclosure provides a chip hold time violation repair device. It constructs a delay ratio factor calculated across process corners based on repair unit delay information, and performs statistical analysis on hold time violation reports to locate the set of timing nodes to be repaired. Based on this, it calculates the minimum setup time margin under a baseline process corner and uses it as a constraint. Then, under the dual constraints of hold time repair requirements and setup time margin, it selects a combination of repair units to determine the actual increase in delay, dynamically updates the margin and violation metric until the repair conditions are met, and finally generates an executable engineering change instruction file. This achieves more consistent hold time repair across multiple process corners, avoids introducing new setup violations, reduces manual screening and iterative costs, and improves overall timing convergence efficiency and repair stability.

[0100] Corresponding to Figure 1 and Figure 2 In addition to the chip hold-time violation repair method, this disclosure also provides an electronic device 400, such as... Figure 4The diagram shown is a structural schematic of an electronic device 400 provided in an embodiment of this disclosure, including: Processor 41, memory 42, and bus 43; memory 42 is used to store execution instructions, including main memory 421 and external memory 422; the main memory 421, also called internal memory, is used to temporarily store the computational data in processor 41, as well as the data exchanged with external memory 422 such as hard disk. Processor 41 exchanges data with external memory 422 through main memory 421. When the electronic device 400 is running, processor 41 and memory 42 communicate through bus 43, enabling processor 41 to execute... Figure 1 and Figure 2 The steps for fixing chip hold-time violations.

[0101] This disclosure also provides a computer-readable storage medium storing a computer program. When executed by a processor, the computer program performs the steps of the chip hold-time violation repair method described in the above-described method embodiments. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0102] This disclosure also provides a computer program product, which includes computer instructions. When the computer instructions are executed by a processor, they can perform the steps of the chip hold-time violation repair method described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0103] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0104] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this disclosure, it should be understood that the disclosed device and method can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0105] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0106] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0107] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0108] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A method for repairing chip hold-time violations, characterized in that, include: Obtain the repair unit delay information required for holding time repair, and determine the delay ratio factor required across process corners based on the repair unit delay information; Parse and statistically analyze hold-time violation reports to determine the set of time-series nodes to be repaired and their corresponding violation metrics. Obtain the setup time margin and calculate the minimum setup time margin under the reference process angle based on the delay ratio factor; For the set of time-series nodes, under the dual constraints of the hold-time repair requirement and the minimum setup time margin, a repair unit combination is selected to determine the actual increase in delay, and the setup time margin and hold-time violation metric are updated during the repair process until the preset repair conditions are met. Based on the repair results, generate an engineering change order document for repairing retention time violations.

2. The method according to claim 1, characterized in that, Obtain the repair unit delay information required for holding time repair, and determine the delay ratio factor required across process corners based on the repair unit delay information, specifically including: Extract the initial delay information of the buffer or delay unit used for time-repair from the process library; By combining the on-chip deviation data built into the process library, the initial delay information is corrected using the Gaussian distribution principle to eliminate systematic deviations; The delay ratio factor is obtained by fitting the multi-process angle delay ratio based on the corrected delay information.

3. The method according to claim 1, characterized in that, Parse and statistically analyze hold-time violation reports to determine the set of time-series nodes to be repaired and their corresponding violation metrics, specifically including: Extract the path identifier, timing node identifier, and violation value from the hold-time violation report; Statistical analysis of time-series nodes is performed to obtain the number of occurrences, maximum violation value, and cumulative violation value; Generate an EDA script file for obtaining setup time margin; The extraction results of the time-keeping violation report are integrated with the statistical results of the time-series nodes to generate a traversal data table containing the path identifier, the time-series node identifier, the violation value, the occurrence count, the maximum violation value, and the cumulative violation value.

4. The method according to claim 3, characterized in that, Obtaining the setup time margin and calculating the minimum setup time margin under the reference process angle based on the delay scaling factor specifically includes: Using the EDA script file, obtain the establishment time margin of each of the time-series nodes under at least one signature establishment angle; The set-up time margin is converted to a reference process angle based on the delay ratio factor, and the minimum value of the conversion result is taken as the minimum set-up time margin.

5. The method according to claim 1, characterized in that, Under the dual constraints of maintaining the time repair requirement and the minimum setup time margin, the combination of repair units is selected to determine the actual increase in delay, specifically including: Within the current path, time-series nodes are sorted according to their occurrence frequency or cumulative violation value to determine repair priority; The delay value that can be increased is calculated for the current time sequence node. The delay value that can be increased is determined by the current hold time repair requirement and the minimum setup time margin. Based on the principle of proximity priority, a combination of repair units is selected from the repair units so that the actual increase in delay is close to the increase in delay value.

6. The method according to claim 5, characterized in that, During the repair process, the setup time margin and hold time violation metric are updated until the preset repair conditions are met, specifically including: Record the timing nodes and the corresponding actual increased delay, and update the minimum setup time margin based on the actual increased delay; After updating the minimum setup time margin, the next time-series node on the same path continues to be processed to calculate the increase in delay value and update the minimum setup time margin based on the actual increase in delay, until the hold-time violation metric meets the preset repair condition or the path traversal ends.

7. The method according to claim 1, characterized in that, Based on the repair results, an engineering change order file for repairing retention time violations is generated, specifically including: The updated timing nodes and corresponding repair unit combination information are converted into engineering change instructions that can be executed by the EDA tool to generate the engineering change instruction file.

8. A chip hold-time violation repair device, characterized in that, include: The delay information processing module is used to acquire the repair unit delay information required for holding time repair, and determine the delay ratio factor required for cross-process corner calculation based on the repair unit delay information; The violation report parsing module is used to parse hold time violation reports and perform statistical analysis to determine the set of time-series nodes to be repaired and their corresponding violation measurement information; The time margin calculation module is used to obtain the setup time margin and calculate the minimum setup time margin under the reference process angle based on the delay ratio factor. The timing path repair module is used to select a combination of repair units to determine the actual increase in delay for the set of timing nodes under the bidirectional constraints of the hold-time repair requirement and the minimum setup time margin, and to update the setup time margin and hold-time violation metric during the repair process until the preset repair conditions are met. The file generation module is used to generate engineering change instruction files for fixing retention time violations based on the repair results.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they perform the steps of the chip hold-time violation repair method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the chip hold-time violation repair method as described in any one of claims 1 to 7.

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