Circuit layout adjustment method, signal transmission module and storage medium

Abstract

The invention relates to a circuit layout adjustment method, a signal transmission module and a storage medium, and the method comprises the steps: obtaining a first impedance distribution curve of a first signal transmission module which is manufactured based on a first circuit layout structure of a signal transmission link and is provided with a physical module of a device in the signal transmission link; determining a target parameter value of each assembly parasitic model in a first simulation circuit of the first signal transmission module, the assembly parasitic model characterizing an assembly parasitic parameter introduced for assembling the corresponding target device, and the first simulation circuit being determined based on the first circuit layout structure and the assembly parasitic parameter of the target device, the target parameter value enables a second impedance distribution curve of the first simulation circuit to be matched with the first impedance distribution curve; and determining a target circuit layout structure of the signal transmission link by taking improvement of the impedance distribution characteristic as an adjustment target based on the target parameter value of each assembly parasitic model.

Description

Technical Field

[0001] This invention relates to the field of electronic testing technology, specifically to a method for adjusting the circuit layout of a signal transmission link, a signal transmission module, and a non-volatile computer-readable storage medium. Background Technology

[0002] For the transmission of uncompressed, ultra-high-resolution video, audio, and control data in harsh environments, signal integrity is a core element for ensuring reliable communication. During circuit layout design, parasitic parameters can significantly alter the impedance characteristics of the signal transmission link, leading to increased return loss and signal distortion. Therefore, it is essential to accurately characterize parasitic effects to effectively suppress return loss and ensure signal integrity. Summary of the Invention

[0003] This disclosure provides a technical solution for optimizing the circuit layout of a signal transmission link by precisely controlling parasitic effects, thereby improving signal integrity.

[0004] According to a first aspect of this disclosure, a method for adjusting the circuit layout of a signal transmission link is provided, the method comprising: Obtain the first impedance distribution curve of the first signal transmission module; wherein, the first signal transmission module is a physical module manufactured based on the first circuit layout structure of the signal transmission link and assembled with the devices in the signal transmission link, and the first impedance distribution curve is... The target parameter value of each assembly parasitic model in the first simulation circuit of the first signal transmission module is determined; wherein, the first simulation circuit is modeled based on the first circuit layout structure and the assembly parasitic parameters of the target device in the signal transmission link, each assembly parasitic model corresponds to a target device in the signal transmission link, and is used to characterize the assembly parasitic parameters introduced by assembling the corresponding target device, and the target parameter value makes the second impedance distribution curve of the first simulation circuit match the first impedance distribution curve to satisfy a first set condition. Based on the target parameter values ​​of each assembly parasitic model, the target circuit layout structure of the signal transmission link is determined; wherein, the target circuit layout structure makes the impedance drop of the corresponding target signal transmission module at the link location where the target device is located less than the impedance drop of the first signal transmission module at the corresponding link location.

[0005] Optionally, before determining the target parameter values ​​of each assembly parasitic model in the first simulation circuit of the first signal transmission module, the method further includes: Obtain the third impedance distribution curve of the second simulation circuit of the first signal transmission module; wherein the second simulation circuit is modeled based on the first circuit layout structure, and the second simulation circuit does not have the assembly parasitic model; The third impedance distribution curve is compared with the first impedance distribution curve, and the target device affecting the impedance distribution is determined based on the comparison result.

[0006] Optionally, determining the target parameter values ​​of each assembly parasitic model in the first simulation circuit of the first signal transmission module includes: Set initial parameter values ​​for each of the assembly parasitic models; In the first simulation circuit, the initial parameter values ​​of each assembly parasitic model are used as a reference, and the parameter values ​​of the corresponding assembly parasitic model are adjusted based on their respective adjustment step sizes until the target parameter values ​​that satisfy the first set conditions are obtained.

[0007] Optionally, determining the target circuit layout structure of the signal transmission link based on the target parameter values ​​of each of the assembly parasitic models includes: Obtain the second circuit layout structure based on the adjustment of the first circuit layout structure; Obtain the fourth impedance distribution curve of the third simulation circuit obtained by modeling the assembly parasitic parameters of the target device based on the second circuit layout structure and the second circuit layout structure; wherein, each assembly parasitic model in the third simulation circuit is assigned a corresponding target parameter value; If the fourth impedance distribution curve satisfies the second set condition, the second circuit layout structure is determined as the target circuit layout structure; wherein, the second set condition means that the impedance drop of the fourth impedance distribution curve at the link location where the target device is located is less than the impedance drop of the first impedance distribution curve at the corresponding link location.

[0008] Optionally, the adjustment based on the first circuit layout structure is an adjustment of the routing area where the target device is located.

[0009] Optionally, when the impedance drop caused by the assembly parasitic parameters of the target device is less than or equal to a set threshold, the routing area where the target device is located is the routing segment where the pads of the target device are located; when the impedance drop is greater than the set threshold, the routing area where the target device is located includes the routing segment where the pads of the target device are located, and the adjacent routing segment located on at least one side of the pads of the target device.

[0010] Optionally, the signal transmission link includes a connector, a monitoring resistor, a capacitor, a TVS diode, and a serializer chip connected sequentially in the signal transmission direction. The connector is the signal input terminal, and the serializer chip is the signal output terminal. The monitoring resistor and the TVS diode are both target devices.

[0011] According to a second aspect of the present disclosure, a signal transmission module is also provided, including a circuit board and various devices mounted on the circuit board. The devices are interconnected through traces on the circuit board to form a complete signal transmission link. The circuit board is fabricated based on a target circuit layout structure of the signal transmission link. The target circuit layout structure maximizes the vertical spacing between the link traces and the reference layer at at least some of the device mounting positions, so as to compensate for the assembly parasitic parameters of the corresponding devices through the layout parasitic parameters of the target circuit layout structure at the corresponding device positions.

[0012] Optionally, the signal transmission link includes a connector, a monitoring resistor, a capacitor, a transient voltage suppressor diode, and a serializer chip connected sequentially in the signal transmission direction. The connector is an input device, and the serializer chip is an output device. The transient voltage suppressor diode is part of the at least some of the devices. The trace between the TVS diode and the serializer chip is referenced to the same reference layer as the TVS diode.

[0013] According to a third aspect of this disclosure, a non-volatile computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described in accordance with the first aspect of this disclosure.

[0014] One beneficial effect of this disclosure is that, in the circuit layout design of the signal transmission link, this disclosure comprehensively considers the influence of layout parasitic parameters and parasitic parameters introduced by device assembly on the impedance characteristic distribution, and adjusts the circuit layout accordingly. Compared with the traditional method that only considers layout parasitic parameters, this disclosure improves the accuracy and completeness of parasitic parameter modeling, and can more realistically reflect the link impedance distribution, thereby effectively reducing return loss and significantly improving the signal integrity of the signal transmission link.

[0015] Other features and advantages of the embodiments of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with their description, serve to explain the principles of the embodiments of the present disclosure.

[0017] Figure 1A schematic diagram of the basic structural components of the signal transmission module is shown. Figure 2 A flowchart of a circuit layout adjustment method according to some embodiments is shown; Figure 3 A schematic diagram of the composition structure of a video output module according to some embodiments is shown; Figure 4 A schematic diagram of a first simulation circuit of a first signal transmission module according to some embodiments is shown; Figure 5 A schematic diagram of a second simulation circuit of a first signal transmission module according to some embodiments is shown; Figure 6 A comparative schematic diagram of a first impedance distribution curve and a third impedance distribution curve according to some embodiments is shown; Figure 7 A schematic diagram showing the matching state of the first impedance distribution curve and the second impedance distribution curve according to some embodiments is shown. Figure 8 A comparative schematic diagram of a first impedance distribution curve and an adjusted impedance distribution curve according to some embodiments is shown; Figure 9 A schematic diagram illustrating the circuit layout adjustment process according to some embodiments is shown; Figure 10 A schematic diagram showing the return loss of the signal transmission module before and after adjustment is provided. Figure 11 A schematic diagram of a signal transmission module according to some embodiments is shown. Detailed Implementation

[0018] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0019] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0020] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0021] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0023] This disclosure relates to a circuit layout adjustment scheme for a signal transmission link. A signal transmission link is a complete path defined in an electronic system for reliable signal transmission, consisting of fixed electrical connections. The signal transmission module, as the physical entity implementing the signal transmission link, typically uses a printed circuit board (PCB) as the transmission medium, and the devices mounted on it provide interfaces and signal processing functions. The circuit layout adjustment described in this disclosure optimizes the PCB layout to control parasitic effects and impedance characteristics of the transmission path, thereby improving the signal integrity of the signal transmission module.

[0024] like Figure 1 As shown, the signal transmission module includes input devices, output devices, and an intermediate link connecting the two. Figure 1 In the example, the intermediate links may include, but are not limited to, sequentially connected devices 1, 2, and 3. The intermediate links may include fewer or more devices, which is not limited here. Input devices are used to connect to a signal source to receive input signals from the signal source. These signals are processed by the intermediate links and then transmitted to the output devices. Output devices are used to connect to downstream modules and convert the signal transmission method according to the interface requirements of the downstream modules, such as converting parallel signals to serial signals.

[0025] In related technologies, the circuit layout design of signal transmission links typically only considers the impact of PCB layout parasitic parameters on impedance characteristics, while ignoring assembly parasitic parameters introduced by component assembly. In reality, once components are assembled onto the PCB, their bodies, the air cavities between the components and the PCB, and the solder joints generated by soldering all generate parasitic effects. These parasitic effects introduced by component assembly are collectively referred to in this disclosure as assembly parasitic parameters. Although assembly parasitic parameters are independent of the circuit layout structure, they interact with the layout parasitic parameters determined by the layout structure to affect the impedance characteristics of the signal transmission link. Therefore, only by accurately characterizing the assembly parasitic parameters and adjusting the layout parasitic parameters accordingly can the final manufactured signal transmission module achieve the expected impedance characteristics.

[0026] Therefore, this disclosure provides a technical solution for optimizing the circuit layout of a signal transmission link by precisely controlling parasitic effects. The following is in conjunction with... Figure 1 The following describes various embodiments of this disclosure.

[0027] <First Embodiment> Figure 2A method for adjusting the circuit layout of a signal transmission link according to some embodiments is shown. For example... Figure 2 As shown, the method in this embodiment includes the following steps S210 to S230: Step S210: Obtain the first impedance distribution curve of the first signal transmission module as measured by the test instrument.

[0028] In this embodiment, the first signal transmission module is a physical module manufactured based on a first circuit layout structure of a signal transmission link and in which the devices in the signal transmission link are assembled. The first circuit layout structure is an initial circuit layout structure, which can be generated based on traditional layout design methods or based on design experience.

[0029] The testing instrument can be a vector network analyzer (VNA). During testing, the instrument is connected to both ends of the measurement range of the first signal transmission module to measure the first impedance distribution curve of the first signal transmission module. The first impedance distribution curve is the result of the combined effect of layout parasitic parameters and assembly parasitic parameters on the impedance characteristics.

[0030] See Figure 1 The test interval can be selected as the link between the input side of the input device and the input side of the output device. When the output device is an active device that performs signal transmission mode conversion, it is not necessary to include the output device in the test interval to avoid interference from the active device with the measurement results.

[0031] During testing, the two test fixtures of the testing instrument can be connected to the test points at both ends of the test interval. Then, the two test fixtures are connected to the measurement ports of the measuring instrument. The testing instrument can measure the scattering parameter (S-parameter) curve of the test interval. The testing instrument uses inverse Fourier transform to convert the frequency domain data into a time domain response, and then converts the scattering parameter curve into an impedance distribution curve output. S-parameters are a set of frequency domain parameters describing the signal scattering characteristics between ports of the signal transmission module in high-frequency signal transmission. They are used to quantify the module's ability to transmit, reflect, and isolate signals of different frequencies. The impedance distribution curve is also known as the TDR (Time Domain Reflectometry) impedance curve. Figure 6 The first impedance distribution curve L1 is shown; see [link / reference]. Figure 6 The impedance distribution curve is the characteristic impedance distribution curve along the length of the tested link. The vertical axis of the impedance distribution curve is the characteristic impedance T, in ohms, and the horizontal axis is time, in nanoseconds (nsec). Each time point on the horizontal axis maps to the transmission distance, representing a specific location on the link. Figure 6As shown, the characteristic impedance changes abruptly at the locations of some devices. For return loss measurement, abrupt change point 1 corresponds to the input device, abrupt change point 2 corresponds to device 1, and abrupt change point 3 corresponds to device 3.

[0032] Figure 3 A schematic diagram of a signal transmission module based on some examples is shown. In this example, the signal transmission module is a video output module 200, including a connector, a monitoring resistor R1, a coupling capacitor C1, a transient voltage suppression diode T1 (TVS diode), and a serializer chip connected in sequence. The connector serves as an input device, receiving the parallel video signal output from the central controller; the serializer chip serves as an output device, converting the parallel video signal into a serial video signal for transmission to the graphics card for display output via a Gigabit Multimedia Serial Link 3 (GMSL3). Figure 3 The video transmission module 200 shown has its connector, monitoring resistor R1, coupling capacitor C1, and TVS diode T1 located in the measurement range, respectively corresponding to... Figure 1 Device 1, Device 2 and Device 3 in the middle.

[0033] Step S220: Determine the target parameter values ​​of each assembly parasitic model in the first simulation circuit of the first signal transmission module.

[0034] In this embodiment, to accurately evaluate the assembly parasitic parameters of the devices, a first simulation circuit of the first signal transmission module can be built using simulation software. The first simulation circuit models each device forming the signal transmission link and its connection relationship, the layout parasitic parameters of the first circuit layout structure, and the assembly parasitic parameters of the target devices on the signal transmission link. In other words, the first simulation circuit can be modeled based on the signal transmission link, the first circuit layout structure, and the assembly parasitic parameters of the target devices in the signal transmission link.

[0035] When building the first simulation circuit, the device itself can be modeled using an ideal model or an S-parameter model provided by the manufacturer. For example, for Figure 3 The video output module 200 shown can use an ideal model for monitoring resistor R1 and TVS diode T1, and the coupling capacitor can use the S-parameter model provided by the manufacturer. The transmission line can use a zero-connection model, etc. To simplify the calculation, the pads on the link can be equivalent to a uniform transmission line for characteristic impedance calculation.

[0036] When building the first simulation circuit, the parasitic parameter values ​​of the first layout are extracted based on the first circuit layout structure, and then the influence of layout parasitic effects on impedance distribution characteristics is reflected in the simulation. These parasitic parameter values ​​can be extracted from the corresponding first circuit layout structure by layout design software.

[0037] In this embodiment, devices whose assembly affects the characteristic impedance of their location can be selected within the test interval as target devices that need to be compensated through layout adjustment. Alternatively, all devices within the test interval can be considered target devices. Each assembly parasitic model in the first simulation circuit corresponds to a target device in the signal transmission link, used to characterize the assembly parasitic parameters introduced by assembling the corresponding target device.

[0038] Figure 4 It shows Figure 1 The first simulation circuit of the signal transmission module. For example... Figure 4 As shown, the first simulation circuit includes equivalent models of the input devices and equivalent models of the intermediate links. The equivalent model of the intermediate links encapsulates the equivalent models of devices 1, 2, and 3 themselves, as well as the corresponding parasitic parameter values ​​of the first layout. In addition, the first simulation circuit also models the assembly parasitic parameters of the target device, forming an assembly parasitic model of the target device. The two ends of the first simulation circuit are impedance matching terminals TermG1 and TermG2. The characteristic impedance value of the impedance matching terminals can be set according to a target value, such as 50 ohms.

[0039] The assembly parasitic parameters of the target device may be parasitic capacitance, parasitic inductance, or both. In examples where parasitic capacitance is dominant, the capacitance model can be directly used as the assembly parasitic model. Figure 1 Device 1 (corresponding to) Figure 3 The monitoring resistor R1 and device 3 (corresponding to) Figure 3 Taking the TVS diode T1 as an example, as shown in the example... Figure 4 As shown, the first assembly parasitic model CAP1 and the second assembly parasitic model CAP2 corresponding to device 1 can be connected to both ends of the equivalent model of the intermediate link.

[0040] In this embodiment, based on the first simulation circuit, by adjusting the parameter values ​​of each assembly parasitic model, a target parameter value can be searched to ensure that the fit between the second impedance distribution curve of the first simulation circuit and the first impedance distribution curve meets a first set condition. The second impedance distribution curve of the first simulation circuit can be generated by simulation software. The first set condition may include: the impedance difference at the same location is less than or equal to a first set threshold; the same location refers to the same time point.

[0041] Figure 7 A comparison diagram of the first impedance distribution curve L1 and the second impedance distribution curve L2 is shown. Figure 7 As shown, by assigning appropriate target parameter values ​​to the assembly parasitic model, the second impedance distribution curve L2 will match the first impedance distribution curve L1. At this time, the impedance at the abrupt change point obtained by simulation and actual test is in good agreement. This means that the target parameter values ​​of the assembly parasitic model determined in the simulation can more realistically reflect the actual assembly parasitic parameter values ​​during the corresponding target period.

[0042] In some examples, selecting a target device on a signal transmission link may include the following steps: obtaining a third impedance distribution curve of a second simulation circuit of a first signal transmission module; and comparing the third impedance distribution curve with a first impedance distribution curve of the first signal transmission module, and determining the target device that affects the impedance distribution based on the comparison result.

[0043] In this example, the second simulation circuit is also modeled based on the first circuit layout and signal transmission link. That is, the second simulation circuit considers the influence of layout parasitic parameters on impedance distribution characteristics, but ignores the influence of assembly parasitic parameters on impedance distribution characteristics. In other words, the second simulation circuit does not have... Figure 4 The assembly parasitic model in the second simulation circuit is as follows: Figure 5 As shown, the main difference between the second simulation circuit and the first simulation circuit is that the second simulation circuit does not have the assembly parasitic model found in the first simulation circuit. Thus, by comparing the first impedance distribution curve with the third impedance distribution curve of the second simulation circuit, the target device whose assembly affects the characteristic impedance can be intuitively determined. Here, "affect" refers to causing the characteristic impedance to decrease by at least a second set threshold. The second set threshold can be set as needed and is not limited here.

[0044] Figure 6 A comparison diagram of the first impedance distribution curve L1 and the third impedance distribution curve L3 of the second simulated circuit is shown. It can be seen that the assembly of the input devices has a limited impact on the characteristic impedance, while devices 1 and 3 have a greater impact. Therefore, it can be... Figure 1 Devices 1 and 3 in the link are selected as target devices. Compared to selecting all devices as target devices, selectively choosing target devices in the link can reduce the scanning burden of searching for target parameter values ​​and improve processing efficiency.

[0045] In another example, target devices can also be selected based on experience. For instance, experience shows that resistors and TVS devices have a significant impact on characteristic impedance, so resistors and TVS devices in the link can be directly used as target devices.

[0046] In some examples, determining the target parameter value of each assembly parasitic model in the first simulation circuit of the first signal transmission module in step S220 may include the following steps: setting initial parameter values ​​for each assembly parasitic model; and, in the first simulation circuit, adjusting the parameter values ​​of the corresponding assembly parasitic models based on their respective adjustment step sizes, with the initial parameter values ​​of each assembly parasitic model as a reference, until the target parameter values ​​that satisfy the first set conditions are obtained.

[0047] In this example, the initial parameter values ​​for each assembly parasitic model can be set to 0. Alternatively, appropriate cutoff values ​​can be empirically set for each assembly parasitic model to limit the scan range.

[0048] In this example, the same or different adjustment step sizes can be set for different assembly parasitic models. Specifically, each assembly parasitic model can be assigned its own adjustment step size based on experience, or it can be referenced... Figure 6 The magnitude of the characteristic impedance difference at the target device location is used to set the adjustment step size for the corresponding assembly parasitic model. Using the set adjustment step size, parameter value scanning is performed, which helps to obtain accurate target parameter values.

[0049] Furthermore, since the parasitic assembly parameters of the target device are caused by the device's own assembly and primarily affect the characteristic impedance at the target device's location, and the parasitic assembly parameters of each target device are relatively independent, the parameter values ​​of each assembly parasitic model can be adjusted simultaneously in each scan. After obtaining the target parameter value of any assembly parasitic model, the adjustment of that model's parameter value can be stopped, and in subsequent scans, the parameter values ​​of other assembly parasitic models can be adjusted until the target parameter value of each assembly parasitic model is determined.

[0050] by Figure 4 For example, in the first round of scanning, the parameter values ​​of the first assembly parasitic model are set to... The parameter values ​​of the second assembly parasitic model are ,in, , Adjust the step size for each of the two models. , For example, all values ​​are 0.01 picofarads (PF). Then, using the first set condition as a constraint, it is determined whether the current parameter value meets the requirements. If not, the second round of scanning continues. In the second round of scanning, the parameter values ​​of the first assembly parasitic model are set to... The parameter values ​​of the second assembly parasitic model are Then, using the first set condition as a constraint, it is determined whether the current parameter value meets the requirements. If at least one condition is not met, the third round of scanning continues, and so on, until the target parameter value of each assembly parasitic model is determined.

[0051] In other examples, it can also be based on Figure 6 The characteristic impedance difference at mutation points 2 and 3 is used to estimate the assembly parasitic parameter values ​​of the corresponding devices, and fine-tuning is performed based on the estimation results.

[0052] Step S230: Based on the target parameter values ​​of each assembly parasitic model, determine the target circuit layout structure of the signal transmission link.

[0053] In this embodiment, the target parameter values ​​of the assembly parasitic model represent the assembly parasitic parameter values ​​of the corresponding device. After determining the target parameter values ​​of each assembly parasitic model in step S220, the layout parasitic parameter values ​​of the signal transmission link can be adjusted in a targeted manner based on these target parameter values. This can be done by adjusting the first layout parasitic parameter values ​​to obtain target layout parasitic parameter values ​​that can improve the impedance continuity of the signal transmission module. The target layout parasitic parameter values ​​are mapped to the target circuit layout structure.

[0054] In this embodiment, after determining the assembly parasitic parameter values, the adjustment of the layout parasitic parameter values ​​aims to improve the overall impact of the combined effect of layout parasitic parameters and assembly parasitic parameters on the link impedance characteristics. For example... Figure 8 As shown, this results in a target signal transmission module, manufactured and assembled with devices in the signal transmission link based on the target circuit layout structure, exhibiting a smaller impedance drop at the link location where the target device is located, compared to the first signal transmission module. Consequently, the impedance distribution characteristics of the impedance distribution curve L0 are closer to the predetermined impedance distribution characteristics. The predetermined impedance distribution characteristics can be, for example, a flat and stable predetermined impedance distribution curve Ls, whose impedance value is always equal to the target characteristic impedance value (e.g., 50Ω). In this embodiment, the impedance drop refers to the drop relative to the predetermined impedance distribution curve. That is, at least at the link location where the target device is located in the signal transmission link, the deviation between the characteristic impedance value of the target signal transmission module at that link location and the target characteristic impedance value will be less than the deviation between the characteristic impedance value of the first signal transmission module at the corresponding link location and the target characteristic impedance value.

[0055] In this embodiment, a target for adjusting the circuit layout structure or parasitic parameters can be preset to achieve the goal of making the impedance distribution characteristics of the target signal transmission module closer to the preset impedance distribution characteristics. This adjustment target can be constrained from at least one of the following dimensions: the overall characteristic impedance level of the entire link, the characteristic impedance fluctuation range of the entire link, and the local extreme values ​​of the characteristic impedance in the entire link.

[0056] In some examples, the target circuit layout structure can be determined based on the first circuit layout structure, combined with the simulation circuit, that is, the parasitic parameter values ​​of the target layout can be determined to improve optimization efficiency.

[0057] In these examples, determining the target circuit layout structure of the signal transmission link based on the target parameter values ​​of each assembly parasitic model in step S230 may include the following steps: Step S231: Obtain the second circuit layout structure based on the adjustment of the first circuit layout structure.

[0058] It is possible to Figure 7 The second impedance distribution curve L2 serves as a guide to determine the direction of adjustment for layout parasitic parameter values. For example... Figure 7 As shown, the second impedance distribution curve exhibits a lower impedance abrupt change at the corresponding positions of devices 1 and 3. When adjusting the circuit layout, the characteristic impedance value determined by both layout parasitic parameters and assembly parasitic parameters at these two positions can be increased by reducing the layout parasitic capacitance at these two positions, thereby reducing the impedance discontinuity caused by parasitic effects.

[0059] Taking device 1 as an example, reducing the parasitic capacitance at its location can be achieved by increasing the spacing between the pads of device 1 and the reference layer, reducing the width of the corresponding conductors, or a combination of both. One way to increase the spacing in circuit layout design is to partially remove (i.e., remove the copper in that area) at least one adjacent reference layer directly below the pads of device 1. This forces the pads to form parasitic capacitance only with reference layers further away, thereby increasing the effective spacing of the parasitic capacitance and reducing the overall parasitic capacitance.

[0060] Since the adjustment of layout parasitic parameters is mainly used to compensate for the assembly parasitic effect of the target device, and the assembly parasitic effect mainly affects the characteristic impedance of the corresponding target device location, in some examples, the adjustment based on the first circuit layout structure in step S231 can be an adjustment of the trace area where the target device is located, so as to provide adjustment efficiency while ensuring the adjustment effect.

[0061] The routing area where the target device is located must include at least the routing segment defined by the target device pads.

[0062] When the impedance drop caused by parasitic assembly parameters of the target device is significant, exceeding the third preset threshold, or when the characteristic impedance value at the location of the target device deviates from the target characteristic impedance value by more than the fourth preset threshold, simply adjusting the layout structure of the mounting area defined by the target device pads will not be sufficient to achieve the desired compensation effect. In this case, the adjacent trace segments of the target device can be further adjusted to raise the overall characteristic impedance level of the entire link, making it closer to the set impedance distribution characteristics. That is, when the impedance drop exceeds the third preset threshold, the trace area where the target device is located includes the trace segment defined by the target device pads, as well as the adjacent trace segment located on at least one side of the target device pads.

[0063] For example, see Figure 6 The impedance drop caused by the parasitic assembly parameters of device 3 is large, and the characteristic impedance value at the corresponding position deviates greatly from the target characteristic impedance value. When adjusting the layout parasitic parameters, not only can the trace segment marked by the pad of device 3 be adjusted, but also the trace segment between device 3 and the output device can be adjusted.

[0064] Step S232: Obtain the fourth impedance distribution curve of the third simulation circuit obtained by modeling the parasitic assembly parameters of the target device based on the second circuit layout structure and the assembly of the second circuit.

[0065] In this example, such as Figure 9 As shown, the first simulation circuit, whose assembly parasitic model is assigned target parameter values ​​(i.e., the final state of the first simulation circuit), can be used as the initial state of the third simulation circuit. In other words, the third simulation circuit inherits each assembly parasitic model from the first simulation circuit, and this assembly parasitic model is assigned corresponding target parameter values. During the circuit layout adjustment based on the third simulation circuit, the parameter values ​​of the assembly parasitic model remain unchanged as target parameter values.

[0066] After adjusting the circuit layout structure through step S232, the third simulation circuit can be updated based on the second layout parasitic parameter values ​​of the adjusted second circuit layout structure. That is, the layout parasitic parameter values ​​in the third simulation circuit are updated to the second layout parasitic parameter values, thereby obtaining the fourth impedance distribution curve of the third simulation circuit.

[0067] Step S233: If the fourth impedance distribution curve satisfies the second set condition, the second circuit layout structure is determined as the target circuit layout structure.

[0068] The second condition means that the impedance drop of the fourth impedance distribution curve at the link location where the target device is located is less than the impedance drop of the first impedance distribution curve at the corresponding link location.

[0069] In this example, when the fourth impedance distribution curve meets the second set condition, the third simulation circuit is the simulation circuit of the target signal transmission module. The fourth impedance distribution curve is close to the impedance distribution curve of the target signal transmission module. Therefore, the second set condition can be set according to the above-mentioned layout parasitic parameter adjustment target.

[0070] If the fourth impedance distribution curve does not meet the second set condition, step S231 can be executed again to further adjust the circuit layout structure until the fourth impedance distribution curve meets the second set condition.

[0071] According to steps S210 to S230, the method of this embodiment is described below. Figure 8 The adjusted target circuit layout structure allows the impedance distribution characteristics of the corresponding target signal transmission module to be closer to the set impedance distribution characteristics than the first impedance distribution characteristics presented by the initial first impedance distribution curve L1 of the first signal transmission module. Therefore, the method of this embodiment can improve impedance discontinuity, reduce return loss SDD11, and enhance signal integrity.

[0072] Figure 10 The figure shows a comparison of the return loss SDD11 test results for the first signal transmission module and the target signal transmission module. In the figure, curve La represents the SDD11 limit required by the GMSL3 protocol specification, curve Lb is the test result for the first signal transmission module, and curve Lc is the test result for the target signal transmission module. It can be seen that curve Lc is generally below curve La (SPEC limit), indicating that it meets the protocol requirements and maintains a certain design margin. At the same time, curve Lc's return loss performance in the relevant frequency band is better than curve Lb, reflecting an improvement in impedance characteristics.

[0073] Each step of the method described in this embodiment can be configured as computer program instructions and executed by a processor to achieve automated processes.

[0074] <Second Embodiment> This disclosure also provides a signal transmission module. For example... Figure 11 As shown, the signal transmission module 1100 includes a circuit board 1101 and devices mounted on the circuit board. These devices are connected by traces formed on the circuit board 1101 to form a signal transmission link.

[0075] In this embodiment, circuit board 1101 is manufactured based on a target circuit layout structure. The target circuit layout structure forms a maximum reference spacing at the locations of at least some components. This allows the layout parasitic parameters of the target circuit layout structure at the locations of the corresponding components to compensate for the assembly parasitic parameters of the corresponding components, thereby improving the impedance drop caused by the assembly parasitic effects of the components. In this embodiment, the reference spacing refers to the vertical spacing between the link trace and the reference layer.

[0076] This disclosure also provides a signal transmission module. For example... Figure 11 As shown, the signal transmission module 1100 includes a circuit board 1101 and various devices mounted on the circuit board 1101, including input devices, output devices, and devices 1, 2, and 3 located in the intermediate link. The devices are interconnected through the traces of the circuit board 1101 to form a complete signal transmission link.

[0077] In this embodiment, circuit board 1101 is fabricated based on a target circuit layout structure. This target circuit layout structure maximizes the vertical spacing (i.e., the "reference spacing" defined in this embodiment) between the link trace and the reference layer at the assembly locations of at least some devices (i.e., at least some target devices). This compensates for the assembly parasitic parameters of the device by using the layout parasitic parameters formed at the corresponding device locations. Specifically, the layout parasitic parameter value at the device location is determined based on the device's assembly parasitic parameter value, thereby improving the impedance drop caused by assembly parasitic effects and ensuring that the impedance distribution characteristics of the entire link meet the set requirements. The set requirements can refer to the above-described layout parasitic parameter adjustment target settings, which will not be elaborated here.

[0078] by Figure 3 Taking the video output module as an example, the target circuit layout structure ensures that the vertical spacing between the device pads and the reference layer at the mounting location of at least one of the TVS diode T1 and the monitoring resistor R1 reaches its maximum value along the entire link, which is at least 10 mils. This can be achieved by partially removing the copper of the two parameter layers adjacent to the corresponding device, allowing the device to reference a third reference layer to meet the vertical spacing requirement. However, the vertical spacing between the link traces and the reference layer at other locations in the target circuit layout structure can be less than this maximum value, for example, by referencing a second reference layer or the nearest first reference layer.

[0079] by Figure 3 Taking the video output module shown as an example, the target circuit layout structure ensures that the vertical spacing between the device pads and the reference layer at the mounting position of at least one of the TVS diode T1 and the monitoring resistor R1 reaches the maximum value in the entire signal transmission link, and this maximum value is not less than 10 mils. Specifically, this can be achieved by partially removing the two parameter layer copper layers adjacent to the corresponding device, allowing the device to use the third reference layer as a reference, thereby satisfying the above-mentioned vertical spacing requirement.

[0080] In some examples, Figure 3 In the video output module, the traces between the TVS diode and the serializer chip can be referenced to the same reference layer as the TVS diode, meaning the vertical spacing between these traces and the reference layer is also the maximum value for the entire link. In this example, the impedance drop caused by the assembly parasitic parameters of the TVS diode can be further compensated by reducing the layout parasitic parameter values ​​of the traces adjacent to the TVS diode.

[0081] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0082] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement any of the methods in the foregoing embodiments of this disclosure. The computer-readable storage medium may be a non-transitory storage medium, but is not limited thereto, and may also be a temporary storage medium.

[0083] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media may include, for example, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), compact disc-read-only memory (CD-ROM), digital versatile disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any combination thereof. The computer-readable storage medium used herein is not to be interpreted as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0084] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include one or more of copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to computer-readable storage media in the respective computing / processing device.

[0085] The computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source or object programs written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as the "C" language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network (e.g., a local area network or a wide area network), or it may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays, or programmable logic arrays, can execute computer-readable program instructions to implement various aspects of the embodiments of this disclosure by utilizing state information from the computer-readable program instructions.

[0086] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus, and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0087] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0088] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0089] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions. It should be noted that implementation in hardware, implementation in software, and implementation using a combination of software and hardware are all equivalent.

[0090] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of this disclosure is defined by the appended claims.

Claims

1. A method for adjusting the circuit layout of a signal transmission link, characterized in that, include: Obtain the first impedance distribution curve of the first signal transmission module; wherein, the first signal transmission module is a physical module manufactured based on the first circuit layout structure of the signal transmission link and assembled with the devices in the signal transmission link; The target parameter value of each assembly parasitic model in the first simulation circuit of the first signal transmission module is determined; wherein, the first simulation circuit is modeled based on the first circuit layout structure and the assembly parasitic parameters of the target device in the signal transmission link, each assembly parasitic model corresponds to a target device in the signal transmission link, and is used to characterize the assembly parasitic parameters introduced by assembling the corresponding target device, and the target parameter value makes the second impedance distribution curve of the first simulation circuit match the first impedance distribution curve to satisfy a first set condition. Based on the target parameter values ​​of each assembly parasitic model, the target circuit layout structure of the signal transmission link is determined; wherein, the target circuit layout structure makes the impedance drop of the corresponding target signal transmission module at the link location where the target device is located less than the impedance drop of the first signal transmission module at the corresponding link location.

2. The method according to claim 1, characterized in that, Before determining the target parameter values ​​of each assembly parasitic model in the first simulation circuit of the first signal transmission module, the method further includes: Obtain the third impedance distribution curve of the second simulation circuit of the first signal transmission module; wherein the second simulation circuit is modeled based on the first circuit layout structure, and the second simulation circuit does not have the assembly parasitic model; The third impedance distribution curve is compared with the first impedance distribution curve, and the target device affecting the impedance distribution is determined based on the comparison result.

3. The method according to claim 1, characterized in that, Determining the target parameter values ​​of each assembly parasitic model in the first simulation circuit of the first signal transmission module includes: Set initial parameter values ​​for each of the assembly parasitic models; In the first simulation circuit, the initial parameter values ​​of each assembly parasitic model are used as a reference, and the parameter values ​​of the corresponding assembly parasitic model are adjusted based on their respective adjustment step sizes until the target parameter values ​​that satisfy the first set conditions are obtained.

4. The method according to claim 1, characterized in that, The determination of the target circuit layout structure of the signal transmission link based on the target parameter values ​​of each of the assembly parasitic models includes: Obtain the second circuit layout structure based on the adjustment of the first circuit layout structure; Obtain the fourth impedance distribution curve of the third simulation circuit obtained by modeling the assembly parasitic parameters of the target device based on the second circuit layout structure and the second circuit layout structure; wherein, each assembly parasitic model in the third simulation circuit is assigned a corresponding target parameter value; If the fourth impedance distribution curve satisfies the second set condition, the second circuit layout structure is determined as the target circuit layout structure; wherein, the second set condition means that the impedance drop of the fourth impedance distribution curve at the link location where the target device is located is less than the impedance drop of the first impedance distribution curve at the corresponding link location.

5. The method according to claim 4, characterized in that, The adjustment based on the first circuit layout structure is an adjustment of the routing area where the target device is located.

6. The method according to claim 5, characterized in that, When the impedance drop caused by the assembly parasitic parameters of the target device is less than or equal to a set threshold, the routing area where the target device is located is the routing segment where the pads of the target device are located; when the impedance drop caused by the assembly parasitic parameters is greater than the set threshold, the routing area where the target device is located includes the routing segment where the pads of the target device are located, and the adjacent routing segment located on at least one side of the pads of the target device.

7. The method according to any one of claims 1 to 6, characterized in that, The signal transmission link includes a connector, a monitoring resistor, a capacitor, a TVS diode, and a serializer chip connected sequentially in the signal transmission direction. The connector is the signal input terminal, and the serializer chip is the signal output terminal. The monitoring resistor and the TVS diode are both target devices.

8. A signal transmission module, comprising a circuit board and various components mounted on the circuit board, wherein the components are interconnected through traces on the circuit board to form a complete signal transmission link; characterized in that, The circuit board is fabricated based on the target circuit layout structure of the signal transmission link. The target circuit layout structure maximizes the vertical spacing between the link trace and the reference layer at at least some of the device assembly locations, so as to compensate for the assembly parasitic parameters of the corresponding devices through the layout parasitic parameters of the target circuit layout structure at the corresponding device locations.

9. The signal transmission module according to claim 8, characterized in that, The signal transmission link includes a connector, a monitoring resistor, a capacitor, a transient voltage suppressor diode, and a serializer chip connected sequentially in the signal transmission direction. The connector is an input device, and the serializer chip is an output device. The transient voltage suppressor diode is part of at least some of the devices. The trace between the TVS diode and the serializer chip is referenced to the same reference layer as the TVS diode.

10. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1 to 7.

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