Display device and driving method thereof

Abstract

The invention provides a display device and a driving method thereof, the display device comprises a display panel, the display panel comprises a plurality of data lines, a plurality of gate lines and a plurality of pixel units, in one row of pixel units, one data line is electrically connected with two adjacent pixel units, and one row of pixel units is electrically connected with two gate lines. In the jth row of pixel units, the polarity of data signals received by the (3k-2) th column of pixel units, the (3k-1) th column of pixel units and the (3k) th column of pixel units is the first polarity, the polarity of data signals received by the (3 (k + 1)-2) th column of pixel units, the (3 (k + 1)-1) th column of pixel units and the (k + 1) th column of pixel units is the second polarity, and in the (j + 1) th row of pixel units, the polarity of data signals received by the (j + 1) th column of pixel units is the second polarity. And the polarities of the pixel units at the corresponding positions are opposite. The technical problem that the image granular sensation of the display device of the DLS architecture is obvious can be solved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method. Background Technology

[0002] In traditional 1G1D architecture display panels, each column of pixel units corresponds to one data line, meaning each data line provides data signals only to one column of pixel units. This architecture requires a large number of data lines, resulting in a larger number of data driver chips and higher manufacturing costs.

[0003] DLS (Data Line Share) architecture displays reduce the number of data lines by having a single data line provide data signals to multiple columns of pixel units. Specifically, in a DLS architecture display panel, one data line provides data signals to two adjacent columns of pixel units at different times, thus reducing the number of data lines by about half compared to a traditional 1G1D architecture display panel. This architecture can significantly reduce the number of data driver chips and manufacturing costs.

[0004] However, while DLS (Digital Substances) display panels reduce costs, they also introduce the technical problem of noticeable pixelation. This pixelation issue affects the display quality. The main reasons for pixelation include: firstly, the asymmetric coupling of parasitic capacitance Cpd in DLS display panels leads to brightness differences between different pixel units; secondly, in traditional DLS display panels, pixel units of the same polarity are spatially clustered, and this polarity clustering results in significant brightness differences between adjacent areas, thus creating a macroscopic pixelation.

[0005] In traditional DLS (Digital Substances) display panels, a column inversion method is typically used to drive pixel units. In this method, pixel units within the same column have the same polarity, adjacent columns have opposite polarities, and the polarity changes every two columns. This inversion method results in a continuous horizontal distribution of pixel units with the same polarity, making graininess a prominent issue.

[0006] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0007] The purpose of this application is to provide a display device and its driving method, which aims to solve the technical problem of obvious pixelation in the display device based on DLS architecture.

[0008] This application provides a display device, which includes a display panel. The display panel includes: multiple data lines; multiple gate lines; and multiple pixel units arranged in an array. In a row of pixel units, one data line is electrically connected to two adjacent pixel units, and a row of pixel units is electrically connected to two gate lines. One of the two gate lines is electrically connected to a pixel unit located in an odd-numbered column, and the other of the two gate lines is electrically connected to a pixel unit located in an even-numbered column. Specifically, in the j-th row of pixel units, the data received by the (3k-2)-th, (3k-1)-th, and (3k-th)-th column pixel units... The polarity of the signal is the first polarity, and the polarity of the data signals received by the pixel units in the 3(k+1)-2, 3(k+1)-1, and 3(k+1) columns is the second polarity. The first polarity is opposite to the second polarity, where j and k are positive integers. In the pixel units in the (j+1)th row, the polarity of the data signals received by the pixel units in the 3k-2, 3k-1, and 3k columns is the second polarity, and the polarity of the data signals received by the pixel units in the 3(k+1)-2, 3(k+1)-1, and 3(k+1) columns is the first polarity.

[0009] This application also provides a driving method for a display device, the display device including a display panel, the display panel including multiple data lines, multiple gate lines, and multiple pixel units arranged in an array, wherein in a row of pixel units, one data line is electrically connected to two adjacent pixel units, a row of pixel units is electrically connected to two gate lines, one of the two gate lines is electrically connected to a pixel unit located in an odd-numbered column, and the other of the two gate lines is electrically connected to a pixel unit located in an even-numbered column; the driving method includes: driving the multiple pixel units through the multiple data lines and the multiple gate lines, such that in the j-th row of pixel units, the pixel unit in the 3k-2th column, the pixel unit in the 3k-1th column, and The polarity of the data signal received by the pixel unit in column 3k is a first polarity, and the polarity of the data signals received by the pixel units in columns 3(k+1)-2, 3(k+1)-1, and 3(k+1) is a second polarity. Furthermore, in the pixel units of row j+1, the polarity of the data signals received by the pixel units in columns 3k-2, 3k-1, and 3k is a second polarity, and the polarity of the data signals received by the pixel units in columns 3(k+1)-2, 3(k+1)-1, and 3(k+1) is a first polarity. The first polarity is opposite to the second polarity, and k and j are positive integers.

[0010] The display device provided in this application employs a specific pixel driving method. In this method, within the same row of pixel units, every three consecutive pixel units receive data signals of the same polarity. The polarities of adjacent groups of three pixel units are opposite, and the polarities of corresponding pixel units in adjacent rows are also opposite. This technical solution can improve the problem of noticeable graininess in DLS architecture display devices. In traditional DLS architecture display devices, when driving pixel units using a column inversion method, the polarity of pixel units in the same column is the same, and the polarity changes every two columns. This results in a large-area continuous distribution of pixel units with the same polarity in the horizontal direction, leading to significant brightness differences between adjacent areas and thus creating noticeable graininess on a macroscopic scale. The technical solution of this application changes the polarity distribution method, causing pixel units with the same polarity to be spatially dispersed rather than clustered. Specifically, since red, green, and blue pixel units are arranged adjacently in the same row, and pixel units in the same column have the same color, in the technical solution of this application, every three adjacent pixel units are red, green, and blue pixel units, respectively. These three pixel units receive data signals of the same polarity, thus forming a pixel unit group. Adjacent pixel unit groups receive data signals of opposite polarity. This method allows pixel units of different polarities to be distributed alternately in the horizontal direction in units of pixel unit groups. Compared with the traditional column reversal method, the period of polarity change is shortened, and the distribution of brightness differences is more uniform, thereby reducing graininess. At the same time, in the vertical direction, the polarities of corresponding pixel units in adjacent rows are opposite, which also disperses the brightness differences in the vertical direction, further reducing graininess.

[0011] Furthermore, in DLS architecture display devices, a single data line provides data signals to two adjacent columns of pixel units at different times. This application's technical solution, while maintaining the advantage of DLS architecture display devices by reducing the number of data lines, improves the graininess problem by optimizing the polarity distribution. This application's technical solution allows pixel units of different brightness to be spatially mixed. When the human eye observes the display image, the brightness differences between adjacent areas are dispersed and mixed, significantly improving the macroscopic graininess. Compared to the traditional column reversal method, this application's technical solution performs polarity reversal in a cycle of three pixel units horizontally and in a cycle of one row vertically, resulting in a polarity distribution similar to dot reversal. This effectively improves the inherent graininess problem of DLS architecture display devices without increasing additional costs, thus enhancing the display quality of the device. Attached Figure Description

[0012] Figure 1 This is a block diagram of a display device provided in an embodiment of this application.

[0013] Figure 2 This is a schematic diagram of the polarity distribution of the display device provided in the embodiments of this application.

[0014] Figure 3 This is a schematic diagram of the first embodiment of the display device provided in this application.

[0015] Figure 4 This is a schematic diagram of a second embodiment of the display device provided in this application. Detailed Implementation

[0016] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0017] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0018] The technical solutions of different embodiments of this application can be combined with each other.

[0019] Embodiments of this application provide a display device and its driving method. The display device adopts a DLS (DataLine Share) architecture, which, while maintaining the low-cost advantage of the DLS architecture, improves the image graininess and brightness differences caused by the asymmetric coupling capacitance and polarity aggregation between the data line and the pixel electrode by optimizing the pixel unit polarity distribution.

[0020] In traditional DLS-based display devices, pixel units of the same polarity are spatially clustered. Due to the asymmetrical length of the connection lines between pixel units and data lines, there are significant differences in the coupling capacitance between the data lines and pixel electrodes, resulting in noticeable brightness differences between adjacent areas. This manifests macroscopically as graininess, lines, and other defects. Embodiments of this application improve the consistency of coupling capacitance, storage capacitance, and liquid crystal capacitance among different pixel units by employing a symmetrical "double short connection line" architecture or a "long-short connection line" architecture in the connection structure between pixel units and data lines. Furthermore, embodiments of this application employ a dot-reversal method in the polarity distribution, where three adjacent columns of pixel units are treated as a single polarity repeating unit. The first and second polarities are alternately distributed in both row and column directions to break up polarity clustering and mix brightness differences, significantly reducing graininess.

[0021] The above technical solution effectively suppresses the inherent graininess problem of DLS architecture display devices without increasing the number of data lines or driving complexity.

[0022] like Figure 1 As shown, the display device provided in the embodiments of this application includes a display panel. The display device is a liquid crystal display device. The display device also includes a timing controller and a source driver chip. The timing controller receives externally input image data and control signals, processes the image data and control signals, and outputs them respectively to the source driver chip and the gate driver circuit. The source driver chip converts the image data into data signals and outputs them to data lines.

[0023] The display panel includes multiple data lines, multiple gate lines, and multiple pixel units (PX). The display panel also includes a gate driving circuit located in the non-display area of ​​the panel. The gate driving circuit is electrically connected to the gate lines and outputs gate signals to the gate lines to activate the pixel units (PX). A source driver chip is electrically connected to the data lines and outputs data signals to the data lines. The multiple pixel units (PX) are arranged in an array to form a pixel unit array.

[0024] Each pixel unit (PX) includes a thin-film transistor (TFT). The active layer of the TFT is made of amorphous silicon or an oxide semiconductor material. Oxide semiconductor materials include, but are not limited to, indium gallium zinc oxide, indium zinc oxide, and indium tin oxide. The gate of the TFT is electrically connected to the gate line, the source of the TFT is electrically connected to the data line, and the drain of the TFT is electrically connected to the pixel electrode.

[0025] In this pixel unit array, pixel units PX in the same column have the same color, while pixel units PX in adjacent columns have different colors. Specifically, multiple pixel units PX include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel. Horizontally, the red, green, and blue pixel units are arranged sequentially. Figure 2 , Figure 3 and Figure 4 As shown, the (3k-2)th, (3k-1)th, and (3k)th columns of pixel units are one of the following: red, green, and blue pixel units, respectively, and each of the three has a different color, where k is a positive integer. With this arrangement, every three consecutive columns of pixel units PX form a pixel unit group (a point).

[0026] In the embodiments of this application, the polarity of the data signal refers to the positive or negative potential difference between the voltage of the data signal and the common voltage of the display panel. If the voltage of the data signal is higher than the common voltage, the polarity of the data signal is positive; if the voltage of the data signal is lower than the common voltage, the polarity of the data signal is negative. A first polarity is one of positive or negative polarity, and a second polarity is the other of positive or negative polarity. The first polarity and the second polarity are opposite. At a certain moment, the data signals transmitted by two adjacent data lines have the same polarity, that is, the polarity of the data signal transmitted by the i-th data line Di is the same as the polarity of the data signal transmitted by the (i+1)-th data line Di+1. At another moment, the data signals transmitted by two adjacent data lines have opposite polarities, that is, the polarity of the data signal transmitted by the i-th data line Di is opposite to the polarity of the data signal transmitted by the (i+1)-th data line Di+1, where i is a positive integer.

[0027] In a row of pixel units PX, a data line is electrically connected to two adjacent pixel units PX, providing data signals to these two pixel units PX at different time periods. The row of pixel units PX is electrically connected to two gate lines. These two gate lines control the pixel units PX located in odd-numbered columns and even-numbered columns within the row, respectively. Specifically, one of these two gate lines is electrically connected to the pixel units PX located in odd-numbered columns, and the other is electrically connected to the pixel units PX located in even-numbered columns. These two gate lines output gate signals sequentially. By outputting gate signals sequentially, these two gate lines sequentially turn on the pixel units PX located in odd-numbered columns and even-numbered columns, allowing the data line electrically connected to these pixel units PX to provide data signals to them at different time periods.

[0028] like Figure 3 and Figure 4 As shown, in the j-th or j+1-th row, the pixel unit PX located in the 3k-2, 3k, and 3k+2 columns is electrically connected to one of the two gate lines, and the pixel unit PX located in the 3k-1, 3k+1, and 3k+3 columns is electrically connected to the other of the two gate lines.

[0029] In the j-th row of pixel units PX, the polarity of the data signals received by the (3k-2), (3k-1), and (3k-1)-th column pixel units PX is the first polarity, and the polarity of the data signals received by the (3k+1)-2, (3k+1)-1, and (3k+1)-th column pixel units PX is the second polarity, where j and k are positive integers. In the j+1-th row of pixel units PX, the polarity of the data signals received by the (3k-2), (3k-1), and (3k-1)-th column pixel units PX is the second polarity, and the polarity of the data signals received by the (3k+1)-2, (3k+1)-1, and (3k+1)-th column pixel units PX is the first polarity.

[0030] Therefore, in the row direction, every three consecutive pixel units PX (corresponding to a pixel unit group) receive data signals of the same polarity, and the polarities of adjacent three pixel unit groups are opposite; in the column direction, the polarities of the three pixel units PX at corresponding positions in two adjacent rows are also opposite. This polarity distribution essentially constitutes a dot reversal method based on pixel unit groups, that is, dot reversal in groups of three columns: the three sub-pixels within the same pixel unit group have the same polarity, the polarities of adjacent pixel unit groups in the row direction are opposite, and the polarities of corresponding pixel unit groups in adjacent rows in the column direction are opposite.

[0031] Compared with the traditional column reversal method (same column, same polarity, reversal by column or column pair), this embodiment subdivides the spatial period of polarity reversal to the pixel unit group level, so that pixel units PX of different polarities are fully interleaved in two-dimensional space, which not only breaks up the bright and dark bands caused by polarity aggregation, but also mixes the brightness differences on a macroscopic level, thereby significantly reducing the graininess.

[0032] like Figure 3 As shown, in the first embodiment, the display panel adopts a dual short connection line architecture. In this architecture, the two columns of pixel units PX electrically connected to the data line are arranged symmetrically with respect to the data line, and the lengths of the connection lines on both sides of the data line are equal. This structurally improves the left-right asymmetry of the coupling capacitor, which is beneficial to ensuring the consistency of the storage capacitor and liquid crystal capacitor of different columns of pixel units PX.

[0033] In this dual short connection line architecture, the i-th data line Di is located between the (3k-2)-th column pixel unit PX and the (3k-1)-th column pixel unit PX, and is electrically connected to both the (3k-2)-th and (3k-1)-th column pixel units PX. The (i+1)-th data line Di+1 is located between the (3k-2)-th and (3k+1)-th column pixel units PX, and is electrically connected to both the (3k-2)-th and (3k+1)-th column pixel units PX. The (i+2)-th data line Di+2 is located between the (3k+2)-th and (3k+3)-th column pixel units PX, and is electrically connected to both the (3k+2)-th and (3k+3)-th column pixel units PX. The data line is located between two columns of pixel units PX that are electrically connected to it. The data line is electrically connected to the two columns of pixel units PX located on its left and right sides through two connecting lines, and both connecting lines are relatively short, thus forming a double short connecting line structure.

[0034] For the j-th row pixel unit PX, the two gate lines S(j)-1 and S(j)-2 electrically connected to the j-th row pixel unit PX are configured to turn on the 3k-2 column pixel units PX, the 3k-1 column pixel unit PX, the 3k column pixel unit PX, the 3k+1 column pixel unit PX, the 3k+2 column pixel unit PX, and the 3k+3 column pixel unit PX. The ith data line Di is configured to output a data signal of the first polarity to the 3k-2 column pixel unit PX and the 3k-1 column pixel unit PX. The ith+1 data line Di+1 is configured to output a data signal of the first polarity to the 3k column pixel unit PX and a data signal of the second polarity to the 3k+1 column pixel unit PX. The ith+2 data line Di+2 is configured to output a data signal of the second polarity to the 3k+2 column pixel unit PX and the 3k+3 column pixel unit PX.

[0035] For the (j+1)th row pixel unit PX, the two gate lines S(j+1)-1 and S(j+1)-2 electrically connected to the (j+1)th row pixel unit PX are configured to enable the (3k-2)th column pixel unit PX, the (3k-1)th column pixel unit PX, the (3k)th column pixel unit PX, the (3k+1)th column pixel unit PX, the (3k+2)th column pixel unit PX, and the (3k+3)th column pixel unit PX. The ith data line Di is configured to output a second polarity data signal to the (3k-2)th column pixel unit PX and the (3k-1)th column pixel unit PX. The ith data line Di+1 is configured to output a second polarity data signal to the (3k)th column pixel unit PX and a first polarity data signal to the (3k+1)th column pixel unit PX. The ith data line Di+2 is configured to output a first polarity data signal to the (3k+2)th column pixel unit PX and the (3k+3)th column pixel unit PX. This achieves the aforementioned point reversal pattern that swaps polarity between adjacent rows.

[0036] In the dual short connection line architecture, pixel units PX are electrically connected to data lines via either a first connection line or a second connection line. In the j-th row of pixel units PX, the (3k-2)th column pixel unit PX and the 3kth column pixel unit PX, which receive data signals of the first polarity, are electrically connected to the i-th data line Di and the (i+1)th data line Di+1, respectively, via two first connection lines. The (3k-1)th column pixel unit PX, which also receives data signals of the first polarity, is electrically connected to the i-th data line Di via a second connection line. The (3k+1)th column pixel unit PX and the (3k+3)th column pixel unit PX, which receive data signals of the second polarity, are electrically connected to the (i+1)th data line Di+1 and the (i+2)th data line Di+2, respectively, via two second connection lines. The (3k+2)th column pixel unit PX, which receives data signals of the second polarity, is electrically connected to the (i+2)th data line Di+2 via a first connection line.

[0037] In the (j+1)th row pixel unit PX, the (3k-2)th column pixel unit PX and the 3kth column pixel unit PX, which receive the second polarity data signal, are electrically connected to the i-th data line Di and the (i+1)th data line Di+1, respectively, via two first connection lines. The (3k-1)th column pixel unit PX, which receives the second polarity data signal, is electrically connected to the i-th data line Di via one second connection line. The (3k+1)th column pixel unit PX and the (3k+3)th column pixel unit PX, which receive the first polarity data signal, are electrically connected to the (i+1)th data line Di+1 and the (i+2)th data line Di+2, respectively, via two second connection lines. The (3k+2)th column pixel unit PX, which receives the first polarity data signal, is electrically connected to the (i+2)th data line Di+2 via one first connection line.

[0038] The absolute value of the difference between the length of the first connecting line and the length of the second connecting line is less than 30% of the length of the first connecting line. Preferably, the lengths of the first and second connecting lines are equal, and both connecting lines are relatively short, thus forming a double short connecting line architecture. Since the lengths of the connecting lines on both sides are close, the coupling capacitance of the data lines to the adjacent pixel units PX is basically symmetrical, which helps to ensure the consistency of the storage capacitance and liquid crystal capacitance of different pixel units PX, reduce the brightness difference caused by the asymmetry of the coupling capacitance, and thus further alleviate the graininess problem in the display device of DLS architecture.

[0039] like Figure 4 As shown, in the second embodiment, the display panel employs a long-short connection line architecture. In this architecture, by alternately changing the relative positions of the data lines and pixel units PX between adjacent rows, two columns of pixel units PX on one side of the same data line are electrically connected to the data line through a shorter connection line and a longer connection line, thereby forming a long-short connection line structure. This structure relaxes the restrictions on connection line length matching to a certain extent, keeping the differences in the equivalent coupling capacitance and storage capacitance of each pixel unit PX within an acceptable range, and, in conjunction with the dot inversion method, reduces macroscopic graininess.

[0040] In this display device with a long and short connection line architecture, in the j-th row of pixel units PX, the 3k-2th column pixel unit PX and the 3k-1th column pixel unit PX are located on one side of the i-th data line Di, and the i-th data line Di is electrically connected to the 3k-2th column pixel unit PX and the 3k-1th column pixel unit PX. The 3kth column pixel unit PX and the 3k+1th column pixel unit PX are located on one side of the (i+1)th data line Di+1, and the (i+1)th data line Di+1 is electrically connected to the 3kth column pixel unit PX and the 3k+1th column pixel unit PX. The 3k+2th column pixel unit PX and the 3k+3th column pixel unit PX are located on one side of the (i+2)th data line Di+2, and the (i+2)th data line Di+2 is electrically connected to the 3k+2th column pixel unit PX and the 3k+3th column pixel unit PX.

[0041] In the (j+1)th row pixel unit PX, the (3k-2)th column pixel unit PX and the (3k-1)th column pixel unit PX are located on the other side of the (i+1)th data line Di+1, and the (i+1)th data line Di+1 is electrically connected to the (3k-2)th column pixel unit PX and the (3k-1)th column pixel unit PX. The (3k)th column pixel unit PX and the (3k+1)th column pixel unit PX are located on the other side of the (i+2)th data line Di+2, and the (i+2)th data line Di+2 is electrically connected to the (3k)th column pixel unit PX and the (3k+1)th column pixel unit PX. The (3k+2)th column pixel unit PX and the (3k+3)th column pixel unit PX are located on the other side of the (i+3)th data line Di+3, and the (i+3)th data line Di+3 is electrically connected to the (3k+2)th column pixel unit PX and the (3k+3)th column pixel unit PX.

[0042] In a display device with a long-short connection line architecture, in row j, the data line is located on one side of the two columns of pixel units PX electrically connected to it, and in row j+1, the data line is located on the other side of the two columns of pixel units PX electrically connected to it. The data line is electrically connected to the two columns of pixel units PX through a shorter connection line and a longer connection line, thus forming a combination of short and long connection lines.

[0043] For the j-th row pixel unit PX, the two gate lines S(j)-1 and S(j)-2 electrically connected to the j-th row pixel unit PX are configured to turn on the 3k-2 column pixel units PX, the 3k-1 column pixel unit PX, the 3k column pixel unit PX, the 3k+1 column pixel unit PX, the 3k+2 column pixel unit PX, and the 3k+3 column pixel unit PX. The ith data line Di is configured to output a data signal of the first polarity to the 3k-2 column pixel unit PX and the 3k-1 column pixel unit PX. The ith+1 data line Di+1 is configured to output a data signal of the first polarity to the 3k column pixel unit PX and a data signal of the second polarity to the 3k+1 column pixel unit PX. The ith+2 data line Di+2 is configured to output a data signal of the second polarity to the 3k+2 column pixel unit PX and the 3k+3 column pixel unit PX.

[0044] For the (j+1)th row pixel unit PX, the two gate lines S(j+1)-1 and S(j+1)-2 electrically connected to the (j+1)th row pixel unit PX are configured to enable the (3k-2)th column pixel unit PX, the (3k-1)th column pixel unit PX, the (3k)th column pixel unit PX, the (3k+1)th column pixel unit PX, the (3k+2)th column pixel unit PX, and the (3k+3)th column pixel unit PX. The (i+1)th data line Di+1 is configured to output a data signal of second polarity to the (3k-2)th column pixel unit PX and the (3k-1)th column pixel unit PX. The (i+2)th data line Di+2 is configured to output a data signal of second polarity to the (3k)th column pixel unit PX and a data signal of first polarity to the (3k+1)th column pixel unit PX. The (i+3)th data line Di+3 is configured to output a data signal of first polarity to the (3k+2)th column pixel unit PX and the (3k+3)th column pixel unit PX. Thus, the aforementioned point reversal pattern of three columns grouped together, in which the polarity is interchanged between adjacent rows, is also realized.

[0045] In a display device with a long-short connection line architecture, pixel units PX are electrically connected to data lines via third and fourth connection lines. In the j-th row of pixel units PX, the (3k-2)th column pixel unit PX and the 3kth column pixel unit PX, which receive data signals of the first polarity, are electrically connected to the i-th data line Di and the (i+1)th data line Di+1, respectively, via two third connection lines. The (3k-1)th column pixel unit PX, which also receives data signals of the first polarity, is electrically connected to the i-th data line Di via one fourth connection line. The (3k+1)th column pixel unit PX and the (3k+3)th column pixel unit PX, which receive data signals of the second polarity, are electrically connected to the (i+1)th data line Di+1 and the (i+2)th data line Di+2, respectively, via two fourth connection lines. The (3k+2)th column pixel unit PX, which receives data signals of the second polarity, is electrically connected to the (i+2)th data line Di+2 via one third connection line.

[0046] In the (j+1)th row pixel unit PX, the (3k-2)th column pixel unit PX and the (3k)th column pixel unit PX, which receive the second polarity data signal, are electrically connected to the (i+1)th data line Di+1 and the (i+2)th data line Di+2, respectively, via two fourth connection lines. The (3k-1)th column pixel unit PX, which receives the second polarity data signal, is electrically connected to the (i+1)th data line Di+1 via a third connection line. The (3k+1)th column pixel unit PX and the (3k+3)th column pixel unit PX, which receive the first polarity data signal, are electrically connected to the (i+2)th data line Di+2 and the (i+3)th data line Di+3, respectively, via two third connection lines. The (3k+2)th column pixel unit PX, which receives the first polarity data signal, is electrically connected to the (i+3)th data line Di+3 via a fourth connection line.

[0047] The length of either the third or fourth connecting line is greater than the other. Specifically, the absolute value of the difference between the lengths of the third and fourth connecting lines is greater than 30% of the length of the third connecting line. The significant difference in length between the third and fourth connecting lines, with one being shorter and the other longer, creates a long-short connecting line architecture. By alternating the combination of data lines and pixel positions and connecting line lengths between adjacent rows, the equivalent electrical characteristics of each pixel unit (PX) are kept within allowable deviations. When used in conjunction with dot inversion, the overall image graininess is further reduced.

[0048] Embodiments of this application also provide a driving method for a display device. The display device includes a display panel, which includes multiple data lines, multiple gate lines, and multiple pixel units PX arranged in an array. The data signals transmitted by adjacent data lines have opposite polarities. The pixel units PX in the same column have the same color, while the pixel units PX in adjacent columns have different colors. In a row of pixel units PX, one data line is electrically connected to two adjacent pixel units PX. A row of pixel units PX is electrically connected to two gate lines. One of the two gate lines is electrically connected to a pixel unit PX located in an odd-numbered column, and the other of the two gate lines is electrically connected to a pixel unit PX located in an even-numbered column.

[0049] This driving method drives multiple pixel units PX through multiple data lines and multiple gate lines, such that in the j-th row of pixel units PX, the polarity of the data signals received by the 3k-2, 3k-1, and 3k-column pixel units PX is a first polarity, and the polarity of the data signals received by the 3(k+1)-2, 3(k+1)-1, and 3(k+1)-column pixel units PX is a second polarity, and in the j+1-th row of pixel units PX, the polarity of the data signals received by the 3k-2, 3k-1, and 3k-column pixel units PX is a second polarity, and the polarity of the data signals received by the 3(k+1)-2, 3(k+1)-1, and 3(k+1)-column pixel units PX is a first polarity. This driving method achieves polarity reversal while ensuring common voltage balance and response speed.

[0050] In the driving method of the display device with a dual short connection line architecture, the i-th data line Di is located between the 3k-2th column pixel unit PX and the 3k-1th column pixel unit PX, and is electrically connected to both the 3k-2nd column pixel unit PX and the 3k-1th column pixel unit PX. The (i+1)-th data line Di+1 is located between the 3kth column pixel unit PX and the 3k+1th column pixel unit PX, and is electrically connected to both the 3kth column pixel unit PX and the 3k+1th column pixel unit PX. The (i+2)-th data line Di+2 is located between the 3k+2nd column pixel unit PX and the 3k+3rd column pixel unit PX, and is electrically connected to both the 3k+2nd column pixel unit PX and the 3k+3rd column pixel unit PX.

[0051] In the j-th row pixel unit PX, the 3k-2 column pixel unit PX, the 3k-1 column pixel unit PX, the 3k column pixel unit PX, the 3k+1 column pixel unit PX, the 3k+2 column pixel unit PX, and the 3k+3 column pixel unit PX are turned on through two gate lines S(j)-1 and S(j)-2 that are electrically connected to the j-th row pixel unit PX. A first polarity data signal is output to the 3k-2 column pixel unit PX and the 3k-1 column pixel unit PX through the i-th data line Di. A first polarity data signal is output to the 3k column pixel unit PX and a second polarity data signal is output to the 3k+1 column pixel unit PX through the i+1 data line Di+1. A second polarity data signal is output to the 3k+2 column pixel unit PX and the 3k+3 column pixel unit PX through the i+2 data line Di+2.

[0052] In the (j+1)th row pixel unit PX, the 3k-2th column pixel unit PX, the 3k-1st column pixel unit PX, the 3kth column pixel unit PX, the 3k+1st column pixel unit PX, the 3k+2nd column pixel unit PX, and the 3k+3rd column pixel unit PX are turned on through two gate lines S(j+1)-1 and S(j+1)-2, which are electrically connected to the (j+1)th row pixel unit PX. A second polarity data signal is output to the 3k-2th column pixel unit PX and the 3k-1st column pixel unit PX through the i-th data line Di. A second polarity data signal is output to the 3kth column pixel unit PX and a first polarity data signal is output to the 3k+1st column pixel unit PX through the i+1st data line Di+1. A first polarity data signal is output to the 3k+2th column pixel unit PX and the 3k+3rd column pixel unit PX through the i+2nd data line Di+2.

[0053] In the driving method of the display device with a long and short connection line architecture, in the pixel unit PX of the j-th row, the pixel unit PX of the 3k-2 column and the pixel unit PX of the 3k-1 column are located on one side of the i-th data line Di, and the i-th data line Di is electrically connected to the pixel unit PX of the 3k-2 column and the pixel unit PX of the 3k-1 column. The pixel unit PX of the 3k-2 column and the pixel unit PX of the 3k+1 column are located on one side of the data line Di+1 of the i+1 column, and the data line Di+1 of the i+1 column is electrically connected to the pixel unit PX of the 3k-2 column and the pixel unit PX of the 3k+1 column. The pixel unit PX of the 3k+2 column and the pixel unit PX of the 3k+3 column are located on one side of the data line Di+2 of the i+2 column, and the data line Di+2 of the i+2 column is electrically connected to the pixel unit PX of the 3k+2 column and the pixel unit PX of the 3k+3 column.

[0054] In the (j+1)th row pixel unit PX, the (3k-2)th column pixel unit PX and the (3k-1)th column pixel unit PX are located on the other side of the (i+1)th data line Di+1. The (i+1)th data line Di+1 is electrically connected to the (3k-2)th column pixel unit PX and the (3k-1)th column pixel unit PX. The (3k)th column pixel unit PX and the (3k+1)th column pixel unit PX are located on the other side of the (i+2)th data line Di+2. The (i+2)th data line Di+2 is electrically connected to the (3k)th column pixel unit PX and the (3k+1)th column pixel unit PX. The (3k+2)th column pixel unit PX and the (3k+3)th column pixel unit PX are located on the other side of the (i+3)th data line Di+3. The (i+3)th data line Di+3 is electrically connected to the (3k+2)th column pixel unit PX and the (3k+3)th column pixel unit PX.

[0055] In the j-th row pixel unit PX, the 3k-2 column pixel unit PX, the 3k-1 column pixel unit PX, the 3k column pixel unit PX, the 3k+1 column pixel unit PX, the 3k+2 column pixel unit PX, and the 3k+3 column pixel unit PX are turned on through two gate lines S(j)-1 and S(j)-2 that are electrically connected to the j-th row pixel unit PX. A first polarity data signal is output to the 3k-2 column pixel unit PX and the 3k-1 column pixel unit PX through the i-th data line Di. A first polarity data signal is output to the 3k column pixel unit PX and a second polarity data signal is output to the 3k+1 column pixel unit PX through the i+1 data line Di+1. A second polarity data signal is output to the 3k+2 column pixel unit PX and the 3k+3 column pixel unit PX through the i+2 data line Di+2.

[0056] In the (j+1)th row pixel unit PX, the 3k-2th column pixel unit PX, the 3k-1st column pixel unit PX, the 3kth column pixel unit PX, the 3k+1st column pixel unit PX, the 3k+2nd column pixel unit PX, and the 3k+3rd column pixel unit PX are turned on through two gate lines S(j+1)-1 and S(j+1)-2, which are electrically connected to the (j+1)th row pixel unit PX. A second polarity data signal is output to the 3k-2th column pixel unit PX and the 3k-1st column pixel unit PX through the (i+1)th data line Di+1. A second polarity data signal is output to the 3kth column pixel unit PX and a first polarity data signal is output to the 3k+1st column pixel unit PX through the (i+2)th data line Di+2. A first polarity data signal is output to the 3k+2nd column pixel unit PX and the 3k+3rd column pixel unit PX through the (i+3)th data line Di+3.

[0057] The display device and driving method provided in the embodiments of this application are applicable to various types of display panels. The display panel supports multiple refresh rates, including but not limited to 60Hz, 90Hz, 120Hz, and 144Hz. The display panel adopts multiple display modes, including but not limited to VA mode (vertical alignment mode), IPS mode (planar conversion mode), FFS mode (edge ​​field switching mode), and STN mode (super twisted nematic mode).

[0058] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, The display device includes a display panel, the display panel comprising: Multiple data cables; Multiple gate lines; and Multiple pixel units are arranged in an array. In a row of pixel units, a data line is electrically connected to two adjacent pixel units. A row of pixel units is electrically connected to two gate lines. One of the two gate lines is electrically connected to a pixel unit located in an odd-numbered column, and the other of the two gate lines is electrically connected to a pixel unit located in an even-numbered column. In the j-th row of pixel units, the polarity of the data signals received by the 3k-2, 3k-1, and 3k-th column pixel units is the first polarity, and the polarity of the data signals received by the 3(k+1)-2, 3(k+1)-1, and 3(k+1)-th column pixel units is the second polarity. The first polarity is opposite to the second polarity, where j and k are positive integers. In the (j+1)th row of pixel units, the polarity of the data signals received by the 3k-2nd, 3k-1st, and 3kth column pixel units is the second polarity, while the polarity of the data signals received by the 3(k+1)-2nd, 3(k+1)-1st, and 3(k+1)th column pixel units is the first polarity.

2. The display device according to claim 1, characterized in that, The i-th data line is located between the (3k-2)-th column pixel unit and the (3k-1)-th column pixel unit, and the i-th data line is electrically connected to the (3k-2)-th column pixel unit and the (3k-1)-th column pixel unit, where i is a positive integer; The (i+1)th data line is located between the 3kth and 3k+1th pixel units, and the (i+1)th data line is electrically connected to the 3kth and 3k+1th pixel units. The (i+2)th data line is located between the (3k+2)th and (3k+3)th pixel units, and is electrically connected to the (3k+2)th and (3k+3)th pixel units.

3. The display device according to claim 2, characterized in that, For the j-th row pixel unit, the two gate lines electrically connected to the j-th row pixel unit are configured to turn on the 3k-2 column pixel unit, the 3k-1 column pixel unit, the 3k column pixel unit, the 3k+1 column pixel unit, the 3k+2 column pixel unit, and the 3k+3 column pixel unit. The i-th data line is configured to output a data signal of a first polarity to the 3k-2 column pixel unit and the 3k-1 column pixel unit. The i+1 data line is configured to output a data signal of the first polarity to the 3k column pixel unit and a data signal of a second polarity to the 3k+1 column pixel unit. The i+2 data line is configured to output a data signal of the second polarity to the 3k+2 column pixel unit and the 3k+3 column pixel unit. The first polarity and the second polarity are opposite. For the (j+1)th row pixel unit, the two gate lines electrically connected to the (j+1)th row pixel unit are configured to turn on the 3k-2th column pixel unit, the 3k-1th column pixel unit, the 3kth column pixel unit, the 3k+1th column pixel unit, the 3k+2th column pixel unit, and the 3k+3th column pixel unit. The i-th data line is configured to output a data signal of the second polarity to the 3k-2th column pixel unit and the 3k-1th column pixel unit. The i+1th data line is configured to output a data signal of the second polarity to the 3kth column pixel unit and to output a data signal of the first polarity to the 3k+1th column pixel unit. The i+2th data line is configured to output a data signal of the first polarity to the 3k+2th column pixel unit and the 3k+3th column pixel unit.

4. The display device according to claim 2, characterized in that, In the j-th row of pixel units, the (3k-2)th column pixel unit and the 3kth column pixel unit that receive the first polarity data signal are electrically connected to the i-th data line and the (i+1)th data line respectively through two first connection lines. The (3k-1)th column pixel unit that receives the first polarity data signal is electrically connected to the i-th data line through one second connection line. The (3k+1)th column pixel unit and the 3k+3th column pixel unit that receive the second polarity data signal are electrically connected to the (i+1)th data line and the (i+2)th data line respectively through two second connection lines. The (3k+2)th column pixel unit that receives the second polarity data signal is electrically connected to the (i+2)th data line through one first connection line. In the (j+1)th row of pixel units, the (3k-2)th column pixel unit and the (3k)th column pixel unit that receive the second polarity data signal are electrically connected to the i-th data line and the (i+1)th data line respectively through two first connecting lines. The (3k-1)th column pixel unit that receives the second polarity data signal is electrically connected to the i-th data line through one second connecting line. The (3k+1)th column pixel unit and the (3k+3)th column pixel unit that receive the first polarity data signal are electrically connected to the (i+1)th data line and the (i+2)th data line respectively through two second connecting lines. The (3k+2)th column pixel unit that receives the first polarity data signal is electrically connected to the (i+2)th data line through one first connecting line. Wherein, the absolute value of the difference between the length of the first connecting line and the length of the second connecting line is less than 30% of the length of the first connecting line.

5. The display device according to claim 1, characterized in that, In the j-th row of pixel units, the (3k-2)-th column pixel unit and the (3k-1)-th column pixel unit are located on one side of the i-th data line, and the i-th data line is electrically connected to the (3k-2)-th column pixel unit and the (3k-1)-th column pixel unit. The 3k-th column pixel unit and the (3k+1)-th column pixel unit are located on one side of the (i+1)-th data line, and the (i+1)-th data line is electrically connected to the 3k-th column pixel unit and the (3k+1)-th column pixel unit. The 3k+2-th column pixel unit and the (3k+3)-th column pixel unit are located on one side of the (i+2)-th data line, and the (i+2)-th data line is electrically connected to the 3k+2-th column pixel unit and the (3k+3)-th column pixel unit. Here, i is a positive integer. In the (j+1)th row of pixel units, the (3k-2)th and (3k-1)th column pixel units are located on the other side of the (i+1)th data line, which is electrically connected to the (3k-2)th and (3k-1)th column pixel units. The (3k)th and (3k+1)th column pixel units are located on the other side of the (i+2)th data line, which is electrically connected to the (3k)th and (3k+1)th column pixel units. The (3k+2)th and (3k+3)th column pixel units are located on the other side of the (i+3)th data line, which is electrically connected to the (3k+2)th and (3k+3)th column pixel units.

6. The display device according to claim 5, characterized in that, For the j-th row pixel unit, the two gate lines electrically connected to the j-th row pixel unit are configured to turn on the 3k-2 column pixel unit, the 3k-1 column pixel unit, the 3k column pixel unit, the 3k+1 column pixel unit, the 3k+2 column pixel unit, and the 3k+3 column pixel unit. The i-th data line is configured to output a data signal of a first polarity to the 3k-2 column pixel unit and the 3k-1 column pixel unit. The i+1 data line is configured to output a data signal of the first polarity to the 3k column pixel unit and a data signal of a second polarity to the 3k+1 column pixel unit. The i+2 data line is configured to output a data signal of the second polarity to the 3k+2 column pixel unit and the 3k+3 column pixel unit. The first polarity and the second polarity are opposite. For the (j+1)th row pixel unit, the two gate lines electrically connected to the (j+1)th row pixel unit are configured to turn on the 3k-2th column pixel unit, the 3k-1st column pixel unit, the 3kth column pixel unit, the 3k+1st column pixel unit, the 3k+2nd column pixel unit, and the 3k+3rd column pixel unit. The (i+1)th data line is configured to output a data signal of the second polarity to the 3k-2th column pixel unit and the 3k-1st column pixel unit. The (i+2)th data line is configured to output a data signal of the second polarity to the 3kth column pixel unit and output a data signal of the first polarity to the 3k+1st column pixel unit. The (i+3)th data line is configured to output a data signal of the first polarity to the 3k+2nd column pixel unit and the 3k+3rd column pixel unit.

7. The display device according to claim 5, characterized in that, In the j-th row of pixel units, the (3k-2)th column pixel unit and the 3kth column pixel unit that receive the first polarity data signal are electrically connected to the i-th data line and the (i+1)th data line respectively through two third connecting lines. The (3k-1)th column pixel unit that receives the first polarity data signal is electrically connected to the i-th data line through one fourth connecting line. The (3k+1)th column pixel unit and the 3k+3th column pixel unit that receive the second polarity data signal are electrically connected to the (i+1)th data line and the (i+2)th data line respectively through two fourth connecting lines. The (3k+2)th column pixel unit that receives the second polarity data signal is electrically connected to the (i+2)th data line through one third connecting line. In the (j+1)th row of pixel units, the (3k-2)th column pixel unit and the (3k)th column pixel unit that receive the second polarity data signal are electrically connected to the (i+1)th data line and the (i+2)th data line respectively through two fourth connecting lines. The (3k-1)th column pixel unit that receives the second polarity data signal is electrically connected to the (i+1)th data line through one third connecting line. The (3k+1)th column pixel unit and the (3k+3)th column pixel unit that receive the first polarity data signal are electrically connected to the (i+2)th data line and the (i+3)th data line respectively through two third connecting lines. The (3k+2)th column pixel unit that receives the first polarity data signal is electrically connected to the (i+3)th data line through one fourth connecting line. Among them, the length of the third connecting line and the length of the fourth connecting line are greater than the other.

8. A driving method for a display device, characterized in that, The display device includes a display panel, which includes multiple data lines, multiple gate lines, and multiple pixel units arranged in an array. In a row of pixel units, one data line is electrically connected to two adjacent pixel units, and the row of pixel units is electrically connected to two gate lines. One of the two gate lines is electrically connected to a pixel unit located in an odd-numbered column, and the other of the two gate lines is electrically connected to a pixel unit located in an even-numbered column. The driving method includes: The plurality of pixel units are driven by the plurality of data lines and the plurality of gate lines such that the polarity of the data signals received by the pixel units in the 3k-2, 3k-1, and 3k columns in the j-th row of pixel units is a first polarity, and the polarity of the data signals received by the pixel units in the 3(k+1)-2, 3(k+1)-1, and 3(k+1) columns is a second polarity, and the polarity of the data signals received by the pixel units in the 3k-2, 3k-1, and 3k columns in the j+1-th row of pixel units is a second polarity, and the polarity of the data signals received by the pixel units in the 3(k+1)-2, 3(k+1)-1, and 3(k+1) columns is a first polarity, wherein the first polarity is opposite to the second polarity, and k and j are positive integers.

9. The driving method for the display device according to claim 8, characterized in that, The i-th data line is located between the (3k-2)-th column pixel unit and the (3k-1)-th column pixel unit, and the i-th data line is electrically connected to the (3k-2)-th column pixel unit and the (3k-1)-th column pixel unit, where i is a positive integer; The (i+1)th data line is located between the 3kth and 3k+1th pixel units, and the (i+1)th data line is electrically connected to the 3kth and 3k+1th pixel units. The (i+2)th data line is located between the (3k+2)th and (3k+3)th pixel units, and the (i+2)th data line is electrically connected to the (3k+2)th and (3k+3)th pixel units. The driving method includes: In the j-th row of pixel units, the 3k-2 column pixel units, the 3k-1 column pixel units, the 3k column pixel units, the 3k+1 column pixel units, the 3k+2 column pixel units, and the 3k+3 column pixel units are turned on through the two gate lines electrically connected to the j-th row pixel units. A data signal of the first polarity is output to the 3k-2 column pixel units and the 3k-1 column pixel units through the i-th data line. A data signal of the first polarity is output to the 3k column pixel units and a data signal of the second polarity is output to the 3k+1 column pixel units through the i+1 data line. A data signal of the second polarity is output to the 3k+2 column pixel units and the 3k+3 column pixel units through the i+2 data line. The first polarity and the second polarity are opposite. In the (j+1)th row of pixel units, the 3k-2th column pixel unit, the 3k-1st column pixel unit, the 3kth column pixel unit, the 3k+1st column pixel unit, the 3k+2nd column pixel unit, and the 3k+3rd column pixel unit are turned on through the two gate lines electrically connected to the (j+1)th row pixel unit. The second polarity data signal is output to the 3k-2th column pixel unit and the 3k-1st column pixel unit through the i-th data line. The second polarity data signal is output to the 3kth column pixel unit and the first polarity data signal is output to the 3k+1st column pixel unit through the i+1st data line. The first polarity data signal is output to the 3k+2nd column pixel unit and the 3k+3rd column pixel unit through the i+2nd data line.

10. The driving method for the display device according to claim 8, characterized in that, In the j-th row of pixel units, the (3k-2)-th column pixel unit and the (3k-1)-th column pixel unit are located on one side of the i-th data line, and the i-th data line is electrically connected to the (3k-2)-th column pixel unit and the (3k-1)-th column pixel unit. The 3k-th column pixel unit and the (3k+1)-th column pixel unit are located on one side of the (i+1)-th data line, and the (i+1)-th data line is electrically connected to the 3k-th column pixel unit and the (3k+1)-th column pixel unit. The 3k+2-th column pixel unit and the (3k+3)-th column pixel unit are located on one side of the (i+2)-th data line, and the (i+2)-th data line is electrically connected to the 3k+2-th column pixel unit and the (3k+3)-th column pixel unit. Here, i is a positive integer. In the (j+1)th row of pixel units, the (3k-2)th and (3k-1)th column pixel units are located on the other side of the (i+1)th data line, which is electrically connected to the (3k-2)th and (3k-1)th column pixel units. The (3k)th and (3k+1)th column pixel units are located on the other side of the (i+2)th data line, which is electrically connected to the (3k)th and (3k+1)th column pixel units. The (3k+2)th and (3k+3)th column pixel units are located on the other side of the (i+3)th data line, which is electrically connected to the (3k+2)th and (3k+3)th column pixel units. The driving method includes: In the j-th row of pixel units, the 3k-2 column pixel units, the 3k-1 column pixel units, the 3k column pixel units, the 3k+1 column pixel units, the 3k+2 column pixel units, and the 3k+3 column pixel units are turned on through the two gate lines electrically connected to the j-th row pixel units. A data signal of the first polarity is output to the 3k-2 column pixel units and the 3k-1 column pixel units through the i-th data line. A data signal of the first polarity is output to the 3k column pixel units and a data signal of the second polarity is output to the 3k+1 column pixel units through the i+1 data line. A data signal of the second polarity is output to the 3k+2 column pixel units and the 3k+3 column pixel units through the i+2 data line. The first polarity and the second polarity are opposite. In the (j+1)th row of pixel units, the 3k-2th column pixel unit, the 3k-1st column pixel unit, the 3kth column pixel unit, the 3k+1st column pixel unit, the 3k+2nd column pixel unit, and the 3k+3rd column pixel unit are turned on through the two gate lines electrically connected to the (j+1)th row pixel unit. The second polarity data signal is output to the 3k-2th column pixel unit and the 3k-1st column pixel unit through the (i+1)th data line. The second polarity data signal is output to the 3kth column pixel unit and the first polarity data signal is output to the 3k+1st column pixel unit through the (i+2)th data line. The first polarity data signal is output to the 3k+2nd column pixel unit and the 3k+3rd column pixel unit through the (i+3)th data line.

Images