Memory with beamwidth access line and reading method and manufacturing method thereof

Abstract

The invention discloses a memory with beamwidth access lines and a reading method and a manufacturing method thereof. A memory includes a first group, a second group, a third group, and a fourth group stacked on each other with respect to a first direction and correspondingly including memory cells. Each of the first to fourth groups includes a first partition and a second partition separated from each other with respect to the first direction by a local access manager. (A) the first and second groups and (B) the third and fourth groups are organized as corresponding first and second bundles. The memory also includes a global access manager separating the first bundle and the second bundle relative to the first direction. A global access manager is coupled to the first and second beams through corresponding first and second beam width write lines or corresponding first and second beam width read lines, respectively. The global access manager is configured to selectively access the first beam and the second beam on a mutually exclusive basis.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device technology, and more specifically to a memory having a bundle width access line and methods for reading and manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry produces a wide variety of analog and digital devices to solve problems in many different fields. Advances in semiconductor process technology nodes have gradually reduced component size and spacing, leading to a gradual increase in transistor density. ICs are becoming smaller. Summary of the Invention

[0003] According to a first aspect of this disclosure, a memory is provided, comprising: a first group, a second group, a third group, and a fourth group, stacked on top of each other relative to a first direction and correspondingly including memory cells, and each group including: a first partition and a second partition and a local access manager; (A) the first group and the second group and (B) the third group and the fourth group are organized into corresponding first bundles and second bundles; and a global access manager separating the first bundle and the second bundle relative to the first direction, the global access manager being coupled to the first bundle and the second bundle respectively via corresponding first bundle-width write lines and second bundle-width write lines or corresponding first bundle-width read lines and second bundle-width read lines.

[0004] According to a second aspect of this disclosure, a method of manufacturing a memory is provided, the method comprising: forming a structure including components, the components including memory cells, local access managers, and global access managers, the formation of the structure including components comprising: arranging a first component of the components including the memory cells into a first group, a second group, a third group, and a fourth group stacked on top of each other relative to a first direction, including, for each of the first group to the fourth group, arranging an α component and a β component of the first component into a corresponding first partition and a second partition; arranging (A) the first group and the second group and (B) the third group and the fourth group into corresponding first bundles and second bundles; and arranging the group including the local access managers into... The second component in the component is arranged such that for each of the first group, the second group, the third group, and the fourth group, the first partition and the second partition are separated from each other relative to the first direction by a corresponding local access manager of the local access managers; the third component in the component including the global access manager is arranged such that the global access manager separates the first bundle and the second bundle relative to the first direction; and mutual coupling is formed between the components, at least resulting in: a first bundle-width write line and a second bundle-width read line or a first bundle-width read line and a second bundle-width read line, the first bundle-width write line and the second bundle-width read line correspondingly coupling the global access manager to the first bundle and the second bundle.

[0005] According to a third aspect of this disclosure, a method for reading from a memory is provided, the method comprising: accessing a first bundle and a second bundle of the memory on a mutually exclusive basis; the first bundle and the second bundle correspondingly comprising (A) a first group and a second group of the memory and (B) a third group and a fourth group of the memory; the first group, the second group, the third group, and the fourth group are stacked on top of each other relative to a first direction and correspondingly comprised of memory cells, and each memory cell in the memory cells includes a first partition and a second partition and a local access manager, the memory including a global access manager separating the first bundle and the second bundle relative to the first direction, and the global access manager being divided by corresponding first bundle-width write lines and second bundle-width write lines. The data is not coupled to the first bundle and the second bundle, and the global access manager includes a first delay line and a multiplexer coupled to the first bundle and the second bundle via corresponding first and second bundle width read lines; for a selected memory cell in one of the memory cells in a corresponding bundle of the first bundle and the second bundle, accessing the first bundle and the second bundle includes: providing a group-level signal to the corresponding local access manager to transfer data from a selected memory cell in the memory cells to a corresponding bundle width read line of the first bundle width read line and the second bundle width read line; delaying a control signal by a first delay factor; and configuring the control signal to cause the multiplexer to select the first bundle width read line or the second bundle width read line. Attached Figure Description

[0006] One or more embodiments are shown in the accompanying drawings by way of example and not limitation, wherein elements with the same reference numerals always denote similar elements. Unless otherwise disclosed, the drawings are not drawn to scale.

[0007] Figure 1 These are block diagrams based on some embodiments.

[0008] Figures 2A to 2E These are corresponding schematic diagrams based on some embodiments.

[0009] Figures 3A to 3B as well as Figure 4 These are timing diagrams based on some embodiments.

[0010] Figure 5 , Figures 6A to 6D as well as Figure 7 This is a flowchart of a corresponding method according to some embodiments.

[0011] Figure 8 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0012] Figure 9 This is a block diagram of an integrated circuit (IC) manufacturing system and the associated IC manufacturing process according to some embodiments. Detailed Implementation

[0013] The following disclosure discloses numerous different embodiments or examples of various features for implementing this subject matter. Examples of components, materials, values, steps, operations, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc., may also be considered. For example, in the following description, forming a first feature on or on a second feature includes embodiments where the first and second features are formed in direct contact, and also includes embodiments where an additional feature is formed between the first and second features such that the first and second features do not directly contact each other. Furthermore, reference numerals and / or letters are repeated in various examples in this disclosure. This repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, spatially related terms (e.g., "below," "below," "lower," "above," "higher," etc.) are used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). In addition to the orientations depicted in the figures, spatially related terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein are similarly interpreted accordingly. In some embodiments, the term standard cell structure refers to a standardized component included in various standard cell structure libraries. In some embodiments, various standard cell structures are selected from their libraries and used as components in layout diagrams representing circuits.

[0015] In some embodiments, a memory includes a first group, a second group, a third group, and a fourth group stacked on top of each other relative to a first direction and correspondingly including memory cells. Each of the first to fourth groups includes a first partition and a second partition, as well as a local access manager. (A) The first and second groups and (B) the third and fourth groups are organized into corresponding first bundles and second bundles. The memory also includes a global access manager that separates the first bundle and the second bundle relative to the first direction. The global access manager is coupled to the first bundle and the second bundle via corresponding first bundle-width write lines and second bundle-width write lines or corresponding first bundle-width read lines and second bundle-width read lines, respectively. The global access manager is configured to selectively access the first bundle and the second bundle on a mutually exclusive basis.

[0016] Consider a memory according to another method, which is a counterpart to a memory (the memory of this disclosure) according to one or more embodiments of this disclosure, wherein the counterpart memory includes: a group of counterparts to a group of this disclosure; global input / output (I / O) circuitry as a counterpart to global I / O (GIO) circuitry included in a global access manager of this disclosure; a global controller (GCNT) as a counterpart to a GCNT of this disclosure included in a GCNT of this disclosure; and local I / O circuitry (LIO) as a counterpart to a LIO of this disclosure included in a local access manager. Each counterpart GIO circuit is coupled to a counterpart GIO via a memory-wide signal line. Because each memory-wide signal line in the counterpart method is coupled to each of the counterpart LIOs, the memory-wide signal lines in the counterpart method extend to all counterpart groups, such that the memory-wide signal lines in the counterpart method are long.

[0017] As part of developing at least some of the memories disclosed herein, one or more inventors recognized at least the following: because the memory wide signal lines according to another method are long, they experience significant RC loads, which reduce signal propagation speed, reduce signal quality, and increase power consumption; for example, about 20% of the power consumed during the read phase of the corresponding memory operation is consumed by the global bit lines of the corresponding memory; and there is an opportunity to reduce signal line length compared to the memory according to another method. Therefore, the memory of this disclosure reduces the access line length by using bundle-width access lines, which improves signal propagation speed, improves signal quality, and reduces power consumption compared to the use of memory wide signal lines in the memory according to another method. One or more memories of this disclosure reduce power consumption by about 13% compared to the memory according to another method. Regarding one or more memories of this disclosure, the use of bundle-width access lines by one of the corresponding GIOs of this disclosure reduces associated power consumption by about 19% compared to the power consumption associated with the use of memory wide signal lines by the corresponding GIO according to another method.

[0018] Figure 1 This is a block diagram of a memory 100 according to some embodiments.

[0019] exist Figure 1 In this context, a memory includes memory cells (see...). Figure 2A Groups 106(1), 106(2), 106(3) and 106(4) are stacked on or on each other relative to a first direction (e.g., parallel to the Y-axis). Figure 1Assume the following: group 106(1) is stacked on group 106(2) such that group 106(1) is adjacent to group 106(2); and group 106(3) is stacked on group 106(4). In some embodiments, group 106(1) is stacked on group 106(2) such that group 106(1) is substantially not adjacent to group 106(2) with respect to the Y-axis. In some embodiments, group 106(3) is stacked on group 106(4).

[0020] Groups 106(1) to 106(4) are organized into corresponding bundles 102(1) and 102(2). Bundle 102(1) consists of groups 106(1) and 106(2). Bundle 102(2) consists of groups 106(3) and 106(4). Bundle 102(1) is stacked on top of bundle 102(2) relative to the Y-axis. Bundle 102(1) is separated from bundle 102(2) relative to the Y-axis by global access manager 104. Figure 1 Assume the following: Bundle 102(1) is stacked on top of Global Access Manager 104; and Global Access Manager 104 is stacked on top of Bundle 102(2). In some embodiments, Bundle 102(1) is stacked on top of Global Access Manager 104. In some embodiments, Global Access Manager 104 is stacked on top of Bundle 102(2).

[0021] exist Figure 1 In this context, each of groups 106(1) to 106(4) includes partition 108, local access manager 112, and partition 110. Relative to the Y-axis, for each of groups 106(1) to 106(4): partition 108 is stacked on top of partition 110; and partition 108 is separated from partition 110 by local access manager 112. Figure 1 Assume the following: Partition 108 is stacked on access manager 112; and local access manager 112 is stacked on partition 110. In some embodiments, partition 108 is stacked on top of local access manager 112. In some embodiments, local access manager 112 is stacked on top of partition 110.

[0022] Each partition 108 and each partition 110 includes a memory cell array 128, a row decoder & write line (WL) driver 126, and a memory cell array 130. Array 128 is separated from array 130 by the row decoder & WL driver 126 relative to a second direction perpendicular to the first direction (e.g., parallel to the X-axis), and for each partition 108 and each partition 110. Figure 1Assume the following: Array 128 is adjacent to line decoder & WL driver 126; and line decoder & WL driver 126 is adjacent to array 130. In some embodiments, array 128 is close to line decoder & WL driver 126, but not substantially adjacent to line decoder & WL driver 126. In some embodiments, line decoder & WL driver 126 is close to array 130, but not substantially adjacent to array 130. In some embodiments, the first direction and the second direction correspond to vertical directions other than the Y-axis and X-axis.

[0023] In some embodiments, for each of groups 106(1) to 106(4), and about axis of symmetry 142: array 128 of partition 110 is mirror-symmetric to array 128 of partition 108; and array 130 of partition 110 is mirror-symmetric to array 130 of partition 108. In some embodiments, axis 142 is referred to as local polyline 142. In some embodiments, each of groups 106(1) to 106(4) is described as folded at the partition level. In some embodiments, each of groups 106(1) to 106(4) is described as exhibiting partition-level folding.

[0024] In some embodiments, bundle 102(2) is symmetrical to bundle 102(1) about axis of symmetry 140, according to groups 106(1) to 106(4) and partitions 108 and 110. However, bundle 102(2) is asymmetrical about the orientation of arrays 128 and 130 about axis of symmetry 140. In some embodiments, axis 140 is referred to as global polyline 140. In some embodiments, memory 100 is referred to as folded memory 100 according to polylines 140 and 142. In some embodiments, memory 100 is described as being folded at the bundle level. In some embodiments, memory 100 is described as exhibiting bundle-level folding.

[0025] exist Figure 1 In this configuration, each local access manager 112 includes a local input / output (I / O) circuit 122, a local controller (LCNT) 120, and a local I / O circuit (LIO) 124. Regarding the X-axis, LIO 122 is separated from LIO 124 via LCNT 120. Figure 1 Assume the following: LIO 122 is adjacent to LCNT 120; and LCNT 120 is adjacent to LIO 124. In some embodiments, LIO 122 is close to LCNT 120, but not substantially adjacent to LCNT 120. In some embodiments, LCNT 120 is close to LIO 124, but not substantially adjacent to LIO 124.

[0026] For each of groups 106(1) to 106(4), LIO 122 is coupled to array 128 in the corresponding partition 108 and to array 128 in the corresponding partition 110 via signal lines including bank-wide access lines 132(1) and 132(2) (see [link]). Figure 2A Access lines 132(1) and 132(2) are group memory access lines. For the sake of simplicity, Figure 1 Not all such signal lines are shown (including all group width access lines 132(1) or all group width access lines 132(2)). Group width access lines 132(1) and 132(2) include write lines and read lines, etc.

[0027] For each of groups 106(1) to 106(4), LIO 124 is coupled to array 130 in the corresponding partition 108 and to array 130 in the corresponding partition 110 via signal lines including bank-wide access lines 132(1) and 132(2) (see [link]). Figure 2A Access lines 132(1) and 132(2) are group memory access lines. For the sake of simplicity, Figure 1 Not all such signal lines are shown (including all group width access lines 132(1) or all group width access lines 132(2)).

[0028] The global access manager 104 includes a global I / O (GIO) circuit 116, a global controller (GCNT) 114, and a GIO circuit 118. Regarding the X-axis, the GIO circuit 116 is separated from the GIO circuit 118 via the GCNT 114. Figure 1 Assume the following: GIO circuit 116 is adjacent to GCNT 114; and GCNT 114 is adjacent to GIO circuit 118. In some embodiments, GIO circuit 116 is close to GCNT 114, but not substantially adjacent to GCNT 114. In some embodiments, GCNT 114 is close to GIO circuit 118, but not substantially adjacent to GIO circuit 118.

[0029] exist Figure 1 In this configuration, the Global Access Manager 104 is coupled to bundles 102(1) and 102(2), respectively. More specifically, with respect to bundle 102(1), GIO 116 is coupled via signal lines including bundle-width access lines 134(1) and 134(2) to each of the LIO 122 in group 106(1) and LIO 122 in group 106(2) (see [link to relevant documentation]). Figure 2AAccess lines 134(1) and 134(2) are in-bundle signal lines because they do not extend into another bundle (e.g., bundle 102(2)). For the sake of simplicity, Figure 1 Not all such signal lines are shown (including all beamwidth access lines 134(1) or all beamwidth access lines 134(2)). Beamwidth access lines 134(1) and 134(2) include write lines and read lines, etc.

[0030] Regarding bundle 102(2), GIO 118 is coupled to each of LIO 124 in group 106(3) and LIO 124 in group 106(4) via signal lines including bundle width access lines 136(1) and 136(2) (see Figure 2A Access lines 136(1) and 136(2) are bundle access lines because they do not extend into another bundle (e.g., bundle 102(1)). For the sake of simplicity, Figure 1 Not all such signal lines are shown (including all beamwidth access lines 136(1) or all beamwidth access lines 136(2)). Beamwidth access lines 136(1) and 136(2) include write lines and read lines, etc.

[0031] Consider a memory according to another method, which is a counterpart of memory 100 and includes: a group of counterparts as groups 106(1) to 106(4), a GIO circuit as a counterpart of GIO circuits 116 and 118, a GCNT as a counterpart of GCNT 114, and a LIO as a counterpart of LIOs 122 and 124. Each counterpart of the GIO circuit is coupled to the corresponding GIO via a memory-wide signal line. Because each memory-wide signal line in the counterpart of the other method is coupled to each of the corresponding LIOs, the memory-wide signal lines in the counterpart of the other method extend into all the counterparts, making the memory-wide signal lines in the counterpart of the other method long.

[0032] As part of developing at least some of the memories disclosed herein, one or more inventors have recognized at least the following: because the memory wide signal lines according to another method are long, they experience significant RC loads, which reduce signal propagation speed, reduce signal quality, and increase power consumption, etc.; for example, about 20% of the power consumed during the read phase in the operation of the corresponding memory is consumed by the global bit lines of the corresponding memory; and there is an opportunity to reduce the signal line length compared to the memory according to another method. Therefore, at least some embodiments of this example (e.g., memory 100) reduce the length of the access lines by using bundle-width access lines (e.g., bundle-width access lines 134(1) to 134(2) and 136(1) to 136(2)), which improves signal propagation speed, improves signal quality, and reduces power consumption, etc., compared to the use of memory wide signal lines in the memory according to another method. In some embodiments, memory 100 reduces power consumption by about 13% compared to the memory according to another method. In some embodiments, the use of bundle-width access lines 134(1) to 134(2) and 136(1) to 136(2) by GIO 118 reduces the power consumption associated therewith by approximately 19% compared to the power consumption associated with the use of memory wide signal lines by the corresponding GIO according to another method.

[0033] Figure 2A This is a schematic diagram of the amplification section 246A of the memory 200A according to some embodiments.

[0034] Memory 200A is Figure 1 Example of memory 100. By acting as an amplification section, section 246A is compared to... Figure 1 The corresponding part is more detailed. Figure 2A and Figure 1 Similar. For the sake of brevity, the discussion will focus on Figure 2A and Figure 1 The difference is compared to the similarity. Figure 2A In and Figure 1 Components similar to those in the text use the same... Figure 1 The corresponding component has a series number similar to the series number 1 of the 2 series.

[0035] Figure 2AThe context of at least a portion of the write phase in the operation of memory 200A is assumed. Memory 200A includes: bundle 202; groups 206(1) to 206(2); instances of partition 208; instances of partition 210; instances of LCNT 220; instances of LIO 224; instances of line decoder & WL driver 226; instances of array 230; GCNT 214; and GIO 218. For simplicity of illustration, only one instance of partition 208 and only one instance of partition 210 are indicated by reference numerals.

[0036] Figure 2A Some components (e.g., instances of GCNT 214, GIO 218, LCNT 220, one instance of LIO 224, and one instance of array 230) are shown as internal components that include at least a portion of the write phase in the operation of memory 200A. For simplicity, instances of GCNT 214, GIO 218, LCNT 220, one instance of LIO 224 in group 206(1), and other internal components of array 230 in partition 208 of group 206(1) are not shown. Generally, grayscale format is used to illustrate. Figure 2A Components that are inactive in the context of at least a portion of the write phase discussed. Figure 2A In this context, each instance of LCNT 220 includes a corresponding instance of pulse generator 248.

[0037] Each instance of LIO 224 in bundle 202(1) is coupled to GIO 218 via bundle width write lines 260(1) and 260(2). Each instance of LIO 224 in bundle 202(2) is coupled to GIO 218 via bundle width write lines 260(3) and 260(4). Bundle width write line 260(1) carries the bundle write data signal BW_UP generated by GIO 218 (see Figure 3A (Discussed below). Beam width write line 260(2) carries the beam write data signal BW_UP_bar generated by GIO 218 (discussed below). The beam write data signal BW_UP_bar is the inverse of the beam write data signal BW_UP. Beam width write line 260(3) carries the beam write data signal BW_DN generated by GIO 218 (discussed below). Beam width write line 260(4) carries the beam write data signal BW_DN_bar generated by GIO 218. The beam write data signal BW_DN_bar is the inverse of the beam write data signal BW_DN.

[0038] exist Figure 2A In this context, instances of array 230 in partition 208 of group 206(1) include instances of bit cells 250. Figure 2AIn this context, it is assumed that bit cell 250 is a six-transistor (6T) static random access memory (SRAM) cell. In some embodiments, bit cell 250 is an SRAM bit cell comprising a plurality of transistors in addition to six transistors. In some embodiments, bit cell 250 is a bit cell of a type other than an SRAM bit cell. With respect to an instance of the line decoder & WL driver 226 in partition 208 of group 206(1), instances of word lines WL_U(0), WL_U(1), ... couple an instance of the line decoder & WL driver 226 to a corresponding instance of bit cell 250 in partition 208 of group 206(1).

[0039] Figure 2A An instance of LIO 224 in group 206(1) includes a first upper (uplink) multiplexer (MUX) and a first lower (or downlink) MUX. The first uplink MUX is coupled to an instance of bit cell 250 in array 230 of partition 208. The first downlink MUX is coupled to an instance of bit cell 250 in array 230 of partition 210 (not shown).

[0040] Each of the first uplink multiplexer and the first downlink multiplexer is coupled to the beamwidth write line 260(1) via a first inverter. That is, each of the first uplink multiplexer and the first downlink multiplexer is coupled to the output of the first inverter; and the input of the first inverter is coupled to the beamwidth write line 260(1). The first inverter inverts the beamwrite data signal BW_UP, and the inverted version of the beamwrite data signal BW_UP is referred to as the partial write data signal WT (see [link to relevant documentation]). Figure 3A ).

[0041] Each of the first uplink multiplexer and the first downlink multiplexer is also coupled to the beamwidth write line 260(2) via a second inverter. That is, each of the first uplink multiplexer and the first downlink multiplexer is coupled to the output of the second inverter; and the input of the second inverter is coupled to the beamwidth write line 260(2). The second inverter inverts the beamwrite data signal BWB_UP, and the inverted version of the beamwrite data signal BWB_UP is referred to as the partial write data signal WC.

[0042] exist Figure 2A In this configuration, GCNT 214 includes an address latch and decoder (AL&D) circuit 252 and a pulse generator 254. Each of the AL&D circuit 252 and the pulse generator 254 is configured to provide one or more corresponding signals to GIO 218.

[0043] Signal line 262(1) couples AL&D circuit 252 to each of the following: each instance of LCNT 220 in bundle 206(1); each instance of LCNT 220 in bundle 206(2); each instance of line decoder & WL driver 226 in bundle 206(1); and each instance of line decoder & WL driver 226 in bundle 206(2). Signal line 262(1) is a memory-wide signal line because signal line 262(1) extends beyond a single bundle and into at least one other bundle. Figure 2A Assume that signal line 262(1) extends into all bundles, that is, into bundles 206(1) and 206(2).

[0044] Signal line 262(2) couples pulse generator 254 to each of the following: each instance of LCNT 220 in bundle 206(1); and each instance of LCNT 220 in bundle 206(2). Signal line 262(2) is a memory-wide signal line. Figure 2A Assume that signal line 262(2) extends into all bundles, that is, into bundles 206(1) and 206(2).

[0045] exist Figure 2A In the GIO 218, there are: select gates 256(1), 256(2), 256(3) and 256(4); and drivers 258(1), 258(2), 258(3) and 258(4). Figure 2A Assume that each of the drivers 258(1) to 258(4) is an inverter. In some embodiments, drivers 258(1) to 258(4) are respectively powered by inverters. Figure 2A The components are composed of one or more different components. Inverter 258(1) is coupled between select gate 256(1) and beamwidth write line 260(1). Inverter 258(2) is coupled between select gate 256(2) and beamwidth write line 260(2). Inverter 258(3) is coupled between select gate 256(3) and beamwidth write line 260(3). Inverter 258(4) is coupled between select gate 256(4) and beamwidth write line 260(4). Figure 2A Assume that each of the selection gates 256(1) to 256(4) is a corresponding AND gate. In some embodiments, selection gates 256(1) to 256(4) are correspondingly composed of AND gates. Figure 2A The logic gates shown are composed of different logic gate arrangements.

[0046] Selection gate 256(1) is configured to receive a first discrimination signal. The first discrimination signal consists of a selection signal BW_PRE (see [link to selection gate]). Figure 3AThe signal is represented by a combination of the selection signal UD_SELB and the selection signal UD_SEL. The selection signal UD_SELB is the inverse of the selection signal UD_SEL (see [link to code]). Figure 3A In some embodiments, the selection signals UD_SEL and UD_SELB are generated by AL&D circuit 252.

[0047] Selection gate 256(2) is configured to receive a second discrimination signal. The second discrimination signal is represented by a combination of signals including selection signal UD_SELB and selection signal BWB_PRE. Selection signal BWB_PRE is the inverse of selection signal BWB_PRE. In some embodiments, selection signals BW_PRE and BWB_PRE are generated by AL&D circuit 252.

[0048] Selection gate 256(3) is configured to receive a third discrimination signal. The third discrimination signal is represented by a combination of signals including selection signal BW_PRE and selection signal UD_SEL. Selection gate 256(4) is configured to receive a fourth discrimination signal. The fourth discrimination signal is represented by a combination of signals including selection signal BWB_PRE and selection signal UD_SEL.

[0049] Based on the first to fourth beam discrimination signals, GIO 218 selectively accesses beams 202(1) and 202(2) on a mutually exclusive basis using selection gates 256(1) to 256(4). GIO 218 performs either of the following operations: (A) accesses beam 202(1) but not beam 202(2); or (B) accesses beam 202(2) but not beam 202(1). In other words, based on a combination of the described selection signals UD_SEL, UD_SELB, BW_PRE, or BWB_PRE, GIO 218 selectively accesses beams 202(1) and 202(2) on a mutually exclusive basis using selection gates 256(1) to 256(4). Figure 2A In the context of the operation of memory 200A, at least a portion of the write phase is discussed. Figure 3A This will be discussed in the context of [the subject] (see below).

[0050] Figure 2B This is a schematic diagram of the amplification section 246B of the memory 200B according to some embodiments.

[0051] Memory 200B is Figure 1 Example of memory 100. By acting as an amplification section, part 246B is larger than... Figure 1 The corresponding part is more detailed. Figure 2B and Figure 1 and Figure 2A Similar. For the sake of brevity, the discussion will focus on Figure 2B and Figure 1 and Figure 2A The comparison focuses on differences, not similarities. Figure 2A Same, Figure 2B In and Figure 1 Similar components in the text use the same components as... Figure 1 The corresponding component has a series number similar to the series number 1 of the 2 series.

[0052] Figure 2B Assuming at least a portion of the context of the read phase in the operation of memory 200B, and Figure 2A Assume the context of at least a portion of the write phase in the operation of memory 200A. In some embodiments, memory 200B is identical to memory 200A. Figure 2A and Figure 2B The differences in the components shown in the diagram stem from the simplification of the drawing to reflect the context of the corresponding read and write phases.

[0053] Figure 2B The instances of LIO 224 in group 206(1) include a second uplink MUX and a second downlink MUX. It can be seen that... Figure 2A The instances of LIO 224 in group 206(1) include: a first uplink MUX and a first downlink MUX. Figure 2B Examples of LIO 224 in group 206(1) also include: a sense amplifier SA and a selective pull-up / pull-down circuit 284.

[0054] The second uplink MUX is coupled to group data line 290(1) and group data line 290(2) through a corresponding first transmission gate, and the first transmission gate is controlled by the corresponding transmission gate control signal PGB_UP (see [link]). Figure 3B The control signal PGB_UP is the inverse of the transmission gate control signal PG_UP. Figure 2B Assume the first transmission gate used for the second uplink MUX is a field-effect transistor (FET), and more specifically a positive-channel metal-oxide-semiconductor (PMOS) FET (PFET). Therefore, the control signal PGB_UP, instead of the control signal PG_UP, is provided to the PFET.

[0055] An example of the second uplink MUX coupled to bit cell 250 in array 230 of partition 208. An example of the second downlink MUX coupled to bit cell 250 in array 230 of partition 210 (not shown). The second downlink MUX is also coupled to group data lines 290(1) and 290(2), but through a corresponding second transmission gate controlled by the transmission gate control signal PGB_DN. The control signal PGB_DN is the inverse of the transmission gate control signal PG_DN. Figure 2BAssume the second transmission gate for the second down-conversion MUX is a PFET. Therefore, the control signal PGB_DN, instead of the control signal PG_UP, is provided to the PFET.

[0056] In memory 200B, the input of sense amplifier SA is correspondingly coupled to group data line 290(1) and group data line 290(2), and sense amplifier SA receives the corresponding group data signals DL_IN and DLB_IN through group data line 290(1) and group data line 290(2). Figure 2B Assume that the control signal PGB_DN is the inverse of the control signal PGB_UP, such that the second downward MUX and the second upward MUX are mutually exclusive coupled to the sense amplifier SA. The sense amplifier SA is coupled to the beamwidth readout line 286 (1) via a selective pull-up / pull-down (SPUD) circuit 284. The sense amplifier SA is controlled by the sense amplifier control signal SAE. The SPUD circuit 284 is controlled by the control signal SAEC.

[0057] exist Figure 2B In this configuration, GIO 218 includes a multiplexer (MUX) 282. The inputs of MUX 282 are correspondingly coupled to beamwidth readout lines 286(1) and 286(2). Thus, beamwidth readout line 286(1) couples each instance of LIO 224 in beam 202(1) to GIO 218. Beamwidth readout line 286(2) couples each instance of LIO 224 in beam 202(2) to GIO 218. Therefore, MUX 282 is configured to receive: the beam bit line signal BBL_UP on beamwidth readout line 286(1); and the beam bit line signal BBL_DN on beamwidth readout line 286(2). Based on the first state of the MUX enable signal MUX_EN (not shown), the MUX 282 is enabled to select between the beam position line signal BBL_UP and the beam position line signal BBL_DN according to the control signal BBL_SEL (discussed below), and outputs the selected signal as the beam position output signal BB_OUT. The output of the MUX 282 is coupled to an inverter configured to generate an inverted version of the beam position output signal BB_OUT, which is referred to as the beam position bar output signal BB_OUT. Based on the second state of the MUX enable signal MUX_EN, the MUX 282 is disabled and cannot select between the beam position line signal BBL_UP or the beam position line signal BBL_DN.

[0058] The GIO 218 also includes latches 278(3) and 278(4). Each of latches 278(3) and 278(4) includes a tri-state inverter and an inverter coupled in a loop. In each of latches 278(3) and 278(4), the tri-state inverter is configured to receive a latch signal LAT and a latch signal LATB. The latch signal LATB is the inverse of the latch signal LAT.

[0059] exist Figure 2B In this circuit, GCNT 214 includes: AL&D circuitry 252; pulse generator 254; trigger (FF) 272; and delay line 276B. Generally, FF 272 is configured to receive the beamline tracking precursor signal TRK_PRE from AL&D circuitry 252 and output a delayed version of the signal TRK_PRE, referred to herein as signal TRK_PRE_D. Generally, delay line 288 is configured to receive signal TRK_PRE_D from FF 272 and generate control signal BBL_SEL.

[0060] FF 272 includes: a sleep pre-latch latch 272; a sleep follower latch 274; and a delay line 288. The sleep pre-latch latch 272 includes a first tri-state inverter coupled in series with an internal latch 278(1), wherein the internal latch 278(1) includes a second tri-state inverter and an inverter coupled in a first loop. The sleep pre-latch latch 272 is called a sleep-type latch because the pre-latch latch 278(1) can be selectively placed into sleep mode by coordinating the operating states of the first tri-state inverter and the second tri-state inverter.

[0061] The sleep follower latch 274 includes a tri-state inverter coupled in series with an internal latch 278(2), wherein the internal latch 278(2) includes a fourth tri-state inverter and an inverter coupled in a second loop. The sleep follower latch 274 is called a sleep latch because the follower latch 278(2) can be selectively placed into a sleep mode by coordinating the operating states of the third tri-state inverter and the fourth tri-state inverter.

[0062] Delay line 288 is series-coupled between sleep pre-latch 272 and sleep follower latch 274. Delay line 288 includes one or more inverters series-coupled. Figure 2B Assume that the number of inverters including delay line 288 is three. In some embodiments, delay line 288 includes a number of inverters other than three, depending on the magnitude of the delay to be caused by delay line 288. In some embodiments, delay line 288 is not an inverter-based circuit.

[0063] The sleep pre-signal latch 272 is configured to receive the signal TRK_PRE and generate a first delayed version of the signal TRK_PRE. The delay line 288 is configured to receive the first delayed version of the signal TRK_PRE and generate a second delayed version of the signal TRK_PRE. The sleep follower latch 274 is configured to receive the second delayed version of the signal TRK_PRE and generate a third delayed version of the signal TRK_PRE, wherein the third delayed version of the signal TRK_PRE represents the signal TRK_PRE_D.

[0064] FF 272 is configured to receive a trigger signal TRGR from pulse generator 254 (see [link]). Figure 3B In some embodiments, the trigger signal TRGR controls the sleep follower latch 274 to receive a second delayed version of the signal TRK_PRE and output a third delayed version of the signal TRK_PRE. In some embodiments, the output of the third delayed version of the signal TRK_PRE (i.e., the generation of the signal TRK_PRE_D) is represented by changing the state of the signal TRK_PRE_D. In some embodiments, the trigger signal TRGR (see...) Figure 3B The signal changes from a state representing logic zero to a state representing logic one, and then the signal TRK_PRE_D( Figure 3A (Not shown in the image) changes from logic zero to logic one, then tracks the signal BBL_TRK (discussed below; see also...) Figure 3B (From logical zero to logical one)

[0065] The FF enable signal FF_EN (not shown) controls the active state of FF 272. For example, when the FF enable signal FF_EN transitions to the active state, FF 272 is active; and when the FF enable signal FF_EN transitions to the inactive state, FF 272 is inactive. The FF enable signal FF_EN transitions to the active state, for example, at the start of the read phase in the operation of memory 200B.

[0066] MUX 282 is enabled to select between the beamline signal BBL_UP and the beamline signal BBL_DN based on the control signal BBL_SEL (discussed below). The output of MUX 282 (discussed below) is coupled to an inverter. Based on the second state of the MUX enable signal MUX_EN, MUX 282 is disabled and cannot be selected between the beamline signal BBL_UP or the beamline signal BBL_DN.

[0067] Delay line 276B includes a tracking line 280B series-coupled between a first inverter and a second inverter. The first inverter receives the signal TRK_PRE_D and generates a tracking signal BBL_TRK, which is a delayed and inverted version of the former. The second inverter receives the tracking signal BBL_TRK and generates a control signal BBL_SEL, which is also a delayed and inverted version of the former.

[0068] In some embodiments, the tracking line 280B is a signal path consisting of one or more conductive segments. When the tracking signal BBL_TRL propagates along the tracking line 280B, the cumulative length of the one or more conductive segments (i.e., the length of the tracking line 280B) causes a delay in the tracking signal BBL_TRL. When the control signal BBL_SEL is the inverse of the tracking signal BBL_TRL, the delay in the tracking signal BBL_TRL causes a corresponding delay in the control signal BBL_SEL.

[0069] The length of the tracking line 280B is selected such that the delayed tracking signal BBL_TRK causes the control signal BBL_SEL to change state after either of the following conditions, resulting in a valid operation: (A) the bundle bit line signal BBL_UP has changed state in the context of accessing bundle 202(1) or (B) the bundle bit line signal BBL_DN has changed state in the context of accessing bundle 202(1). However, if the length of the tracking line 280B is insufficient, the delayed tracking signal BBL_TRK will not cause a sufficient delay in the control signal BBL_SEL to change state before either of the following conditions, resulting in an invalid operation (i.e., causing a glitch): (A) the bundle bit line signal BBL_UP has changed state in the context of accessing bundle 202(1) or (B) the bundle bit line signal BBL_DN has changed state in the context of accessing bundle 202(1). Figure 2B It is also assumed that bundles 202(1) and 202(2) are substantially symmetrical, such that the propagation delay experienced by the bundle position line signal BBL_UP on the bundle width readout line 286(1) is substantially the same as the propagation delay experienced by the bundle position line signal BBL_DN on the bundle width readout line 286(2). For the context of the substantially asymmetric nature of bundles 202(1) and 202(2) such that the propagation delay experienced by the bundle position line signal BBL_UP on the bundle width readout line 286(1) is substantially different from the propagation delay experienced by the bundle position line signal BBL_DN on the bundle width readout line 286(2), see [link to relevant documentation]. Figure 2E wait.

[0070] In some embodiments, the length L_280 of the tracking line 280B is about half the length L_286(1) of the bundle width readout line 286(1), such that L_280≈1 / 2*L_286(1).

[0071] The length of the beamwidth reading line 286(1) is substantially equal to the length of the beamwidth reading line 286(2), such that L_286(2)≡L_286(1), and the symbol ≡ is used herein to denote substantially equal. As used herein, substantially equal is understood to be more equal than approximately equal, that is, substantially equal is understood to represent a smaller difference than is understood to be represented by approximately equal. As used herein, substantially equal is understood to cover a difference in a first range, and approximately equal is understood to cover a difference in a second range, wherein the second range is larger than the first range and the second range includes the first range. Therefore, the length of the tracking line 280B is also approximately half the length of the beamwidth reading line 286(2), such that L_280≈1 / 2*L_286(2).

[0072] Based on the control signal BBL_SEL, the GIO 218 uses the MUX 282 to selectively access bundles 202(1) and 202(2) on a mutually exclusive basis. The GIO 218 performs either of the following operations: (A) accessing bundle 202(1) but not accessing bundle 202(2); or (B) accessing bundle 202(2) but not accessing bundle 202(1). Figure 2B In the context of the operation of memory 200B, at least a portion of the read phase is discussed. Figure 3B This will be discussed in the context of [the subject] (see below).

[0073] Figure 2C This is a schematic diagram of the amplification section 246C of the memory 200C according to some embodiments.

[0074] Figure 2C The memory 200C is Figure 2B Version 200B of the memory; thus, memory 200C is Figure 1 An example of memory 100. For the sake of brevity, the discussion will focus on Figure 2C and Figure 2B The difference is compared to the similarity.

[0075] exist Figure 2C In the middle, delay line 276C and tracking line 280C have been replaced accordingly. Figure 2B The delay line 276B and the tracking line 280B.

[0076] In some embodiments, the length of the tracing line 280C is sufficient to extend into one of the instances of LIO 224 in the bundle 202(1). Figure 2C In this example, it is assumed that the length of the tracing line 280C is sufficient to extend into the instance of LIO 224 in group 206(2) of bundle 202(1).

[0077] Figure 2C Assuming that bundles 202(1) and 202(2) are substantially symmetrical, such that the propagation delay experienced by the bundle position line signal BBL_UP on the bundle width readout line 286(1) is substantially the same as the propagation delay experienced by the bundle position line signal BBL_DN on the bundle width readout line 286(2). For the context regarding the substantially asymmetric nature of bundles 202(1) and 202(2) such that the propagation delay experienced by the bundle position line signal BBL_UP on the bundle width readout line 286(1) is substantially different from the propagation delay experienced by the bundle position line signal BBL_DN on the bundle width readout line 286(2), see [link to relevant documentation]. Figure 2E wait.

[0078] Figure 2D This is a schematic diagram of the amplification section 246D of the memory 200D according to some embodiments.

[0079] Figure 2D The memory 200D is Figure 2B Version 200B of the memory; thus, memory 200D is Figure 1 An example of memory 100. For the sake of brevity, the discussion will focus on Figure 2D and Figure 2B The difference is compared to the similarity.

[0080] exist Figure 2D In the middle, delay line 276D and tracking line 280D have been replaced accordingly. Figure 2B Delay line 276B and tracking line 280B, etc.

[0081] In some embodiments, the length of the tracing line 280D is sufficient to extend into one of the instances of LIO 224 in the bundle 202(2). Figure 2D In this example, it is assumed that the length of the tracing line 280D is sufficient to extend into the instance of LIO 224 in group 206(3) of bundle 202(2).

[0082] Figure 2D Assuming that bundles 202(1) and 202(2) are substantially symmetrical, such that the propagation delay experienced by the bundle position line signal BBL_UP on the bundle width readout line 286(1) is substantially the same as the propagation delay experienced by the bundle position line signal BBL_DN on the bundle width readout line 286(2). For the context regarding the substantially asymmetric nature of bundles 202(1) and 202(2) such that the propagation delay experienced by the bundle position line signal BBL_UP on the bundle width readout line 286(1) is substantially different from the propagation delay experienced by the bundle position line signal BBL_DN on the bundle width readout line 286(2), see [link to relevant documentation]. Figure 2E wait.

[0083] Figure 2EThis is a schematic diagram of the amplification section 246D of the memory 200D according to some embodiments.

[0084] Figure 2E The memory 200E is Figure 2B Version 200B of the memory; thus, version 200E is Figure 1 An example of memory 100. For the sake of brevity, the discussion will focus on Figure 2E and Figure 2B The comparison is based on differences, not similarities. In some embodiments, Figure 2E Described as Figure 2C and Figure 2D The combination of .

[0085] exist Figure 2E middle: Figure 2C The delay line 276C and Figure 2D The delay line 276D has been replaced. Figure 2B The delay line 276B; and Figure 2C The tracking line 280C and Figure 2D The 280D tracking line has been replaced. Figure 2B The tracking line 280B. Correspondingly with Figures 2C to 2D Compared to delay lines 276C and 276D, Figure 2E The delay line 276E also includes a switch 277, which is configured to selectively couple either the tracking line 280C or the tracking line 280D between the first inverter and the second inverter of the delay line 276E.

[0086] Figure 2E Assume that bundles 202(1) and 202(2) are substantially asymmetrical, such that the propagation delay experienced by the bundle bit line signal BBL_UP on the bundle width readout line 286(1) is substantially different from the propagation delay experienced by the bundle bit line signal BBL_DN on the bundle width readout line 286(2). Figure 2E In this example, we assume the following: the length of tracking line 280C is substantially different from the length of tracking line 280D. More specifically, Figure 2E The example assumes that the length of trace line 280C is sufficient to extend all the way through an instance of LIO 224 in group 206(2) of bundle 202(1); and that the length of trace line 280D is sufficient to extend slightly into an instance of LIO 224 in group 206(3) of bundle 202(2). For the context of bundles 202(1) and 202(2) being substantially symmetrical such that the propagation delay experienced by the beam bit line signal BBL_UP on the beam width readout line 286(1) is substantially the same as the propagation delay experienced by the beam bit line signal BBL_DN on the beam width readout line 286(2), see [context missing]. Figures 2B to 2D wait.

[0087] Figure 3AIt is a timing diagram based on some embodiments.

[0088] Figure 3A The timing diagram includes the time series diagrams with .... Figure 2A The waveforms related to at least a portion of the write phase in the operation of the memory 200A are discussed in the context of this discussion.

[0089] More specifically, Figure 3A The timing diagram includes the following waveforms: the waveform representing the clock CLK; the waveform representing the select signal UD_SEL; the waveform representing the clock CKP_W; the waveform representing the beam write precursor signal BW_PRE; the waveform representing the beam width write data signal BW_UP; the waveform representing the partial write data signal WT; the waveform representing the beam bit line control signal BBL; and the waveform representing the beam word line signal BWL. The clock signal CLK is the global clock signal. The clock signal CKP_W is the write phase signal based on the clock signal CLK.

[0090] Figure 3B It is a timing diagram based on some embodiments.

[0091] Figure 3B The timing diagram includes the time series diagrams with .... Figure 2B The waveforms related to at least a portion of the read phase in the operation of memory 200B discussed in the context of this discussion.

[0092] More specifically, Figure 3B The timing diagram includes the following waveforms: the waveform representing the clock CLK; the waveform representing the clock CKP_R; the waveform representing the bundle word line signal BWL; the waveform representing the bundle bit line control signal BBL; the waveform representing the transmission gate control signal PGB_UP; the waveform representing the sense amplifier control signal SAE; the waveform representing the group data signal DL_IN; the waveform representing the latch signal LAT; the waveform representing the control signal SAEC; the waveform representing the bundle bit line signal BBL_UP; the waveform representing the feedback signal BBL_FB_UP based on the signal BBL_UP; the waveform representing the control signal BBL_SEL; the waveform representing the tracking signal BBL_TRK; and the waveform representing the trigger signal TRGR.

[0093] The clock signal CKP_R is the read phase signal based on the clock signal CLK. The signal BBL_FB_UP is the inverted and delayed version of the signal BBL_FB_UP. Once the feedback signal BBL_FB_UP has become stable, it indicates that the signal BBL_UP has become stable, and then the latch 278(3) is opened, that is, activated to store the value of the signal BBL_UP.

[0094] Figure 4 It is a timing diagram based on some embodiments.

[0095] Figure 4 The timing diagram includes the time series diagrams with .... Figure 2A The context of discussing at least a portion of the write phase in the operation of memory 200B and related to... Figure 2B The waveforms related to at least a portion of the read phase in the operation of memory 200B discussed in the context of this discussion.

[0096] More specifically, Figure 4 The timing diagram includes the following waveforms: a waveform representing the clock CLK; a waveform representing the write enable bar signal WEB; a waveform BW_ADDR, which indicates (i) group 206(1) or 206(2) of bundle 202(1) or (ii) group 206(3) or 206(4) of bundle 202(2) is being addressed; a waveform representing the trigger signal TRGR; a waveform representing the control signal BBL_SEL; a waveform representing the bundle bit line signal BBL_UP; a waveform representing the bundle bit line signal BBL_DN; and a waveform representing the bundle bit output signal BB_OUT. The write enable bar signal WEB is the inverse of the write enable bar signal WE (not shown).

[0097] Figure 5 This is a flowchart 500 of a method for manufacturing a memory according to some embodiments.

[0098] Flowchart 500 is an example of box 704 (see Figure 7 (Discussed below). According to some embodiments, the method of flowchart 600 can, for example, use IC manufacturing system 900 (see...). Figure 9 (This will be discussed below) to achieve this. Examples of memories that can be manufactured according to the method of flowchart 500 include the memories disclosed herein. Flowchart 500 includes blocks 502 to 514.

[0099] At box 502, a structure is formed, comprising components including memory cells, local access managers, and global access managers. Examples of structures including the described components are discussed below. Examples of memory cells include... Figures 2A to 2B Bit unit 250, etc. Examples of local access managers include... Figure 1 Examples of local access managers, such as 112, etc. An example of a global access manager is... Figure 1 Global access manager 104, etc. Box 502 includes boxes 504 to 508. Within box 502, the process proceeds to box 504.

[0100] Regarding block 502, examples of structures including the described components include: structures including semiconductor devices (e.g., transistors), structures facilitating coupling to transistors, etc. In some embodiments, the structure including the transistor and the structure facilitating coupling to the transistor are formed in one or more first layers, which are collectively referred to as transistor layers. Examples of transistors include PFETs, negative channel metal-oxide-semiconductor (NMOS) FETs (NFETs), etc.

[0101] Regarding block 502, examples of transistor structures include: an active region in a semiconductor layer; a well region surrounding a selected active region; a source / drain (S / D) region in the active region; a channel region in the active region located between corresponding S / D region pairs; a gate structure located above the corresponding active region and (optionally) a buried gate (BG) structure located below the corresponding active region; and so on.

[0102] Regarding block 502, examples of structures that facilitate coupling to transistors include: metal-to-source / drain (MD) contacts located above and coupled to the S / D region, and (optionally) corresponding buried MD (BMD) contacts located below and coupled to the S / D region; metal-to-gate (MG) contacts coupled to the gate structure, and (optionally) corresponding buried MG (BMG) contacts coupled to the BG structure; via-to-MD (VD) contacts coupled to MD contacts, and corresponding buried VD (BVD) contacts coupled to BMD contacts; via-to-MG (VG) contacts coupled to MG contacts, and corresponding buried VG (BVG) contacts coupled to BMG contacts; local interconnect (LI) structures that couple, for example, MD contacts and / or gate structures together, and (optionally) buried LI (BLI) structures that couple, for example, BMD contacts and / or BG gate structures together; and so on.

[0103] At box 504, a first component of the assembly including the memory cell is arranged into a first group, a second group, a third group, and a fourth group stacked on top of each other relative to a first direction. Examples of the first to fourth groups correspondingly include: stacked on top of each other relative to the Y-axis. Figure 1 Groups 106(1) to 106(4), stacked relative to the Y-axis Figures 2A to 2B Groups 206(1) to 206(4), etc. Box 506 includes boxes 506 to 508. Within box 504, the process proceeds to box 506.

[0104] At box 506, the α and β components of the first component including the memory cell are arranged into the corresponding first and second partitions. Examples of the first and second partitions include those corresponding to... Figure 1Partitions 108 and 110 of each group in groups 106(1) to 106(4). From box 506, the process proceeds to box 508.

[0105] At box 508, arrange (A) the first and second groups, and (B) the third and fourth groups, into the corresponding first and second bundles. An example of the first bundle is... Figure 1 Bundle 102(1) (which includes groups 106(1) and 106(2)), etc. An example of the second bundle is... Figure 1 Bundle 102(2) (which includes embankments 106(3) and 106(4)), etc. From box 508, the process exits box 504 and proceeds to box 510.

[0106] At box 510, the second component of the components including the local access manager is arranged such that for each of the first through fourth groups, the first and second partitions are separated from each other relative to a first direction. Examples of local access managers that separate the corresponding first and second partitions include: instances of local access managers 112 that separate partitions 108 and 110 of group 106(1) relative to the Y-axis; instances of local access managers 112 that separate partitions 108 and 110 of group 106(2) relative to the Y-axis; instances of local access managers 112 that separate partitions 108 and 110 of group 106(3) relative to the Y-axis; instances of local access managers 112 that separate partitions 108 and 110 of group 106(4) relative to the Y-axis; and so on. From box 512, the process exits box 502 and proceeds to box 514.

[0107] At box 514, mutual coupling is formed between components, such that at least the first & second bundle-width write lines or the first & second bundle-width read lines couple the global access manager to the first and second bundles, respectively. Examples of the first & second bundle-width write lines include: Figure 2A The beam width is written to lines 260(1) & 260(3). Figure 2A The beamwidth write lines are 260(3) & 260(4), etc. Examples of the first & second beamwidth read lines include Figure 2B The beam width reading lines are 286(1) & 286(2), etc.

[0108] Regarding block 514, examples of forming mutual coupling include forming wiring segments and / or grid (PG) segments in metallization layers correspondingly located above and (optionally) below the transistor layer. The wiring segments and PG segments are conductive. In some embodiments, these segments are configured to carry signals including input / output (I / O) signals, control signals, etc. In such embodiments, the wiring segments are correspondingly coupled to VD contacts, MG contacts, (optionally) BVD contacts, (optionally) BVG contacts, etc. In some embodiments, the PG segments are configured to be energized using a corresponding reference voltage in the grid (PG) reference voltage. In such embodiments, the PG segments are correspondingly coupled to VD contacts, MG contacts, (optionally) BVD contacts, (optionally) BVG contacts, etc. For example, a first PG segment of such PG segments is configured to be energized using a first reference voltage (e.g., VDD), and a second PG segment of such PG segments is configured to be energized using a second reference voltage (e.g., VSS).

[0109] Regarding block 512, in some embodiments, the arrangement of a third component in the components including a global access manager (e.g., 104) includes configuring the global access manager (e.g., 104) to access the first bundle (e.g., 102(1)) and the second bundle (e.g., 102(2)) on a mutually exclusive basis.

[0110] Regarding block 502, in some embodiments, forming the structure including components further includes: using an α component in a third component including a global access manager (e.g., 104) to form a first global I / O circuit (e.g., 116) and a second global I / O circuit (e.g., 118); using a β component in a third component including a global access manager (e.g., 104) to form a global controller (e.g., 114); and arranging the β component in a third component including a global access manager (e.g., 104) such that the global controller (e.g., 114) separates the first global I / O circuit (e.g., 116) and the second global I / O circuit (e.g., 118) relative to a second direction (e.g., X-axis) perpendicular to a first direction (e.g., Y-axis).

[0111] Regarding block 512, in some embodiments, using a β component in a third component including a global access manager (e.g., 104) to form a global controller (e.g., 114) includes: arranging a first component in the β component to include a first selection gate (e.g., 256(1)); arranging a second component in the β component to include a second selection gate (e.g., 256(3)); arranging a third component in the β component to include a first driver (e.g., 258(1)); and arranging a fourth component in the β component to include a second driver (e.g., 258(3)). Also regarding block 512, in some embodiments, forming (e.g., 604) mutual coupling between components also results in at least: a first select gate (e.g., 256(1)) being configured to receive a first beam select signal (e.g., UD_SELB+BW_PRE); a second select gate (e.g., 256(3)) being configured to receive a second beam select signal (e.g., UD_SEL+BW_PRE); a first driver (e.g., 258(1)) being coupled between the first select gate (e.g., 256(1)) and a first beam wide write line (e.g., 260(1)); and a second driver (e.g., 258(3)) being coupled between the second select gate (e.g., 256(3)) and the second beam wide write line (e.g., 260(3)).

[0112] Also regarding block 512, in some embodiments: the first bundle selection signal (e.g., UD_SELB+BW_PRE) includes a first selection signal (e.g., UD_SELB) and a second selection signal (e.g., BW_PRE); and the second bundle selection signal (e.g., UD_SEL+BW_PRE) includes a second selection signal (e.g., BW_PRE) and a third selection signal (e.g., UD_SEL). Also regarding block 512, in some embodiments, forming (e.g., 604) mutual coupling between components also results in at least: a first selection gate (e.g., 256(1)) being configured as a first AND gate and also configured to receive the first selection signal (e.g., UD_SELB) and the second selection signal (e.g., BW_PRE); and a second selection gate (e.g., 256(3)) being configured as a second AND gate and also configured to receive the second selection signal (e.g., BW_PRE) and the third selection signal (e.g., UD_SEL).

[0113] Regarding block 506, in some embodiments, using a β component of a third component including a global access manager (e.g., 104) to form a global controller (e.g., 214) further includes: arranging a fifth component of the β component to include a third selection gate (e.g., 256(2)); arranging a sixth component of the β component to include a fourth selection gate (e.g., 256(4)); arranging a seventh component of the β component to include a third driver (e.g., 258(2)); and arranging an eighth component of the β component to include a fourth driver (e.g., 258(4)). Also regarding block 512, in some embodiments, the mutual coupling formed between components (e.g., 604) also results in at least the following: a third beamwidth write line (e.g., 286(1)) and a fourth beamwidth write line (e.g., 260(4)) couple the global access manager (e.g., 104) to the first beam (e.g., 102(1)) and the second beam (e.g., 102(2)), respectively; and a third select gate (e.g., 256(2)) is operable to receive a third select signal (e.g., signals UD_SELB and GWB). _PRE); a fourth select gate (e.g., 256(4)) is operable to receive a fourth select signal (e.g., signal UD_SEL and signal GWB_PRE); a third driver (e.g., 258(2)) is coupled between the third select gate (e.g., 256(2)) and the third beamwidth write line (e.g., 286(1)); and a fourth driver (e.g., 258(4)) is coupled between the third select gate (e.g., 256(4)) and the fourth beamwidth write line (e.g., 260(4)).

[0114] Regarding block 506, in some embodiments, using a β component in a third component including a global access manager (e.g., 104) to form a global controller (e.g., 214) further includes: arranging a first component in the β component to include a trigger (e.g., 272); and arranging a second component in the β component to include a first delay line (e.g., 276B). Also regarding block 512, in some embodiments, forming (e.g., 604) mutual coupling between components further results in at least: the trigger (e.g., 272) being configured to receive a first beam selection signal (e.g., TRK_PRE); and the first delay line (e.g., 276B) being coupled to the trigger (e.g., 272) and configured to generate a second beam selection signal (e.g., BBL_SEL) based on the output signal (e.g., TRK_PRE_D) of the trigger (e.g., 272).

[0115] Regarding block 506, in some embodiments, using a β component among a third component including a global access manager (e.g., 104) to form a global controller (e.g., 214) further includes arranging the third component among the β components to include a second delay line (e.g., 288). Also regarding block 512, in some embodiments, forming (e.g., 604) mutual coupling between components also at least results in the second delay line (e.g., 288) being coupled between a leading latch (e.g., 272) and a following latch (e.g., 274).

[0116] Regarding block 506, in some embodiments, using a β component from a third component including a global access manager (e.g., 104) to form a global controller (e.g., 214) further includes: arranging the third component in the β component to include a first inverter (e.g., a first INV of 276B); and configuring a fourth component in the β component to include a second inverter (e.g., a second INV of 276B). Also regarding block 512, in some embodiments, forming (e.g., 604) mutual coupling between components also at least results in a trace line (e.g., 280B) being cascaded coupled between the first inverter (e.g., the first INV of 276B) and the second inverter (e.g., the second INV of 276B).

[0117] Figure 6A This is a flowchart (flowchart) of a method 600 for operating a memory according to some embodiments.

[0118] Examples of memories operable according to method 600 include the memories disclosed herein. Method 600 includes block 602.

[0119] At box 602, the first and second bundles of memory are accessed on a mutually exclusive basis, wherein: the first bundle & the second bundle correspondingly include (A) a first group and a second group of memory and (B) a third group and a fourth group of memory; the first group to the fourth group are stacked on top of each other and are respectively composed of memory cells, and each group includes a first partition and a second partition separated from each other by a local access manager; the memory includes a global access manager that separates the first bundle and the second bundle; and the global access manager is coupled to the first bundle and the second bundle respectively by a corresponding first bundle-width write line & second bundle-width write line or a corresponding first bundle-width read line & second bundle-width read line.

[0120] Regarding box 602, examples of the first and second bundles are correspondingly included. Figure 1 Bundles 102(1) and 102(2), Figures 2A to 2B Bundles 202(1) and 202(2), etc. An example of the second bundle is... Figure 1Bundle 102(2) (which includes embankments 106(3) and 106(4)), etc. Examples of accessing the first and second bundles on a mutually exclusive basis include those mentioned above. Figure 2A The discussion of GIO 218 in the context of the above text Figure 2B Discussions of GCNT 218 and GIO 218 in the context of [the relevant context].

[0121] Similarly, regarding box 602, the examples in the first through fourth groups correspondingly include those stacked on top of each other relative to the Y-axis. Figure 1 Groups 106(1) to 106(4), stacked relative to the Y-axis Figures 2A to 2B Groups 206(1) to 206(4), etc. An example of the first bundle including two groups is... Figure 1 Bundle 102(1) (which includes groups 106(1) and 106(2)), etc. An example of a second bundle including two groups is... Figure 1 Bundle 102(2) (which includes libraries 106(3) and 106(4)), etc. Examples of the first and second partitions include those corresponding to Figure 1 The partitions of each group in groups 106(1) to 106(4) are 108 and 110, etc.

[0122] Similarly, regarding box 602, examples of structures include components such as memory cells, local access managers, and global access managers. Examples of structures including the described components are discussed below. Examples of memory cells include... Figures 2A to 2B Bit unit 250, etc. Examples of local access managers include... Figure 1 Examples of local access managers, such as 112, etc. An example of a global access manager is... Figure 1 Global Access Manager 104, etc.

[0123] Similarly, regarding box 602, an example of the global access manager is... Figure 1 The global access manager 104 (which separates bundle 102(1) from bundle 102(2)) etc. Examples of first & second bundle-width write lines include: Figure 2A The beam width is written to lines 260(1) & 260(3). Figure 2A The beamwidth write lines are 260(3) & 260(4), etc. Examples of the first & second beamwidth read lines include Figure 2B The beam width reading lines are 286(1) & 286(2), etc.

[0124] Regarding box 602, the above text... Figure 5 The context of box 502 discusses examples of structures including the described components. Regarding box 514, the above text... Figure 5 Examples of mutual coupling are discussed in the context of box 514.

[0125] about Figure 6A In some embodiments, accessing the first bundle (e.g., 102(1)) and the second bundle (e.g., 102(2)) of the memory on a mutually exclusive basis further includes: receiving a first bundle discrimination signal (e.g., UD_SELB+BW_PRE) at a first select gate (e.g., 256(1)) which is included in a global access manager (e.g., 104); providing the output signal of the first select gate (e.g., 256(1)) to a first driver (e.g., 258(1)) coupled between the first select gate (e.g., 256(1)) and the first bundle wide write line (e.g., 260(1));

[0126] A second beam discrimination signal (e.g., UD_SEL+BW_PRE) is received at a second select gate (e.g., 256(3)), which is included in a global access manager (e.g., 104); the output signal of the second select gate (e.g., 256(3)) is provided to a second driver (e.g., 258(3)), which is coupled between the second select gate (e.g., 256(3)) and the second beam wide write line (e.g., 260(3)).

[0127] about Figure 6A In some embodiments: the first beam discrimination signal (e.g., UD_SELB+BW_PRE) includes a first selection signal (e.g., UD_SELB) and a second selection signal (e.g., BW_PRE); the second beam discrimination signal (e.g., UD_SEL+BW_PRE) includes a second selection signal (e.g., BW_PRE) and a third selection signal (e.g., UD_SEL); the first selection gate (e.g., 256(1)) is a first AND gate; the second selection gate (e.g., 256(3)) is a second AND gate. In some embodiments, accessing the first bundle (e.g., 102(1)) and the second bundle (e.g., 102(2)) of the memory on a mutually exclusive basis further includes: providing a second selection signal (e.g., BW_PRE) to each of the first AND gate (e.g., 256(1)) and the second AND gate (e.g., 256(3)); providing a first selection signal (e.g., UD_SELB) to the first AND gate (e.g., 256(1)); and providing a third selection signal (e.g., UD_SEL) to the second AND gate (e.g., 256(3)).

[0128] about Figure 6AIn some embodiments, accessing the first bundle (e.g., 102(1)) and the second bundle (e.g., 102(2)) of the memory on a mutually exclusive basis further includes: receiving a first bundle selection signal (e.g., TRK_PRE) at a flip-flop (e.g., 272), the flip-flop (e.g., 272) being included in a global controller (e.g., 214), the global controller being included in a global access manager (e.g., 104); and generating a second bundle selection signal (e.g., BBL_SEL) using a first delay line (e.g., 276B) based on the output signal (e.g., TRK_PRE_D) of the flip-flop (e.g., 272), the first delay line (e.g., 276B) being included in the global controller (e.g., 214) and coupled to the flip-flop (e.g., 272).

[0129] about Figure 6A In some embodiments, accessing the first bundle (e.g., 102(1)) and the second bundle (e.g., 102(2)) of the memory on a mutually exclusive basis further includes: receiving a second bundle selection signal (e.g., BBL_SEL) from a preamble latch (e.g., 272) at a second delay line (e.g., 288), the second delay line (e.g., 288) and the preamble latch (e.g., 272) being included in a flip-flop (e.g., 272); using the second delay line (e.g., 288) to delay the second bundle selection signal (e.g., BBL_SEL); and receiving the second bundle selection signal (e.g., BBL_SEL) from the second delay line (e.g., 288) at a follower latch (e.g., 274), the follower latch (e.g., 274) also being included in a flip-flop (e.g., 272), and the output signal of the follower latch (e.g., 274) representing the output signal of the flip-flop (e.g., 272) (e.g., TRK_PRE_D).

[0130] about Figure 6AIn some embodiments, using a first delay line (e.g., 276B) to generate a second beam selection signal (e.g., BBL_SEL) includes: using a first delay line (e.g., 288) to delay the output signal (e.g., TRK_PRE_D) of a trigger (e.g., 272), resulting in a delayed version of the output signal (e.g., TRK_PRE_D) of the trigger (e.g., 272), which is the second beam selection signal (e.g., BBL_SEL). In some embodiments, using a first delay line (e.g., 288) to delay the output signal (e.g., TRK_PRE_D) of a trigger (e.g., 272) includes: propagating the output signal (e.g., TRK_PRE_D) of the trigger (e.g., 272) through a trace line (e.g., 280B), and wherein: the trace line (e.g., 280B) has a first length sufficient to cause the propagation delay through the trace line to shape the second beam selection signal (e.g., BBL_SEL) into a shape greater than that correspondingly on the first beam width readout line (e.g., 286(1)) or the second beam width readout line. The first signal (e.g., BBL_UP) or the second signal (e.g., BBL_DN) on the line (e.g., 286(2)) is slower; and the first wide read line (e.g., 286(1)) and the second wide read line (e.g., 286(2)) have a second length (e.g., L_286(1)) and a third length (e.g., L_286(2)), the second length (e.g., L_286(1)) and the third length (e.g., L_286(2)) correspondingly exhibit a second propagation delay and a third propagation delay proportional to the first wide read line and the second wide read line.

[0131] Figure 6B This is a flowchart (flowchart) of a method for writing to memory according to some embodiments.

[0132] Figure 6B Provided Figure 6A Details of the example for box 602 are available. Figure 6B Examples of memory operated by the methods described herein include the memory disclosed herein (e.g., Figure 2B Memory 200B, etc. With Figure 6B The corresponding timing diagram example is Figure 3B The timing diagram (and the waveforms included therein), etc. Therefore, it will be... Figure 2B and Figure 3B The context of the explanation Figure 6B The discussion. In Figure 6B In the middle, box 602 includes boxes 624 to 634.

[0133] At box 624, the control signal SAE causes the sensing amplifier (e.g., Figure 2BBefore the SA in the signal can be sensed, the transmission gate control signal PGB_UP is lowered, which will correspondingly couple the data stored in the corresponding instance of bit cell 250 to the input of the sense amplifier SA. From block 624, the flow proceeds to block 626.

[0134] At box 626, the control signal SAE is raised to enable the sense amplifier (e.g., Figure 2B The SA in the middle can be sensed. Then, it makes it possible to... Figure 3B In the context of the example, the group data signal DL_IN decreases. From box 628, the flow proceeds to box 628.

[0135] At block 628, in response to a drop in the latch signal LAT, the value in latch 278 is released. In some embodiments, releasing the value in latch 278 is described as clearing the value in latch 278. In some embodiments, releasing the value in latch 278 is described as resetting the value in latch 278. Then the control signal SAEC drops, which causes the SPUD circuit 284 to connect / couple the output of the sense amplifier SA to the beamwidth readout line 286(1), which allows... Figure 3B In the context of the example, the bit line signal BBL_UP rises. The rise of the bit line signal BBL_UP causes the feedback signal BBL_FB_UP to fall. Furthermore, shortly after the control signal SAEC falls, the trigger signal TRGR rises, which causes the track signal BBL_TRK to rise. From box 628, the flow proceeds to box 630.

[0136] At box 630, after the bit line signal BBL_UP has reached a stable state, the control signal BBL_SEL is decremented, which causes the MUX 282 to select the beam bit line signal BBL_UP on beam width readout line 286(1). Figure 3B In the context of the example: when the control signal BBL_SEL is in a logic high state, multiplexer 282 is configured to select the bundle bit line signal BBL_DN; and when the control signal BBL_SEL is in a logic low state, MUX 282 is configured to select the bundle bit line signal BBL_UP. To recap, when the MUX enable signal MUX_EN (not shown) is in a first state, multiplexer 282 is enabled to select between the bundle bit line signals BBL_UP and BBL_DN, and when the MUX enable signal MUX_EN (not shown) is in a second state, multiplexer 282 is disabled and cannot select between the bundle bit line signals BBL_UP and BBL_DN. Figure 3A Assume the MUX enable signal MUX_EN (not shown) is in the second state.

[0137] Regarding box 630, it should be recalled that the control signal BBL_SEL is a delayed and inverted version of the tracking signal BBL_TRK. It should also be recalled that the tracking signal BBL_TRK propagates along tracking line 280B, the length of which is selected such that the delayed tracking signal BBL_TRK causes the control signal BBL_SEL to change state after either of the following conditions, resulting in effective operation: (A) the beam bit line signal BBL_UP on beam width read line 286(1) has reached a stable state in the context of accessing beam 202(1), or (B) the beam bit line signal BBL_DN on beam width read line 286(2) has reached a stable state in the context of accessing beam 202(1).

[0138] Regarding block 630, if the tracking signal BBL_TRK does not experience a delay while propagating along tracking line 280B, the tracking signal BBL_TRK is at risk of arriving prematurely at the second inverter of delay line 276B, causing the control signal BBL_SEL to drop prematurely. That is, the tracking signal BBL_TRK arrives at the second inverter of delay line 276B too quickly, causing the control signal BBL_SEL to drop before either of the following conditions, resulting in a glitch (i.e., invalid operation): (a) the beam bit line signal BBL_UP on beam width read line 286(1) has reached a stable state in the context of accessing beam 202(1) or (B) the beam bit line signal BBL_DN on beam width read line 286(2) has reached a stable state in the context of accessing beam 202(1). From block 630, the flow proceeds to block 632.

[0139] At block 632, after the feedback signal BBL_FB is decremented, the latch signal LAT is decremented, causing each of latches 278(3) and 278(4) to latch / store the voltage / value corresponding to the bit line signal BBL_UP on the bundle width read line 286(1) of bundle 202(1) and the bit line signal BBL_DN on the bundle width read line 286(2) of bundle 202(2). From block 632, the flow proceeds to block 634.

[0140] At box 634, the control signal SAEC rises, which causes the SPUD circuit 284 to disconnect / decouple the output of the sense amplifier SA from the beamwidth readout line 286(1).

[0141] Figure 6C This is a flowchart (flow diagram) of a method for reading from memory according to some embodiments.

[0142] Figure 6C Provided Figure 6A Details of the example for box 602 are available. Figure 6BExamples of memory operated by the methods described herein include the memory disclosed herein (e.g., Figure 2B Memory 200B, etc. With Figure 6C The corresponding timing diagram example is Figure 3B The timing diagram (and the waveforms included therein), etc. Therefore, it will be... Figure 2B and Figure 3B The context of the explanation Figure 6C The discussion. Figure 6C Suppose the context of a selected memory cell in the corresponding bundle (e.g., 250) of the first bundle (e.g., 102(1)) and the second bundle (e.g., 102(2)). Figure 6B In the middle, box 602 includes boxes 644 to 658.

[0143] At block 644, group-level signals (e.g., PGB_UP, SAE, DL_IN, SAEC, etc.) are provided to the corresponding local access manager (e.g., 112(x)), causing data to be transferred from a selected memory cell (e.g., 250) to the corresponding bundle-width read line in the first bundle-width read line (e.g., 286(1)) and the second bundle-width read line (e.g., 286(2)). From block 644, the flow proceeds to block 646.

[0144] At block 646, a control signal (e.g., BBL_SEL) is delayed by a first delay factor, and the control signal is configured to cause a multiplexer (e.g., 282) to select either a first beamwidth readout line (e.g., 286(1)) or a second beamwidth readout line (e.g., 286(2)). The first delay factor is sufficient to cause a delay in the control signal (e.g., BBL_SEL) such that the corresponding voltage / value of the signal (e.g., BBL_UP or BBL_DN) on one of the selected beamwidth readout lines (e.g., 286(1)) and the second beamwidth readout line (e.g., 286(2)) reaches a stable state before the control signal (BBL_SEL) couples the multiplexer (282) to select the first beamwidth readout line or the second beamwidth readout line. Block 646 includes blocks 648 through 658. Within block 646, the flow proceeds to block 648.

[0145] At box 648, a first select signal (e.g., TRK_PRE) is received at a first node (e.g., latch 272), which is included in a global access manager (e.g., 104). From box 648, the flow proceeds to box 650.

[0146] At block 650, a second beam selection signal (e.g., BBL_TRK) is generated based on the first beam selection signal (e.g., TRK_PRE). Block 650 includes block 652.

[0147] At box 652, a first selection signal (e.g., TRK_PRE) propagates along a first delay line (e.g., 288), resulting in a delayed version of the first selection signal (e.g., TRK_PRE). The first delay line (e.g., 288) includes at least a portion of the signal path between a first node (e.g., latch 272) and a second node (e.g., latch 274), and a fourth node is included in a global access manager (e.g., 104). The flow proceeds from box 652 to exit box 650. From box 650, the flow proceeds to box 654.

[0148] At block 654, the propagation of the second beam selection signal (e.g., BBL_TRK) from the third node (e.g., the output of the first inverter of delay line 276) to the fourth node (e.g., the input of the first inverter of delay line 276) of the second delay line (e.g., 276) is delayed by a second delay factor. The second delay factor is based in part on the length of the tracking line (e.g., 280B). Block 654 includes block 656.

[0149] At block 656, the second beam selection signal (BBL_TRK) propagates along a tracking line (e.g., 280B), which includes at least a portion of a first signal path between the third node (e.g., the output of the first inverter of delay line 276) and the second node (e.g., the input of the second inverter of delay line 276) of the second delay line (276). From block 656, the flow exits block 654. From block 654, the flow proceeds to block 658.

[0150] At box 658, a control signal (e.g., BBL_SEL) is generated based on the second beam selection signal (e.g., BBL_TRK).

[0151] Figure 6D This is a flowchart (flowchart) of a method for writing to memory according to some embodiments.

[0152] Figure 6D Provided Figure 6A Details of the example for box 602 are available. Figure 6B Examples of memory operated by the methods described herein include the memory disclosed herein (e.g., Figure 2A Memory 200A, etc. With Figure 6D The corresponding timing diagram example is Figure 3B The timing diagram (and the waveforms included therein), etc. Therefore, it will be... Figure 2B and Figure 3B The context of the explanation Figure 6B The discussion. Figure 6CSuppose the context of a selected memory cell in the corresponding bundle (e.g., 250) of the first bundle (e.g., 102(1)) and the second bundle (e.g., 102(2)). Figure 6D In the middle, box 602 includes boxes 654 to 664.

[0153] At box 654, the first set of discrimination signals (e.g., UD_SELB and BW_PRE) are provided to the first selection gate (e.g., 256(1) in GIO 218). From box 654, the process proceeds to box 656.

[0154] At box 656, a second set of discrimination signals (e.g., UD_SEL and BW_PRE) are provided to the second selection gate (256(3)) in GIO 218. From box 656, the flow proceeds to box 658.

[0155] At box 658, a selection is made between the first bundle (102(1)) and the second bundle (102(2)). Box 658 includes boxes 660 and 662.

[0156] In block 658, the process can proceed to either block 660 or block 662, as indicated by the mutex process symbol 666. At block 662, a first beam discrimination signal (e.g., UD_SELB and BW_PRE) is configured to enable a first selection gate (e.g., 256(1)) and thereby select a first beam (e.g., 102(1)), and a second beam discrimination signal (e.g., UD_SEL and BW_PRE) is configured to disable a second selection gate (e.g., 256(3)). At block 664, a first beam discrimination signal (e.g., UD_SELB and BW_PRE) is configured to disable a first selection gate (e.g., 256(1)), and a second beam discrimination signal (e.g., UD_SEL and BW_PRE) is configured to enable a second selection gate (e.g., 256(3)) and thereby select a second beam (e.g., 102(2)).

[0157] Figure 7 This is a flowchart (flow diagram) of a method 700 for manufacturing a system or device according to some embodiments.

[0158] According to some embodiments, an EDA system 800 can be used, for example. Figure 8 (discussed below) and IC Manufacturing System 900 ( Figure 9 (This will be discussed below) to implement method 700. Examples of memories that can be manufactured according to method 700 include the memories disclosed herein.

[0159] exist Figure 7In flowchart 700, the method includes blocks 702 to 704. At block 702, a layout diagram is generated, which includes one or more layout diagrams corresponding to one or more memories disclosed herein. According to some embodiments, an EDA system 800 may be used, for example. Figure 8 (This will be discussed below) to implement box 702. From box 702, the process proceeds to box 704.

[0160] At box 704, based on the layout diagram, at least one of the following operations is performed: (A) performing one or more photolithographic exposures, or (B) fabricating one or more photolithographic masks, or (C) fabricating one or more components (e.g., devices) in the device layer. See below for further details. Figure 9 Discussion of IC manufacturing system 900 in China.

[0161] Figure 8 This is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0162] In some embodiments, EDA system 800 includes an Automatic Placement and Routing (APR) system. In some embodiments, EDA system 800 is a general-purpose computing device including a hardware processor 802 and a non-transitory computer-readable storage medium 804. The storage medium 804 is encoded with (i.e., stores) computer program code 806 (i.e., a set of executable instructions) and other items. Execution of the instructions 806 by the hardware processor 802 represents (at least partially) an EDA tool that implements part or all of one or more embodiments (hereinafter, the processes and / or methods described), such as one or more methods for generating a layout diagram corresponding to the memory, etc., disclosed herein.

[0163] Storage medium 804 stores layout diagram 811 (e.g., a layout diagram corresponding to the memory disclosed herein).

[0164] Processor 802 is electrically coupled to computer-readable storage medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically connected to processor 802 via bus 808. Network interface 812 is connected to network 814, enabling processor 802 and computer-readable storage medium 804 to be connected to external components via network 814. Processor 802 is configured to execute computer program code 806 encoded in computer-readable storage medium 804 to make EDA system 800 available for performing some or all of the described processes and / or methods. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0165] In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 804 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0166] In one or more embodiments, storage medium 804 stores computer program code 806 configured to enable EDA system 800 (where such execution (at least partially) represents an EDA tool) to perform some or all of the described processes and / or methods. In one or more embodiments, storage medium 804 also stores information facilitating the execution of some or all of the described processes and / or methods. In one or more embodiments, storage medium 804 stores a standard cell library 807 comprising standard cells corresponding to components of the memory disclosed herein. Storage medium 804 stores one or more layout diagrams 816 (e.g., one or more layout diagrams corresponding to the memory disclosed herein).

[0167] EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 802.

[0168] EDA system 800 also includes a network interface 812 coupled to processor 802. Network interface 812 allows EDA system 800 to communicate with a network 814 to which one or more other computer systems are connected. Network interface 812 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the described processes and / or methods are implemented in two or more EDA systems 800.

[0169] EDA system 800 is configured to receive information via I / O interface 810. The information received via I / O interface 810 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 802. The information is transmitted to processor 802 via bus 808. EDA system 800 is also configured to receive information related to the user interface (UI) via I / O interface 810. This information is stored in computer-readable medium 804 as UI 842.

[0170] In some embodiments, some or all of the described processes and / or methods are implemented as a standalone software application for processor execution. In some embodiments, some or all of the described processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, some or all of the described processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the described processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, at least one of the described processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, methods such as those available from CADENCE DESIGN SYSTEMS are used. Tools such as those used to generate layout diagrams, or another suitable layout generation tool, can be used to generate layout diagrams that include standard cells.

[0171] In some embodiments, these processes are implemented as the functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more of the following: optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memory (e.g., ROMs), RAMs, memory cards, etc.

[0172] Figure 9 This is a block diagram of an integrated circuit (IC) manufacturing system 900 according to some embodiments and the associated IC manufacturing process.

[0173] In some embodiments, based on Figure 7 The layout diagram generated by frame 702 is implemented in IC manufacturing system 900. Figure 7 Box 704, wherein the manufacturing system 900 manufactures at least one of the following: (A) one or more semiconductor masks or (B) at least one component in an early semiconductor integrated circuit layer. In some embodiments, the IC manufacturing system 900 implements Figure 5 Flowcharts, etc.

[0174] exist Figure 9In this IC manufacturing system 900, entities such as design room 920, mask room 930, and IC fab 950 interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of IC devices 960. The entities in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 920, mask room 930, and IC fab 950 are owned by a single large company. In some embodiments, two or more of design room 920, mask room 930, and IC fab 950 coexist in a common facility and use common resources.

[0175] Design studio (or design team) 920 generates IC design layout 922. IC design layout 922 includes various geometric patterns designed for IC device 960. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the integrated circuit device 960 to be manufactured. The various layers are combined together to form various IC features. For example, a portion of IC design layout 922 includes various IC features such as active regions, gate terminals, source and drain terminals, metal lines or vias for interlayer interconnects, and openings for bonding pads to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. One or more source / drain regions may refer to a source or drain individually, or collectively to source and drain, depending on the context. Design studio 920 implements appropriate design procedures to form IC design layout 922. Design procedures include one or more logic designs, physical designs, or site and routing. IC design layout 922 is presented in one or more data files containing information about the geometric patterns. For example, IC design layout 922 is represented using GDSII file format or DFII file format.

[0176] Mask chamber 930 includes data preparation 932 and mask fabrication 934. Mask chamber 930 uses IC design layout 922 to fabricate one or more masks 935 for fabricating various layers of IC device 960 according to IC design layout 922. Mask chamber 930 performs mask data preparation 932, whereby IC design layout 922 is converted into a representative data file (“RDF”). Mask data preparation 932 provides the RDF to mask fabrication 934. Mask fabrication 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (etched lines) or semiconductor wafer. The design layout is manipulated by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of IC fab 950. Figure 9 In this embodiment, mask data preparation 932, mask manufacturing 934, and mask 935 are shown as separate elements. In some embodiments, mask data preparation 932 and mask manufacturing 934 are collectively referred to as mask data preparation.

[0177] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 also includes resolution enhancement techniques (RET), such as off-axis illumination, subresolution adjustment features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) that treats OPC as an inverse imaging problem is also used.

[0178] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that uses a set of mask creation standard rules to check the IC design layout already processed in the OPC. This set of mask creation standard rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 934, and can undo some modifications performed by the OPC to meet the mask creation standard rules.

[0179] In some embodiments, mask data preparation 932 includes a lithography process inspection (LPC) simulating a process to be implemented by IC fab 950 to manufacture IC device 960. The LPC simulates this process based on IC design layout 922 to manufacture a simulated device, such as IC device 960. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, or combinations thereof. In some embodiments, after the simulated device is manufactured by the LPC, if the shape of the simulated device is insufficient to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 922.

[0180] For clarity, the description of mask data preparation 932 above has been simplified. In some embodiments, mask data preparation 932 includes additional features such as logic operations (LOPs) to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0181] After mask data preparation 932 and during mask fabrication 934, a mask 935 or a set of masks 935 is fabricated based on a modified IC design layout. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to form a pattern on the mask (photomask or scribe line) based on the modified IC design layout. Various techniques are used to form the mask. In some embodiments, a binary technique is used to form the mask. In some embodiments, the mask pattern includes opaque and transparent regions. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer is blocked by the opaque regions and passes through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, a phase-shifting technique is used to form the mask. In a phase-shifting mask (PSM), various features in the pattern formed on the mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask is a decaying PSM or an alternating PSM. One or more masks generated by Mask Fabrication 934 are used in a variety of processes. For example, one or more such masks are used in ion implantation processes to form various doped regions in a semiconductor wafer, one or more such masks are used in etching processes to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0182] IC fab 950 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC fab 950 is a semiconductor foundry. For example, there may be a manufacturing facility (front-end process (FEOL) manufacturing) for the front-end manufacturing of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end process (BEOL) manufacturing) for the interconnection and packaging of IC products, and a third manufacturing facility may provide other services to the foundry enterprise.

[0183] IC fab 950 uses a mask 935, fabricated by mask chamber 930, to fabricate IC device 960 using fabrication tooling 952. Therefore, IC fab 950 fabricates IC device 960 at least indirectly using IC design layout 922. In some embodiments, semiconductor wafer 953 is fabricated by IC fab 950 using one or more masks 935 to form IC device 960. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate having a layer of material formed thereon. The semiconductor wafer also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent fabrication steps).

[0184] In some embodiments, a memory includes a first group, a second group, a third group, and a fourth group stacked on top of each other relative to a first direction and correspondingly including memory cells, and each group includes: a first partition and a second partition and a local access manager; (A) the first group and the second group and (B) the third group and the fourth group are organized into corresponding first bundles and second bundles; and a global access manager that separates the first bundle and the second bundle relative to the first direction, the global access manager being coupled to the first bundle and the second bundle via corresponding first bundle-width write lines and second bundle-width write lines or corresponding first bundle-width read lines and second bundle-width read lines, respectively.

[0185] In some embodiments, the global access manager is configured to selectively access the first and second bundles on a mutual exclusion basis.

[0186] In some embodiments, the global access manager includes: a first global I / O circuit and a second global I / O circuit, and a global controller.

[0187] In some embodiments, each of the first global I / O circuit and the second global I / O circuit includes: a first select gate configured to receive a first beam discrimination signal; a second select gate configured to receive a second beam discrimination signal; a first driver coupled between the first select gate and the first beamwidth write line; and a second driver coupled between the second select gate and the second beamwidth write line.

[0188] In some embodiments, the first beam discrimination signal includes a first selection signal and a second selection signal; the second beam discrimination signal includes a second selection signal and a third selection signal; the first selection gate is a first AND gate; the second selection gate is a second AND gate; and each of the first AND gate and the second AND gate is configured to receive the second selection signal; the first AND gate is also configured to receive the first selection signal; and the second AND gate is also configured to receive the third selection signal.

[0189] In some embodiments, the global controller includes: a trigger coupled to a first delay line; the trigger being configured to receive a first beam selection signal; and the first delay line being configured to generate a second beam selection signal based on the output signal of the trigger.

[0190] In some embodiments, the first delay line includes a tracking line coupled in series between the first inverter and the second inverter.

[0191] In some embodiments, the first beamwidth readout line and the second beamwidth readout line exhibit corresponding first and second propagation delays proportional to the first and second lengths of the first and second beamwidth readout lines; the second beamselect signal is based on the output signal of the trigger; the tracking line exhibits a third propagation delay proportional to the third length of the tracking line; and the third length of the tracking line delays the second beamselect signal to a slower rate than the first or second bit signal corresponding to the first or second beamwidth readout line.

[0192] In some embodiments, each of the first global I / O circuit and the second global I / O circuit includes: a first latch and a second latch, respectively coupled to a first beamwidth readout line and a second beamwidth readout line; and a multiplexer coupled to each of the first latch and the second latch, the multiplexer being configured to receive a second beamselect signal, and the multiplexer being further configured to select a first bit signal or a second bit signal corresponding to the first beamwidth readout line or the second beamwidth readout line according to the second beamselect signal.

[0193] In some embodiments, a method of (manufacturing memory) includes forming a structure comprising components, the components including memory cells, local access managers, and global access managers. Forming the structure comprising components includes: arranging a first component of the components including memory cells into a first group, a second group, a third group, and a fourth group stacked on top of each other relative to a first direction, including, for each of the first to fourth groups, arranging an α component and a β component of the first component into a corresponding first partition and a second partition; arranging (A) the first and second groups and (B) the third and fourth groups into corresponding first bundles and second bundles; and arranging a second component of the components including local access managers such that, for each of the first, second, third, and fourth groups, the first partition and the second partition are separated from each other relative to the first direction by a corresponding local access manager in the local access managers; arranging a third component of the components including global access managers such that the global access managers separate the first bundle and the second bundle relative to the first direction; and forming mutual coupling between the components, such that at least a first bundle wide write line and a second bundle wide write line or a first bundle wide read line and a second bundle wide read line couple the global access manager to the first bundle and the second bundle, respectively.

[0194] In some embodiments, arranging a third component in a component that includes a global access manager includes configuring the global access manager to access the first bundle and the second bundle on a mutually exclusive basis.

[0195] In some embodiments, forming the structure including components further includes: using an α component in a third component including a global access manager to form a first global I / O circuit and a second global I / O circuit; using a β component in a third component including a global access manager to form a global controller; and arranging the β component in a third component including a global access manager such that the global controller separates the first global I / O circuit and the second global I / O circuit relative to a second direction perpendicular to the first direction.

[0196] In some embodiments, using a β component in a third component including a global access manager to form a global controller further includes: arranging a fifth component in the β component to include a third select gate, arranging a sixth component in the β component to include a fourth select gate, arranging a seventh component in the β component to include a third driver, and arranging an eighth component in the β component to include a fourth driver; and forming mutual coupling between the components further results in at least the third beamwidth write line and the fourth beamwidth write line correspondingly coupling the global access manager to the first beam and the second beam, respectively, the third select gate being operable to receive a third select signal, the fourth select gate being operable to receive a fourth select signal, the third driver being coupled between the third select gate and the third beamwidth write line, and the fourth driver being coupled between the third select gate and the fourth beamwidth write line.

[0197] In some embodiments, forming a global controller using a beta component in a third component including a global access manager includes: arranging a first component in the beta component to include a first select gate; arranging a second component in the beta component to include a second select gate; arranging a third component in the beta component to include a first driver; and arranging a fourth component in the beta component to include a second driver. In some embodiments, forming mutual coupling between components further results in at least: the first select gate being configured to receive a first beam select signal; the second select gate being configured to receive a second beam select signal; the first driver being coupled between the first select gate and a first beamwidth write line; and the second driver being coupled between the second select gate and the second beamwidth write line.

[0198] In some embodiments, forming a global controller using a beta component in a third component including a global access manager includes: arranging a first component in the beta component to include a trigger; and arranging a second component in the beta component to include a first delay line. In some embodiments, forming mutual coupling between the components further results in at least: the trigger being configured to receive a first beam selection signal; and the first delay line being coupled to the trigger and configured to generate a second beam selection signal based on the output signal of the trigger.

[0199] In some embodiments, a method (for reading from memory) includes: accessing a first bundle and a second bundle of memory on a mutually exclusive basis; the first bundle and the second bundle correspondingly include (A) a first group and a second group of memory and (B) a third group and a fourth group of memory; the first group, the second group, the third group, and the fourth group are stacked on top of each other relative to a first direction and correspondingly include memory cells, and each memory cell includes a first partition and a second partition and a local access manager; the memory includes a global access manager that separates the first bundle and the second bundle relative to the first direction; and the global access manager is coupled to a first bundle width write line and a second bundle width write line, respectively. The first and second bundles, and the global access manager includes a first delay line and a multiplexer coupled to the first and second bundles via corresponding first and second bundle-width read lines; accessing the first and second bundles for a selected memory cell in one of the corresponding memory cells in the first and second bundles includes providing a group-level signal to the corresponding local access manager, thereby transferring data from a selected memory cell in the memory cells to a corresponding bundle-width read line in the first and second bundle-width read lines, and delaying a control signal by a first delay factor; and configuring the control signal to cause the multiplexer to select either the first or second bundle-width read line.

[0200] In some embodiments, for a selected memory cell in a memory cell of a corresponding bundle of a first bundle and a second bundle, the delay control signal includes: delaying the propagation of the first bundle selection signal from a first node to a second node of a first delay line by a second delay factor, the first delay factor being based on the second delay factor; and generating a control signal based on the first bundle selection signal.

[0201] In some embodiments, delaying the propagation of the first selected signal includes: propagating the first selected signal along a tracking line that includes at least a portion of a first signal path between a first node and a second node of the first delay line; and a second delay factor that is partially based on the length of the tracking line.

[0202] In some embodiments, delaying the propagation of the first selection signal includes: receiving a second selection signal at a third node, the third node being included in the global access manager; and generating the first selection signal based on the second selection signal.

[0203] In some embodiments, generating the first beam selection signal includes propagating the second beam selection signal along a second delay line, the second delay line including at least a portion of a signal path between a third node and a fourth node, the fourth node being included in a global access manager.

[0204] Those skilled in the art will readily recognize that one or more embodiments of the present disclosure achieve one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to implement various variations, equivalent substitutions, and various other embodiments as broadly disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the appended claims and their equivalents.

[0205] Example

[0206] Example 1. A memory comprising: a first group, a second group, a third group, and a fourth group, stacked on top of each other relative to a first direction and correspondingly including memory cells, and each group comprising: a first partition and a second partition and a local access manager; (A) the first group and the second group and (B) the third group and the fourth group being organized into corresponding first bundles and second bundles; and a global access manager separating the first bundle and the second bundle relative to the first direction, the global access manager being coupled to the first bundle and the second bundle respectively via corresponding first bundle-width write lines and second bundle-width write lines or corresponding first bundle-width read lines and second bundle-width read lines.

[0207] Example 2. The memory according to Example 1, wherein: the global access manager is configured to selectively access the first bundle and the second bundle on a mutually exclusive basis.

[0208] Example 3. The memory according to Example 1, wherein the global access manager includes: separate first global I / O circuitry and second global I / O circuitry, and a global controller.

[0209] Example 4. The memory according to Example 3, wherein each of the first global I / O circuit and the second global I / O circuit includes: a first select gate configured to receive a first beam discrimination signal; a second select gate configured to receive a second beam discrimination signal; a first driver coupled between the first select gate and the first beamwidth write line; and a second driver coupled between the second select gate and the second beamwidth write line.

[0210] Example 5. The memory according to Example 4, wherein: the first beam discrimination signal includes a first selection signal and a second selection signal; the second beam discrimination signal includes the second selection signal and a third selection signal; the first selection gate is a first AND gate; the second selection gate is a second AND gate; and each of the first AND gate and the second AND gate is configured to receive the second selection signal; the first AND gate is also configured to receive the first selection signal; and the second AND gate is also configured to receive the third selection signal.

[0211] Example 6. The memory according to Example 3, wherein: the global controller includes a trigger coupled to a first delay line; the trigger is configured to receive a first beam selection signal; and the first delay line is configured to generate a second beam selection signal based on the output signal of the trigger.

[0212] Example 7. The memory according to Example 6, wherein: the first delay line includes a tracking line series coupled between the first inverter and the second inverter.

[0213] Example 8. The memory according to Example 7, wherein: the first beamwidth readout line and the second beamwidth readout line exhibit corresponding first propagation delay and second propagation delay proportional to a first length and a second length corresponding to the first beamwidth readout line and the second beamwidth readout line; the second beamselect signal is based on the output signal of the trigger; the tracking line exhibits a third propagation delay proportional to a third length of the tracking line; and the third length of the tracking line delays the second beamselect signal such that the second beamselect signal is slower than the first bit signal or the second bit signal corresponding to the first beamwidth readout line or the second beamwidth readout line.

[0214] Example 9. The memory according to Example 6, wherein each of the first global I / O circuit and the second global I / O circuit includes: a first latch and a second latch, correspondingly coupled to the first beamwidth read line and the second beamwidth read line; and a multiplexer, coupled to each of the first latch and the second latch, the multiplexer being configured to receive a second beamselect signal, and the multiplexer being further configured to select a first bit signal or a second bit signal corresponding to the first beamwidth read line or the second beamwidth read line according to the second beamselect signal.

[0215] Example 10. A method of manufacturing a memory, the method comprising: forming a structure including components, the components including memory cells, local access managers, and global access managers, the forming of the structure including components comprising: arranging a first component of the components including the memory cells into a first group, a second group, a third group, and a fourth group stacked on top of each other relative to a first direction, including, for each of the first group to the fourth group, arranging an α component and a β component of the first component into a corresponding first partition and a second partition; arranging (A) the first group and the second group and (B) the third group and the fourth group into corresponding first bundles and second bundles; and arranging a first component of the components including the local access managers into a third component. The two components are arranged such that, for each of the first group, the second group, the third group, and the fourth group, the first partition and the second partition are separated from each other relative to the first direction by a corresponding local access manager of the local access managers; a third component of the components including the global access manager is arranged such that the global access manager separates the first bundle and the second bundle relative to the first direction; and mutual coupling is formed between the components, at least resulting in: a first bundle-width write line and a second bundle-width read line or a first bundle-width read line and a second bundle-width read line, the first bundle-width write line and the second bundle-width read line correspondingly coupling the global access manager to the first bundle and the second bundle.

[0216] Example 11. The method according to Example 10, wherein the arrangement includes a third component of the components of the global access manager, comprising: configuring the global access manager to access the first bundle and the second bundle on a mutually exclusive basis.

[0217] Example 12. The method according to Example 10, wherein forming the structure including components further includes: using an α component of the third component including the global access manager to form a first global I / O circuit and a second global I / O circuit; using a β component of the third component including the global access manager to form a global controller; and arranging the β component of the third component including the global access manager such that the global controller separates the first global I / O circuit and the second global I / O circuit relative to a second direction perpendicular to the first direction.

[0218] Example 13. The method according to Example 12, wherein: the step of forming a global controller using a β component in the third component including the global access manager includes: arranging a first component in the β component to include a first select gate; arranging a second component in the β component to include a second select gate; arranging a third component in the β component to include a first driver; and arranging a fourth component in the β component to include a second driver; and the step of forming mutual coupling between the components further results in at least: the first select gate being configured to receive a first beam select signal; the second select gate being configured to receive a second beam select signal; the first driver being coupled between the first select gate and the first beamwidth write line; and the second driver being coupled between the second select gate and the second beamwidth write line.

[0219] Example 14. The method according to Example 13, wherein: the use of the β component in the third component including the global access manager to form a global controller further includes: arranging a fifth component in the β component to include a third select gate; arranging a sixth component in the β component to include a fourth select gate; arranging a seventh component in the β component to include a third driver; and arranging an eighth component in the β component to include a fourth driver; and the formation of mutual coupling between the components further results in at least: a third beamwidth write line and a fourth beamwidth write line correspondingly coupling the global access manager to the first beam and the second beam; the third select gate being operable to receive a third select signal; the fourth select gate being operable to receive a fourth select signal; the third driver being coupled between the third select gate and the third beamwidth write line; and the fourth driver being coupled between the third select gate and the fourth beamwidth write line.

[0220] Example 15. The method according to Example 12, wherein: the step of forming a global controller using a β component in the third component including the global access manager includes: arranging a first component in the β component to include a trigger; and arranging a second component in the β component to include a first delay line; and the formation of mutual coupling between the components further results in at least: the trigger being configured to receive a first beam selection signal; and the first delay line being coupled to the trigger and configured to generate a second beam selection signal based on the output signal of the trigger.

[0221] Example 16. A method for reading from memory, the method comprising: accessing a first bundle and a second bundle of memory on a mutually exclusive basis; the first bundle and the second bundle correspondingly comprising (A) a first group and a second group of the memory and (B) a third group and a fourth group of the memory; the first group, the second group, the third group and the fourth group are stacked on top of each other relative to a first direction and correspondingly comprised of memory cells, and each memory cell in the memory cells includes a first partition and a second partition and a local access manager, the memory including a global access manager separating the first bundle and the second bundle relative to the first direction, and the global access manager being coupled to a corresponding first bundle-width write line and a second bundle-width write line, respectively. The first bundle and the second bundle, and the global access manager includes a first delay line and a multiplexer coupled to the first bundle and the second bundle via corresponding first bundle-width read lines and second bundle-width read lines; for a selected memory cell in one of the memory cells of a corresponding bundle of the first bundle and the second bundle, accessing the first bundle and the second bundle includes: providing a group-level signal to the corresponding local access manager, thereby transferring data from a selected memory cell in the memory cells to a corresponding bundle-width read line of the first bundle-width read line and the second bundle-width read line; delaying a control signal by a first delay factor; and configuring the control signal to cause the multiplexer to select the first bundle-width read line or the second bundle-width read line.

[0222] Example 17. The method according to Example 16, wherein, for a selected memory cell in one of the memory cells in a corresponding bundle of the first bundle and the second bundle, the delay control signal includes: delaying the propagation of the first bundle selection signal from a first node to a second node of the first delay line by a second delay factor, the first delay factor being based on the second delay factor; and generating the control signal based on the first bundle selection signal.

[0223] Example 18. The method according to Example 17, wherein: the delay of propagation of the first beam selection signal comprises: propagating the first beam selection signal along a tracking line, the tracking line comprising at least a portion of a first signal path between a first node and a second node of the first delay line; and the second delay factor being partially based on the length of the tracking line.

[0224] Example 19. The method according to Example 17, wherein: delaying the propagation of the first beam selection signal includes: receiving a second beam selection signal at a third node, the third node being included in the global access manager; and generating the first beam selection signal based on the second beam selection signal.

[0225] Example 20. The method according to Example 19, wherein: generating the first beam selection signal includes: propagating the second beam selection signal along a second delay line, the second delay line including at least a portion of a signal path between the third node and the fourth node, the fourth node being included in the global access manager.

Claims

1. A memory, comprising: The first, second, third, and fourth groups are stacked on top of each other relative to the first direction and correspondingly include memory cells, and each group includes: First partition, second partition, and local access manager; (A) Groups 1 and 2, and (B) Groups 3 and 4, are organized into corresponding bundles 1 and 2; and A global access manager separates the first and second bundles relative to the first direction. The global access manager is coupled to the first beam and the second beam respectively through the corresponding first beamwidth write line and the second beamwidth write line or the corresponding first beamwidth read line and the second beamwidth read line.

2. The memory according to claim 1, wherein: The global access manager is configured to selectively access the first bundle and the second bundle on a mutually exclusive basis.

3. The memory according to claim 1, wherein, The global access manager includes: Separate first global I / O circuits, second global I / O circuits, and a global controller.

4. The memory according to claim 3, wherein, Each of the first global I / O circuit and the second global I / O circuit includes: The first selection gate is configured to receive the first discrimination signal; The second selection gate is configured to receive the second discrimination signal; A first driver, coupled between the first selection gate and the first beamwidth write line; and The second driver is coupled between the second selection gate and the second beamwidth write line.

5. The memory according to claim 4, wherein: The first beam discrimination signal includes a first selection signal and a second selection signal; The second beam discrimination signal includes the second selection signal and the third selection signal; The first choice gate is the first AND gate; The second choice gate is the second AND gate; and Each of the first AND gate and the second AND gate is configured to receive the second selection signal; The first AND gate is also configured to receive the first selection signal; and The second AND gate is also configured to receive the third selection signal.

6. The memory according to claim 3, wherein: The global controller includes a trigger coupled to the first delay line; The trigger is configured to receive a first selection signal; as well as The first delay line is configured to generate a second beam selection signal based on the output signal of the trigger.

7. The memory according to claim 6, wherein: The first delay line includes a tracking line coupled in series between the first inverter and the second inverter.

8. The memory according to claim 7, wherein: The first beamwidth readout line and the second beamwidth readout line exhibit a first propagation delay and a second propagation delay that are proportional to the first length and the second length corresponding to the first beamwidth readout line and the second beamwidth readout line, respectively. The second beam selection signal is based on the output signal of the trigger; The tracking line exhibits a third propagation delay proportional to the third length of the tracking line; and The third length element of the tracking line delays the second beam selection signal so that the second beam selection signal is slower than the first or second bit signal corresponding to the first or second beam width readout line.

9. A method of manufacturing a memory, the method comprising: Forming a structure comprising components, the components including memory cells, local access managers, and global access managers, the structure comprising components including: Arranging the first component of the components including the memory cell into a first group, a second group, a third group, and a fourth group stacked on top of each other relative to a first direction, including, for each of the first group to the fourth group, arranging the α component and the β component of the first component into the corresponding first partition and second partition; Arrange (A) the first and second groups and (B) the third and fourth groups into the corresponding first and second bundles; and The second component of the components including the local access manager is arranged such that for each of the first group, the second group, the third group, and the fourth group, the first partition and the second partition are separated from each other relative to the first direction by a corresponding local access manager of the local access manager. The third component of the components including the global access manager is arranged such that the global access manager separates the first bundle and the second bundle relative to the first direction; and The mutual coupling between the components results in at least the following: A first beamwidth write line and a second beamwidth read line or a first beamwidth read line and a second beamwidth read line, wherein the first beamwidth write line and the second beamwidth read line correspondingly couple the global access manager to the first beam and the second beam.

10. A method for reading from a memory, the method comprising: Access to the first and second bundles of the memory is based on mutual exclusion; The first bundle and the second bundle correspondingly include (A) the first and second groups of the memory and (B) the third and fourth groups of the memory; The first group, the second group, the third group, and the fourth group are stacked on top of each other relative to a first direction and are respectively composed of memory cells. Each memory cell includes a first partition, a second partition, and a local access manager. The memory includes a global access manager that separates the first bundle and the second bundle relative to the first direction. The global access manager is coupled to the first bundle and the second bundle via corresponding first bundle-width write lines and second bundle-width write lines, respectively. The global access manager includes a first delay line and a multiplexer coupled to the first bundle and the second bundle via corresponding first bundle-width read lines and second bundle-width read lines. For a selected memory cell in one of the corresponding memory cells of the first and second bundles, accessing the first and second bundles includes: A group-level signal is provided to the corresponding local access manager, thereby transferring data from a selected memory cell in the memory cell to a corresponding beamwidth readout line of the first beamwidth readout line and the second beamwidth readout line. as well as Delay the control signal by the first delay factor; and The control signal is configured to cause the multiplexer to select either the first beamwidth readout line or the second beamwidth readout line.

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