Semiconductor device and preparation method thereof, and storage system

Abstract

The invention provides a semiconductor device and a preparation method thereof, and a storage system. The semiconductor device comprises a substrate, a first device structure and a first shielding structure. A first device structure is disposed on the substrate, the first device structure comprises a latch structure, and the first device structure has a first orthographic projection on the substrate. At least one part of the first shielding structure is arranged on the side, away from the substrate, of the first device structure, the first shielding structure has a second orthographic projection on the surface of the substrate, and the first orthographic projection is within the range of the second orthographic projection. Therefore, the first shielding structure can reduce radiation particles entering the first device structure, so that the soft failure rate of the device can be reduced.

Description

Technical Field

[0001] This application generally relates to the field of semiconductors, and more specifically, to a semiconductor device and its fabrication method, and a storage system. Background Technology

[0002] Latch structures are frequently used in various semiconductor devices, such as Complementary Metal Oxide Semiconductor (CMOS) integrated circuits and Static Random Access Memory (SRAM). A latch is a level-triggered memory cell that operates by determining the data storage action based on the level of an input signal.

[0003] However, the drain terminals of latch structures in semiconductor devices are susceptible to ionizing radiation, leading to soft failures. Soft failures manifest as temporary data errors without damaging the semiconductor structure. Therefore, reducing the soft failure rate of semiconductor devices is a key research focus in this field. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor device and its fabrication method, as well as a storage system, with the aim of reducing the soft failure rate of the semiconductor device.

[0005] This application provides a semiconductor device, including:

[0006] Substrate;

[0007] A first device structure disposed on the substrate, the first device structure including a latching structure, the first device structure having a first orthographic projection on the substrate;

[0008] A first shielding structure, at least a portion of which is disposed on the side of the first device structure away from the substrate, the first shielding structure having a second orthographic projection on the substrate surface, and the first orthographic projection being within the range of the second orthographic projection.

[0009] In some embodiments, the first shielding structure includes:

[0010] The first shielding portion is disposed in a film layer parallel to the substrate;

[0011] The second shielding portion extends toward the substrate along a first direction, which intersects with the substrate.

[0012] In some embodiments, it also includes:

[0013] An interconnect layer is located on the side of the first device structure away from the substrate;

[0014] The first shielding portion is located on the side of the interconnect layer away from the substrate.

[0015] In some embodiments, the semiconductor device further includes:

[0016] A first dielectric layer is located between the interconnect layer and the first shielding portion, and the second shielding portion penetrates the first dielectric layer along the first direction.

[0017] In some embodiments, it also includes:

[0018] An interconnect layer is located on the side of the first device structure away from the substrate. The interconnect layer includes multiple overlapping interconnect portions, and the first shielding portion is located between two adjacent interconnect portions.

[0019] In some embodiments, the second shielding portion is disposed around the edge of the first shielding portion.

[0020] In some embodiments, the second shielding portion includes at least one embedded portion connected to the edge of the first shielding portion, and adjacent embedded portions are interconnected.

[0021] In some embodiments, the first shielding structure further includes:

[0022] The third shielding portion extends through the interconnect layer along the second direction, which intersects the substrate, and the third shielding portion is located on the side of the second shielding portion away from the first device structure;

[0023] The fourth shielding portion is located between the interconnect layer and the first dielectric layer, and the fourth shielding portion is connected between the third shielding portion and the second shielding portion.

[0024] In some embodiments, the first shielding structure further includes:

[0025] The third shielding portion extends through the interconnect layer along the second direction, which intersects the substrate, and the third shielding portion is located on the side of the second shielding portion closer to the first device structure;

[0026] The fourth shielding portion is located on the periphery of the first device structure and extends along a third direction, which intersects with the substrate. The fourth shielding portion is located on the side of the third shielding portion closer to the first device structure.

[0027] The third shielding portion includes a first end close to the first shielding portion and a second end away from the first shielding portion. The first end extends to the membrane layer where the second shielding portion is located, and the second end extends to the membrane layer where the fourth shielding portion is located.

[0028] In some embodiments, the latching structure includes a doped region, a source, a drain, and a gate. The doped region is located within the substrate, the gate is located on the surface of the substrate and connected to the doped region, and the source and drain are located within the doped regions on both sides of the gate.

[0029] The semiconductor device further includes a second dielectric layer covering the first device structure and the substrate, the second dielectric layer being located between the interconnect layer and the substrate.

[0030] In some embodiments, the third shielding portion further penetrates the second dielectric layer along the second direction, and the fourth shielding portion extends in the substrate along the third direction.

[0031] In some embodiments, the dimension of the fourth shielding portion along the third direction is greater than or equal to the dimension of the doped region along the third direction.

[0032] In some embodiments, the fourth shielding portion penetrates the second dielectric layer along the third direction and extends into the substrate.

[0033] In some embodiments, the interconnect layer includes an insulating layer and a metal layer located in the insulating layer, and the second shielding portion is connected to the insulating layer.

[0034] In some embodiments, it also includes:

[0035] A second device structure is located on the surface of the substrate and is disposed adjacent to the first device structure, and the second device structure has a third orthographic projection on the surface of the substrate.

[0036] The second shielding structure has a fourth orthographic projection on the substrate surface, and the third orthographic projection is within the range of the fourth orthographic projection.

[0037] In some embodiments, the second shielding structure is located between the second device structure and the insulating layer;

[0038] The second shielding portion also penetrates the insulating layer along the first direction and is connected to the second shielding structure.

[0039] In some embodiments, the second shielding structure is connected to the first shielding portion in the same layer.

[0040] In some embodiments, the second device structure includes at least one of a non-volatile memory array, a digital logic circuit, an analog circuit, and a peripheral circuit;

[0041] The first device structure includes at least one of a static random access memory array and a dynamic random access memory array.

[0042] In some embodiments, the first shielding portion includes a shielding layer and a stress-buffering structure located within the shielding layer.

[0043] In some embodiments, the semiconductor device further includes:

[0044] A third dielectric layer covers the first shielding portion and is connected to the stress buffer structure;

[0045] The stress buffer structure is made of the same material as the third dielectric layer.

[0046] In some embodiments, the semiconductor device further includes:

[0047] A redistribution layer is located within the third dielectric layer;

[0048] A connecting structure extends through the stress buffer structure and is connected to the redistribution layer;

[0049] The encapsulation layer is located on the side of the third dielectric layer away from the first shielding structure.

[0050] In some embodiments, the first shielding structure includes at least one of a metal, a metal compound, graphene, and carbon nanotubes.

[0051] In some embodiments, the second shielding portion includes a first end away from the substrate and a second end close to the substrate, wherein the dimension of the first end along a fourth direction is greater than the dimension of the second end along the fourth direction, and the fourth direction is parallel to the substrate.

[0052] This application provides a method for fabricating a semiconductor device, comprising:

[0053] Provide substrate;

[0054] A first device structure is formed on the substrate, the first device structure including a latching structure, and the first device structure having a first orthographic projection on the substrate;

[0055] A first shielding structure is formed on one side of the substrate, at least a portion of the first shielding structure is disposed on the side of the first device structure away from the substrate, the first shielding structure has a second orthographic projection on the substrate surface, and the first orthographic projection is within the range of the second orthographic projection.

[0056] This application provides a storage system, including:

[0057] Semiconductor devices in any of the above embodiments;

[0058] A controller, connected to the semiconductor device, is used to control the semiconductor device to store data.

[0059] This application provides a semiconductor device and its fabrication method, as well as a memory system. The semiconductor device includes a substrate, a first device structure, and a first shielding structure. Since the first orthographic projection of the first device structure falls within the range of the second orthographic projection of the first shielding structure, the first shielding structure can reduce the entry of radiation particles into the first device structure, thereby reducing the soft failure rate of the device. Attached Figure Description

[0060] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0061] Figure 1 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application;

[0062] Figure 2 This is provided by some embodiments of this application. Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor device along the A-A1 direction;

[0063] Figure 3 This is a circuit diagram of a static random access memory array provided in some embodiments of this application;

[0064] Figure 4 This is a top view schematic diagram of the first shielding structure provided in some embodiments of this application;

[0065] Figure 5 This is provided by some embodiments of this application. Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor device along the A-A1 direction;

[0066] Figure 6 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application;

[0067] Figure 7 This is provided by some embodiments of this application. Figure 6 A schematic diagram of the cross-sectional structure of a semiconductor device along the B-B1 direction;

[0068] Figure 8 This is provided by some embodiments of this application. Figure 6 A schematic diagram of the cross-sectional structure of a semiconductor device along the B-B1 direction;

[0069] Figure 9 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application;

[0070] Figure 10 This is provided by some embodiments of this application. Figure 9 A schematic diagram of the cross-sectional structure of a semiconductor device along the C-C1 direction;

[0071] Figure 11 This is provided by some embodiments of this application. Figure 9 A schematic diagram of the cross-sectional structure of a semiconductor device along the C-C1 direction;

[0072] Figure 12 This is provided by some embodiments of this application. Figure 1 A schematic cross-sectional view of a semiconductor device along the A-A1 direction;

[0073] Figure 13 Other embodiments provided in this application Figure 1 A schematic cross-sectional view of a semiconductor device along the A-A1 direction;

[0074] Figures 14-16 This is a top view of the first shielding portion provided in some embodiments of this application;

[0075] Figure 17 This is provided by some embodiments of this application. Figure 1 A schematic cross-sectional view of a semiconductor device along the A-A1 direction;

[0076] Figure 18 This is a schematic flowchart of a method for fabricating a semiconductor device provided in some embodiments of this application;

[0077] Figures 19-22 These are schematic diagrams illustrating the structure of semiconductor devices during fabrication according to some embodiments of this application;

[0078] Figure 23 This is a schematic diagram of the structure of a storage system provided in some embodiments of this application. Detailed Implementation

[0079] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0080] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this application.

[0081] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0082] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a range smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along the surface of the tapered substrate. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers, as well as one or more dielectric layers.

[0083] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0084] This paper uses Cartesian coordinates to represent directions, where “X” represents the fourth direction; “Y1”, “Y2”, and “Y3” represent the first, second, and third directions, respectively; and “Z” represents the direction perpendicular to “X”, “Y1”, “Y2”, and “Y3”.

[0085] Taking Static Random-Access Memory (SRAM) as an example, we will explain the soft failure of the device.

[0086] With the advancement of semiconductor technology, the requirements for SRAM soft failures have become increasingly stringent. In semiconductor fields with extremely high safety requirements, such as automotive electronics and aerospace, SRAM soft failures have become a critical factor affecting chip reliability. Currently, SRAM soft failures mainly originate from ionizing radiation (such as alpha particle radiation in the packaging material and neutron radiation in the atmosphere). Due to the latching structure within SRAM, the drain of N / P metal-oxide-semiconductor (N / PMOS) is susceptible to the effects of ionizing radiation. Additionally, some digital circuits with latching structures may also be affected by ionizing radiation, leading to device soft failures.

[0087] For the reasons mentioned above, this application provides a semiconductor device to reduce the soft failure rate of semiconductor devices.

[0088] The semiconductor device in this embodiment includes a substrate, a first device structure, and a first shielding structure. The first device structure is disposed on the substrate and includes a latching structure. The first device structure has a first orthographic projection on the substrate. At least a portion of the first shielding structure is disposed on the side of the first device structure away from the substrate. The first shielding structure has a second orthographic projection on the substrate surface, and the first orthographic projection is within the range of the second orthographic projection. Therefore, the first shielding structure can reduce the entry of radiated particles into the first device structure, thereby reducing the soft failure rate of the device.

[0089] The structure of the semiconductor device is described below with reference to the accompanying drawings.

[0090] Please see Figure 1 and Figure 2 , Figure 1 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application. Figure 2 This is provided by some embodiments of this application. Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor device along the A-A1 direction.

[0091] Semiconductor device 100 includes a substrate 10, a first device structure 20, and a first shielding structure 30. The first device structure 20 is disposed on the substrate 10, and includes a latching structure. The first device structure 20 has a first orthographic projection on the substrate 10. At least a portion of the first shielding structure 30 is disposed on a side of the first device structure 20 away from the substrate 10. The first shielding structure 30 has a second orthographic projection on the surface of the substrate 10, and the first orthographic projection is within the range of the second orthographic projection. Therefore, the first shielding structure 30 can reduce the entry of radiated particles into the first device structure 20, thereby reducing the soft failure rate of the device.

[0092] In some embodiments, the substrate 10 is a semiconductor substrate, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), silicon-on-insulator (SOI), or germanium-on-insulator (GOI). In other embodiments, the semiconductor substrate may also be a substrate comprising semiconductors of other elements or compound semiconductors, and may also be a stacked structure, such as Si / SiGe.

[0093] In some embodiments, the first device structure 20 includes at least one of a static random-access memory (SRAM) array and a dynamic random-access memory (DRAM) array.

[0094] It should be noted that, Figure 2 The latch structure is illustrated using only one transistor; the latch structure will be described in detail below.

[0095] In other embodiments, the first device structure 20 may include other circuits with latching structures, such as sensitive digital circuits. Therefore, the first shielding structure 30 in this embodiment can also reduce the soft failure rate of sensitive digital circuits.

[0096] The following section uses the first device structure 20 as an example of a static random access memory array to explain the structure and principle of the first device structure 20.

[0097] Please see Figure 3 , Figure 3 This is a circuit diagram of a static random access memory (SRAM) array provided in some embodiments of this application. The SRAM array can be a 6T structure or an 8T structure.

[0098] Taking a 6T SRAM as an example, the SRAM includes two cross-coupled inverters and two access transistors. The two cross-coupled inverters consist of PU1, PD1 and PU2, PD2. The outputs of these two inverters are connected to the inputs of each other, forming a latch structure for storing data bits. The two access transistors, PG1 and PG2, are used to control data reading and writing. The gates of PG1 and PG2 are connected to the word line (WL), and their source / drain are connected to the bit lines (BL and BLB).

[0099] In this system, Q and QB nodes latch data via cross-coupled transistors. Alpha particles and neutrons can easily enter the drain of the pull-up (PU) or pull-down (PD) transistors in the SRAM. Corresponding electron-hole pairs are generated in the drain and the PN junction of the substrate 10. The electrons are collected by the QB nodes of the SRAM, and the voltage of the QB nodes is pulled down, resulting in data errors (i.e., soft failures).

[0100] In the semiconductor device 100 provided in this application, the first shielding structure 30 can reduce the entry of alpha particles and neutrons into the first device structure 20, thereby reducing data errors in the first device structure 20 and thus reducing the soft failure rate of the semiconductor device 100.

[0101] In some embodiments, the first shielding structure 30 includes at least one of a metal, a metal compound, graphene, and carbon nanotubes. The metal may be at least one of W, Cu, and Al, and the metal compound may be at least one of TAN, Al₂O₃, and TiN.

[0102] like Figure 1 As shown, the semiconductor device 100 may further include a second device structure 40, which is located on the surface of the substrate 10 and is disposed adjacent to the first device structure 20.

[0103] It should be noted that, due to Figure 1 It's a top view, actually in Figure 1 The first shielding structure 30 is not visible in the image, so a dashed box D is used to indicate the area where the first shielding structure 30 is located. It can be seen that the area of ​​the first orthographic projection of the first device structure 20 is smaller than the area of ​​the second orthographic projection of the first shielding structure 30.

[0104] In some embodiments, the second device structure 40 may include at least one of a non-volatile memory array 41, a digital logic circuit 42, an analog circuit 43, and a peripheral circuit 44.

[0105] For example, the non-volatile memory array 41 can be a flash memory structure, or a resistive random access memory (RRAM) or a magnetoresistive random access memory (MRAM) structure. The digital logic circuit 42 can include logic operation units, high-speed buses, clock units, etc. The analog circuit 43 includes common analog modules, such as digital-to-analog converters (DACs). The peripheral circuit 44 includes commonly used input / output circuits, electrostatic discharge protection units, Schmitt triggers, etc.

[0106] For example, the second device structure 40 can be one or more of the following devices: complementary metal-oxide-semiconductor (CMOS), DRAM, radio frequency (RF), NAND, NOR FLASH, photodiode, avalanche diode, etc.

[0107] In some embodiments, such as Figure 2 As shown, the first shielding structure 30 includes a first shielding portion 31 and a second shielding portion 32. The first shielding portion 31 is disposed in a film layer parallel to the substrate 10, and the second shielding portion 32 extends toward the substrate 10 along a first direction Y1, which intersects the substrate 10. For example, the first direction Y1 can be perpendicular to the substrate 10, so the second shielding portion 32 is perpendicular to the first shielding portion 31.

[0108] In some examples, the second shielding portion 32 is arranged around the edge of the first shielding portion 31, which can improve the shielding capability.

[0109] The first shielding portion 31 has its orthographic projection on the substrate 10 within the range of the second orthographic projection. Therefore, the first shielding portion 31 can completely cover the first device structure 20, reflecting or absorbing radiation particles from above (in the illustrated direction) of the first device structure 20, thereby shielding ionizing radiation from above the first device structure 20. The second shielding portion 32 can shield ionizing radiation from the sides, thereby further reducing the soft failure rate of the first device structure 20.

[0110] In some embodiments, the first shielding structure 30 can be a single-layer structure or a multi-layer combination structure of the aforementioned materials, and the thickness of the first shielding structure 30 can be 1 nm to 20 nm. Wherein, a single-layer structure means that the first shielding portion 31 and / or the second shielding portion 32 is a single film layer; a multi-layer combination structure means that the first shielding portion 31 and / or the second shielding portion 32 is composed of film layers of multiple materials. The thickness of the first shielding structure 30 can be understood as the thickness of the first shielding portion 31.

[0111] Please see Figure 4 , Figure 4 This is a top view schematic diagram of the first shielding structure provided in some embodiments of this application.

[0112] In some embodiments, the second shielding portion 32 includes at least one embedded portion 321, the embedded portion 321 being connected to the edge of the first shielding portion 31, and adjacent embedded portions 321 being interconnected.

[0113] For example, the second shielding portion 32 includes four embedded portions 321, each embedded portion 321 being connected to the edge of the first shielding portion 31, and adjacent embedded portions 321 being interconnected. It is understood that the number of embedded portions 321 can be set according to actual needs; for example, the second shielding portion 32 may also include two or three embedded portions 321, etc., and this application does not limit this.

[0114] In some embodiments, the embedded portion 321 may extend toward the substrate 10 along a first direction Y1, and the first direction Y1 may intersect the substrate 10 at a specific angle.

[0115] In some examples, the embedded portion 321 forms an acute angle with the substrate 10. For example, the included angle between the embedded portion 321 and the substrate 10 may be 30°, 45°, or 60°.

[0116] See back Figure 2 The semiconductor device 100 may further include an interconnect layer 50, which is located on the side of the first device structure 20 away from the substrate 10. The first shielding portion 31 is located on the side of the interconnect layer 50 away from the substrate 10, i.e., the first shielding portion 31 is located above the interconnect layer 50 (as shown in the figure), which is more conducive to the implementation of the first shielding portion 31 process.

[0117] In some embodiments, the semiconductor device 100 further includes a first dielectric layer 60 located between the interconnect layer 50 and the first shielding portion 31, wherein the second shielding portion 32 penetrates at least through the first dielectric layer 60 along the first direction Y1. The first dielectric layer 60 not only protects the interconnect layer 50 but also serves as a means to form the first shielding structure 30.

[0118] For example, the first dielectric layer 60 may be composed of one or more materials such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbide.

[0119] In some embodiments, the interconnect layer 50 may include an insulating layer 51 and a metal layer 52 located within the insulating layer 51, and the second shielding portion 32 may extend to and connect with the insulating layer 51. Therefore, the impact on signal transmission of the metal layer 52 due to contact between the second shielding portion 32 and the metal layer 52 can be minimized.

[0120] In other embodiments, the interconnect layer 50 may include multiple overlapping interconnect portions (not shown), with the first shielding portion 31 located between two adjacent interconnect portions, i.e., the first shielding portion 31 may be disposed inside the interconnect layer 50. For example, the interconnect layer 50 includes overlapping first interconnect portions, second interconnect portions, and third interconnect portions, and the first shielding portion 31 may be disposed between the first interconnect portion and the second interconnect portion, or between the second interconnect portion and the third interconnect portion.

[0121] Please see Figure 5 , Figure 5 This is provided by some embodiments of this application. Figure 1 This is a schematic cross-sectional view of a semiconductor device along the A-A1 direction. For ease of understanding and brief explanation, the same structures as in the above embodiments will continue to use the same reference numerals, and the same structures will not be described in detail. This embodiment only provides detailed descriptions of different structures.

[0122] In this embodiment, the semiconductor device 200 and Figure 2 The difference in the semiconductor device 100 is that the first shielding structure 30a includes not only the first shielding portion 31 and the second shielding portion 32, but also the third shielding portion 33 and the fourth shielding portion 34.

[0123] The third shielding portion 33 penetrates the interconnect layer 50 along the second direction Y2, which intersects the substrate 10, and is located on the side of the second shielding portion 32 away from the first device structure 20. The fourth shielding portion 34 is located between the interconnect layer 50 and the first dielectric layer 60, and is connected between the third shielding portion 33 and the second shielding portion 32. Therefore, the first shielding portion 31, the second shielding portion 32, the fourth shielding portion 34, and the third shielding portion 33 are sequentially connected to form a complete shielding structure. Since the third shielding portion 33 penetrates the interconnect layer 50, it can shield against radiation particles that directly enter the first device structure 20 from the interconnect layer 50, further improving the shielding capability.

[0124] It should be noted that this shielding structure, which is composed of a horizontal part (the first shielding part 31 and the fourth shielding part 34) and a vertical part (the second shielding part 32 and the third shielding part 33), can alleviate the stress generated by the shielding structure to a certain extent, while reducing the complexity of the process and making it more convenient and flexible to use.

[0125] Please see Figure 6 and Figure 7 , Figure 6 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application. Figure 7 This is provided by some embodiments of this application. Figure 6 A schematic cross-sectional view of the semiconductor device along the B-B1 direction. For ease of understanding and brief explanation, the same structures as in the above embodiments will continue to use the same reference numerals, and the same structures will not be described in detail. This embodiment will only describe the different structures in detail.

[0126] In this embodiment, the semiconductor device 300 and Figure 2 The difference in the semiconductor device 100 is that the first shielding structure 30b includes not only the first shielding portion 31 and the second shielding portion 32, but also the third shielding portion 33b and the fourth shielding portion 34b.

[0127] The second shielding portion 32 penetrates the first dielectric layer 60 along the first direction Y1. The third shielding portion 33b penetrates the interconnect layer 50 along the second direction Y2, which intersects the substrate 10. The third shielding portion 33b is located on the side of the second shielding portion 32 closer to the first device structure 20. The fourth shielding portion 34b is located on the periphery of the first device structure 20 and extends along a third direction Y3, which intersects the substrate 10. The fourth shielding portion 34b is located on the side of the third shielding portion 33b closer to the first device structure 20.

[0128] In some embodiments, the first direction Y1, the second direction Y2, and the third direction Y3 may be parallel to each other. For example, the first direction Y1, the second direction Y2, and the third direction Y3 may all be perpendicular to the substrate 10.

[0129] in, Figure 6 The dashed boxes D1, D2 and D3 represent the range of the fourth shielding part 34b, the range of the third shielding part 33b and the range of the second shielding part 32, respectively. That is, the fourth shielding part 34b is closer to the first device structure 20 and the second shielding part 32 is farther away from the first device structure 20.

[0130] In some embodiments, the third shielding portion 33b includes a first end 331 near the first shielding portion 31 and a second end 332 away from the first shielding portion 31. The first end 331 extends into the film layer where the second shielding portion 32 is located, and the second end 332 extends into the film layer where the fourth shielding portion 34b is located. In other words, the end of the second shielding portion 32 near the third shielding portion 33b extends into the film layer where the third shielding portion 33b is located, and the end of the fourth shielding portion 34b near the third shielding portion 33b extends into the film layer where the third shielding portion 33b is located.

[0131] Therefore, the second shielding portion 32, the third shielding portion 33b and the fourth shielding portion 34b can form a continuous shielding structure on the side of the first device structure 20, thereby reducing ionizing radiation from the side and further reducing the failure rate of the first device structure 20.

[0132] In some embodiments, the first end 331 of the third shielding portion 33b and the second shielding portion 32 have a dimension of L1 along the fourth direction X, and the second end 332 of the third shielding portion 33b and the fourth shielding portion 34b have a dimension of L2 along the fourth direction X. The fourth direction X is parallel to the substrate 10, and L1 can be greater than or equal to 0, and L2 can be greater than or equal to 0.

[0133] Both L1 and L2 are greater than 0, meaning that there is a certain distance between the third shielding part 33b and the second shielding part 32, and a certain distance between the fourth shielding part 34b and the third shielding part 33b. This simplifies the process and eliminates the need for alignment.

[0134] For example, L1 can be 1um to 50um, and L2 can also be 1um to 50um.

[0135] Since ionizing radiation generally comes from above or diagonally above the first device structure 20, even if L1 and L2 are both greater than 0, the second shielding part 32, the third shielding part 33b and the fourth shielding part 34b can still block ionizing radiation from diagonally above.

[0136] The semiconductor device 300 may further include a second dielectric layer 70 covering the first device structure 20 and the substrate 10, the second dielectric layer 70 being located between the interconnect layer 50 and the substrate 10, thereby separating the substrate 10 from the interconnect layer 50.

[0137] In some embodiments, the fourth shielding portion 34b penetrates the second dielectric layer 70 along the third direction Y3 and extends into the substrate 10.

[0138] In some embodiments, the second shielding portion 32 may overlap with the third shielding portion 33b to enhance the shielding effect; that is, the second shielding portion 32 may extend downward into the interconnect layer 50, and / or the third shielding portion 33b may extend upward into the first dielectric layer 60. The third shielding portion 33b may overlap with the fourth shielding portion 34b to enhance the shielding effect; that is, the third shielding portion 33b may extend downward into the second dielectric layer 70, and / or the fourth shielding portion 34b may extend upward into the interconnect layer 50.

[0139] Please see Figure 8 , Figure 8 This is provided by some embodiments of this application. Figure 6 A schematic cross-sectional view of the semiconductor device along the B-B1 direction. For ease of understanding and brief explanation, the same structures as in the above embodiments will continue to use the same reference numerals, and the same structures will not be described in detail. This embodiment will only describe the different structures in detail.

[0140] The semiconductor device 400 in this embodiment and Figure 7 The difference in the embodiment is that the third shielding portion 33c also penetrates the second dielectric layer 70 along the second direction Y2, and the fourth shielding portion 34c extends in the substrate 10 along the third direction Y3. In other words, the third shielding portion 33c penetrates the interconnect layer 50 and the second dielectric layer 70 along the second direction Y2, and the fourth shielding portion 34c is located within the substrate 10.

[0141] The latch structure in the first device structure 20 may include a doped region 21, a source 22, a drain 23, and a gate 24. The doped region 21 is located within the substrate 10, and the gate 24 is located on the surface of the substrate 10 and connected to the doped region 21. The source 22 and the drain 23 are located within the doped region 21 on both sides of the gate 24.

[0142] In some embodiments, the fourth shielding portion 34c has a dimension L3 along the third direction Y3 that is greater than or equal to the dimension L4 of the doped region 21 along the third direction Y3, thereby reducing the impact of ionizing radiation on the doped region 21.

[0143] For example, the difference between L3 and L4 can be in the range of 2um to 5um.

[0144] Please see Figure 9 and Figure 10 , Figure 9 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application. Figure 10 This is provided by some embodiments of this application. Figure 9 A schematic cross-sectional view of a semiconductor device along the C-C1 direction. For ease of understanding and brief explanation, the same reference numerals are used for structures identical to those in the above embodiments, and identical structures are not described in detail again. This embodiment only provides detailed descriptions of different structures.

[0145] The semiconductor device 500 in this embodiment and Figure 2 The main difference in the embodiment is that the semiconductor device 500 further includes a second shielding structure 35, which has a fourth orthographic projection on the surface of the substrate 10, and the second device structure 40 has a third orthographic projection on the surface of the substrate 10, wherein the third orthographic projection is within the range of the fourth orthographic projection. Therefore, the second shielding structure 35 can reduce the impact of ionizing radiation on the second device structure 40.

[0146] In some embodiments, the second shielding structure 35 is located between the second device structure 40 and the insulating layer 51. The second shielding portion 32 also penetrates the insulating layer 51 along the first direction Y1 and is connected to the second shielding structure 35. Therefore, the second shielding structure 35 can also block radiation particles from entering the first device structure 20 from below the second shielding portion 32.

[0147] In some embodiments, the first shielding structure 30 includes a first shielding portion 31 and a second shielding portion 32, wherein the second shielding portion 32 penetrates the first dielectric layer 60 and the interconnect layer 50.

[0148] In some embodiments, the second device structure 40 may include a non-volatile memory array 41, a digital logic circuit 42, and an analog circuit 43. Figure 9 The range of the first shielding portion 31 is indicated by a dashed box D4, and the range of the second shielding structure 35 is indicated by a dashed box D5. It can be seen that the first device structure 20 is within the range of the first shielding structure 30, and the second device structure 40 is within the range of the second shielding structure 35, thereby providing shielding against ionizing radiation for the non-volatile memory array 41, the digital logic circuit 42, and the analog circuit 43.

[0149] Please see Figure 11 , Figure 11 This is provided by some embodiments of this application. Figure 9A schematic cross-sectional view of a semiconductor device along the C-C1 direction. For ease of understanding and brief explanation, the same reference numerals are used for structures identical to those in the above embodiments, and identical structures are not described in detail again. This embodiment only provides detailed descriptions of different structures.

[0150] In this embodiment, the semiconductor device 600 and Figure 10 The difference in the Chinese embodiment is that the second shielding structure 35a is connected to the first shielding part 31 in the same layer. The first shielding part 31 and the second shielding structure 35a together can completely cover the range of the first device structure 20 and the second device structure 40, thereby achieving the effect of shielding the first device and the second device structure 40 from ionizing radiation.

[0151] In some embodiments, the second shielding portion 32 may penetrate at least through the first dielectric layer 60, for example, extending to the interconnect layer 50 or the second dielectric layer 70, or even extending into the substrate 10, thereby enhancing the shielding effect of the first device structure 20 against ionizing radiation.

[0152] In some embodiments, the cross-sectional shape of the second shielding portion 32 may be an inverted triangle, trapezoid, rectangle, polygon, or a combination of two or more of the above shapes.

[0153] Please see Figure 12 and Figure 13 , Figure 12 This is provided by some embodiments of this application. Figure 1 A schematic cross-sectional view of a semiconductor device along the A-A1 direction. Figure 13 Other embodiments provided in this application Figure 1 A schematic cross-sectional view of a semiconductor device along the A-A1 direction.

[0154] The second shielding portion 32d in the first shielding structure 30d includes a first end 321 away from the substrate 10 and a second end 322 close to the substrate 10. The dimension of the first end 321 along the fourth direction X is larger than the dimension of the second end 322 along the fourth direction X, which is parallel to the substrate 10. In other words, the second shielding portion 32d has a structure that is larger at the top and smaller at the bottom. For example, the cross-sectional shape of the second shielding portion 32d is an inverted triangle or a trapezoid.

[0155] Please see Figures 14-16 , Figures 14-16 This is a top view of the first shielding portion provided in some embodiments of this application.

[0156] In some embodiments, see Figure 14 The first shielding part 31 is a full-surface shielding layer.

[0157] In some embodiments, see Figure 14 and Figure 15 The first shielding portion 31a includes a shielding layer 311 and a stress buffer structure 312 located in the shielding layer 311. The stress buffer structure 312 can reduce the stress of the first shielding portion 31a on the semiconductor device.

[0158] In some embodiments, the stress buffer structure 312 may be square, with a width of 0.2µm to 5µm; the stress buffer structure 312 may also be circular, with a diameter of 0.2µm to 5µm.

[0159] The material of the shielding layer 311 may include at least one of a metal, a metal compound, graphene, and carbon nanotubes. The metal may be at least one of W, Cu, and Al, and the metal compound may be at least one of TAN, Al₂O₃, and TiN. The material of the stress buffer structure 312 may include silicon nitride, silicon dioxide, or other materials with low dielectric constants.

[0160] Please see Figure 17 , Figure 17 This is provided by some embodiments of this application. Figure 1 A schematic cross-sectional view of a semiconductor device along the A-A1 direction. For ease of understanding and brief explanation, the same reference numerals are used for structures identical to those in the above embodiments, and identical structures are not described in detail again. This embodiment only provides detailed descriptions of different structures.

[0161] In this embodiment, the semiconductor device 700 and Figure 2 The difference in the semiconductor device 100 is that the first shielding portion 31a in the first shielding structure 30' includes a shielding layer 311 and a stress buffer structure 312 located in the shielding layer 311. The semiconductor device 700 also includes a third dielectric layer 80, which covers the first shielding portion 31a and is connected to the stress buffer structure 312. The stress buffer structure 312 is made of the same material as the third dielectric layer 80, so that the stress buffer structure 312 can be formed using the same process as the third dielectric layer 80, thereby simplifying the process.

[0162] The semiconductor device 700 further includes a redistribution layer 91, a connection structure 92, and a packaging layer (not shown). The redistribution layer 91 is located within the third dielectric layer 80. The connection structure 92 penetrates the stress buffer structure 312 and is connected to the redistribution layer 91. The packaging layer is located on the side of the third dielectric layer 80 away from the first shielding structure 30'.

[0163] Since the stress buffer structure 312 can be an insulating material, it can reserve a position for the connection structure 92, allowing the connection structure 92 to pass through the stress buffer structure 312. Thus, the connection structure 92 does not need to penetrate the shielding layer 311, thereby reducing the process difficulty of etching the connection structure 92.

[0164] Since the first shielding portion 31a is located between the encapsulation layer and the first device structure 20, the first shielding portion 31a can also reduce soft failures caused by alpha particle radiation in the encapsulation material.

[0165] This application also provides a method for fabricating a semiconductor device. Please refer to [link to relevant documentation]. Figure 18 , Figure 18 This is a schematic flowchart of a method for fabricating a semiconductor device according to some embodiments of this application. The fabrication method includes:

[0166] Step S1: Provide a substrate;

[0167] Step S2: A first device structure is formed on the substrate, the first device structure including a latching structure, and the first device structure having a first orthographic projection on the substrate;

[0168] Step S3: A first shielding structure is formed on one side of the substrate. At least a portion of the first shielding structure is disposed on the side of the first device structure away from the substrate. The first shielding structure has a second orthographic projection on the substrate surface, and the first orthographic projection is within the range of the second orthographic projection.

[0169] In the fabrication method of the semiconductor device, a first shielding structure is formed, and the first orthographic projection of the first device structure is located within the range of the second orthographic projection of the first shielding structure. Thus, the first shielding structure can reduce the entry of radiation particles into the first device structure, thereby reducing the soft failure rate of the device.

[0170] The following describes the fabrication method of the semiconductor device provided in the embodiments of this application with reference to the accompanying drawings.

[0171] Please see Figures 19-22 , Figures 19-22 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this application during the fabrication process. The fabrication method of the semiconductor device includes the following steps S1-S4.

[0172] Step S1: Provide substrate 10. See [link to relevant documentation]. Figure 19 .

[0173] The substrate 10 is a semiconductor substrate, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), silicon-on-insulator (SOI), or germanium-on-insulator (GOI). In other embodiments, the semiconductor substrate may also be a substrate comprising semiconductors of other elements or compound semiconductors, and may also be a stacked structure, such as Si / SiGe.

[0174] Step S2: A first device structure 20 is formed on the substrate 10. The first device structure 20 includes a latching structure and has a first orthographic projection on the substrate 10. (See also...) Figure 19 .

[0175] In some embodiments, the method of forming a latch structure may include: first forming a doped region 21 in a substrate 10; forming a source 22 and a drain 23 spaced apart in the doped region 21; and forming a gate 24 connected to the doped region 21 on the surface of the substrate 10, wherein the source 22 and the drain 23 are located on opposite sides of the gate 24.

[0176] The method for fabricating the semiconductor device may further include: forming a second device structure 40 adjacent to the first device structure 20 on a substrate 10; forming a second dielectric layer 70 covering the first device structure 20 and the second device structure 40; forming an interconnect layer 50 on the second dielectric layer 70; and forming a first dielectric layer 60 on the interconnect layer 50.

[0177] Step S3: A first shielding structure 30 is formed on one side of the substrate 10. At least a portion of the first shielding structure 30 is disposed on the side of the first device structure 20 away from the substrate 10. The first shielding structure 30 has a second orthographic projection on the surface of the substrate 10, and the first orthographic projection is within the range of the second orthographic projection. (See also...) Figures 20-22 .

[0178] See Figure 20 The first dielectric layer 60 and the interconnect layer 50 can be etched using an etching process (dry etching or wet etching) to form trenches 301.

[0179] See Figure 21 A first shielding structure 30 and a second shielding structure 35a are formed by filling the trench 301 and the surface of the first dielectric layer 60 with a filling material. The filling material may include at least one of metals, metal compounds, graphene and carbon nanotubes.

[0180] The first shielding structure 30 can be formed by a deposition process. The deposition process can be, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), such as thermal oxidation, evaporation, sputtering, and other methods.

[0181] See Figure 22 Alternatively, an etching process can be used to remove the second shielding structure 35a that covers the first device structure 20, forming a first shielding structure 30 including a first shielding portion 31 and a second shielding portion 32.

[0182] In some embodiments, a groove can be formed in the first shielding portion 31 by an etching process, and then a stress buffer structure 312 can be formed in the groove by a deposition process. See [link to documentation]. Figure 17 Then the first shielding part 31 becomes the first shielding part 31a, and the first shielding part 31a and the second shielding part 32 constitute the first shielding structure 30'.

[0183] See Figure 17 The method for fabricating the semiconductor device may further include: after forming the first shielding structure 30', forming a third dielectric layer 80 covering the first shielding structure 30' and the first dielectric layer 60; forming a redistribution layer 91 and a connection structure 92 connecting the redistribution layer 91 and the interconnect layer 50 in the third dielectric layer 80, wherein the connection structure 92 may be formed by a process and a deposition process.

[0184] In some embodiments, before forming the third dielectric layer 80, a groove is first formed in the first shielding portion 31. The third dielectric layer 80 is then deposited in the groove to form a stress buffer structure 312, thereby saving process steps. Furthermore, the position of the groove can correspond to the position of the connecting structure 92, so that the stress buffer structure 312 is etched when forming the connecting structure 92, without needing to etch the first shielding portion 31, thus reducing process complexity.

[0185] The method for fabricating the semiconductor device may further include: forming an encapsulation layer covering the third dielectric layer 80.

[0186] This application also provides a storage system; please refer to [link / reference]. Figure 23 , Figure 23 This is a schematic diagram of the structure of a storage system provided in some embodiments of this application.

[0187] The storage system 1000 includes a memory 1001 and a controller 1002. The memory 1001 can be the memory in any of the above embodiments, and the memory 1001 can include any of the semiconductor devices in the above embodiments. The controller 1002 is electrically connected to the memory 1001 and is used to control the memory 1001 to store data. The memory 1001 can perform the operation of storing data based on the control of the controller 1002.

[0188] In some implementations, the storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0189] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A first device structure disposed on the substrate, the first device structure including a latching structure, the first device structure having a first orthographic projection on the substrate; A first shielding structure, at least a portion of which is disposed on the side of the first device structure away from the substrate, the first shielding structure having a second orthographic projection on the substrate surface, and the first orthographic projection being within the range of the second orthographic projection.

2. The semiconductor device according to claim 1, characterized in that, The first shielding structure includes: The first shielding portion is disposed in a film layer parallel to the substrate; The second shielding portion extends toward the substrate along a first direction, which intersects with the substrate.

3. The semiconductor device according to claim 2, characterized in that, Also includes: An interconnect layer is located on the side of the first device structure away from the substrate; The first shielding portion is located on the side of the interconnect layer away from the substrate.

4. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes: A first dielectric layer is located between the interconnect layer and the first shielding portion, and the second shielding portion penetrates the first dielectric layer along the first direction.

5. The semiconductor device according to claim 2, characterized in that, Also includes: An interconnect layer is located on the side of the first device structure away from the substrate. The interconnect layer includes multiple overlapping interconnect portions, and the first shielding portion is located between two adjacent interconnect portions.

6. The semiconductor device according to claim 2, characterized in that, The second shielding portion is arranged around the edge of the first shielding portion.

7. The semiconductor device according to claim 2, characterized in that, The second shielding portion includes at least one embedded portion, which is connected to the edge of the first shielding portion and adjacent embedded portions are interconnected.

8. The semiconductor device according to claim 4, characterized in that, The first shielding structure further includes: The third shielding portion extends through the interconnect layer along the second direction, which intersects the substrate, and the third shielding portion is located on the side of the second shielding portion away from the first device structure; The fourth shielding portion is located between the interconnect layer and the first dielectric layer, and the fourth shielding portion is connected between the third shielding portion and the second shielding portion.

9. The semiconductor device according to claim 4, characterized in that, The first shielding structure further includes: The third shielding portion extends through the interconnect layer along the second direction, which intersects the substrate, and the third shielding portion is located on the side of the second shielding portion closer to the first device structure; The fourth shielding portion is located on the periphery of the first device structure and extends along a third direction, which intersects with the substrate. The fourth shielding portion is located on the side of the third shielding portion closer to the first device structure. The third shielding portion includes a first end close to the first shielding portion and a second end away from the first shielding portion. The first end extends to the membrane layer where the second shielding portion is located, and the second end extends to the membrane layer where the fourth shielding portion is located.

10. The semiconductor device according to claim 9, characterized in that, The latching structure includes a doped region, a source, a drain, and a gate. The doped region is located within the substrate, the gate is located on the surface of the substrate and connected to the doped region, and the source and drain are located within the doped regions on both sides of the gate. The semiconductor device further includes a second dielectric layer covering the first device structure and the substrate, the second dielectric layer being located between the interconnect layer and the substrate.

11. The semiconductor device according to claim 10, characterized in that, The third shielding portion also penetrates the second dielectric layer along the second direction, and the fourth shielding portion extends in the substrate along the third direction.

12. The semiconductor device according to claim 11, characterized in that, The dimension of the fourth shielding portion along the third direction is greater than or equal to the dimension of the doped region along the third direction.

13. The semiconductor device according to claim 10, characterized in that, The fourth shielding portion penetrates the second dielectric layer along the third direction and extends into the substrate.

14. The semiconductor device according to claim 4, characterized in that, The interconnect layer includes an insulating layer and a metal layer located in the insulating layer, and the second shielding portion is connected to the insulating layer.

15. The semiconductor device according to claim 14, characterized in that, Also includes: A second device structure is located on the surface of the substrate and is disposed adjacent to the first device structure, and the second device structure has a third orthographic projection on the surface of the substrate. The second shielding structure has a fourth orthographic projection on the substrate surface, and the third orthographic projection is within the range of the fourth orthographic projection.

16. The semiconductor device according to claim 15, characterized in that, The second shielding structure is located between the second device structure and the insulating layer; The second shielding portion also penetrates the insulating layer along the first direction and is connected to the second shielding structure.

17. The semiconductor device according to claim 15, characterized in that, The second shielding structure is connected to the first shielding part in the same layer.

18. The semiconductor device according to claim 15, characterized in that, The second device structure includes at least one of a non-volatile memory array, a digital logic circuit, an analog circuit, and a peripheral circuit. The first device structure includes at least one of a static random access memory array and a dynamic random access memory array.

19. The semiconductor device according to claim 1, characterized in that, The first shielding portion includes a shielding layer and a stress buffer structure located within the shielding layer.

20. The semiconductor device according to claim 19, characterized in that, The semiconductor device further includes: A third dielectric layer covers the first shielding portion and is connected to the stress buffer structure; The stress buffer structure is made of the same material as the third dielectric layer.

21. The semiconductor device according to claim 20, characterized in that, The semiconductor device further includes: A redistribution layer is located within the third dielectric layer; A connecting structure extends through the stress buffer structure and is connected to the redistribution layer; The encapsulation layer is located on the side of the third dielectric layer away from the first shielding structure.

22. The semiconductor device according to claim 1, characterized in that, The first shielding structure includes at least one of a metal, a metal compound, graphene, and carbon nanotubes.

23. The semiconductor device according to claim 2, characterized in that, The second shielding portion includes a first end away from the substrate and a second end close to the substrate, wherein the dimension of the first end along a fourth direction is greater than the dimension of the second end along the fourth direction, and the fourth direction is parallel to the substrate.

24. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A first device structure is formed on the substrate, the first device structure including a latching structure, and the first device structure having a first orthographic projection on the substrate; A first shielding structure is formed on one side of the substrate, at least a portion of the first shielding structure is disposed on the side of the first device structure away from the substrate, the first shielding structure has a second orthographic projection on the substrate surface, and the first orthographic projection is within the range of the second orthographic projection.

25. A storage system, characterized in that, include: The semiconductor device according to any one of claims 1 to 23; A controller, connected to the semiconductor device, is used to control the semiconductor device to store data.

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