Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention discloses a semiconductor device, a preparation method thereof and electronic equipment. The preparation method of the semiconductor device comprises the steps that a first initial stacking structure and a second initial stacking structure are formed, and each of the first initial stacking structure and the second initial stacking structure comprises a semiconductor thin film and a bonding thin film which are stacked; one first initial stacking structure and one second initial stacking structure are bonded to form a first stacking structure; preparing a first group of storage unit layers based on the first stack structure; wherein the first group of storage unit layers comprises two storage unit layers, each storage unit layer comprises a plurality of storage units arranged in an array, and the semiconductor thin film of the first group of storage unit layers is used for forming an active layer of the first group of storage unit layers. According to the preparation method provided by the invention, the quality of the active layer can be improved, the process complexity of stacking is reduced, and the occupied area of the semiconductor device can be reduced, so that the production cost is reduced.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking daily, while the types and number of devices contained in a single chip are increasing. This means that even minor differences in the manufacturing process can affect device performance. To minimize product costs, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands.

[0003] As the demand for memory continues to increase, the requirements for miniaturization of memory devices are becoming increasingly stringent. However, due to limitations in existing structures and processes, miniaturization of devices faces numerous difficulties, and existing fabrication processes are complex and produce products of relatively poor quality. Summary of the Invention

[0004] This disclosure provides a semiconductor device and its fabrication method, as well as an electronic device, which can solve problems such as high process difficulty, poor semiconductor device quality, high production cost, and large footprint.

[0005] On one hand, embodiments of this disclosure provide a method for fabricating a semiconductor device, comprising: A first initial stacked structure and a second initial stacked structure are formed, wherein both the first initial stacked structure and the second initial stacked structure include stacked semiconductor thin films and bonding thin films; A first initial stacked structure and a second initial stacked structure are bonded together to form a first stacked structure; The first set of storage cell layers is prepared based on the first stacked structure; The first group of memory cell layers includes two memory cell layers, each of which includes multiple memory cells arranged in an array. The semiconductor thin film of the first group of memory cell layers is used to form the active layer of the first group of memory cell layers.

[0006] In some exemplary embodiments, the semiconductor device includes N groups of memory cell layers, where N is an integer greater than or equal to 2, and each group of memory cell layers includes two memory cell layers; the fabrication method includes: The first initial stacking structure and the second initial stacking structure are bonded together to form the nth stacking structure; where n is an integer greater than or equal to 2 and less than or equal to N; The nth stack structure is bonded to the (n-1)th group of memory cell layers; The nth group of memory cell layers is prepared based on the nth stacked structure; Repeat the above operations until the Nth set of memory cell layers is prepared.

[0007] In some exemplary embodiments, the semiconductor device further includes N memory cell layers, where N is an integer greater than or equal to 1; the fabrication method includes: The nth first initial stack structure is bonded to the (n+1)th memory cell layer; where n is an integer greater than or equal to 1 and less than or equal to N; The (n+2)th memory cell layer is prepared based on the nth first initial stacking structure; Repeat the above operations until the Nth memory cell layer is prepared.

[0008] In some exemplary embodiments, the semiconductor device further includes N memory cell layers, where N is an integer greater than or equal to 1; the fabrication method includes: The nth second initial stack structure is bonded to the (n+1)th memory cell layer; where n is an integer greater than or equal to 1 and less than or equal to N; The (n+2)th memory cell layer is prepared based on the nth second initial stacking structure; Repeat the above operations until the Nth memory cell layer is prepared.

[0009] In some exemplary embodiments, the first initial stacked structure includes: a first semiconductor thin film, a second semiconductor thin film, a third semiconductor thin film, a first conductive thin film, and a first bonding thin film sequentially stacked on a first carrier plate; The second initial stacked structure includes: a fourth semiconductor film, a fifth semiconductor film, a sixth semiconductor film, and a second bonding film sequentially stacked on a second carrier plate; The step of bonding a first initial stacked structure and a second initial stacked structure to form a first stacked structure includes: bonding a first bonding film of the first initial stacked structure to a second bonding film of the second initial stacked structure to form a bonding layer, and removing the second carrier plate to form the first stacked structure.

[0010] In some exemplary embodiments, the two memory cell layers are a first memory cell layer and a second memory cell layer; the fabrication of the first set of memory cell layers based on the first stacking structure includes: The first stacked structure is etched along a third direction to form a plurality of spaced columnar structures, the columnar structures including the active layer of the first group of memory cell layers; Multiple bit lines are formed to form the first memory cell layer, and the bit lines extend along a first direction and are spaced apart in a second direction; Multiple first gate electrodes are formed to form the first memory cell layer. Multiple first gate electrodes arranged along the second direction are interconnected to form multiple word lines. The first direction and the second direction intersect. The third direction is perpendicular to the plane formed by the first direction and the second direction. The multiple word lines extend along the second direction and are distributed at intervals in the first direction. The second storage cell layer is formed along a third direction on the side of the first storage cell layer away from the first carrier.

[0011] In some exemplary embodiments, the plurality of bit lines forming the first memory cell layer include: Based on the columnar structure, metallic materials are deposited; An annealing process is performed to react the first semiconductor thin film with the metal material to form a metallization, and the metallization is etched to form multiple bit lines.

[0012] In some exemplary embodiments, the formation of a plurality of spaced columnar structures includes: The first semiconductor thin film forms a plurality of first electrodes, the second semiconductor thin film forms a plurality of first channel layers, and the third semiconductor thin film forms a plurality of second electrodes; the first conductive thin film forms a plurality of conductive structures, the conductive structures being used to form the first electrode plates of the first capacitor of the first memory cell layer. The sixth semiconductor thin film forms a plurality of third electrodes, the fifth semiconductor thin film forms a plurality of second channel layers, and the fourth semiconductor thin film forms a plurality of fourth electrodes; The active layer of the first memory cell layer includes the first electrode, the first channel layer, and the second electrode stacked sequentially along a third direction; The active layer of the second memory cell layer includes the third electrode, the second channel layer, and the fourth electrode, which are stacked sequentially along the third direction.

[0013] In some exemplary embodiments, the plurality of first gate electrodes forming the first memory cell layer include: A first dielectric film and a second dielectric film are formed sequentially, and the surface of the first dielectric film away from the first substrate is closer to the first substrate than the surface of the first trench layer away from the first substrate. The second dielectric film includes a first portion and a second portion connected to each other, and the first portion is closer to the first carrier plate than the second portion; the first portion and the second portion together form a plurality of first accommodating spaces, and the surface of the first portion away from the first carrier plate is closer to the first carrier plate than the surface of the first channel layer away from the first carrier plate.

[0014] In some exemplary embodiments, the plurality of first gate electrodes forming the first memory cell layer further include: A gate metal film is formed, and the gate metal film is located within the first accommodating space; wherein, the gate metal film includes a third part and a fourth part connected to each other, and the third part is closer to the first carrier plate than the fourth part, and the third part and the fourth part together form a plurality of second accommodating spaces; A sacrificial layer is formed, and the sacrificial layer is located within the second accommodating space. The second dielectric film and the gate metal film that are not covered by the sacrificial layer are removed. The sacrificial layer is removed to form a plurality of trenches spaced apart along a first direction. The second dielectric film and the gate metal film located in the trenches are removed to expose a portion of the first dielectric film. The second dielectric film forms a plurality of first gate insulating layers, and the gate metal film forms a plurality of first gate electrodes. The first gate insulating layers surround the sidewalls of the first channel layer, and the first gate electrodes surround the sidewalls of the first gate insulating layers.

[0015] In some exemplary embodiments, after forming the first gate electrode, the process includes: A third dielectric film is formed, and at least a portion of the third dielectric film fills the trench; A dielectric thin film and a second conductive thin film are sequentially formed to cover the conductive structure; The dielectric film and the second conductive film are etched to form the first dielectric layer of a first capacitor with multiple first memory cell layers, and the second conductive film forms the second electrode plate of the first capacitor with multiple first memory cell layers.

[0016] In some exemplary embodiments, prior to sequentially forming the dielectric thin film and the second conductive thin film, the process includes: The conductive structure is etched to form the first plate of the first capacitor of the first memory cell layer.

[0017] In some exemplary embodiments, forming the second storage cell layer along a third direction on the side of the first storage cell layer away from the first carrier includes: An isolation layer is formed on the side of the first storage cell layer away from the first carrier board; Multiple bit lines of the second memory cell layer are formed on the side of the isolation layer away from the first carrier plate, extending along the first direction and spaced apart in the second direction; A plurality of second gate insulating layers and a plurality of second gate electrodes are formed on the side of the bit line away from the first carrier plate; A third electrode plate, a second dielectric layer, and a fourth electrode plate are sequentially formed on the side of the columnar structure away from the first carrier plate. The third electrode plate, the second dielectric layer, and the fourth electrode plate form the second capacitor of the second memory cell layer.

[0018] On the other hand, embodiments of this disclosure provide a semiconductor device, including: Substrate; A plurality of stacked memory cell layers are located on the substrate, and each memory cell layer includes a plurality of memory cells arranged in an array; and Multiple bonding layers are provided, and the bonding layers are provided between the storage cells of two adjacent storage cell layers.

[0019] In some exemplary embodiments, each of the memory cells includes an active layer and a gate electrode, wherein the active layer extends along a direction perpendicular to the plane of the substrate, and the gate electrode surrounds the sidewall of the active layer and is insulated from the active layer.

[0020] In some exemplary embodiments, the plurality of memory cell layers include a first memory cell layer and a second memory cell layer; the first memory cell layer includes a first capacitor, the first capacitor includes a first electrode, a first dielectric layer and a second electrode, the first electrode extends along a direction perpendicular to the plane of the substrate, the first dielectric layer surrounds the outer wall of the first electrode, and the second electrode surrounds the outer wall of the first dielectric layer. The bonding layer located between the first memory cell layer and the second memory cell layer is located on the side of the first electrode away from the substrate, and the bonding layer extends in a direction perpendicular to the plane of the substrate, with the first dielectric layer surrounding the outer wall of the bonding layer.

[0021] In some exemplary embodiments, the bonding layer includes a first bonding sublayer and a second bonding sublayer stacked thereon, the first bonding sublayer being closer to the substrate than the second bonding sublayer, and the first dielectric layer surrounding the outer wall of the first bonding sublayer and the outer wall of the second bonding sublayer, and the surface of the second bonding sublayer away from the substrate being farther from the substrate than the surface of the first dielectric layer away from the substrate.

[0022] On the other hand, embodiments of this disclosure provide an electronic device, including a semiconductor device manufactured by the method described in any of the foregoing semiconductor devices, or a semiconductor device described in any of the foregoing embodiments.

[0023] The semiconductor device fabrication method provided in this disclosure involves forming a first initial stacked structure and a second initial stacked structure, and then bonding the first initial stacked structure and the second initial stacked structure using a bonding process to form a first stacked structure. This allows for etching and other operations on the first stacked structure to form multiple active layers, thereby improving the quality of the active layers, reducing the complexity of the stacking process, reducing the area occupied by the semiconductor device, facilitating the miniaturization design of the semiconductor device, and reducing production costs.

[0024] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description

[0025] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0026] Figure 1 This is a schematic diagram of a three-dimensional structure of a semiconductor device according to an embodiment of the present disclosure; Figure 2A This is a cross-sectional schematic diagram of a semiconductor device after forming a first initial stacking structure according to an embodiment of the present disclosure; Figure 2B This is a cross-sectional schematic diagram of a semiconductor device after forming a second initial stacking structure according to an embodiment of the present disclosure; Figure 3 This is a cross-sectional schematic diagram of a semiconductor device after being formed into a stacked structure according to an embodiment of the present disclosure; Figure 4 This is a cross-sectional schematic diagram of a semiconductor device after forming the bit line of the first memory cell layer according to an embodiment of the present disclosure; Figure 5 This is a cross-sectional schematic diagram of a semiconductor device after the formation of a second dielectric thin film according to an embodiment of the present disclosure; Figure 6 This is a cross-sectional schematic diagram of a semiconductor device after a gate metal thin film has been formed, according to an embodiment of the present disclosure; Figure 7 This is a cross-sectional schematic diagram of a semiconductor device after the formation of a sacrificial layer according to an embodiment of the present disclosure; Figure 8 This is a cross-sectional schematic diagram of a semiconductor device after the gate electrode structure has been formed according to an embodiment of the present disclosure; Figure 9A and Figure 9B This is a schematic diagram of a semiconductor device after trenching according to an embodiment of the present disclosure; Figure 10 This is a cross-sectional schematic diagram of a semiconductor device after a third dielectric thin film has been formed according to an embodiment of the present disclosure; Figure 11 This is a cross-sectional schematic diagram of a semiconductor device after the first electrode plate has been formed according to an embodiment of the present disclosure; Figure 12 This is a cross-sectional schematic diagram of a semiconductor device after a dielectric thin film has been formed according to an embodiment of the present disclosure; Figure 13 This is a cross-sectional schematic diagram of a semiconductor device after the formation of a second conductive thin film according to an embodiment of the present disclosure; Figure 14 This is a cross-sectional schematic diagram of a semiconductor device after the second electrode plate has been formed according to an embodiment of the present disclosure; Figure 15 This is a cross-sectional schematic diagram of a semiconductor device after forming the bit line of the second memory cell layer according to an embodiment of the present disclosure; Figure 16 This is a cross-sectional schematic diagram of a semiconductor device after the formation of a fourth dielectric thin film according to an embodiment of the present disclosure; Figure 17 This is a cross-sectional schematic diagram of a semiconductor device after the formation of a fifth dielectric thin film according to an embodiment of the present disclosure; Figure 18 This is a schematic cross-sectional view of a semiconductor device after forming a second capacitor according to an embodiment of the present disclosure; Figure 19 This is a cross-sectional view of a semiconductor device after the first group of memory cell layers and the first initial stacking structure are bonded, according to another embodiment of this disclosure. Figure 20 This is a cross-sectional view of a semiconductor device after the first group of memory cell layers and the second initial stacking structure are bonded, according to another embodiment of this disclosure. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0028] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0029] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.

[0030] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0031] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0032] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0033] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0034] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0035] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0036] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0037] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0038] Memory is a storage device used to store information in modern information technology. With the development of technology, the types of memory have become increasingly diverse, such as dynamic random access memory (DRAM), magnetic random access memory (MRAM), and static random access memory (SRAM).

[0039] As the demand for DRAM continues to increase, the size of memory cells is approaching its physical limits. Miniaturization of DRAM remains challenging due to process limitations. A viable approach is to further reduce the size of memory cells by implementing a 3D stacked vertical channel transistor structure for DRAM.

[0040] This disclosure provides a method for fabricating a semiconductor device, comprising: A first initial stacked structure and a second initial stacked structure are formed, wherein both the first initial stacked structure and the second initial stacked structure include stacked semiconductor thin films and bonding thin films; A first initial stacked structure and a second initial stacked structure are bonded together to form a first stacked structure; The first set of storage cell layers is prepared based on the first stacked structure; The first group of memory cell layers includes two memory cell layers, each of which includes multiple memory cells arranged in an array. The semiconductor thin film of the first group of memory cell layers is used to form the active layer of the first group of memory cell layers.

[0041] The semiconductor device fabrication method provided in this disclosure involves forming a first initial stacked structure and a second initial stacked structure, and then bonding the first initial stacked structure and the second initial stacked structure using a bonding process to form a first stacked structure. This allows for etching and other operations on the first stacked structure to form multiple active layers, thereby improving the quality of the active layers, reducing the complexity of the stacking process, reducing the area occupied by the semiconductor device, facilitating the miniaturization design of the semiconductor device, and reducing production costs.

[0042] Figure 1 This is a schematic diagram of a three-dimensional structure of a semiconductor device according to an embodiment of this disclosure. Figure 1 As shown, in this embodiment of the disclosure, three directions are defined: a first direction X, a second direction Y, and a third direction Z. The first direction X, the second direction Y, and the third direction Z can be mutually perpendicular. The semiconductor device may include multiple memory cell layers, which can be stacked sequentially along the third direction Z. For example, the semiconductor device may include two sequentially stacked memory cell layers, or it may include three sequentially stacked memory cell layers, or it may include four sequentially stacked memory cell layers, etc. In this embodiment of the disclosure, the illustration shows a semiconductor device including two memory cell layers as an example. However, this disclosure does not limit the number of memory cell layers included in the semiconductor device. The semiconductor device includes two memory cell layers, which can be referred to as a first memory cell layer 100a and a second memory cell layer 100b, respectively.

[0043] The first storage cell layer 100a may include a plurality of first storage cells 101. For example, the first storage cell layer 100a may include two first storage cells 101, or the first storage cell layer 100a may include four first storage cells 101, etc. The plurality of first storage cells 101 within the first storage cell layer 100a may be arranged in an array. For example, the plurality of first storage cells 101 may be arranged in a rectangular array, etc. In the embodiments of this disclosure, the first storage cell layer 100a includes nine first storage cells 101 as an example. However, this disclosure does not limit the number of first storage cells included in the first storage cell layer. The nine first storage cells 101 within the first storage cell layer 100a may be arranged in a form of 3 rows (first direction X) and 3 columns (second direction Y).

[0044] The first storage cell 101 may include at least one first transistor 11. For example, the first storage cell 101 may include one first transistor 11 or two first transistors 11, etc. In this embodiment of the disclosure, the first storage cell 101 includes one first transistor 11 and one first capacitor 21 as an example.

[0045] In some exemplary embodiments, such as Figure 1 As shown, the first memory cell layer 100a may further include at least one word line WL and at least one bit line BL. For example, the first memory cell layer 100a may include one word line WL and one bit line BL, or the first memory cell layer 100a may include two word lines WL and two bit lines BL, etc. In this embodiment of the disclosure, three word lines WL and three bit lines BL are used as an example. However, this disclosure does not limit the number of word lines and bit lines included in the first memory cell layer.

[0046] Within the first memory cell layer 100a, the bit lines BL are farther away from the second memory cell layer 100b than the word lines WL. Multiple bit lines BL can extend along a first direction X, and are spaced apart along a second direction Y. For example, multiple bit lines BL can be arranged at equal intervals along the second direction Y. Multiple word lines WL can also extend along the second direction Y, and are spaced apart along the first direction X. For example, multiple word lines WL can be arranged at equal intervals along the first direction X.

[0047] In some exemplary embodiments, such as Figure 1 As shown, the first memory cell layer 100a may include at least one memory cell row, and the memory cell row may include a plurality of first memory cells 101. The plurality of first transistors 11 of the plurality of first memory cells 101 located within the same memory cell row may be connected to the same bit line BL. For example, as... Figure 1 As shown, the first storage cell layer 100a includes three storage cell rows, and each storage cell row includes three first storage cells.

[0048] In some exemplary embodiments, such as Figure 1 As shown, the first memory cell layer 100a may include at least one memory cell column, and the memory cell column may include a plurality of first memory cells 101. A plurality of first transistors 11 of the plurality of first memory cells 101 located within the same memory cell column may be connected to the same word line WL. For example, as... Figure 1 As shown, the first storage cell layer 100a includes three storage cell columns, and each storage cell column includes three first storage cells.

[0049] In some exemplary embodiments, such as Figure 1As shown, the first transistor 11 may include a first channel layer 11-3 and a first gate electrode 11-4. The first channel layer 11-3 may extend in the third direction Z. The first gate electrode 11-4 may surround the sidewall of the first channel layer 11-3 and is insulated from the first channel layer 11-3 via a first gate insulating layer. Figure 1 The first gate insulating layer is not shown. In the embodiments of this disclosure, the first transistor can be formed as a vertical channel transistor (VCT), which is beneficial for forming a 3D stacked semiconductor structure. This can reduce the footprint of the semiconductor device, reduce production costs, and increase integration density. Furthermore, the short-channel effect of the first transistor can be improved by changing the length of the first channel layer (i.e., the dimension along the third direction), thereby improving the performance of the semiconductor device.

[0050] In some exemplary embodiments, the second storage cell layer 100b may include a plurality of second storage cells 102. For example, the second storage cell layer 100b may include two second storage cells 102, or the second storage cell layer 100b may include four second storage cells 102, etc. The plurality of second storage cells 102 within the second storage cell layer 100b may be arranged in an array, for example, the plurality of second storage cells 102 may be arranged in a rectangular array, etc. In the embodiments of this disclosure, the second storage cell layer 100b includes nine second storage cells 102 as an example. However, this disclosure does not limit the number of second storage cells included in the second storage cell layer. The nine second storage cells 102 within the second storage cell layer 100b may be arranged in a form of 3 rows (first direction X) and 3 columns (second direction Y).

[0051] The second memory cell 102 may include at least one second transistor 12. For example, the second memory cell 102 may include one or two second transistors 12, etc. In this embodiment, the second memory cell 102 includes one second transistor 12 and a second capacitor 22 as an example. The second transistor 12 may include a second channel layer 12-2 and a second gate electrode 12-1. The second channel layer 12-2 may extend in the third direction Z. The second gate electrode 12-1 may surround the sidewall of the second channel layer 12-2 and be insulated from the second channel layer 12-2 via a second gate insulating layer. Figure 1 The second gate insulating layer is not shown. In embodiments of this disclosure, the second transistor may be formed as a vertical channel transistor (VCT).

[0052] In some exemplary embodiments, the structure of the second storage cell layer 100b may be the same as or different from that of the first storage cell layer 100a.

[0053] In some exemplary embodiments, the semiconductor device may include at least one memory cell string 100c, which may include at least two memory cells stacked sequentially along a third direction Z. For example, the memory cell string 100c may include two memory cells, namely a first memory cell 101 and a second memory cell 102. This disclosure does not limit the number of memory cells included in a memory cell string. In embodiments of this disclosure, taking a semiconductor device comprising nine memory cell strings 100c as an example, the nine memory cell strings 100c may be arranged in a 3-row (first direction X) 3-column (second direction Y) configuration.

[0054] The following example illustrates the structure of a semiconductor device through its fabrication process. Taking the formation of a first set of memory cell layers as an example, the fabrication process includes a first memory cell layer and a second memory cell layer. The fabrication process of the first set of memory cell layers may include the following steps:

[0055] (01) Forming a first initial stacked structure, which may include: sequentially forming a first semiconductor thin film 1-1, a second semiconductor thin film 1-2, a third semiconductor thin film 1-3, a first conductive thin film 1-4, and a first bonding thin film 1-5 on a first carrier plate 1, such as Figure 2A As shown. For example, an epitaxial process can be used to sequentially form a first semiconductor thin film 1-1, a second semiconductor thin film 1-2, and a third semiconductor thin film 1-3 on the first substrate 1. For example, a deposition process can be used to form a first conductive thin film 1-4 and a first bonding thin film 1-5 on the first substrate 1. The deposition process can include atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0056] In some exemplary embodiments, the first carrier 1 may be a silicon wafer, etc. For example, the silicon wafer may be a silicon wafer, etc.

[0057] In some exemplary embodiments, the first semiconductor thin film 1-1, the second semiconductor thin film 1-2, and the third semiconductor thin film 1-3 can be used to form the active layer of the first transistor in subsequent processes. The materials of the first semiconductor thin film 1-1, the second semiconductor thin film 1-2, and the third semiconductor thin film 1-3 can all include N-type semiconductor materials; for example, the N-type semiconductor material includes silicon. For example, the first transistor can be of the N+NN+ doped type.

[0058] In some exemplary embodiments, the material of the first conductive film 1-4 may include a metallic material or other conductive material, and the first conductive film 1-4 may be used in a subsequent process to form the first electrode of the first capacitor. For example, the metallic material may include at least one of tungsten (W), molybdenum (Mo), cobalt (Co), titanium (Ti), copper (Cu), aluminum (Al), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), silver (Ag), or gold (Au), or an alloy of the above metals. The first conductive film 1-4 may be a single-layer or multi-layer structure. For example, the first conductive film 1-4 may be a multi-layer structure formed of titanium nitride (TiN) and tungsten (W). Alternatively, the first conductive film 1-4 may be a single-layer structure formed of titanium nitride (TiN).

[0059] In some exemplary embodiments, the material of the first bonding film 1-5 may include silicon oxynitride (SiO2). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x ) or aluminum oxide (AlO x ) or hafnium oxide (HfO) x At least one of the following: . The first bonding film 1-5 can be a single layer or a multilayer structure. The first bonding film 1-5 can be used as a protective layer for the first conductive film 1-4, and the first bonding film 1-5 can be used to form a bonding layer in subsequent processes.

[0060] (02) Forming a second initial stacked structure may include: sequentially forming a fourth semiconductor thin film 2-9, a fifth semiconductor thin film 2-8, a sixth semiconductor thin film 2-7, and a second bonding thin film 2-6 on the second carrier plate 2, such as Figure 2B As shown. For example, an epitaxial process can be used to sequentially form a fourth semiconductor thin film 2-9, a fifth semiconductor thin film 2-8, and a sixth semiconductor thin film 2-7 on the second substrate 2. For example, a deposition process can be used to form a second bonding thin film 2-6 on the second substrate 2. The deposition process can include atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0061] In some exemplary embodiments, the second carrier 2 may be a silicon wafer, etc. For example, the silicon wafer may be a silicon crystalline wafer, etc. The material and dimensions of the second carrier may be the same as or different from those of the first carrier.

[0062] In some exemplary embodiments, the fourth semiconductor thin film 2-9, the fifth semiconductor thin film 2-8, and the sixth semiconductor thin film 2-7 can be used to form the active layer of the second transistor in subsequent processes. The materials of the fourth semiconductor thin film 2-9, the fifth semiconductor thin film 2-8, and the sixth semiconductor thin film 2-7 can all include N-type semiconductor materials; for example, the N-type semiconductor material includes silicon. For example, the second transistor can be of the N+NN+ doped type. The doping type of the second transistor can be the same as or different from the doping type of the first transistor.

[0063] In some exemplary embodiments, the material of the second bonding film 2-6 may include silicon oxynitride (SiO2). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x ) or aluminum oxide (AlO x ) or hafnium oxide (HfO) x At least one of the following. The second bonding film 2-6 can be a single layer or a multilayer structure. The second bonding film 2-6 can be used as a protective layer for the sixth semiconductor film 2-7, and the second bonding film 2-6 can be used to form a bonding layer in subsequent processes.

[0064] In some exemplary embodiments, the operations of forming the second initial stacking structure and the operations of forming the first initial stacking structure may be interchanged in order. Alternatively, the operations of forming the second initial stacking structure and the operations of forming the first initial stacking structure may be performed simultaneously.

[0065] (03) Forming a stacked structure, which may include: bonding a first initial stacked structure to a second initial stacked structure using a bonding process, and then removing the second carrier board to form the stacked structure, such as Figure 3 As shown, the first carrier plate becomes the substrate. Since the fabrication process is based on the formation of the first set of memory cell layers, the first stacked structure is simply referred to as the stacked structure.

[0066] The first bonding film 1-5, located away from the first conductive film 1-4, is bonded to the second bonding film 2-6, located away from the sixth semiconductor film 2-7, using a bonding process. The stacked structure may include the first semiconductor film 1-1, the second semiconductor film 1-2, the third semiconductor film 1-3, the first conductive film 1-4, the first bonding film 1-5, the second bonding film 2-6, the sixth semiconductor film 2-7, the fifth semiconductor film 2-8, and the fourth semiconductor film 2-9, which are stacked sequentially.

[0067] (04) Forming the bit line of the first memory cell layer, which may include: etching the stacked structure formed by the aforementioned operation from the side of the fourth semiconductor thin film 2-9 away from the first semiconductor thin film 1-1 toward the side closer to the first semiconductor thin film 1-1, so that the stacked structure forms at least one columnar structure 200, and then forming at least one bit line BL of the first memory cell layer, such as Figure 4 As shown. The etching process can include at least one of dry etching and wet etching.

[0068] In some exemplary embodiments, the stacked structure formed by the aforementioned operation is etched from the side of the fourth semiconductor thin film 2-9 away from the first semiconductor thin film 1-1 toward the direction closer to the first semiconductor thin film 1-1, so that the stacked structure forms a plurality of equally spaced columnar structures 200.

[0069] In some exemplary embodiments, the stacked structure formed by the aforementioned operations is etched such that the first semiconductor thin film 1-1 forms the first electrode 11-1 of at least one first transistor 11, such as... Figure 4 As shown, the first electrode 11-1 of three first transistors is illustrated, and the second semiconductor thin film 1-2 forms the first channel layer 11-3 of at least one first transistor 11, and the third semiconductor thin film 1-3 forms the second electrode 11-2 of at least one first transistor 11. In the embodiments of this disclosure, the first electrode, the first channel layer and the second electrode are stacked sequentially along the third direction Z to form the active layer of a first transistor of the first memory cell layer.

[0070] In some exemplary embodiments, the stacked structure formed by the aforementioned operations is etched such that a sixth semiconductor thin film 2-7 forms the third electrode 12-3 of at least one second transistor 12, a fifth semiconductor thin film 2-8 forms the second channel layer 12-2 of at least one second transistor 12, and a fourth semiconductor thin film 2-9 forms the fourth electrode 12-4 of at least one second transistor 12. The third electrode 12-3 is one of the source and drain electrodes of the second transistor, and the fourth electrode 12-4 is the other of the source and drain electrodes of the second transistor. In embodiments of this disclosure, the third electrode, the second channel layer, and the fourth electrode, which are sequentially stacked along the third direction Z, constitute the active layer of a second transistor in the second memory cell layer.

[0071] In some exemplary embodiments, the stacked structure formed by the aforementioned operations is etched such that the first conductive film 1-4 forms at least one conductive structure 5, which is used to form the first electrode of the first capacitor of the first memory cell layer in a subsequent process.

[0072] In some exemplary embodiments, the stacked structure formed by the aforementioned operations is etched such that at least one bonding layer 4 is formed on the first bonding film 1-5 and the second bonding film 2-6. A first transistor and a second transistor can be bonded together via a bonding layer 4. For example, the side of the conductive structure 5 away from the second electrode 11-2 of the first transistor 11 is bonded to the third electrode 12-3 of the second transistor 12 via a bonding layer 4.

[0073] In some exemplary embodiments, the bonding layer 4 may include a first bonding sublayer 4-1 and a second bonding sublayer 4-2 stacked sequentially. During the fabrication process, the first bonding film 1-5 is etched to form at least one first bonding sublayer 4-1, and the second bonding film 2-6 is etched to form at least one second bonding sublayer 4-2.

[0074] In some exemplary embodiments, such as Figure 4 As shown, the columnar structure 200 may include a first electrode 11-1, a first channel layer 11-3, a second electrode 11-2, a conductive structure 5, a first bonding layer 4-1, a second bonding layer 4-2, a third electrode 12-3, a second channel layer 12-2, and a fourth electrode 12-4, which are sequentially stacked in a direction away from the first carrier plate 1. For example, the multiple columnar structures 200 may extend along a third direction and be arranged at equal intervals in the first direction X and the second direction Y.

[0075] In some exemplary embodiments, forming multiple bit lines BL of the first memory cell layer may include: after forming the columnar structure 200, depositing a conductive material, such as TiN, or a metallic material, such as Ni, Cu, Co, etc., on the first substrate 1, followed by annealing. The first semiconductor thin film reacts with the metal to form a metallization, which is then patterned and etched to form multiple bit lines BL of the first memory cell layer. For example, the bit lines BL of the first memory cell layer may extend along a first direction X, and the multiple bit lines BL may be spaced apart along a second direction Y. The plane formed by the first direction X and the second direction Y is parallel to the plane of the first substrate 1.

[0076] (05) A first dielectric film 6 and a second dielectric film 7 are sequentially formed on the first carrier plate 1 that forms the aforementioned structure, such as Figure 5 As shown, for example, a deposition process can be used to sequentially form a first dielectric film 6 and a second dielectric film 7.

[0077] The first dielectric film 6 can fill the space between two adjacent columnar structures 200 and the space near the edge of the columnar structure 200 on the first carrier plate 1. The surface of the first dielectric film 6 away from the first carrier plate 1 is closer to the first carrier plate 1 than the surface of the first channel layer 11-3 away from the first carrier plate 1. That is, after forming the first dielectric film 6, part or all of the first channel layer 11-3 is exposed to allow for the fabrication of a gate insulating layer and a gate electrode on the channel layer surface. In this embodiment, the first dielectric film can compensate for the Z-direction drop between the second dielectric film and the first carrier plate, facilitating the formation of a first gate electrode surrounding the first channel layer in subsequent processes. The orthographic projection of the second dielectric film 7 onto the plane of the first carrier plate 1 can encompass the orthographic projection of multiple columnar structures 200 onto the plane of the first carrier plate 1. In this embodiment, the second dielectric film is configured to form at least one first gate insulating layer in subsequent processes.

[0078] In some exemplary embodiments, the second dielectric film 7 may form at least one first receiving space 301, the first receiving space 301 being an annular shape surrounding the columnar structure 200 in its orthographic projection onto the plane of the first carrier plate 1. Multiple first receiving spaces 301 may be interconnected. In embodiments of this disclosure, the first receiving spaces are configured to receive a gate metal film in subsequent processes.

[0079] In some exemplary embodiments, the second dielectric film 7 may include a first portion 7-1 and a second portion 7-2 connected to each other, with the first portion 7-1 being closer to the first carrier plate 1 than the second portion 7-2. The first portion 7-1 is parallel to the first carrier plate 1 and covers the side of the first dielectric film 6 away from the first carrier plate 1, while the second portion 7-2 extends in a third direction and surrounds the surface of the columnar structure 200. The first portion 7-1 and the second portion 7-2 together form at least one first receiving space 301. The surface of the first portion 7-1 away from the first carrier plate 1 is closer to the first carrier plate 1 than the surface of the first channel layer 11-3 away from the first carrier plate 1, so as to facilitate the formation of a first gate electrode surrounding the first channel layer in subsequent processes.

[0080] In some exemplary embodiments, the material of the first dielectric film may be the same as or different from the material of the second dielectric film.

[0081] In some exemplary embodiments, the material of the first dielectric film may be spin-coated insulating dielectric material SOD.

[0082] In some exemplary embodiments, the material of the second dielectric thin film may include silicon oxynitride (SiO2). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x) or aluminum oxide (AlO x ) or hafnium oxide (HfO) x At least one of the following. For example, the material of the second dielectric film may include a low-K dielectric material, i.e., a dielectric material with a dielectric constant K < 3.9, such as silicon dioxide (SiO2). Alternatively, the material of the second dielectric film may include a high dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. For example, a high dielectric material may include at least one of hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO), and strontium titanate (SrTiO3). The inclusion of a high dielectric material in the second dielectric film can improve the insulation performance between the first channel layer and the first gate electrode of the first transistor, thereby improving the electrical performance of the semiconductor device.

[0083] (06) A grid metal thin film 8 is formed on the first carrier plate 1 that forms the aforementioned structure, such as Figure 6 As shown. For example, a deposition process can be used to form a gate metal film 8. The gate metal film 8 is located within a first receiving space 301 and surrounds the columnar structure 200. In embodiments of this disclosure, the gate metal film is configured to form at least one first gate electrode in a subsequent process.

[0084] In some exemplary embodiments, the gate metal film 8 may form at least one second accommodating space 302, which in this embodiment is configured to accommodate a sacrificial layer in a subsequent process.

[0085] In some exemplary embodiments, the gate metal film 8 may include a third portion 8-3 and a fourth portion 8-4 connected to each other, with the third portion 8-3 being closer to the first carrier plate 1 than the fourth portion 8-4. The third portion 8-3 is parallel to the first carrier plate and covers the surface of the first portion 7-1 of the second dielectric film away from the first carrier plate 1. The fourth portion 8-4 extends in a third direction and surrounds the surface of the second portion 7-2 of the second dielectric film away from the columnar structure 200. The third portion 8-3 and the fourth portion 8-4 together form at least one second receiving space 302.

[0086] In some exemplary embodiments, the material of the gate metal film may include a metallic material or other conductive material. For example, the metallic material may include at least one of tungsten (W), molybdenum (Mo), cobalt (Co), titanium (Ti), copper (Cu), aluminum (Al), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), silver (Ag), or gold (Au), or an alloy of the above metals. The gate metal film may be a single-layer or multi-layer structure. For example, the gate metal film may be a multi-layer structure formed of titanium nitride (TiN) and tungsten (W). Alternatively, the gate metal film may be a single-layer structure formed of titanium nitride (TiN).

[0087] (07) A sacrificial layer 9 is formed on the first carrier plate 1 that forms the aforementioned structure, such as Figure 7 As shown. The sacrificial layer 9 is located within the second receiving space 302. The surface of the sacrificial layer 9 away from the first carrier plate 1 is further away from the first carrier plate 1 than the surface of the first channel layer 11-3 away from the first carrier plate 1, or the surface of the sacrificial layer 9 away from the first carrier plate 1 is flush with the surface of the first channel layer 11-3 away from the first carrier plate 1. The surface of the sacrificial layer 9 away from the first carrier plate 1 is closer to the first carrier plate 1 than the surface of the second electrode 11-2 away from the first carrier plate 1. The sacrificial layer 9 can provide protection for the second dielectric film 7 and the gate metal film 8 covered by the sacrificial layer. In subsequent processes, the second dielectric film covered by the sacrificial layer forms an insulating structure, and the gate metal film covered by the sacrificial layer forms a gate electrode structure. In some possible embodiments, the surface of the sacrificial layer 9 away from the first carrier plate 1 is flush with the surface of the second electrode 11-2 away from the first carrier plate 1.

[0088] In some exemplary embodiments, the material of the sacrificial layer may include silicon oxynitride (SiO2). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x ) or aluminum oxide (AlO x ) or hafnium oxide (HfO) x At least one of the following. For example, the material of the sacrificial layer may include silicon nitride.

[0089] (08) The first substrate 1 forming the aforementioned structure is etched to form at least one insulating structure 10 in the second dielectric film and at least one gate electrode structure 13 in the gate metal film, and then the sacrificial layer 9 is removed. The insulating structure 10 surrounds the sidewall of the columnar structure 200, and the gate electrode structure 13 surrounds the sidewall of the insulating structure 10, as shown below. Figure 8 As shown.

[0090] (09) The first carrier plate 1 forming the aforementioned structure is etched to form at least one trench 300, such as... Figure 9A and Figure 9B As shown, Figure 9B for Figure 9A A cross-sectional view at point AA. Figure 9A The first dielectric film 6 and the first carrier plate 1 are not filled to facilitate identification, and the first dielectric film 6 is displayed semi-transparently. Figure 9A In the example shown, nine columnar structures 200 are arranged in a matrix of 3 rows (first direction X) and 3 columns (second direction Y).

[0091] The trench 300, when projected onto the plane of the first substrate 1, can be a rectangle extending along the second direction Y. Both the second dielectric film and the gate metal film within the trench 300 are etched away, exposing a portion of the first dielectric film 6. In this embodiment, the trench separates two adjacent columnar structures along the first direction X, and disconnects the insulating structure and the gate electrode structure in the first direction X, such that the insulating structure forms at least one first gate insulating layer 14, and the gate electrode structure forms at least one first gate electrode 11-4.

[0092] In some exemplary embodiments, a plurality of first gate electrodes 11-4 are spaced apart along the second direction Y and interconnected to form a plurality of word lines WL of the first memory cell layer. The plurality of word lines extend along the second direction and are spaced apart in the first direction.

[0093] (10) A third dielectric film 15 is formed on the first carrier plate 1 that forms the aforementioned structure, such as Figure 10 As shown, for example, a third dielectric film 15 can be formed by deposition. At least a portion of the third dielectric film 15 fills within the trench 300, and the side of the third dielectric film 15 away from the first substrate 1 is planar. The surface of the third dielectric film 15 away from the first substrate 1 can be flush with the surface of the second electrode 11-2 away from the first substrate 1. In this embodiment, on the one hand, the third dielectric film can act as a planarization layer to ensure the quality of the first dielectric layer of the first capacitor formed in subsequent processes. On the other hand, the third dielectric film can act as a compensation structure to compensate for the drop in the third direction Z between the first dielectric layer and the first gate electrode of the first capacitor formed in subsequent processes, thereby reducing the size of the first dielectric layer in the third direction Z and improving the integration density of the semiconductor device. Furthermore, the third dielectric film can act as an insulating layer to avoid signal crosstalk between two adjacent first transistors in the first direction X, thereby improving the performance of the semiconductor device.

[0094] In some possible embodiments, the surface of the third dielectric film 15 away from the first carrier plate 1 is flush with the surface of the trench 300 away from the first carrier plate 1.

[0095] In some exemplary embodiments, the material of the third dielectric film may be the same as or different from the material of the first dielectric film.

[0096] (11) The first carrier plate 1 forming the aforementioned structure is etched so that the conductive structure 5 forms the first electrode 21-1 of the first capacitor, as shown in the figure. Figure 11 As shown. In this embodiment of the disclosure, the columnar structure formed by etching the conductive structure 5 to form the first electrode plate 21-1 can be referred to as column 200a.

[0097] In some possible embodiments, the conductive structure 5 is the first plate 21-1 of the first capacitor.

[0098] (12) A dielectric thin film 16 is formed on the first carrier plate 1 that forms the aforementioned structure, such as Figure 12 As shown. For example, a deposition process can be used to form a dielectric thin film. The orthographic projection of the dielectric thin film 16 onto the plane of the first substrate 1 can cover the orthographic projection of the plurality of pillars 200a onto the plane of the first substrate 1. The dielectric thin film 16 can cover components in the semiconductor device located on the side of the third dielectric thin film 15 away from the first substrate 1; for example, the dielectric thin film 16 can cover the fourth electrode 12-4, the second channel layer 12-2, the third electrode 12-3, the second bonding layer 4-2, the first bonding layer 4-1, and the first electrode 21-1. In embodiments of this disclosure, the dielectric thin film is configured as the first dielectric layer of the first capacitor of the first memory cell layer in a subsequent process.

[0099] (13) A second conductive film 17 is formed on the first carrier plate 1 that forms the aforementioned structure, such as Figure 13 As shown, for example, a deposition process can be used to form the second conductive film. The orthographic projection of the second conductive film 17 onto the plane of the first substrate 1 can cover the orthographic projection of the dielectric film 16 onto the plane of the first substrate 1. The surface of the second conductive film 17 away from the first substrate 1 can be planar. In embodiments of this disclosure, the second conductive film is configured to form the second electrode of a first capacitor of at least one first memory cell layer in a subsequent process.

[0100] In some exemplary embodiments, the material of the second conductive film 17 may include a metallic material or other conductive material. For example, the metallic material may include at least one of tungsten (W), molybdenum (Mo), cobalt (Co), titanium (Ti), copper (Cu), aluminum (Al), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), silver (Ag), or gold (Au), or an alloy of the aforementioned metals. The second conductive film 17 may be a single-layer or multi-layer structure. For example, the second conductive film 17 may be a multi-layer structure formed of titanium nitride (TiN) and tungsten (W). Alternatively, the second conductive film 17 may be a single-layer structure formed of titanium nitride (TiN).

[0101] (14) The first carrier plate 1 forming the aforementioned structure is etched such that at least one first dielectric layer 21-3 is formed in the dielectric film, and at least one second electrode plate 21-2 is formed in the second conductive film, as follows: Figure 14 As shown.

[0102] The surface of the first dielectric layer 21-3 away from the first carrier plate 1 can be flush with the surface of the second electrode 21-2 away from the first carrier plate 1. Moreover, it is closer to the first carrier plate 1 than the surface of the third electrode 12-3 that is closer to the first carrier plate 1. This can reserve space for the bit lines of the subsequently formed isolation layer, the second memory cell layer, and the fourth dielectric film, so as not to affect the performance of the second transistor.

[0103] (15) An isolation layer 18 and a bit line BL of the second memory cell layer are sequentially formed on the first carrier 1 that forms the aforementioned structure, as follows: Figure 15 As shown. Isolation layer 18 can prevent electrical crosstalk between the first memory cell and the second memory cell.

[0104] In some exemplary embodiments, the surface of the isolation layer 18 away from the first memory cell layer is flush with the surface of the bonding layer away from the first memory cell layer, or the surface of the isolation layer 18 away from the first memory cell layer extends beyond the surface of the bonding layer away from the first memory cell layer, covering a portion of the third electrode. The material of the isolation layer 18 may include silicon oxynitride (SiO2). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x ) or aluminum oxide (AlO x ) or hafnium oxide (HfO) x At least one of the following. For example, the material of the isolation layer may include silicon nitride.

[0105] In some exemplary embodiments, the orthographic projection of the third electrode 12-3 onto the plane of the first carrier 1 may be located within the range of the orthographic projection of the bit line BL of the second memory cell layer onto the plane of the first carrier 1, and the third electrode 12-3 is connected to the bit line BL of the second memory cell layer. A plurality of third electrodes 12-3 arranged at intervals along the first direction X may be connected to the same bit line BL of the second memory cell layer.

[0106] In some exemplary embodiments, the bit line BL of the second memory cell layer can be formed using the same or different fabrication methods as the bit line of the first memory cell layer. For example, a conductive material, such as TiN, or a metallic material, such as Ni, Cu, or Co, can be deposited and then annealed. The semiconductor material of the third electrode reacts with the metal to form a metallization, which is then patterned and etched to form at least one bit line BL of the second memory cell layer. Alternatively, a conductive material can be directly deposited to connect multiple third electrodes 12-3 spaced along the first direction X to form at least one bit line BL of the second memory cell layer.

[0107] (16) A fourth dielectric film 19 is formed on the first carrier plate 1 that forms the aforementioned structure, such as Figure 16 As shown. The orthographic projection of the fourth dielectric film 19 onto the plane of the first substrate 1 can cover the orthographic projection of the bit line BL of the second memory cell layer onto the plane of the first substrate 1. In this embodiment of the present disclosure, the fourth dielectric film is used to facilitate the formation of the second gate electrode surrounding the second channel layer in subsequent processes.

[0108] In some exemplary embodiments, the material of the fourth dielectric film 19 may be the same as or different from the material of the first dielectric film 6. For example, the surface of the fourth dielectric film 19 away from the first carrier plate 1 may be flush with the surface of the third electrode 12-3 away from the first carrier plate 1.

[0109] (17) A second gate insulating layer 23, a second gate electrode 12-1, and a fifth dielectric thin film 20 are formed on the first carrier plate 1 on which the aforementioned structure is formed, such as Figure 17 As shown. The surface of the fifth dielectric film 20 away from the first substrate 1 and the surface of the fourth electrode 12-4 away from the first substrate 1 can be flush to facilitate the formation of the second capacitor of the second memory cell layer in subsequent processes. The formation of the second gate insulating layer 23 and the second gate electrode 12-1 can refer to the description of the aforementioned steps (05) to (09). For example, a plurality of second gate electrodes 12-1 arranged along the second direction can be interconnected to form the word lines of the second memory cell layer.

[0110] (18) A plurality of second capacitors 22 are formed on the first carrier plate 1 that forms the aforementioned structure, such as Figure 18As shown. Forming the second capacitor 22 may include sequentially forming a third electrode 22-3, a second dielectric layer 22-2, and a fourth electrode 22-4. For example, the fourth electrode 22-4 of a plurality of second capacitors 22 may be an integral structure interconnected. For example, the orthographic projection of the third electrode 22-3 onto the plane of the first carrier plate 1 may lie within the orthographic projection of the fourth electrode 22-4 onto the plane of the first carrier plate 1.

[0111] In some possible exemplary embodiments, the preparation of the third electrode of the second capacitor can refer to the preparation method of the first electrode of the first capacitor described above. A conductive thin film can be formed first on the second carrier, and then a fourth semiconductor thin film, a fifth semiconductor thin film, a sixth semiconductor thin film and a second bonding film can be formed in sequence. The conductive thin film is used to form the third electrode.

[0112] In some possible exemplary embodiments, the first initial stacking structure and the second initial stacking structure are the same. That is, each set of initial stacking structures includes two first initial stacking structures or two second initial stacking structures.

[0113] In some exemplary embodiments, the semiconductor device includes two sets of memory cell layers. Following the aforementioned fabrication process, after fabricating the first set of memory cell layers, a bonding process is used to stack the first initial stacked structure and the second initial stacked structure of the second set to form a second stacked structure. Subsequently, a bonding film is formed on the first set of memory cell layers, and then a bonding process is used to bond the second stacked structure to the first set of memory cell layers on which the bonding film is formed. Then, the operations described above regarding the first stacked structure (stacked structure) are performed on the second stacked structure to obtain the second set of memory cell layers. In some examples, the fabrication of the first set of memory cell layers and the second stacked structure can be performed simultaneously.

[0114] In some exemplary embodiments, the semiconductor device includes three sets of memory cell layers. Following the aforementioned fabrication process, after fabricating the second set of memory cell layers, a bonding process is used to stack the first initial stacked structure and the second initial stacked structure of the third set to form a third stacked structure. Subsequently, a bonding film is formed on the second set of memory cell layers, and a bonding process is used to bond the third stacked structure to the second set of memory cell layers on which the bonding film is formed. Then, the operations described above regarding the first stacked structure (stacked structure) are performed on the third stacked structure to obtain the third set of memory cell layers. In some examples, the fabrication of the second set of memory cell layers and the third stacked structure can be performed simultaneously.

[0115] In some exemplary embodiments, only the first stack structure retains the first carrier plate, while the first carrier plate is removed in other stack structures.

[0116] Figure 19This is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure, after the first group of memory cell layers is bonded to the first initial stacked structure. Figure 19 As shown, a semiconductor device may include at least one additional memory cell layer beyond the first set of memory cell layers. For example, the semiconductor device may also include one additional memory cell layer, namely the third memory cell layer, or it may include two additional memory cell layers, namely the third memory cell layer and the fourth memory cell layer, etc. Figure 19 In this example, a semiconductor device includes a first set of memory cell layers and a third memory cell layer.

[0117] During the fabrication process, after the first set of memory cell layers is formed, a first initial stacked structure is formed. The formation of the first initial stacked structure may include: sequentially forming a first semiconductor thin film 1-1, a second semiconductor thin film 1-2, a third semiconductor thin film 1-3, a first conductive thin film 1-4, and a first bonding thin film 1-5 on the first carrier plate 1, as described above in the description of forming the first memory cell layer.

[0118] Subsequently, a bonding film is formed on the first set of memory cell layers, and then a bonding process is used to bond the first initial stacked structure to the first set of memory cell layers on which the bonding film is formed.

[0119] Subsequently, the operations described above regarding the first stack structure (stack structure) are performed on the first initial stack structure to obtain the third memory cell layer. In some examples, the first initial stack structure (for forming the third memory cell layer) may be formed simultaneously with the first initial stack structure for forming the first set of memory cell layers.

[0120] In some exemplary embodiments, after the first initial stacked structure is bonded to the first set of memory cell layers forming the bonding film using a bonding process, the first carrier plate 1 of the first initial stacked structure can be removed.

[0121] In some exemplary embodiments, the first conductive thin film 1-4 in the first initial stacked structure is used to form the bit lines of the third memory cell layer.

[0122] Figure 20 This is a cross-sectional schematic diagram showing the bonding of the first group of memory cell layers and the second initial stacked structure of a semiconductor device according to another embodiment of this disclosure. Figure 20 As shown, a semiconductor device may include at least one additional memory cell layer beyond the first set of memory cell layers. For example, the semiconductor device may also include one additional memory cell layer, namely the third memory cell layer, or it may include two additional memory cell layers, namely the third memory cell layer and the fourth memory cell layer, etc. Figure 20In this example, a semiconductor device includes a first set of memory cell layers and a third memory cell layer.

[0123] During the fabrication process, after the first set of memory cell layers is formed, a second initial stacked structure is formed. The formation of the second initial stacked structure may include: sequentially forming a fourth semiconductor thin film 2-9, a fifth semiconductor thin film 2-8, a sixth semiconductor thin film 2-7, and a second bonding film 2-6 on the second carrier plate 2, as described above in the description of forming the second memory cell layer.

[0124] Subsequently, a bonding film is formed on the first set of memory cell layers, and then a bonding process is used to bond the second initial stacked structure to the first set of memory cell layers on which the bonding film is formed.

[0125] Subsequently, the operations described above regarding the first stack structure (stack structure) are performed on the second initial stack structure to obtain the third memory cell layer. In some examples, the second initial stack structure (for forming the third memory cell layer) can be formed simultaneously with the second initial stack structure that forms the first set of memory cell layers.

[0126] In some exemplary embodiments, after the second initial stacked structure is bonded to the first set of memory cell layers forming the bonding film using a bonding process, the second carrier 2 of the second initial stacked structure can be removed.

[0127] This disclosure provides a method for fabricating a semiconductor device, comprising: A first initial stacked structure and a second initial stacked structure are formed, wherein both the first initial stacked structure and the second initial stacked structure include stacked semiconductor thin films and bonding thin films; A first initial stacked structure and a second initial stacked structure are bonded together to form a first stacked structure; The first set of storage cell layers is prepared based on the first stacked structure; The first group of memory cell layers includes two memory cell layers, each of which includes multiple memory cells arranged in an array. The semiconductor thin film of the first group of memory cell layers is used to form the active layer of the first group of memory cell layers.

[0128] In some exemplary embodiments, the semiconductor device includes N groups of memory cell layers, where N is an integer greater than or equal to 2, and each group of memory cell layers includes two memory cell layers; the fabrication method includes: The first initial stacking structure and the second initial stacking structure are bonded together to form the nth stacking structure; where n is an integer greater than or equal to 2 and less than or equal to N; The nth stack structure is bonded to the (n-1)th group of memory cell layers; The nth group of memory cell layers is prepared based on the nth stacked structure; Repeat the above operations until the Nth set of memory cell layers is prepared.

[0129] In some exemplary embodiments, the semiconductor device further includes N memory cell layers, where N is an integer greater than or equal to 1; the fabrication method includes: The nth first initial stack structure is bonded to the (n+1)th memory cell layer; where n is an integer greater than or equal to 1 and less than or equal to N; The (n+2)th memory cell layer is prepared based on the nth first initial stacking structure; Repeat the above operations until the Nth memory cell layer is prepared.

[0130] In some exemplary embodiments, the semiconductor device further includes N memory cell layers, where N is an integer greater than or equal to 1; the fabrication method includes: The nth second initial stack structure is bonded to the (n+1)th memory cell layer; where n is an integer greater than or equal to 1 and less than or equal to N; The (n+2)th memory cell layer is prepared based on the nth second initial stacking structure; Repeat the above operations until the Nth memory cell layer is prepared.

[0131] In some exemplary embodiments, the first initial stacked structure includes: a first semiconductor thin film, a second semiconductor thin film, a third semiconductor thin film, a first conductive thin film, and a first bonding thin film sequentially stacked on a first carrier plate; The second initial stacked structure includes: a fourth semiconductor film, a fifth semiconductor film, a sixth semiconductor film, and a second bonding film sequentially stacked on a second carrier plate; The step of bonding a first initial stacked structure and a second initial stacked structure to form a first stacked structure includes: bonding a first bonding film of the first initial stacked structure to a second bonding film of the second initial stacked structure to form a bonding layer, and removing the second carrier plate to form the first stacked structure.

[0132] In some exemplary embodiments, the two memory cell layers are a first memory cell layer and a second memory cell layer; the fabrication of the first set of memory cell layers based on the first stacking structure includes: The first stacked structure is etched along a third direction to form a plurality of spaced columnar structures, the columnar structures including the active layer of the first group of memory cell layers; Multiple bit lines are formed to form the first memory cell layer, and the bit lines extend along a first direction and are spaced apart in a second direction; Multiple first gate electrodes are formed to form the first memory cell layer. Multiple first gate electrodes arranged along the second direction are interconnected to form multiple word lines. The first direction and the second direction intersect. The third direction is perpendicular to the plane formed by the first direction and the second direction. The multiple word lines extend along the second direction and are distributed at intervals in the first direction. The second storage cell layer is formed along a third direction on the side of the first storage cell layer away from the first carrier.

[0133] In some exemplary embodiments, the plurality of bit lines forming the first memory cell layer include: Based on the columnar structure, metallic materials are deposited; An annealing process is performed to react the first semiconductor thin film with the metal material to form a metallization, and the metallization is etched to form multiple bit lines.

[0134] In some exemplary embodiments, the formation of a plurality of spaced columnar structures includes: The first semiconductor thin film forms a plurality of first electrodes, the second semiconductor thin film forms a plurality of first channel layers, and the third semiconductor thin film forms a plurality of second electrodes; the first conductive thin film forms a plurality of conductive structures, the conductive structures being used to form the first electrode plates of the first capacitor of the first memory cell layer. The sixth semiconductor thin film forms a plurality of third electrodes, the fifth semiconductor thin film forms a plurality of second channel layers, and the fourth semiconductor thin film forms a plurality of fourth electrodes; The active layer of the first memory cell layer includes the first electrode, the first channel layer, and the second electrode stacked sequentially along a third direction; The active layer of the second memory cell layer includes the third electrode, the second channel layer, and the fourth electrode, which are stacked sequentially along the third direction.

[0135] In some exemplary embodiments, the plurality of first gate electrodes forming the first memory cell layer include: A first dielectric film and a second dielectric film are formed sequentially, and the surface of the first dielectric film away from the first substrate is closer to the first substrate than the surface of the first trench layer away from the first substrate. The second dielectric film includes a first portion and a second portion connected to each other, and the first portion is closer to the first carrier plate than the second portion; the first portion and the second portion together form a plurality of first accommodating spaces, and the surface of the first portion away from the first carrier plate is closer to the first carrier plate than the surface of the first channel layer away from the first carrier plate.

[0136] In some exemplary embodiments, the plurality of first gate electrodes forming the first memory cell layer further include: A gate metal film is formed, and the gate metal film is located within the first accommodating space; wherein, the gate metal film includes a third part and a fourth part connected to each other, and the third part is closer to the first carrier plate than the fourth part, and the third part and the fourth part together form a plurality of second accommodating spaces; A sacrificial layer is formed, and the sacrificial layer is located within the second accommodating space. The second dielectric film and the gate metal film that are not covered by the sacrificial layer are removed. The sacrificial layer is removed to form a plurality of trenches spaced apart along a first direction. The second dielectric film and the gate metal film located in the trenches are removed to expose a portion of the first dielectric film. The second dielectric film forms a plurality of first gate insulating layers, and the gate metal film forms a plurality of first gate electrodes. The first gate insulating layers surround the sidewalls of the first channel layer, and the first gate electrodes surround the sidewalls of the first gate insulating layers.

[0137] In some exemplary embodiments, after forming the first gate electrode, the process includes: A third dielectric film is formed, and at least a portion of the third dielectric film fills the trench; A dielectric thin film and a second conductive thin film are sequentially formed to cover the conductive structure; The dielectric film and the second conductive film are etched to form the first dielectric layer of a first capacitor with multiple first memory cell layers, and the second conductive film forms the second electrode plate of the first capacitor with multiple first memory cell layers.

[0138] In some exemplary embodiments, prior to sequentially forming the dielectric thin film and the second conductive thin film, the process includes: The conductive structure is etched to form the first plate of the first capacitor of the first memory cell layer.

[0139] In some exemplary embodiments, forming the second storage cell layer along a third direction on the side of the first storage cell layer away from the first carrier includes: An isolation layer is formed on the side of the first storage cell layer away from the first carrier board; Multiple bit lines of the second memory cell layer are formed on the side of the isolation layer away from the first carrier plate, extending along the first direction and spaced apart in the second direction; A plurality of second gate insulating layers and a plurality of second gate electrodes are formed on the side of the bit line away from the first carrier plate; A third electrode plate, a second dielectric layer, and a fourth electrode plate are sequentially formed on the side of the columnar structure away from the first carrier plate. The third electrode plate, the second dielectric layer, and the fourth electrode plate form the second capacitor of the second memory cell layer.

[0140] This disclosure also provides a semiconductor device, which includes: a substrate; A plurality of stacked memory cell layers are located on the substrate, and each memory cell layer includes a plurality of memory cells arranged in an array; and Multiple bonding layers are provided, and the bonding layers are provided between the storage cells of two adjacent storage cell layers.

[0141] This disclosure also provides an electronic device, which includes the semiconductor device provided in any of the foregoing embodiments, or includes a semiconductor device fabricated using the fabrication method of the semiconductor device provided in any of the foregoing embodiments. This electronic device can be any electronic product with storage function, such as a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0142] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A first initial stacked structure and a second initial stacked structure are formed, wherein both the first initial stacked structure and the second initial stacked structure include stacked semiconductor thin films and bonding thin films; A first initial stacked structure and a second initial stacked structure are bonded together to form a first stacked structure; The first set of storage cell layers is prepared based on the first stacked structure; The first group of memory cell layers includes two memory cell layers, each of which includes multiple memory cells arranged in an array. The semiconductor thin film of the first group of memory cell layers is used to form the active layer of the first group of memory cell layers.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The semiconductor device includes N groups of memory cell layers, where N is an integer greater than or equal to 2, and each group of memory cell layers includes two memory cell layers; the fabrication method includes: The first initial stacking structure and the second initial stacking structure are bonded together to form the nth stacking structure; where n is an integer greater than or equal to 2 and less than or equal to N; The nth stack structure is bonded to the (n-1)th group of memory cell layers; The nth group of memory cell layers is prepared based on the nth stacked structure; Repeat the above operations until the Nth set of memory cell layers is prepared.

3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The semiconductor device further includes N memory cell layers, where N is an integer greater than or equal to 1; the fabrication method includes: The nth first initial stack structure is bonded to the (n+1)th memory cell layer; where n is an integer greater than or equal to 1 and less than or equal to N; The (n+2)th memory cell layer is prepared based on the nth first initial stacking structure; Repeat the above operations until the Nth memory cell layer is prepared.

4. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The semiconductor device further includes N memory cell layers, where N is an integer greater than or equal to 1; the fabrication method includes: The nth second initial stack structure is bonded to the (n+1)th memory cell layer; where n is an integer greater than or equal to 1 and less than or equal to N; The (n+2)th memory cell layer is prepared based on the nth second initial stacking structure; Repeat the above operations until the Nth memory cell layer is prepared.

5. The method for fabricating a semiconductor device according to any one of claims 1 to 4, characterized in that, The first initial stacked structure includes: a first semiconductor thin film, a second semiconductor thin film, a third semiconductor thin film, a first conductive thin film, and a first bonding thin film sequentially stacked on a first carrier plate; The second initial stacked structure includes: a fourth semiconductor film, a fifth semiconductor film, a sixth semiconductor film, and a second bonding film sequentially stacked on a second carrier plate; The step of bonding a first initial stacked structure and a second initial stacked structure to form a first stacked structure includes: bonding a first bonding film of the first initial stacked structure to a second bonding film of the second initial stacked structure to form a bonding layer, and removing the second carrier plate to form the first stacked structure.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The two storage cell layers are a first storage cell layer and a second storage cell layer; the fabrication of the first set of storage cell layers based on the first stacking structure includes: The first stacked structure is etched along a third direction to form a plurality of spaced columnar structures, the columnar structures including the active layer of the first group of memory cell layers; Multiple bit lines are formed to form the first memory cell layer, and the bit lines extend along a first direction and are spaced apart in a second direction; Multiple first gate electrodes are formed to form the first memory cell layer. Multiple first gate electrodes arranged along the second direction are interconnected to form multiple word lines. The first direction and the second direction intersect. The third direction is perpendicular to the plane formed by the first direction and the second direction. The multiple word lines extend along the second direction and are distributed at intervals in the first direction. The second storage cell layer is formed along a third direction on the side of the first storage cell layer away from the first carrier.

7. The method for fabricating a semiconductor device as described in claim 6, characterized in that, The multiple bit lines forming the first memory cell layer include: Based on the columnar structure, metallic materials are deposited; An annealing process is performed to react the first semiconductor thin film with the metal material to form a metallization, and the metallization is etched to form multiple bit lines.

8. The method for fabricating a semiconductor device as described in claim 6, characterized in that, The formation of multiple spaced columnar structures includes: The first semiconductor thin film forms a plurality of first electrodes, the second semiconductor thin film forms a plurality of first channel layers, and the third semiconductor thin film forms a plurality of second electrodes; the first conductive thin film forms a plurality of conductive structures, the conductive structures being used to form the first electrode plates of the first capacitor of the first memory cell layer. The sixth semiconductor thin film forms a plurality of third electrodes, the fifth semiconductor thin film forms a plurality of second channel layers, and the fourth semiconductor thin film forms a plurality of fourth electrodes; The active layer of the first memory cell layer includes the first electrode, the first channel layer, and the second electrode stacked sequentially along a third direction; The active layer of the second memory cell layer includes the third electrode, the second channel layer, and the fourth electrode, which are stacked sequentially along the third direction.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, The plurality of first gate electrodes forming the first memory cell layer include: A first dielectric film and a second dielectric film are formed sequentially, and the surface of the first dielectric film away from the first substrate is closer to the first substrate than the surface of the first trench layer away from the first substrate. The second dielectric film includes a first portion and a second portion connected to each other, and the first portion is closer to the first carrier plate than the second portion; the first portion and the second portion together form a plurality of first accommodating spaces, and the surface of the first portion away from the first carrier plate is closer to the first carrier plate than the surface of the first channel layer away from the first carrier plate.

10. The method for fabricating a semiconductor device as described in claim 9, characterized in that, The plurality of first gate electrodes forming the first memory cell layer further include: A gate metal film is formed, and the gate metal film is located within the first accommodating space; wherein, the gate metal film includes a third part and a fourth part connected to each other, and the third part is closer to the first carrier plate than the fourth part, and the third part and the fourth part together form a plurality of second accommodating spaces; A sacrificial layer is formed, and the sacrificial layer is located within the second accommodating space. The second dielectric film and the gate metal film that are not covered by the sacrificial layer are removed. The sacrificial layer is removed to form a plurality of trenches spaced apart along a first direction. The second dielectric film and the gate metal film located in the trenches are removed to expose a portion of the first dielectric film. The second dielectric film forms a plurality of first gate insulating layers, and the gate metal film forms a plurality of first gate electrodes. The first gate insulating layers surround the sidewalls of the first channel layer, and the first gate electrodes surround the sidewalls of the first gate insulating layers.

11. The method for fabricating a semiconductor device as described in claim 10, characterized in that, After forming the first gate electrode, the process includes: A third dielectric film is formed, and at least a portion of the third dielectric film fills the trench; A dielectric thin film and a second conductive thin film are sequentially formed to cover the conductive structure; The dielectric film and the second conductive film are etched to form the first dielectric layer of a first capacitor with multiple first memory cell layers, and the second conductive film forms the second electrode plate of the first capacitor with multiple first memory cell layers.

12. The method for fabricating a semiconductor device as described in claim 11, characterized in that, Before sequentially forming the dielectric thin film and the second conductive thin film, the process includes: The conductive structure is etched to form the first plate of the first capacitor of the first memory cell layer.

13. The method for fabricating a semiconductor device as described in claim 6, characterized in that, Forming a second storage cell layer along a third direction on the side of the first storage cell layer away from the first carrier board includes: An isolation layer is formed on the side of the first storage cell layer away from the first carrier board; Multiple bit lines of the second memory cell layer are formed on the side of the isolation layer away from the first carrier plate, extending along the first direction and spaced apart in the second direction; A plurality of second gate insulating layers and a plurality of second gate electrodes are formed on the side of the bit line away from the first carrier plate; A third electrode plate, a second dielectric layer, and a fourth electrode plate are sequentially formed on the side of the columnar structure away from the first carrier plate. The third electrode plate, the second dielectric layer, and the fourth electrode plate form the second capacitor of the second memory cell layer.

14. A semiconductor device, characterized in that, include: Substrate; The substrate has multiple stacked memory cell layers, and each memory cell layer includes multiple memory cells arranged in an array. as well as Multiple bonding layers are provided, and the bonding layers are provided between the storage cells of two adjacent storage cell layers.

15. The semiconductor device as claimed in claim 14, characterized in that, Each of the memory cells includes an active layer and a gate electrode, wherein the active layer extends in a direction perpendicular to the plane of the substrate, and the gate electrode surrounds the sidewall of the active layer and is insulated from the active layer.

16. The semiconductor device as claimed in claim 14, characterized in that, The multiple memory cell layers include a first memory cell layer and a second memory cell layer; the first memory cell layer includes a first capacitor, the first capacitor includes a first electrode, a first dielectric layer and a second electrode, the first electrode extends along a direction perpendicular to the plane of the substrate, the first dielectric layer surrounds the outer wall of the first electrode, and the second electrode surrounds the outer wall of the first dielectric layer. The bonding layer located between the first memory cell layer and the second memory cell layer is located on the side of the first electrode away from the substrate, and the bonding layer extends in a direction perpendicular to the plane of the substrate, with the first dielectric layer surrounding the outer wall of the bonding layer.

17. The semiconductor device as claimed in claim 16, characterized in that, The bonding layer includes a first bonding sublayer and a second bonding sublayer stacked together. The first bonding sublayer is closer to the substrate than the second bonding sublayer. The first dielectric layer surrounds the outer wall of the first bonding sublayer and the outer wall of the second bonding sublayer. The surface of the second bonding sublayer away from the substrate is farther from the substrate than the surface of the first dielectric layer away from the substrate.

18. An electronic device, characterized in that, This includes semiconductor devices manufactured by the method of manufacturing a semiconductor device as described in any one of claims 1 to 13, or semiconductor devices as described in any one of claims 14 to 17.

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