Preparation method of diode chip based on high-precision doping control technology

Abstract

The invention discloses a preparation method of a diode chip based on a high-precision doping control technology. The preparation process comprises the following steps of S1, substrate preparation, S2, thermal oxidation process, S3, ion implantation doping, S4, electrode formation and S5, doping verification. According to the method, a monocrystalline silicon wafer with high purity and low defect density is used, the crystal orientation and resistivity are selected according to the requirements of a target device, a strict RCA cleaning process is adopted, surface organic matters, metal ions and particulate pollutants are removed, the cleanliness of a subsequent process is ensured, which is the basis of a high-precision process, a single crystal layer is grown on a substrate, and the high-precision process is realized. The doping type, concentration and thickness can be accurately controlled, and the doping type, concentration and thickness are different from those of a substrate, which is crucial for manufacturing a drift region with accurate doping distribution and preventing substrate impurities from diffusing upwards, so that the production quality of a diode chip is improved, an ion beam of required doping elements is generated through an ion source, other impurity ions are removed, and the yield of the diode chip is improved. And the doping purity is ensured.

Description

Technical Field

[0001] This invention relates to the field of diode chip fabrication technology, specifically to a method for fabricating a diode chip based on high-precision doping control technology. Background Technology

[0002] A diode chip refers to a miniaturized semiconductor structure with diode function fabricated on a semiconductor wafer, usually silicon, but also germanium, gallium arsenide, silicon carbide, or gallium nitride. It is the basic core unit that constitutes various diode devices. The basic diode chip is a PN junction. Through semiconductor doping processes, a P-type semiconductor is formed in a certain area of ​​the chip, and an N-type semiconductor is formed in an adjacent area. A special region called the depletion layer or space charge region is formed at the boundary of the PN junction. It has unidirectional conductivity—allowing current to flow only from the P-region to the N-region. High-precision doping control technology is crucial in diode chip fabrication, as it directly determines the key performance parameters of the PN junction or Schottky junction. Therefore, "the original low-precision operation and poor doping effect are no longer sufficient to complete the current massive workload. The complexity and weight of the content will inevitably affect the fabrication of diode chips," specifically in the following aspects: (1) If the substrate is not thoroughly cleaned after the raw materials are selected, the quality of the subsequent diode manufacturing will be reduced. (2) When manufacturing diode chips normally, it is not possible to ensure that the impurity atoms are ionized and injected evenly, thereby reducing the purity and uniformity of the doping. (3) After the diode chip is produced, only simple verification of the product can be performed. Online and offline monitoring of the production process cannot be carried out, thereby reducing the accuracy of the dosage and activation effect in the production process. Summary of the Invention

[0003] The purpose of this invention is to provide a method for preparing a diode chip based on high-precision doping control technology, in order to solve the problems of the current diode chip preparation methods mentioned in the background art: (1) after selecting raw materials, the substrate is not thoroughly cleaned, which easily leads to a reduction in the quality of subsequent diode manufacturing; (2) during normal diode chip manufacturing, it is not possible to guarantee the uniform injection of impurity atoms, thereby reducing the purity and uniformity of doping; (3) after the diode chip is produced, only simple verification of the product can be performed, and online or offline monitoring of the production process cannot be performed, thereby reducing the accuracy of the determination of dosage and activation effect during the production process.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a method for fabricating a diode chip based on high-precision doping control technology, the fabrication process comprising the following steps: S1, Substrate Preparation S1.1 Wafer selection: Use a single-crystal silicon wafer. S1.2 Cleaning: Remove organic matter, metal ions, and particulate contaminants from the surface of the single-crystal ghost wafer. Then dry the cleaned single-crystal silicon. S1.3 Epitaxial growth: Extend the single-crystal layer on the substrate through chemical vapor deposition to prepare the diode substrate. S2, thermal oxidation process S2.1 Thermal oxidation: The substrate is coated with photoresist, then heated with solvent, then exposed, then dissolved and exposed, and finally cured with photoresist pattern. S2.2 Etching: The pattern on the photoresist is transferred to the oxide layer below by dry etching to form doped windows. S2.3 Photoresist removal and cleaning: The photoresist residue from the etching is removed and then the substrate is cleaned. S3, ion implantation doping S3.1 Ion implantation: The ion source generates an ion beam of the desired doping element. Then, the characteristic ions are screened by a quality analyzer, and the ion beam is uniformly scanned onto the entire wafer surface by magnetic scanning. S3.2 Rapid thermal annealing: Peak annealing: The wafer is heated to a high temperature of 800-1100°C within a few seconds to tens of seconds, and then rapidly cooled to obtain a semi-finished diode. S4, Electrode Formation S4.1 Electrode formation: First, metal deposition is performed on the semi-finished product, then photolithography and etching are performed to define the electrode pattern. Next, low-temperature heat treatment is performed to deposit a passivation layer on the surface. Then, electrode contact windows are opened in the passivation layer. Then, the die is diced and finally the die is packaged into the housing and the electrodes are led out. S5, Doping Verification S5.1 Online monitoring using a four-probe tester; S5.2 Offline analysis using secondary ion mass spectrometry (SIMS) to measure junction depth, peak concentration, and distribution shape during fabrication, followed by measurement of carrier concentration distribution with depth and Hall effect measurement of carrier concentration; S5.3 Electrical testing using IV / CV to test the final device's electrical parameters, followed by verification.

[0005] Preferably, in the doping control point, energy control is used, and the energy of the implanted ions precisely determines the projected range of the impurities in silicon, which is the main determinant of the junction depth.

[0006] Preferably, the dose control at the doping control point, the total number of impurity atoms implanted into a unit area of ​​silicon, in units of atoms / cm², determines the peak concentration near the junction depth, which is 1e11 to 1e16 atoms / cm², and the dose control needs to be better than ±1%, using a Faraday cup to measure the charge.

[0007] Preferably, in the doping control point, the injection angle needs to be controlled to <0.1°, and tilted rotation injection is used to suppress the channel effect.

[0008] Preferably, the uniformity control, scanning system and beam control accuracy in the doping control point ensure the uniformity of dose and energy across the entire wafer by ±1%.

[0009] Preferably, the doping control point includes beam purity / contamination control.

[0010] Preferably, the doping control point is cleaned after injection to remove surface contaminants.

[0011] Preferably, the purpose of the epitaxial growth is to grow a single crystal layer on the substrate.

[0012] Preferably, the doping control point for the epitaxial growth first controls the flow rate, partial pressure, and ratio of the gas source, including SiH4, SiH2Cl, and the doping source gas, including PH3, B2H6, and AsH3. Then, the reaction chamber temperature is typically controlled at 1000-1200℃ and the LPCVD pressure is low. Next, in-situ doping is used. Finally, after growth, the thickness and doping distribution can be analyzed by secondary ion mass spectrometry (SIMS).

[0013] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention uses high-purity, low-defect-density monocrystalline silicon wafers, with crystal orientation and resistivity selected according to the requirements of the target device. A strict RCA cleaning process removes surface organic matter, metal ions, and particulate contaminants, ensuring the cleanliness of subsequent processes. This is the foundation of high-precision processes. A monocrystalline layer is grown on the substrate, and its doping type, concentration, and thickness can be precisely controlled. Unlike the substrate, this is crucial for manufacturing drift regions with precise doping distribution and preventing substrate impurities from diffusing upwards, thereby improving the production quality of diode chips.

[0014] 2. This invention generates an ion beam of the desired doping element using an ion source. The ion beam is accelerated by a high voltage of tens of thousands to hundreds of thousands of volts. Then, ions with a specific charge-to-mass ratio (m / q) are selected to remove other impurity ions, ensuring doping purity. Next, the ion beam is uniformly scanned onto the entire wafer surface using magnetic scanning. Then, the ion implantation is blocked by the area on the wafer surface with an oxide layer mask. Finally, the wafer is heated to a high temperature of 800-1100°C in a few seconds to tens of seconds by peak annealing, followed by rapid cooling. This is the core step for achieving high-precision doping control, ionizing and accelerating the desired impurity atoms, and implanting them into a predetermined depth in a specific area of ​​the silicon wafer, thereby improving the purity and uniformity of the doped atoms.

[0015] 3. This invention utilizes a four-probe tester, Rs (sheet resistance), to monitor the sheet resistance of the doped region, rapidly assessing the dose and activation effect. Then, secondary ion mass spectrometry (SIMS) is used for the most accurate depth distribution analysis, directly measuring the change in doping concentration with depth, including junction depth, peak concentration, and distribution shape. Extended resistance probes are then used to measure the carrier concentration distribution with depth, and Hall effect testing is employed to measure carrier concentration and mobility. Finally, electrical tests, specifically IV / CV testing, are used to measure the electrical parameters of the final device, including breakdown voltage, on-state voltage drop, leakage current, and capacitance, verifying whether the doping control has achieved the design goals. This improves the accuracy of dose and activation effect assessment during the production process. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the preparation process of the present invention; Figure 2 This is a partial operational logic code diagram of the magnetic analyzer of the present invention; Figure 3 This is a partial operational logic code diagram of the four-probe tester of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1: Please see Figures 1-3 A method for fabricating a diode chip based on high-precision doping control technology, the fabrication process includes the following steps: S1, Substrate Preparation S1.1 Wafer Selection: High-purity, low-defect-density monocrystalline silicon wafers are used. S1.2 Cleaning: ① Removal of surface organic matter, metal ions, and particulate contaminants; ② Drying of the substrate. S1.3 Epitaxial Growth: ① Purpose; ② Process: Chemical vapor deposition; ③ Doping control points. High-purity, low-defect-density monocrystalline silicon wafers are used. Crystal orientation and resistivity are selected according to the requirements of the target device. A rigorous RCA cleaning process removes surface organic matter, metal ions, and particulate contaminants, ensuring the cleanliness of subsequent processes. This is the foundation of high-precision processes. A monocrystalline layer is grown on the substrate, and its doping type, concentration, and thickness can be precisely controlled. Unlike the substrate, this is crucial for manufacturing drift regions with precise doping distribution and preventing substrate impurities from diffusing upwards, thereby improving the production quality of diode chips. S2, Processing Technology S2.1 Thermal oxidation: ① Photoresist coating, ② Pre-baking, ③ Exposure, ④ Development, ⑤ Post-baking; S2.2 Etching: Dry etching; S2.3 Photoresist removal and cleaning: Photoresist is uniformly spin-coated onto the oxide layer, heated to evaporate the photoresist solvent, and then exposed under a deep ultraviolet (DUV) lithography machine using a mask to transfer the pattern onto the photoresist. High-precision photolithography is key to achieving precise positioning of doped regions. Next, the pattern is formed by dissolving the photoresist in the exposed positive resist and unexposed negative resist areas. Then, the photoresist pattern is cured to enhance its etching resistance. The pattern on the photoresist is transferred to the underlying oxide layer to form doped windows. Dry etching is the main method because its good anisotropy enables high-precision pattern transfer. S3, Further Processing S3.1 Ion implantation: Ionizing and accelerating the desired impurity atoms, and implanting them into a predetermined depth in a specific region of the silicon wafer, including B, P, As, and Sb. 3.2 Implantation process: ① An ion source generates an ion beam of the desired dopant element. ② The ion beam is accelerated by a high voltage of tens to hundreds of thousands of volts. ③ A mass analyzer, magnetic analyzer, or electromagnetic analyzer filters out ions with a specific charge-to-mass ratio (m / q) and removes other impurity ions to ensure doping purity. ④ A scanning system uses magnetic scanning to uniformly scan the ion beam across the entire wafer surface. ⑤ Areas on the wafer surface with an oxide mask block ion implantation. S3.2 Rapid thermal annealing: Peak annealing, heating the wafer to a high temperature of 800-1100°C within seconds to tens of seconds, followed by rapid cooling. However, an ion beam containing the desired doping element is generated by an ion source. The ion beam is accelerated by a high voltage of tens of thousands to hundreds of thousands of volts. Then, ions with a specific charge-to-mass ratio (m / q) are selected to remove other impurity ions and ensure doping purity. Next, the ion beam is uniformly scanned onto the entire wafer surface by magnetic scanning. Then, the ion implantation is blocked by the area on the wafer surface with an oxide layer mask. Finally, the wafer is heated to a high temperature of 800-1100°C in a few seconds to tens of seconds by peak annealing and then rapidly cooled. This is the core step to achieve high-precision doping control, which ionizes, accelerates, and implants the desired impurity atoms into a predetermined depth in a specific area of ​​the silicon wafer, thereby improving the purity and uniformity of the doped atoms. S4, Subsequent Processes S4.1 Electrode Formation: ① Metal Deposition: Physical vapor deposition (PVD) is used to form ohmic contacts in the doped region. ② Photolithography and Etching: Electrode patterns are defined. ③ Alloying: Low-temperature heat treatment at 400-450℃ improves metal-semiconductor contact resistance. ④ Passivation Layer Deposition: An insulating layer is deposited on the chip surface to protect the device from environmental contamination and mechanical damage, such as SiO2, Si3N4, and polyimide. ⑤ Photolithography and Etching: Electrode contact windows are created on the passivation layer. ⑥ Backside Metallization: If the substrate is to be used as an electrode, it is usually thinned, cleaned, and a backside metal is deposited, such as Ti / Ni / Ag or Al. ⑦ Dicing: The wafer is cut into individual chip dies. ⑧ Testing and Packaging: Electrical performance testing is performed, and the dies are packaged into a housing and the electrodes are brought out. S5, Doping and Verification S5.1 Online monitoring: Four-probe tester, Rs - sheet resistance, used to monitor the sheet resistance of the doped region for rapid evaluation of dose and activation effect. S5.2 Offline analysis: ① Secondary ion mass spectrometry (SIMS): The most accurate depth distribution analysis, directly measuring the change in doping concentration with depth, junction depth, peak concentration, and distribution shape; ② Extended resistance probe: Measuring the distribution of carrier concentration with depth; ③ Hall effect testing: Measuring carrier concentration and mobility. S5.3 Electrical testing: IV / CV. The electrical parameters of the final device, including breakdown voltage, on-state voltage drop, leakage current, and capacitance, are tested to verify whether the doping control has achieved the design goals. A four-probe tester with Rs (sheet resistance) is used to monitor the sheet resistance of the doped region and quickly assess the dose and activation effect. Then, secondary ion mass spectrometry (SIMS) is used for the most accurate depth distribution analysis, directly measuring the change of doping concentration with depth, including junction depth, peak concentration, and distribution shape. Next, an extended resistance probe is used to measure the distribution of carrier concentration with depth, and the Hall effect is used to measure carrier concentration and mobility. Finally, the electrical parameters of the final device, including breakdown voltage, on-state voltage drop, leakage current, and capacitance, are tested by IV / CV to verify whether the doping control has achieved the design goals, thereby improving the accuracy of dose and activation effect judgment during the production process.

[0019] In this embodiment: energy control in the doping control point, the energy of the implanted ions precisely determines the projected range of the impurities in silicon, that is, the main determinant of the junction depth, usually a few nanometers to a few micrometers, and the energy stability requirement is extremely high <±0.1%.

[0020] In this embodiment: Dosage control at the doping control point is the total number of impurity atoms implanted into a unit area of ​​silicon, in units of atoms / cm², to precisely determine the peak concentration near the junction depth, typically 1e11 to 1e16 atoms / cm². The dosage control accuracy needs to be better than ±1% or even higher, and the charge is precisely measured using a Faraday cup.

[0021] In this embodiment: the doping control point is angle control, and the injection angle needs to be precisely controlled to <0.1° in order to avoid the channel effect and ensure that the impurity distribution conforms to the theoretical simulated Gaussian distribution. Usually, tilted rotation injection is used to suppress the channel effect.

[0022] In this embodiment: uniformity control in the doping control point, the accuracy of the scanning system and beam current control ensure that the uniformity of dose and energy on the entire wafer is <±1%, and wafer cooling prevents temperature rise from affecting the implantation distribution.

[0023] In this embodiment: beam purity / contamination control is performed at the doping control point, a high-quality analyzer ensures that only target ions are implanted to avoid cross-contamination, and a high vacuum level is required.

[0024] In this embodiment: after implantation at the doping control point, the surface is cleaned to remove contaminants.

[0025] In this embodiment: the purpose of epitaxial growth in step S1.3 is to grow a single crystal layer on the substrate, whose doping type, concentration and thickness can be precisely controlled. Unlike the substrate, this is crucial for manufacturing drift regions with precise doping distribution and preventing substrate impurities from diffusing upward.

[0026] In this embodiment: the doping control points in step S1.3 for epitaxial growth are: ① precisely controlling the flow rate, partial pressure, and ratio of the gas source including SiH4, SiH2Cl and the doping source gas including PH3, B2H6, and AsH3; ② precisely controlling the reaction chamber temperature, which is usually between 1000-1200℃ and the pressure of LPCVD, which is low; ③ using in-situ doping can achieve high uniformity; ④ after growth, the thickness and doping distribution can be analyzed by secondary ion mass spectrometry (SIMS).

[0027] Example 2: As shown in the figure, unlike Example 1, the fabrication method of a diode chip based on high-precision doping control technology in this example includes the following steps: The first step involves baking the substrate at 1200°C in an MOCVD (Metal-Organic Chemical Vapor Deposition) reactor to remove surface contaminants. The second step involves epitaxially growing a buffer layer with a thickness of 10–50 nm on the substrate surface after the first step in the MOCVD reactor. The third step involves epitaxially growing an N-type semiconductor material with a thickness of 2–8 μm, a multiple quantum well layer, and a P-type semiconductor material with a thickness of 100–500 nm on the buffer layer obtained in the second step in the MOCVD reactor. The fourth step involves depositing a current spreading layer with a thickness of 10–500 nm on the P-type semiconductor material obtained in the third step, and fabricating the current spreading pattern using photolithography and wet etching processes, where the length of the current spreading layer is shorter than that of the P-type semiconductor material. Step 1: Using P-type semiconductor material, a step pattern I is formed. Step 2: On the product obtained in Step 4, photolithography and dry etching processes are used to make the lengths of the P-type semiconductor material, the multiple quantum well layer, and a portion of the N-type semiconductor material shorter than the lengths of the substrate and the buffer layer, and to expose a portion of the N-type semiconductor material. The exposed portion of the N-type semiconductor material is the same length as the substrate and the buffer layer, thus forming a step pattern II. Step 3: On the product obtained in Step 5, an insulating layer is deposited. The material used is SiO2, Si3N4, diamond, LiF, or PMMA, with a thickness of 5–300 nm. It is a continuous film structure or a discontinuous film structure. Then, photolithography and etching techniques are used to retain a portion of the insulating layer. The retention of a portion of the insulating layer can be any one of the following three conditions.

[0028] In summary, compared to Example 2, Example 1 uses a high-purity, low-defect-density monocrystalline silicon wafer. The crystal orientation and resistivity are selected according to the requirements of the target device. A strict RCA cleaning process removes surface organic matter, metal ions, and particulate contaminants, ensuring the cleanliness of subsequent processes. This is the foundation of high-precision processes. A monocrystalline layer is grown on the substrate, and its doping type, concentration, and thickness can be precisely controlled. Unlike the substrate, this is crucial for manufacturing drift regions with precise doping distribution and preventing substrate impurities from diffusing upwards, thereby improving the production quality of diode chips.

[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0030] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for fabricating a diode chip based on high-precision doping control technology, characterized in that: Its preparation process includes the following steps: S1, Substrate Preparation S1.1 Wafer selection: Use a single-crystal silicon wafer. S1.2 Cleaning: Remove organic matter, metal ions, and particulate contaminants from the surface of the single-crystal ghost wafer. Then dry the cleaned single-crystal silicon. S1.3 Epitaxial growth: Extend the single-crystal layer on the substrate through chemical vapor deposition to prepare the diode substrate. S2, thermal oxidation process S2.1 Thermal oxidation: The substrate is coated with photoresist, then heated with solvent, then exposed, then dissolved and exposed, and finally cured with photoresist pattern. S2.2 Etching: The pattern on the photoresist is transferred to the oxide layer below by dry etching to form doped windows. S2.3 Photoresist removal and cleaning: The photoresist residue from the etching is removed and then the substrate is cleaned. S3, ion implantation doping S3.1 Ion implantation: The ion source generates an ion beam of the desired doping element. Then, the characteristic ions are screened by a quality analyzer, and the ion beam is uniformly scanned onto the entire wafer surface by magnetic scanning. S3.2 Rapid thermal annealing: Peak annealing: The wafer is heated to a high temperature of 800-1100°C within a few seconds to tens of seconds, and then rapidly cooled within sixty seconds to obtain a semi-finished diode. S4, Electrode Formation S4.1 Electrode formation: First, metal deposition is performed on the semi-finished product, then photolithography and etching are performed to define the electrode pattern. Next, low-temperature heat treatment is performed to deposit a passivation layer on the surface. Then, electrode contact windows are opened in the passivation layer. Then, the die is diced and finally the die is packaged into the housing and the electrodes are led out. S5, Doping Verification S5.1 Online monitoring using a four-probe tester; S5.2 Offline analysis using secondary ion mass spectrometry (SIMS) to measure junction depth, peak concentration, and distribution shape during fabrication, followed by measurement of carrier concentration distribution with depth and Hall effect measurement of carrier concentration; S5.3 Electrical testing using IV / CV to test the final device's electrical parameters, followed by verification.

2. The method for fabricating a diode chip based on high-precision doping control technology according to claim 1, characterized in that: In the doping control point, energy control means that the energy of the implanted ions precisely determines the projected range of the impurities in silicon, which is the main determinant of the junction depth.

3. The method for fabricating a diode chip based on high-precision doping control technology according to claim 1, characterized in that: The dose control in the doping control point, the total number of impurity atoms injected into a unit area of ​​silicon, in units of atoms / cm², determines the peak concentration near the junction depth, which is 1e11 to 1e16 atoms / cm². The dose control needs to be better than ±1%, and the charge is measured using a Faraday cup.

4. The method for fabricating a diode chip based on high-precision doping control technology according to claim 1, characterized in that: In the doping control point, the injection angle needs to be controlled to <0.1°, and tilted rotation injection is used to suppress the channeling effect.

5. The method for fabricating a diode chip based on high-precision doping control technology according to claim 1, characterized in that: The uniformity control, scanning system, and beam control in the doping control point ensure that the dose and energy uniformity across the entire wafer is ±1%.

6. The method for fabricating a diode chip based on high-precision doping control technology according to claim 1, characterized in that: Beam purity / contamination control at the doping control point.

7. The method for fabricating a diode chip based on high-precision doping control technology according to claim 1, characterized in that: After injection into the doping control point, the surface is cleaned to remove contaminants.

8. The method for fabricating a diode chip based on high-precision doping control technology according to claim 1, characterized in that: The purpose of the epitaxial growth is to grow a single crystal layer on the substrate.

9. The method for fabricating a diode chip based on high-precision doping control technology according to claim 1, characterized in that: The doping control points for the epitaxial growth first control the flow rate, partial pressure, and ratio of the gas source, including SiH4, SiH2Cl, and doping source gases, including PH3, B2H6, and AsH3. Then, control the reaction chamber temperature, typically at 1000-1200℃, and the pressure for LPCVD, which is low. Next, in-situ doping is used. Finally, after growth, the thickness and doping distribution can be analyzed by secondary ion mass spectrometry (SIMS).

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