Super junction structure, manufacturing method thereof and super junction device

Abstract

The invention relates to a super junction structure and a manufacturing method thereof, and a super junction device. The method comprises the following steps: obtaining a substrate on which a first conductive type layer is formed; forming an alignment mark on the first conductive type layer; forming a plurality of grooves in the first conductive type layer through patterning based on the position of the alignment mark; forming a second conductive type column in each groove; forming an epitaxial layer of a first conductive type above each second conductive type column; an injection barrier layer is formed through photoetching, the injection barrier layer is provided with a plurality of injection windows, and a second conductive type column is arranged under each injection window; injecting second conductive type ions into the epitaxial layer through each injection window, and forming a second conductive type region above each second conductive type column; and repeating epitaxy, photoetching and injection for a times, so that each second conductive type column is integrally connected with a + 1 second conductive type regions above the second conductive type column, and obtaining a lengthened second conductive type column. The process difficulty and the manufacturing cost are low.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a superjunction structure, a method for manufacturing the superjunction structure, and a superjunction device. Background Technology

[0002] The two main methods for preparing superjunctions and their main characteristics are as follows:

[0003] Multilayer epitaxial superjunctions: These typically require multiple epitaxial, photolithography, and implantation processes (usually ≥7 layers) to obtain the desired PN alternating superjunction structure. When the pitch (pillar spacing) decreases, to avoid excessive lateral diffusion of dopants, the overall thermal process of the device needs to be reduced. However, to ensure that implanted impurity ions can connect vertically, the thickness of each epitaxial layer needs to be reduced. Therefore, reducing the pitch inevitably leads to an increase in the number of epitaxial layers and an increase in cost.

[0004] Deep Trench Superjunction: The process requires etching a trench with a large aspect ratio (typically ≥8:1), followed by epitaxy inside and outside the trench to obtain the desired PN alternating superjunction structure. As the pitch shrinks, the required trench width decreases, but the depth cannot be reduced due to the limitation of BV (breakdown voltage), thus further increasing the aspect ratio and drastically increasing the process difficulty. Summary of the Invention

[0005] Therefore, it is necessary to provide a superjunction structure and its manufacturing method with low process difficulty and manufacturing cost, as well as a superjunction device.

[0006] A method for manufacturing a superjunction structure includes: Step A, obtaining a substrate with a first conductivity type layer; Step B, forming alignment marks on the first conductivity type layer; Step C, forming a plurality of trenches in the first conductivity type layer by patterning based on the positions of the alignment marks; Step D, forming second conductivity type pillars in each of the trenches; the second conductivity type and the first conductivity type are opposite conductivity types; Step E, forming an epitaxial layer of the first conductivity type above each second conductivity type pillar; Step F, photolithographically forming an implantation barrier layer, the implantation barrier layer having a plurality of implantation windows, each implantation window having a second conductivity type pillar directly below it; Step G, implanting second conductivity type ions into the epitaxial layer through each implantation window, forming a second conductivity type region above each second conductivity type pillar; repeating Step E, Step F and Step G a times, so that each second conductivity type pillar is connected to the a+1 second conductivity type regions above it to obtain an elongated second conductivity type pillar; a is an integer.

[0007] In the manufacturing method of the aforementioned superjunction structure, the lower part of the entire second conductive type pillar (i.e., the elongated second conductive type pillar) is a trench structure, and the upper part is a multilayer epitaxial structure. The depth of the entire second conductive type pillar is distributed between the trench structure and the multilayer epitaxial structure. Therefore, compared to multilayer epitaxial superjunctions and deep trench superjunctions, the manufacturing method of the aforementioned superjunction structure only requires a smaller number of multilayer epitaxial structures / trench structures with relatively small aspect ratios to obtain a superjunction structure with high aspect ratios, resulting in lower process difficulty and manufacturing cost. Furthermore, the alignment marks are formed on the first conductive type layer used to form the trenches, thus reducing the difficulty of trench alignment.

[0008] In one embodiment, the alignment mark is an initial alignment mark.

[0009] In one embodiment, step D involves forming a second conductivity type pillar in each of the trenches by epitaxy of the second conductivity type.

[0010] In one embodiment, the process of repeating steps E, F, and G a times further includes the step of re-adding alignment marks.

[0011] In one embodiment, step C involves forming a plurality of trenches extending downward from the top of the first conductivity type layer by photolithography and etching, wherein the photolithography photomask is aligned by the alignment marks.

[0012] In one embodiment, step A includes forming a first conductivity type layer on a substrate of a first conductivity type, wherein the doping concentration of the substrate is greater than the doping concentration of the first conductivity type layer, and the substrate serves as the drain region of the device.

[0013] In one embodiment, after repeating steps E, F, and G a times, the method further includes: forming a body region, a source region, a gate, a gate dielectric layer, a source electrode, and a drain electrode; the body region has a second conductivity type and is in direct contact with the elongated second conductivity type pillar; the source region has a first conductivity type and is formed in the body region; the gate is formed above the topmost epitaxial layer, and the gate dielectric layer covers the gate; the source electrode is electrically connected to the source region and the body region; and the drain electrode is electrically connected to the drain region.

[0014] A superjunction structure includes a plurality of second conductivity type pillars and a first conductivity type region located between adjacent second conductivity type pillars. Each second conductivity type pillar includes an upper part and a lower part. The lower part is formed in a trench, and an alignment mark is formed on the plane where the top of each trench is located. The upper part is formed by a+1 epitaxy, photolithography and implantation, where a is an integer. The second conductivity type and the first conductivity type are opposite conductivity types.

[0015] In the aforementioned superjunction structure, the lower part of the second conductivity type pillar is a trench structure, and the upper part is a multilayer epitaxial structure. The depth of the second conductivity type pillar is distributed between the trench structure and the multilayer epitaxial structure. Therefore, compared to multilayer epitaxial superjunctions and deep trench superjunctions, the aforementioned superjunction structure only requires a smaller number of multilayer epitaxial structures / trench structures with relatively smaller aspect ratios to obtain a high aspect ratio superjunction structure, resulting in lower process difficulty and manufacturing cost. Furthermore, the alignment marks are formed on the plane at the top of each trench, thus reducing the difficulty of trench alignment.

[0016] In one embodiment, the alignment mark is an initial alignment mark.

[0017] A superjunction device includes: a drain region having a first conductivity type; the aforementioned superjunction structure located on the drain region; a body region having a second conductivity type and in direct contact with the upper part; a source region having a first conductivity type and located in the body region; a gate located above the first conductivity type region; a gate dielectric layer covering the gate; a source electrode electrically connected to the source region and the body region; and a drain electrode electrically connected to the drain region.

[0018] A superjunction structure is manufactured by the manufacturing method of the superjunction structure described in any of the foregoing embodiments.

[0019] This application offers the following advantages: 1. Lower technical difficulty and flexible design; the thickness of the deep trench portion and multilayer epitaxial portion can be adjusted according to actual needs. 2. Lower cost; adjusting the thickness of the deep trench portion / multilayer epitaxial portion based on the etching capabilities of the factory and the epitaxial equipment can achieve the optimal cost solution. 3. Lower photolithographic alignment difficulty; the thickness of the deep trench portion is not limited by the conformal properties of epitaxy. Attached Figure Description

[0020] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0021] Figure 1 This is a flowchart of a method for manufacturing a superjunction structure according to an embodiment of this application.

[0022] Figure 2 This is a cross-sectional structural diagram of the superstructure in the manufacturing process of an embodiment of this application after step S140 is completed.

[0023] Figure 3This is a cross-sectional structural diagram of the superstructure in the manufacturing process of an embodiment of this application after step S170 is completed.

[0024] Figure 4 This is a cross-sectional structural diagram of a superstructure in one embodiment of this application.

[0025] Figure 5 This is a cross-sectional structural schematic diagram of a superjunction device in one embodiment of this application. Detailed Implementation

[0026] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0029] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0032] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0033] An exemplary method for fabricating a superjunction structure involves first forming an initial alignment mark (ZERO MARK), then performing multiple N-type epitaxy processes followed by photolithography and P-type ion implantation (with alignment layers added as needed) to form an alternating PN pillar structure. An N-type epitaxial layer of a certain thickness is then grown on this foundation, followed by deep trench etching and P-type epitaxy to obtain a complete PN pillar alternating superjunction structure. However, because the epitaxial layer cannot perfectly preserve the pattern of the preceding layer, if the epitaxial layer thickness in the deep trench portion is too thick, the pattern etched in the alignment layer of the multi-layer epitaxial portion will be distorted or even disappear, thus increasing the difficulty of photolithographic alignment in the deep trench portion. This leads to significant limitations in the practical application of this method; the epitaxial thickness in the deep trench portion cannot be too thick, otherwise, conformal issues will make photolithographic alignment of subsequent layers difficult.

[0034] This application proposes a method for manufacturing superstructures with relatively low process difficulty and manufacturing cost. Figure 1 This is a flowchart of a method for manufacturing a superjunction structure according to an embodiment of this application, including the following steps:

[0035] S110, Obtain a substrate on which a first conductivity type layer has been formed.

[0036] In one embodiment of this application, a first conductivity type layer 22 is epitaxially formed on substrate 10. The thickness of the first conductivity type layer 22 depends on the etching capability of the etching equipment inside the Fab (semiconductor plant) and the required trench pitch for the product. For example, if the etching equipment can etch trenches with an aspect ratio of 10:1, then a thickness of 20 micrometers for the first conductivity type layer 22 is recommended.

[0037] S120, alignment marks are formed on the first conductivity type layer.

[0038] Alignment marks are used to determine the position / alignment of the photomask during photolithography. In one embodiment of this application, the alignment mark formed in step S120 is an initial alignment mark (ZERO MARK). In another embodiment of this application, step S120 forms the alignment mark through photolithography and etching.

[0039] S130, based on the position of the alignment mark, forms several trenches in the first conductivity type layer by patterning.

[0040] In one embodiment of this application, a plurality of trenches extending downward from the top of the first conductivity type layer 22 are formed by photolithography and etching, and the photolithography photomask is aligned by alignment marks.

[0041] S140, forming a second type of conductive pillar in each trench.

[0042] In one embodiment of this application, second conductivity type pillars 32a are formed in each trench by epitaxy of the second conductivity type, see [link to previous embodiment]. Figure 2 .exist Figure 2 In the illustrated embodiment, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0043] S150, an epitaxial layer of the first conductivity type is formed above each second conductivity type pillar.

[0044] An epitaxial layer 24 is formed by performing an epitaxial layer over the first conductivity type layer 22 and the second conductivity type pillar 32a.

[0045] S160, photolithography forms the injection barrier layer.

[0046] In one embodiment of this application, photoresist is coated on the epitaxial layer 24, then exposed using a corresponding photomask, and then developed. The location where the photoresist is removed exposes the injection window, and the remaining photoresist serves as an injection barrier layer. Directly below each injection window is a second conductivity type pillar 32a. Since the position of the injection window corresponds one-to-one with the second conductivity type pillar 32a, the photolithography in step S160 can use the same photomask as in step S130.

[0047] S170, second conductivity type ions are injected into the epitaxial layer through the injection window of the injection barrier layer.

[0048] The injected second-conductivity type ions form a second-conductivity type region 32b above each second-conductivity type column 32a, as shown in the figure. Figure 3 . Figure 3 The dotted line in the figure represents the boundary between the first conductivity type layer 22 and the epitaxial layer 24.

[0049] S180, repeat steps S150, S160 and S170 a preset number of times.

[0050] The process involves performing steps S150, S160, and S170 a+1 times, where a is a non-negative integer.

[0051] S190 yields a superjunction structure.

[0052] After step S180 is completed, each second conductivity type post 32a is connected to the above a+1 second conductivity type regions 32b to form a complete second conductivity type post 32, as shown in the figure. Figure 4 This yields a superjunction structure with alternating PN pillars. Figure 4 The area below the dotted line is a groove structure, and the area above it is a multi-layered extensional structure.

[0053] In the manufacturing method of the aforementioned superjunction structure, the lower part of the second conductive type pillar 32 is a trench structure, and the upper part is a multilayer epitaxial structure. The depth of the second conductive type pillar 32 is distributed between the trench structure and the multilayer epitaxial structure. Therefore, compared with multilayer epitaxial superjunctions and deep trench superjunctions, the manufacturing method of the aforementioned superjunction structure only requires a multilayer epitaxial structure with fewer layers / a trench structure with a relatively small aspect ratio to obtain a superjunction structure with a high aspect ratio, resulting in lower process difficulty and manufacturing cost. Furthermore, the alignment marks are formed on the first conductive type layer 22 used to form the trenches, thus reducing the difficulty of trench alignment. The trench depth is not limited by the conformal properties of the epitaxial layer, meaning the trench depth can be freely adjusted. The slope of the second conductive type pillar 32 can be flexibly adjusted, thereby allowing for flexible adjustment of parameters such as device withstand voltage and capacitance.

[0054] In one embodiment of this application, when repeating step S150, the step of refreshing the alignment marks is also included, for example, after every two epitaxial layers 24 are formed, the alignment marks are refreshed on the newly formed epitaxial layer 24.

[0055] In one embodiment of this application, the doping concentration of the substrate 10 is greater than the doping concentration of the first conductivity type layer 22, and the substrate 10 serves as the drain region of the device.

[0056] In one embodiment of this application, after step S190, the method further includes forming a body region 44, a source region 42, a gate 54, a gate dielectric layer 52, a source electrode 62, and a drain electrode.

[0057] Reference Figure 5 The body region 44 has a second conductivity type and is in direct contact with the second conductivity type region 32b. The source region 42 has a first conductivity type and is formed in the body region 44. The gate 54 is formed above the topmost epitaxial layer 24, for example, it can be disposed above two adjacent source regions 42, and the gate dielectric layer 52 covers the gate 54. The source electrode 62 is electrically connected to the source region 42 and the body region 44. Figure 5 In the illustrated embodiment, the source electrode 62 is in direct contact with the source region 42 and the body region 44. The drain electrode ( Figure 5 (Not shown) is electrically connected to the drain region (i.e., substrate 10). In one embodiment of this application, the drain electrode is disposed on the back side of substrate 10 (i.e., the side of substrate 10 facing away from the first conductivity type layer 22). In one embodiment of this application, the doping concentration of source region 42 is greater than the doping concentration of the first conductivity type layer 22 and epitaxial layer 24. The materials of source electrode 62 and drain electrode can be metal or alloy.

[0058] In one embodiment of this application, the gate dielectric layer 52 may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum). Alternatively, the gate dielectric layer 52 may comprise a dielectric material with a generally higher dielectric constant having a dielectric constant from about 20 to at least about 100. Such a higher dielectric constant dielectric material may include, but is not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0059] In one embodiment of this application, the gate 54 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate 54.

[0060] In one embodiment of this application, Figure 1 The method for fabricating the superjunction structure shown is used to manufacture a superjunction MOS (metal-oxide-semiconductor) device with a breakdown voltage of 650V and a pitch of 4 micrometers.

[0061] Based on all the above embodiments, the manufacturing method of the superjunction structure of this application has the following advantages: 1. Lower technical difficulty and flexible design; the thickness of the deep trench portion and the multilayer epitaxial portion can be adjusted according to actual needs. 2. Lower cost; adjusting the thickness of the deep trench portion / multilayer epitaxial portion according to the etching and epitaxial machine capabilities within the factory can achieve the optimal cost solution. 3. Less difficult photolithographic alignment; the thickness of the deep trench portion is not limited by the conformal properties of epitaxy.

[0062] An exemplary superjunction structure employs two or more trench layers. In this design, the P-pillar CD at the junction of two trench layers is smaller, affecting the device's breakdown voltage. Furthermore, during trench etching, this design results in poor in-wafer distribution, with CD being larger and deeper near the wafer edge, leading to uneven breakdown voltage distribution within the wafer. To connect the upper and lower trench layers, significant over-etching is required, further amplifying the CD at the wafer edge junction. This further exacerbates the morphological difference between the trenches at the wafer edge and the center, thus affecting the uniformity of breakdown voltage within the wafer. The solution presented in this application avoids these issues.

[0063] This application provides a corresponding superjunction structure, as shown in the reference. Figure 4The superjunction structure includes a plurality of second conductivity type pillars 32, and a first conductivity type pillar (including a first conductivity type layer 22 and an epitaxial layer 24 on the first conductivity type layer 22) located between adjacent second conductivity type pillars 32. Each second conductivity type pillar 32 includes an upper part (second conductivity type region 32b) and a lower part (second conductivity type pillar 32a). The lower part is formed in a trench, and an initial alignment mark is formed on the plane where the top of each trench is located. The upper part is formed by a+1 epitaxial growth, a+1 photolithography, and a+1 implantation, where a is an integer. This superjunction structure can be manufactured by the manufacturing method of the superjunction structure described in any of the foregoing embodiments.

[0064] This application correspondingly provides a superjunction device, which includes the aforementioned superjunction structure. (Refer to...) Figure 5 The superjunction device also includes a drain region (i.e., substrate 10), a body region 44, a source region 42, a gate 54, a gate dielectric layer 52, a source electrode 62, and a drain electrode ( Figure 5 (Not shown). The drain region has a first conductivity type, and its doping concentration is greater than that of the first conductivity type layer 22 and the epitaxial layer 24. The body region 44 has a second conductivity type and is in direct contact with the second conductivity type region 32b. The source region 42 has a first conductivity type and is located in the body region 44. The gate 54 is located above the topmost epitaxial layer 24, for example, it can be disposed above two adjacent source regions 42, and the gate dielectric layer 52 covers the gate 54. The source electrode 62 is electrically connected to the source region 42 and the body region 44. Figure 5 In the illustrated embodiment, the source electrode 62 is in direct contact with the source region 42 and the body region 44. The drain electrode is electrically connected to the drain region. In one embodiment of this application, the drain electrode is disposed on one side of the back side of the substrate 10. In one embodiment of this application, the doping concentration of the source region 42 is greater than the doping concentration of the first conductivity type layer 22 and the epitaxial layer 24. The materials of the source electrode 62 and the drain electrode can be metals or alloys.

[0065] The manufacturing method of the superjunction structure in this application is based on the same inventive concept as the superjunction structure. For details not specifically described in the superjunction structure, please refer to the above introduction of the manufacturing method of the superjunction structure.

[0066] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0067] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0068] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0069] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a superstructure, comprising: Step A: Obtain a substrate with a first conductivity type layer formed thereon; Step B: Form alignment marks on the first conductivity type layer; Step C: Based on the position of the alignment mark, a plurality of trenches are formed in the first conductive type layer by patterning; Step D: Forming a second conductivity type pillar in each of the trenches; the second conductivity type and the first conductivity type are opposite conductivity types; Step E: An epitaxial layer of the first conductivity type is formed above each of the second conductivity type pillars; Step F: Photolithography forms an injection barrier layer, which has multiple injection windows, with a second type of conductive pillar directly below each injection window; Step G: Ions of the second conductivity type are injected into the epitaxial layer through each of the injection windows to form a second conductivity type region above each second conductivity type pillar; Repeat steps E, F, and G a times to connect each second conductive type column with the a+1 second conductive type regions above it to form an elongated second conductive type column; a is an integer.

2. The method for manufacturing a superstructure according to claim 1, characterized in that, The alignment mark is the initial alignment mark.

3. The method for manufacturing a superstructure according to claim 1, characterized in that, Step D involves forming second-conductivity type pillars in each of the trenches by epitaxy of the second conductivity type.

4. The method for manufacturing a superstructure according to claim 1, characterized in that, The process of repeating steps E, F, and G a times also includes the step of re-adding alignment marks.

5. The method for manufacturing a superstructure according to claim 1, characterized in that, Step C involves forming a plurality of trenches extending downward from the top of the first conductivity type layer through photolithography and etching, with the photolithography plate being aligned in position using the alignment marks.

6. The method for manufacturing a superstructure according to claim 1, characterized in that, Step A includes forming a first conductivity type layer on a substrate of a first conductivity type, wherein the doping concentration of the substrate is greater than the doping concentration of the first conductivity type layer, and the substrate serves as the drain region of the device.

7. The method for manufacturing a superstructure according to claim 6, characterized in that, After repeating steps E, F, and G a times, the method further includes: forming a body region, a source region, a gate, a gate dielectric layer, a source electrode, and a drain electrode. The body region has a second conductivity type and is in direct contact with the elongated second conductivity type pillar; the source region has a first conductivity type and is formed in the body region; the gate is formed above the topmost epitaxial layer, and the gate dielectric layer covers the gate; the source electrode is electrically connected to the source region and the body region; the drain electrode is electrically connected to the drain region.

8. A superjunction structure comprising a plurality of second conductivity type pillars and a first conductivity type region located between adjacent second conductivity type pillars, characterized in that, Each second conductivity type post includes an upper part and a lower part, the lower part being formed in a trench, and an alignment mark being formed on the plane at the top of each trench; the upper part is formed by a+1 epitaxial growth, photolithography and implantation, where a is an integer; the second conductivity type and the first conductivity type are opposite conductivity types.

9. A superjunction device, characterized in that, include: The drain region has the first conductivity type; The superjunction structure as described in claim 7 is located on the drain region; The body region has a second conductivity type and is in direct contact with the upper part; The source region, having a first conductivity type, is located in the bulk region; The gate is located above the first conductivity type region; A gate dielectric layer covers the gate. The source electrode is electrically connected to the source region and the body region; The drain electrode is electrically connected to the drain region.

10. A superjunction structure, characterized in that, The superstructure is manufactured by the manufacturing method of any one of claims 1-6.

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