Silicon carbide power device, preparation method thereof and semiconductor device

Abstract

The embodiment of the invention discloses a silicon carbide power device, a preparation method thereof and a semiconductor device, and belongs to the technical field of semiconductors. The silicon carbide power device comprises a substrate, a source electrode structure, a grid electrode structure and an electric field shielding layer; the source structure is arranged on the substrate; the gate structure is arranged in the substrate, and the source structure surrounds at least part of the side surface of the gate structure; the electric field shielding layer covers the bottom of at least part of the cross section of the gate structure and is connected with the source structure. The electric field of the gate dielectric layer of the silicon carbide semiconductor device in a reverse blocking state can be shared on the electric field shielding layer, so that the shielding effect is improved to the maximum extent, the electric field of the gate dielectric layer is reduced, and the semiconductor device has high reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a silicon carbide power device and its fabrication method, and a semiconductor device. Background Technology

[0002] Silicon carbide semiconductors have superior properties such as wide bandgap, high thermal conductivity, high breakdown field strength, and high electron saturation velocity, and have been widely used in power devices.

[0003] When silicon carbide power devices are in reverse blocking mode, the high breakdown field strength of silicon carbide makes the gate dielectric layer easily broken down, leading to a decrease in the performance of the silicon carbide power devices or even failure. In related technologies, an electric field shielding structure is usually wrapped around the trench gate in the drift region of the epitaxial layer. The electric field shielding structure is used to withstand the voltage of the silicon carbide power device in reverse blocking mode, thereby reducing the electric field of the gate dielectric layer.

[0004] However, the shielding effect of the above-mentioned electric field shielding structure is poor. Summary of the Invention

[0005] In view of the above problems, this application provides a silicon carbide power device and its fabrication method, as well as a semiconductor device. When the silicon carbide power device is in the reverse blocking state, it can distribute the electric field of the gate dielectric layer to the electric field shielding layer, thereby helping to reduce the electric field strength of the gate dielectric layer in the reverse blocking state of the silicon carbide power device, thereby improving the reliability of the gate dielectric layer and improving the shielding effect. At the same time, the silicon carbide power device can further reduce the cell size and reduce the forward conduction resistance, thereby ensuring the performance and reliability of the semiconductor device.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] A first aspect of this application provides a silicon carbide power device, comprising:

[0008] Base;

[0009] A source structure, wherein the source structure is disposed on the substrate;

[0010] A gate structure disposed within the substrate, wherein the source structure surrounds at least a portion of the sidewalls of the gate structure;

[0011] An electric field shielding layer is disposed within the substrate, the electric field shielding layer covering the bottom of at least a portion of the cross-section of the gate structure, and the electric field shielding layer is connected to the source structure.

[0012] In one feasible implementation, the electric field shielding layer extends to a depth greater than the depth of the gate structure on the bottom surface of the substrate.

[0013] In one feasible implementation, the electric field shielding layer includes at least a first sub-electric field shielding layer and a second sub-electric field shielding layer, wherein the first sub-electric field shielding layer and the second sub-electric field shielding layer are respectively disposed on both sides of at least a portion of the cross-section of the gate structure.

[0014] In this configuration, at least one of the first sub-electric field shielding layer and the second sub-electric field shielding layer is connected to the source structure.

[0015] In one possible implementation, the first sub-field shielding layer and / or the second sub-field shielding layer cover the entire bottom surface of at least a portion of the cross-section of the gate structure.

[0016] In one feasible implementation, the first sub-electric field shielding layer and the second sub-electric field shielding layer are electrically connected.

[0017] In one possible implementation, the electric field shielding layer further includes a third sub-electric field shielding layer disposed on the bottom surface of at least a portion of the cross-section of the gate structure.

[0018] In one possible implementation, the third sub-electric field shielding layer is electrically connected to the first sub-electric field shielding layer and / or the second sub-electric field shielding layer.

[0019] In one possible implementation, the third sub-electric field shielding layer is disposed on the same cross-section of the gate structure as the first sub-electric field shielding layer and the second sub-electric field shielding layer.

[0020] In one possible implementation, the electric field shielding layer has a protrusion extending toward the bottom surface of the substrate; the protrusion is opposite to the gate structure in a direction perpendicular to the substrate.

[0021] In one feasible implementation, the protrusion includes a main body and an extension along the thickness direction of the substrate;

[0022] Along a direction perpendicular to the substrate, the main body portion is opposite to the gate structure, and the main body portion covers the bottom surface of the gate structure;

[0023] The extension is connected to the side of the main body and extends toward the source structure; wherein the extension also covers at least a portion of the side of the gate structure and is connected to the source structure.

[0024] In one possible implementation, the number of extensions includes two, with the two extensions located on opposite sides of the main body.

[0025] In one feasible implementation, in the same main body portion, the two extension portions are disposed opposite each other, parallel to the plane of the base and along the second direction; or, in the same main body portion, the two extension portions are offset from each other, parallel to the plane of the base and along the second direction.

[0026] In one feasible implementation, the gate structure is strip-shaped on a plane parallel to the substrate, and the gate structure extends along a first direction.

[0027] The source structure includes a plurality of source portions, which are spaced apart along the first direction, and each source portion surrounds a portion of the side surface of the gate structure.

[0028] An electric field shielding layer covering the side of the gate structure extends along the bottom surface away from the substrate and extends between adjacent source portions.

[0029] In one possible implementation, the electric field shielding layer located between adjacent source portions is connected to at least one of the two adjacent source portions.

[0030] In one feasible implementation, the electric field shielding layer located between any adjacent source electrodes has a strip shape in the orthographic projection onto the substrate.

[0031] In one feasible implementation, the electric field shielding layer located between any adjacent source portions has a bent shape in the orthographic projection onto the substrate.

[0032] In one feasible implementation, the electric field shielding layer located between any two adjacent source electrodes has a projection shape on the substrate that includes a plurality of shielding extension segments and shielding connection segments, with adjacent shielding extension segments connected by the shielding connection segments, and any two adjacent shielding extension segments being staggered in a second direction.

[0033] The second direction and the first direction intersect each other.

[0034] In one feasible implementation, the electric field shielding layers located on both sides of the gate structure are arranged in a centrally symmetrical manner with respect to the gate structure.

[0035] Alternatively, the electric field shielding layers located on both sides of the gate structure are arranged symmetrically with respect to the gate structure.

[0036] In one possible implementation, the gate structure includes a plurality of gate structures, which are spaced apart along a second direction;

[0037] The electric field shielding layer covers at least a portion of the cross-section of the entire gate structure.

[0038] In one possible implementation, each of the gate structures includes a gate body and a gate protrusion, the gate body extending along the first direction and the gate protrusion protruding at least one side of the gate body along the second direction.

[0039] In one feasible implementation, the source structure includes a second conductivity type source active region and a first conductivity type source region;

[0040] Along the thickness direction of the substrate, the second conductivity type source active region is disposed on the substrate, and the first conductivity type source region is disposed on the second conductivity type source active region.

[0041] In one possible implementation, the silicon carbide power device further includes a source electrode layer disposed on and connected to the source structure.

[0042] In one feasible implementation, the silicon carbide power device further includes a second conductivity type ohmic contact layer, through which the source electrode layer and the source structure are connected.

[0043] In one feasible implementation, the second conductivity type ohmic contact layer is disposed within the electric field shielding layer;

[0044] Furthermore, the electric field shielding layer is connected to the source structure through the second conductivity type ohmic contact layer and the source electrode layer.

[0045] In one possible implementation, the substrate includes a substrate and a first conductivity type epitaxial layer disposed on the substrate.

[0046] In one possible implementation, the gate structure includes a gate and a gate dielectric layer, the gate dielectric layer covering the bottom and side surfaces of the gate.

[0047] A second aspect of this application provides a method for fabricating a silicon carbide power device, comprising:

[0048] Provide a base;

[0049] A source structure is formed, wherein the source structure is disposed on the substrate;

[0050] An electric field shielding layer and a gate structure are formed within the substrate, the source structure surrounds at least a portion of the side surface of the gate structure, the electric field shielding layer covers at least a portion of the bottom cross-section of the gate structure, and the electric field shielding layer is connected to the source structure.

[0051] In one feasible implementation, the step of forming the source structure includes:

[0052] A source electrode structure material layer is formed, wherein the source electrode structure material layer is disposed on the substrate;

[0053] A first mask layer having a plurality of first mask openings is formed on the source structure material layer, the plurality of first mask openings being arranged at intervals along a second direction, and each first mask opening extending along a first direction; wherein the first direction and the second direction intersect each other;

[0054] The source structure material layer and part of the substrate exposed in the first mask opening are removed to form a gate trench; wherein the remaining source structure material layer constitutes the source structure;

[0055] Remove the first mask layer.

[0056] In one feasible implementation, the step of forming the electric field shielding layer and the gate structure includes:

[0057] A second mask layer is formed, which fills the gate trench and covers the top surface of the source structure;

[0058] The second mask layer is patterned to form a plurality of second mask openings; the plurality of second mask openings are spaced apart along the first direction, and each second mask opening extends along the second direction; wherein the second mask opening exposes a portion of the gate trench;

[0059] Using the second mask layer as a mask, an electric field shielding layer is formed at least on the inner wall of the exposed gate trench through an ion implantation process;

[0060] Remove the second mask layer;

[0061] A gate structure is formed, wherein the gate structure is disposed within the gate trench.

[0062] In one feasible implementation, the step of forming the gate trench includes:

[0063] Through multiple etching processes, multi-level gate trenches are formed in the substrate; wherein, along the direction pointing to the bottom surface of the substrate, the diameter of the gate trenches gradually decreases.

[0064] In one feasible implementation, the step of providing the substrate includes:

[0065] Provide substrate;

[0066] An epitaxial layer of a first conductivity type is formed, and the first conductivity type epitaxial layer is disposed on a substrate.

[0067] In one feasible implementation, the step of forming the source structure includes:

[0068] A second conductivity type source active region is formed, and the second conductivity type source active region is disposed on the first conductivity type epitaxial layer;

[0069] A first conductivity type source region is formed, which is disposed on the second conductivity type source active region.

[0070] A third aspect of this application provides a semiconductor device, including the silicon carbide power device described in the first aspect.

[0071] This application provides a silicon carbide power device and its fabrication method, as well as a semiconductor device. An electric field shielding layer covers at least a portion of the bottom surface of the cross-section of the gate structure, and the electric field shielding layer is connected to the source structure. This effectively distributes the electric field of the gate dielectric layer onto the electric field shielding layer, thereby helping to reduce the electric field of the silicon carbide power device in reverse blocking mode. It prevents the electric field from accumulating at the bottom of the gate dielectric layer, improving the reliability of the gate dielectric layer and avoiding the problem of gate structure failure due to gate dielectric layer breakdown. This ensures the performance and reliability of the gate structure, and further guarantees the performance and reliability of the semiconductor device. Attached Figure Description

[0072] Figure 1 A schematic diagram of the structure of the silicon carbide power device provided in the embodiments of this application. Figure 1 ;

[0073] Figure 2 A schematic diagram of the structure of the silicon carbide power device provided in the embodiments of this application. Figure 2 ;

[0074] Figure 3 for Figure 1 A cross-sectional view along the AA direction;

[0075] Figure 4 for Figure 1 Another sectional view along the AA direction;

[0076] Figure 5 for Figure 2 A cross-sectional view along the BB direction;

[0077] Figure 6for Figure 2 A cross-sectional view along the CC direction;

[0078] Figure 7 A process flow diagram illustrating the fabrication method of the silicon carbide power device provided in the embodiments of this application;

[0079] Figure 8 An arrangement of an electric field shielding layer and a gate structure provided in this application embodiment;

[0080] Figure 9 This application provides another arrangement of the electric field shielding layer and gate structure.

[0081] Explanation of reference numerals in the attached figures:

[0082] 100 - Substrate; 110 - Substrate; 120 - Epitaxial layer of first conductivity type;

[0083] 200 - Gate structure; 210 - Gate; 220 - Gate dielectric layer; 230 - Gate body; 240 - Gate protrusion; 250 - Gate trench;

[0084] 300 - Source structure; 310 - Second conductivity type source active region; 320 - First conductivity type source region; 330 - Source portion;

[0085] 400 - Electric field shielding layer; 410 - First sub-electric field shielding layer; 420 - Second sub-electric field shielding layer; 430 - Third sub-electric field shielding layer; 441 - Main body; 442 - Extension; 444 - Shielding extension section; 445 - Shielding connection section; 446 - Protrusion;

[0086] 500 - Insulation layer;

[0087] 600 - Second type of conductivity ohmic contact layer;

[0088] 700 - Source metal contact hole;

[0089] 800 - Source electrode layer. Detailed Implementation

[0090] Currently, trench-gate silicon carbide (SiC) power devices, compared to planar-gate SiC power devices, have smaller cell sizes and higher channel mobility, resulting in lower forward on-resistance. Therefore, trench-gate SiC power devices are gradually becoming the future development direction for SiC power devices and are widely used in various semiconductor device fields. However, the reliability of the gate dielectric layer in trench-gate SiC power devices is relatively poor. When the trench-gate SiC power device is in reverse blocking mode, the electric field of the gate dielectric layer is mainly concentrated at the bottom of the trench, making the gate dielectric layer prone to breakdown and thus affecting the reliability of the trench-gate SiC power device.

[0091] In related technologies, to protect the gate dielectric layer and improve the reliability of trench-gate silicon carbide semiconductor devices, an electric field shielding structure is typically formed in the epitaxial layer through high-temperature ion implantation. This electric field shielding structure blocks the electric field in the epitaxial layer when the silicon carbide power device is in reverse blocking mode. However, in these technologies, the shielding effect of the electric field shielding structure is poor. Moreover, setting an electric field shielding layer in a trench gate structure requires high-energy ion implantation, which is difficult to process and increases epitaxial defects. Furthermore, the presence of the electric field shielding layer prevents further reduction in the individual cell size, hindering further reduction in the forward conduction resistance of the silicon carbide power device and thus affecting its performance.

[0092] To address the aforementioned technical problems, this application provides a silicon carbide power device and its fabrication method, as well as a semiconductor device. An electric field shielding layer covers at least a portion of the bottom surface of the cross-section of the gate structure, and the electric field shielding layer is connected to the source structure. This maximizes the distribution of the electric field from the gate dielectric layer onto the electric field shielding layer, thereby helping to reduce the electric field in the reverse blocking state of the silicon carbide power device. It prevents the electric field from accumulating at the bottom of the gate dielectric layer, improving the reliability of the gate dielectric layer and avoiding the problem of gate structure failure due to gate dielectric layer breakdown. This ensures the performance and reliability of the gate structure, further guaranteeing the performance and reliability of the semiconductor device.

[0093] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0094] This application provides a silicon carbide power device whose cell structure can be applied to semiconductor devices. This embodiment primarily uses a trench-gate silicon carbide power device as an example.

[0095] Reference Figures 1 to 6 As shown, the silicon carbide power device includes a substrate 100.

[0096] Among them, reference Figures 3 to 6As shown, the substrate 100 includes a substrate 110. The substrate 110 serves as a support component for the silicon carbide power device, supporting other components disposed thereon. The substrate 110 may be made of a semiconductor material. For example, the material of the substrate 110 may include silicon carbide.

[0097] A first conductivity type epitaxial layer 120 is disposed on the front side of the substrate 110, and a drain electrode layer is disposed on the back side of the substrate 110. Herein, the front side of the substrate 110 refers to the upper surface of the substrate 110, and the back side of the substrate 110 refers to the lower surface of the substrate 110.

[0098] It should be noted that the doping concentration of the epitaxial layer 120 is not limited in this embodiment, and can be prepared according to actual needs. Furthermore, the conductivity type of the epitaxial layer 120 is not limited. For example, the conductivity type of the epitaxial layer 120 can be a first conductivity type N-type, or the conductivity type of the epitaxial layer 120 can be a second conductivity type P-type.

[0099] In this embodiment, the first conductivity type epitaxial layer 120 is mainly described as the first conductivity type N-type.

[0100] Reference Figures 1 to 6 As shown, a silicon carbide power device may include a gate structure 200 disposed within a substrate 110, such that the gate structure 200 forms a trench gate. Compared to planar gate semiconductor devices, trench gate semiconductor devices can have smaller cell sizes and higher channel mobility. Therefore, trench gate silicon carbide power devices significantly reduce the resistance during forward conduction, thereby improving the performance of the silicon carbide power device.

[0101] Reference Figures 3 to 6 As shown, the gate structure 200 includes a gate 210 and a gate dielectric layer 220, with the gate dielectric layer 220 covering the bottom and side surfaces of the gate 210. In the specific fabrication process, a first conductivity type epitaxial layer 120 can be grown on the substrate 110 firstly, and then a gate trench can be formed by patterning and etching on the first conductivity type epitaxial layer 120. Subsequently, the gate dielectric layer 220 is formed on the inner wall of the gate trench using thermal oxidation or deposition processes, followed by the formation of the gate 210, which fills the area enclosed by the gate dielectric layer 220. Thus, the gate dielectric layer 220 covers the bottom and side surfaces of the gate 210. The gate dielectric layer 220 is made of silicon oxide. The gate 210 is made of, but is not limited to, polysilicon.

[0102] In this embodiment, the number of gate structures 200 is not limited. For example, there may be multiple gate structures 200; the number of gate structures 200 may include two; or, the number of gate structures 200 may include five; or, the number of gate structures 200 may include more than one. This embodiment does not limit this.

[0103] In this configuration, multiple gate structures 200 are spaced apart along a second direction, which may intersect the extending direction of each gate structure 200. For example, each gate structure 200 extends along a first direction. Figure 1 and attached Figure 2 Taking the indicated direction as an example, the first direction can be the attached direction. Figure 1 and attached Figure 2 In the Y direction, the second direction can be correspondingly... Figure 1 and attached Figure 2 The X direction in the equation.

[0104] This facilitates the arrangement of multiple gate structures 200 and increases the space occupied by the gate structure 200 in the cell structure, thereby increasing the conduction channel area of ​​the gate structure 200 during the operation of the silicon carbide power device, and thus effectively reducing the channel resistance.

[0105] Reference Figure 5 As shown, the silicon carbide power device includes a source structure 300 disposed within a substrate 100. The source structure 300 surrounds at least a portion of the sidewalls of the gate structure 200, thereby forming a channel region between the source structure 300 and the gate structure 200, facilitating the formation of a trench transistor. It should be noted that when the substrate 100 includes a substrate 110 and a first conductivity type epitaxial layer 120, the source structure 300 is disposed on the first conductivity type epitaxial layer 120.

[0106] It should be understood that when the source structure 300 is formed through a doping process, the source structure 300 is disposed within the first conductivity type epitaxial layer 120; when the source structure 300 is formed through a combination of deposition and doping processes, the source structure 300 can be disposed on the first conductivity type epitaxial layer 120. Specifically, this can be understood based on the differences in the actual fabrication process.

[0107] Reference Figure 5 As shown, the source structure 300 includes a second conductivity type source active region 310 and a first conductivity type source region 320 stacked together. Along the thickness direction of the substrate 100, the second conductivity type source active region 310 is disposed on the substrate 100, and the first conductivity type source region 320 is disposed on the second conductivity type source active region 310.

[0108] The first conductivity type can be N-type and the second conductivity type can be P-type; or, the first conductivity type can be P-type and the second conductivity type can be N-type.

[0109] In this embodiment, the first conductivity type source region 320 and the first conductivity type epitaxial layer 120 are N-type, and the second conductivity type source active region 310 is P-type, as an example for illustration.

[0110] When a positive voltage is applied to the gate structure 200, the portion of the second conductivity type source active region 310 that contacts the gate structure 200 can be inverted, so that the conductivity type of the inverted portion of the second conductivity type source active region 310 becomes the first conductivity type. This allows the first conductivity type source region 320 and the first conductivity type epitaxial layer 120 of the silicon carbide power device to be connected through the inversion layer formed by the second conductivity type source active region 310, thereby ensuring that the silicon carbide power device is in a conducting state.

[0111] Please refer to the appendix. Figure 3 As shown, the silicon carbide power device also includes an electric field shielding layer 400, which is disposed within the substrate 100. It should be noted that when the substrate 100 includes a substrate 110 and a first conductivity type epitaxial layer 120, the electric field shielding layer 400 is disposed within the first conductivity type epitaxial layer 120.

[0112] The electric field shielding layer 400 covers the bottom of at least a portion of the cross-section of the gate structure 200, and the electric field shielding layer 400 is connected to the source structure 300. It should be understood that when there are multiple gate structures 200, the electric field shielding layer 400 covers at least a portion of the cross-section of all gate structures 200.

[0113] In this embodiment, at least a partial cross-section refers to the cross-section of the gate structure 200 in a partial direction. For example, see... Figure 1 As shown, the "at least partial cross-section" of the gate structure 200 can be Figure 1 When a section line is drawn along the AA direction, the resulting cross-section, or in other words, the reference section... Figure 2 As shown, the "at least partial cross-section" of the gate structure 200 can be Figure 2 The cross section formed when a section line is drawn along the BB direction.

[0114] In this embodiment, the bottom of the gate structure 200 is defined with reference to the substrate 100. The bottom of the gate structure 200 can be understood as the portion facing the bottom surface of the substrate 100, and this bottom may include the bottom surface of the gate structure 200, and may also include the bottom surface and a portion of the side surface of the gate structure 200. Wherein, as shown in the attached... Figure 1Taking the orientation shown as an example, the bottom surface of the gate structure 200 is the surface facing the bottom surface of the substrate 100, which can be the lower surface of the substrate 100.

[0115] In this embodiment, when the silicon carbide power device is in reverse blocking state, the electric field shielding layer 400 can deplete the electric field accumulated in the substrate 100 to reduce the electric field of the gate dielectric layer 220, thereby ensuring device reliability. Simultaneously, in this embodiment, the electric field shielding layer 400 is connected to the source structure 300, forming a conductive path. Thus, when the silicon carbide power device cell structure is in reverse bias state, it can prevent the electric field from accumulating at the bottom of the gate dielectric layer 220, improving the reliability of the gate dielectric layer and avoiding the problem of gate structure failure due to gate dielectric layer breakdown, thereby ensuring the performance and reliability of the gate structure, and further ensuring the performance and reliability of the semiconductor device.

[0116] The electric field shielding layer 400 covers at least a portion of the bottom cross-section of the gate structure 200, forming an intermittent structure. This helps to further optimize the electric field distribution in the substrate 100, reducing excessive concentration of the electric field in specific areas, thereby improving the overall reliability and performance of the silicon carbide power device. Furthermore, the intermittent structure of the electric field shielding layer 400 ensures effective coverage of the protected area while avoiding overlap with the source structure 300, thus ensuring the performance of the silicon carbide power device.

[0117] To further improve the shielding effect of the electric field shielding layer 400, in this embodiment, the extension depth of the electric field shielding layer 400 to the bottom surface of the substrate 100 is greater than the depth of the gate structure 200. Thus, compared to related technologies, when the silicon carbide power device is in a reverse blocking state, the electric field shielding layer 400 can block the electric field, thereby distributing the electric field of the gate dielectric layer 220 onto the electric field shielding layer 400. This helps to shield the gate dielectric layer electric field 122 when the silicon carbide power device is in a reverse blocking state, improving the reliability of the gate dielectric layer 220 and preventing the gate structure 200 from failing due to the breakdown of the gate dielectric layer 220. This ensures the performance and reliability of the gate structure 200, and further guarantees the performance and reliability of the silicon carbide power device.

[0118] In one possible implementation, refer to Figure 3 and Figure 4 As shown, the electric field shielding layer 400 may include at least a first sub-electric field shielding layer 410 and a second sub-electric field shielding layer 420, which are respectively disposed on both sides of at least a portion of the cross-section of the gate structure 200.

[0119] It should be noted that the positions of the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 are as follows: Figure 3 , Figure 4 and Figure 6 As shown, in Figure 3 and Figure 4 In the middle, the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 are located in the area above the dashed line and are disposed on the left and right sides of the gate structure 200 in the vertical direction.

[0120] In this configuration, at least one of the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 is connected to the source structure 300. That is, the source structure 300 can be connected to one of the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420, or the source structure 300 can be connected to both the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 simultaneously.

[0121] It should be noted that at least two sides of a portion of the cross-section can be: on the cross-section along the AA direction, the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 are respectively located on both sides of the gate structure 200. Figure 4 Taking the orientation shown as an example, the first sub-electric field shielding layer 410 is located on the left side of the gate structure 200, and the second sub-electric field shielding layer 420 is located on the right side of the gate structure 200. Both the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 extend along the thickness direction of the substrate 100, such that the ends of the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 facing the bottom surface of the substrate 100 are positioned near the bottom of the gate structure 200.

[0122] With this configuration, at least one of the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 effectively shields electric field interference from both sides of the gate structure 200, which can significantly reduce the capacitive coupling between the gate structure 200 and the surrounding structure, thereby reducing the impact of the electric field on the device performance.

[0123] On the two vertical sides of the gate structure 200, only one side of the gate structure 200 may be wrapped, while the other side may not be wrapped; or both sides of the gate structure 200 may be wrapped. For example, the first sub-electric field shielding layer 410 and / or the second sub-electric field shielding layer 420 cover the entire bottom surface of at least a portion of the cross-section of the gate structure 200.

[0124] That is, the first sub-electric field shielding layer 410 may extend in a direction perpendicular to the substrate 100 and cover the entire bottom surface of at least a portion of the cross-section of the gate structure 200; or, the second sub-electric field shielding layer 420 may extend in a direction perpendicular to the substrate 100 and cover the entire bottom surface of at least a portion of the cross-section of the gate structure 200; or, it may extend and cover the entire bottom surface of the gate structure 200 simultaneously. This embodiment does not limit this.

[0125] In this embodiment, the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 are electrically connected. This helps to increase the area of ​​the electric field shielding layer 400, further enhancing the shielding effect; in addition, it also facilitates connection with the source structure 300.

[0126] In one possible implementation, refer to Figure 3 and Figure 4 As shown, the electric field shielding layer 400 may further include a third sub-electric field shielding layer 430, which may be disposed on the bottom surface of at least a portion of the cross-section of the gate structure 200.

[0127] It should be noted that the position of the third sub-electric field shielding layer 430 is as follows: Figure 3 and Figure 4 As shown. Among them, in Figure 3 and Figure 4 In the middle, the third sub-electric field shielding layer 430 is located in the region below the dashed line and is disposed at the bottom of the gate structure 200 in a direction perpendicular to the substrate 100.

[0128] In this embodiment, the third sub-electric field shielding layer 430 is electrically connected to at least one of the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420. This helps to increase the area of ​​the electric field shielding layer 400, further enhancing the shielding effect; in addition, it also facilitates connection with the source structure 300.

[0129] In this embodiment, the third sub-electric field shielding layer 430, the first sub-electric field shielding layer 410, and the second sub-electric field shielding layer 420 can be disposed on the same cross-section of the gate structure 200. While ensuring that the third sub-electric field shielding layer 430 is connected to the first sub-electric field shielding layer 410 and / or the second sub-electric field shielding layer 420, and increasing the area of ​​the electric field shielding layer 400, the fabrication process of the electric field shielding layer 400 can be simplified, and the fabrication difficulty of the electric field shielding layer 400 can be reduced.

[0130] It should be noted that the third sub-electric field shielding layer 430, the first sub-electric field shielding layer 410, and the second sub-electric field shielding layer 420 can also be disposed on different cross-sections of the gate structure 200. In this way, the optimal configuration position of the electric field shielding layer can be selected according to specific application requirements and design considerations to adapt to different working environments and performance requirements.

[0131] In one possible implementation, refer to Figure 4 and Figure 6 As shown, the electric field shielding layer 400 has a protrusion 446 extending toward the bottom surface of the substrate 100, and the protrusion 446 is opposite to the gate structure 200 in a direction perpendicular to the substrate 100. Alternatively, the protrusion 446 is located directly below the gate structure 200 in a direction perpendicular to the substrate 100.

[0132] This configuration increases the depth of the electric field shielding layer 400 in the direction perpendicular to the substrate 100, making the depth of the electric field shielding layer 400 much greater than the depth of the gate structure 200. This increases the area of ​​the electric field shielding layer 400, which in turn effectively shields the electric field around the gate structure 200, reducing the risk of electric field concentration in the gate dielectric layer 220 of the gate structure 200. This reduces the risk of silicon carbide power device breakdown and improves the reliability of the silicon carbide power device.

[0133] It should be noted that the protrusion 446 may extend only in a direction perpendicular to the base 100, or other options may be available. For example, refer to... Figure 6 As shown, the protrusion 446 may include a main body 441 and an extension 442.

[0134] Along a direction perpendicular to the substrate 100, the main body portion 441 is opposite to the gate structure 200, and the main body portion 441 covers the bottom surface of the gate structure 200.

[0135] The extension 442 is connected to the side of the main body 441 and extends toward the source structure 300. The extension 442 also covers at least a portion of the side of the gate structure 200 and is connected to the source structure 300. In this way, the main body 441 can be connected to the electric field shielding layer 400 located on both sides of the gate structure 200 through the extension 442.

[0136] In this embodiment, the cross-sectional shape of the protrusion 446 on the cross-section perpendicular to the substrate 100 is similar to an inverted convex shape, which can help increase the area of ​​the protrusion 446, thereby increasing the area of ​​the electric field shielding layer 400, effectively shielding the electric field around the gate structure 200, and reducing the risk of electric field concentration in the gate dielectric layer 220 in the gate structure 200.

[0137] In this embodiment, the number of extensions 442 is not limited. For example, the number of extensions 442 may include two, with the two extensions 442 located on opposite sides of the main body 441.

[0138] In this embodiment, within the same main body 441, two extensions 442 are disposed opposite each other, parallel to the plane of the base 100 and along the second direction; or, within the same main body 441, two extensions 442 are offset from each other, parallel to the plane of the base 100 and along the second direction. Referring to... Figure 6 As shown, the explanation mainly focuses on the two extensions 442 being used relative to each other. In this way, while ensuring the increase in the channel length of the silicon carbide power device, the fabrication difficulty of the electric field shielding layer 400 can be reduced.

[0139] In one possible implementation, refer to Appendix Figure 1 and attached Figure 2 On a plane parallel to the substrate 100, the gate structure 200 is strip-shaped and extends along a first direction. That is, the gate structure 200 is a strip trench gate.

[0140] The source structure 300 includes a plurality of source portions 330, which are spaced apart along a first direction, and each source portion 330 surrounds a portion of the side surface of the gate structure 200; an electric field shielding layer 400 covering the side surface of the gate structure 200 extends along the bottom surface away from the substrate 100 and extends between adjacent source portions 330.

[0141] In this embodiment, both the source structure 300 and the electric field shielding layer 400 are discontinuous, such that the electric field shielding layer 400 is located between any two adjacent source structures 300. Compared to the strip-shaped source structure 300, the discontinuous source structure 300 provides more space for the electric field shielding layer 400, thereby increasing its area. Furthermore, the arrangement of the source structures 300 helps reduce capacitive coupling between the gate structure 200 and the source structure 300, thereby reducing power consumption and increasing the switching speed of the device.

[0142] It is important to understand that the electric field shielding layer 400 needs to be connected to the source structure 300. When the source structure 300 includes multiple source portions 330, the electric field shielding layer 400 located between adjacent source portions 330 is connected to at least one of the two adjacent source portions 330. In one example, the electric field shielding layer 400 located between adjacent source portions 330 is connected to one of the two adjacent source portions 330; in another example, the electric field shielding layer 400 located between adjacent source portions 330 is connected to both of the adjacent source portions 330.

[0143] In this way, the overlap between the source structure 300 and the electric field shielding layer 400 can be avoided, thereby preventing the current flow of the source structure 300 from interfering with the electric field distribution of the electric field shielding layer 400 and ensuring the shielding effect of the electric field shielding layer 400.

[0144] It should be noted that in this embodiment, the electric field shielding layer 400 can be directly connected to the source structure 300 or indirectly connected. For example, the electric field shielding layer 400 covering the side of the gate structure 200 extends along the bottom surface away from the substrate 100, and the extension height is large enough so that the electric field shielding layer 400 extends between adjacent source portions 330 and contacts the source portions 330; in this case, the electric field shielding layer 400 can be directly connected to the source structure 300.

[0145] For example, the electric field shielding layer 400 covering the side of the gate structure 200 extends along the bottom surface away from the substrate 100. When the extension height is small, it can also be connected to the source structure 300 through other components. Exemplarily, the electric field shielding layer 400 is connected to the source structure 300 through a second conductivity type ohmic contact layer 600 and a source electrode layer 800.

[0146] The electric field shielding layer 400, located between any adjacent source electrode portions 330, can have various orthographic projection shapes onto the substrate 100. In one feasible embodiment, referring to... Figure 1 and Figure 2 As shown, the electric field shielding layer 400 located between any adjacent source electrode portions 330 has a strip shape when projected onto the substrate 100. The strip shape can be understood as a straight line extending along the second direction; for example, the strip shape can be a square or a rectangle.

[0147] In another possible implementation, refer to Figure 8 and Figure 9 As shown, the electric field shielding layer 400 located between any adjacent source electrode portions 330 has a bent shape when projected onto the substrate 100. The bent shape can be sawtooth-shaped, wall-shaped, or other shapes.

[0148] For example, the electric field shielding layer 400 located between any adjacent source electrode portions 330 includes a plurality of shielding extension segments 444 and shielding connection segments 445 in the orthographic projection shape of the substrate 100. Two adjacent shielding extension segments 444 are connected by shielding connection segments 445, and any two adjacent shielding extension segments 444 are spaced out and staggered in a second direction; wherein the second direction and the first direction intersect each other.

[0149] The electric field shielding layers 400 located on both sides of the same gate structure 200 can have the same or different shapes. In one example, the electric field shielding layers 400 located on both sides of the gate structure 200 are centrally symmetrically arranged with respect to the gate structure 200, and their structure is as follows: Figure 8 As shown. In another example, the electric field shielding layers 400 located on both sides of the gate structure 200 are arranged symmetrically with respect to the gate structure 200.

[0150] This enhances the structural symmetry of the entire silicon carbide power device, which not only facilitates the standardization of silicon carbide power devices but also improves the mechanical and thermal stability of the devices.

[0151] In one possible implementation, refer to Figure 2 and Figure 6As shown, each gate structure 200 includes a gate body 230 and a gate protrusion 240. The gate body 230 extends along a first direction, and the gate protrusion 240 protrudes from at least one side of the gate body 230 along a second direction. The first and second directions intersect each other.

[0152] In this embodiment, the first direction can be referred to Figure 1 and Figure 2 As shown in the Y direction, the second direction can be referenced. Figure 1 and Figure 2 As shown in the X direction.

[0153] For example, along the second direction, the gate protrusion 240 may protrude from one side of the gate body 230; or, the gate protrusion 240 may protrude from both sides of the gate body 230, so that a stepped surface is formed between the gate protrusion 240 and the gate body 230. This embodiment does not limit this.

[0154] In this embodiment, the example of gate protrusions 240 protruding from both sides of the gate body 230 is used for illustration. In this example, the two gate protrusions 240 can be arranged opposite to each other relative to the gate body 230; alternatively, the two gate protrusions 240 can be staggered. This embodiment does not limit this arrangement.

[0155] The gate protrusion 240 protrudes from one side of the gate body 230, making the gate structure 200 cross-shaped. Compared with a cylindrical gate structure, this greatly extends the channel area of ​​the silicon carbide power device, thereby increasing the forward conduction path and reducing the forward conduction resistance of the device, resulting in higher output characteristics for the silicon carbide power device.

[0156] In this embodiment, the gate protrusion 240 allows the gate structure 200 to be stepped. Accordingly, when fabricating the gate structure 200 and the electric field shielding layer 400, a gate trench needs to be fabricated first. When the gate structure 200 is stepped, the gate trench can be a multi-level trench.

[0157] When the electric field shielding layer 400 is fabricated using a low-energy ion implantation process, the implanted ions will preferentially contact the step surface of the gate trench, thus allowing implantation of the region surrounding the bottom sidewall of the gate trench and the region surrounding the sidewall of the gate trench.

[0158] In this way, on the one hand, by using a lower-energy ion implantation process to prepare the electric field shielding layer 400, the implantation depth and distribution of ions can be controlled more precisely, ensuring that the required electric field shielding layer 400 is formed in a specific region of the gate trench; on the other hand, a lower-energy ion implantation process can prepare a deep electric field shielding layer 400, thereby simplifying the requirements for ion implantation equipment and reducing manufacturing costs and process complexity.

[0159] In addition, the above method can better connect the electric field shielding layer 400 at the bottom of the gate structure 200 and the electric field shielding layer 400 of the source structure 300 during ion implantation. This can avoid the problem that the electric field shielding layer 400 of the source structure 300 cannot connect with the electric field shielding layer 400 at the bottom of the trench when the implantation depth of the bottom electric field shielding layer 400 is less than the trench depth. This ensures that the electric field shielding layer 400 at the bottom of the trench is in contact with the source structure 300, thereby improving the reliability of silicon carbide power devices.

[0160] It should be noted that the gate structure 200 can be stepped, with two, three, or even more steps. Taking a three-step gate structure 200 as an example, based on the above-mentioned gate structure 200 formation process, the gate trench forming the gate structure 200 can be divided into a first gate trench, a second gate trench, and a third gate trench connected in sequence. Along the thickness direction of the substrate 110, and from top to bottom, the diameters of the first, second, and third gate trenches gradually decrease, so that the gate trench includes two step surfaces, namely the first step surface and the second step surface. In this way, a lower energy ion implantation process can be used to prepare the electric field shielding layer 400. Ions will also be implanted downwards through the first and second step surfaces for doping, so that the formed electric field shielding layer 400 can cover the bottom wall and sidewalls of the third gate trench, the step surface between the third and second gate trenches, the sidewalls of the second gate trench, and a portion of the step surface between the second and first gate trenches. In this way, an ideal electric field shielding layer 400 can be obtained using a lower energy ion implantation process. This can reduce the fabrication difficulty and production cost of silicon carbide power devices, improve the shielding effect of the electric field shielding layer 400, and thus improve the performance of silicon carbide power devices.

[0161] Continue to refer to Figures 3 to 6 As shown, in one possible implementation, the silicon carbide power device further includes a source electrode layer 800, which is disposed on and connected to the source structure 300.

[0162] When the source structure 300 includes a second conductivity type source active region 310 and a first conductivity type source region 320 stacked together, the source electrode layer 800 can be connected to at least one of the second conductivity type source active region 310 and the first conductivity type source region 320 in order to provide an electrical signal to the source structure 300.

[0163] The source electrode layer 800 and the source structure 300 can be directly connected or indirectly connected. For example, the silicon carbide power device also includes a second conductivity type ohmic contact layer 600, through which the source electrode layer 800 and the source structure 300 are connected.

[0164] The doping concentration of the second conductivity type ohmic contact layer 600 is greater than that of the second conductivity type source active region 310. Thus, the second conductivity type ohmic contact layer 600 provides a low-resistance path, reducing the contact resistance between the source electrode layer 800 and the second conductivity type source active region 310, thereby improving the device performance.

[0165] The second conductivity type ohmic contact layer 600 may include multiple layers, which extend along a first direction parallel to the plane of the substrate 100 and are spaced apart along a second direction. Each source portion 330 can be connected to the source electrode layer 800 through one second conductivity type ohmic contact layer 600. In this way, the contact resistance between the first conductivity type source region 320 and the source electrode layer 800 can be minimized, thereby improving the performance of the silicon carbide power device.

[0166] When the electric field shielding layer 400 is indirectly connected to the source structure 300, the electric field shielding layer 400 can be connected to the source structure 300 through the second conductivity type ohmic contact layer 600. For example, the second conductivity type ohmic contact layer 600 is disposed within the electric field shielding layer 400; and the electric field shielding layer 400 is connected to the source structure 300 through the second conductivity type ohmic contact layer 600 and the source electrode layer 800.

[0167] In one feasible implementation, refer to Figures 3 to 6 As shown, the silicon carbide power device also includes an insulating layer 500, which covers the gate structure 200 and the source region 320 of the first conductivity type. This achieves insulation between the gate structure 200 and the source region 320 of the first conductivity type. The insulating layer 500 may include silicon oxide, silicon nitride, aluminum oxide, or other insulating materials. (Refer to...) Figure 7 As shown in the figure, this application provides a method for fabricating a silicon carbide power device, including the following steps:

[0168] Step S100: Provide a substrate.

[0169] Step S200: Form a source structure, which is disposed on a substrate.

[0170] Step S300: An electric field shielding layer and a gate structure are formed in the substrate, the source structure surrounds at least a portion of the side surface of the gate structure, the electric field shielding layer covers at least a portion of the bottom of the cross section of the gate structure, and the electric field shielding layer is connected to the source structure.

[0171] The electric field shielding layer in the silicon carbide power device prepared by this method covers at least part of the bottom of the cross-section of the gate structure. This can maximize the distribution of the electric field of the gate dielectric layer onto the electric field shielding layer, thereby helping to reduce the electric field of the silicon carbide power device in the reverse blocking state, improving the reliability of the gate dielectric layer, avoiding the problem of gate structure failure caused by the breakdown of the gate dielectric layer, thus ensuring the performance and reliability of the gate structure, and further ensuring the performance and reliability of the semiconductor device.

[0172] In one possible implementation, the fabrication method of silicon carbide power devices further includes:

[0173] Steps for providing the substrate:

[0174] Provide substrate;

[0175] An epitaxial layer of a first conductivity type is formed and disposed on a substrate.

[0176] For example, an epitaxial layer 120 of a first conductivity type can be formed on the substrate 110 using an epitaxial process. The conductivity type of the first conductivity type epitaxial layer 120 is the same as that of the substrate 110. For example, both the first conductivity type epitaxial layer 120 and the substrate 110 are N-type. The thickness of the first conductivity type epitaxial layer 120 can be 12 micrometers.

[0177] In one possible implementation, the fabrication method of silicon carbide power devices further includes:

[0178] The steps for forming the source structure include:

[0179] A source structure material layer is formed, which is disposed on the first conductivity type epitaxial layer 120. It should be noted that, depending on the fabrication process of the source structure material layer, the source structure material layer can be disposed on or within the first conductivity type epitaxial layer 120.

[0180] In this embodiment, the source structure 300 includes a second conductivity type source active region 310 and a first conductivity type source region 320 stacked together. Therefore, the source structure material layer also includes two layers, which can be referred to as the second conductivity type source active region material layer and the first conductivity type source region material layer.

[0181] For example, the first conductivity type epitaxial layer 120 is processed using an ion implantation process or an ion doping process to form a second conductivity type source active region material layer of a certain thickness in the first conductivity type epitaxial layer 120; wherein, the conductivity type of the first conductivity type epitaxial layer 120 is different from the conductivity type of the second conductivity type source active region material layer. For example, the conductivity type of the second conductivity type source active region material layer is N-type.

[0182] Subsequently, ion implantation or ion doping is used to implant ions into the second conductivity type source active region material layer to form a first conductivity type source active region material layer of a certain thickness within the second conductivity type source active region material layer. The conductivity type of the first conductivity type source active region material layer differs from that of the second conductivity type source active region material layer; for example, the second conductivity type source active region material layer is N-type, while the first conductivity type source active region material layer is P-type.

[0183] Subsequently, a first mask layer with multiple first mask openings is formed on the source structure material layer. The multiple first mask openings are spaced apart along a second direction, and each first mask opening extends along a first direction. The first mask layer can be a photoresist layer or a hard mask layer. For example, the material of the first mask layer includes silicon oxide, but is not limited to this.

[0184] Subsequently, the source structure material layer and part of the first conductivity type epitaxial layer 120 exposed within the first mask opening are removed by an etching process to form the gate trench 250 (see Appendix). Figure 1 The retained source structure material layer constitutes the source structure 300. It should be noted that the etching process in this embodiment can be dry etching or wet etching; specifically, this embodiment does not impose any limitations.

[0185] It should be noted that the etching process can be performed once or multiple times, depending on the structure of the gate trench. For example, if the gate trench 250 is a single-stage trench, then the gate trench 250 can be formed in a single etching process.

[0186] For example, gate trench 250 is a multi-level trench. In this way, multi-level gate trenches can be formed in the substrate through multiple etching processes; wherein, along the direction pointing to the bottom surface of the substrate, the diameter of the gate trench gradually decreases.

[0187] For example, the gate trench extends along the thickness direction of the substrate 100, and the bottom of the gate trench is located within the first conductivity type epitaxial layer 120. The following description will take the gate trench as a secondary trench as an example.

[0188] For example, a first gate trench can be formed first, which penetrates the second conductivity type source active region 310 and the first conductivity type source region 320 and extends into the first conductivity type epitaxial layer 120; then, the first gate trench is filled with a dielectric layer and the dielectric layer is patterned to form an etching opening; the dielectric layer and the first conductivity type epitaxial layer 120 are removed along the etching opening to form a second gate trench, the axes of the second gate trench and the first gate trench are collinear, and the second gate trench is located at the center of the first gate trench, and the bottom of the second gate trench is lower than the bottom of the first gate trench.

[0189] The remaining dielectric layer is removed to form a gate trench in the first conductivity type epitaxial layer 120. The gate trench includes a first gate trench and a second gate trench connected sequentially in the thickness direction of the substrate 100; and the diameters of the first gate trench and the second gate trench gradually decrease from top to bottom, so as to form a step surface between the first gate trench and the second gate trench.

[0190] After the gate trench 250 is formed, the remaining first mask layer can be removed by a cleaning process.

[0191] In one possible implementation, the steps of forming the electric field shielding layer and the gate structure include:

[0192] A second mask layer is formed, which fills the gate trench and covers the top surface of the source structure. The fabrication process and materials of the second mask layer can be the same as or different from those of the first mask layer.

[0193] Subsequently, the second mask layer is patterned to form a plurality of second mask openings; the plurality of second mask openings are spaced apart along a first direction, and each second mask opening extends along a second direction; that is, the extension direction of the second mask opening is perpendicular to the extension direction of the gate trench 250.

[0194] In this embodiment, the gate trench 250 is exposed by the second mask opening.

[0195] Subsequently, using the second mask layer as a mask, an electric field shielding layer is formed at least on the inner wall of the exposed gate trench through an ion implantation process.

[0196] The remaining second mask layer can then be removed using a cleaning process.

[0197] Finally, a gate structure is formed, which is disposed within the gate trench.

[0198] For example, a gate dielectric layer 220 is formed on the inner wall of the gate trench using a deposition process, wherein the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0199] Subsequently, a gate 210 is formed in the region enclosed by the gate dielectric layer 220, and the gate 210 and the gate dielectric layer 220 constitute a gate structure 200.

[0200] Following the step of forming the gate structure, the fabrication method of silicon carbide power devices further includes:

[0201] A second type of conductive ohmic contact layer is formed, wherein the second type of conductive ohmic contact layer is disposed on the electric field shielding layer 400.

[0202] For example, an insulating layer is formed covering the gate structure and the source structure; wherein the insulating layer 500 is made of silicon oxide, silicon nitride, aluminum oxide or other insulating materials.

[0203] Part of the insulating layer is removed to form an opening in the insulating layer that exposes a portion of the electric field shielding layer. Then, ion doping is performed into the opening through a doping process to form an ohmic contact layer of the second conductivity type.

[0204] Afterward, the insulating layer is backfilled and then patterned to form the source metal contact hole 700; the source metal contact hole 700 extends along the first direction and exposes a portion of the second conductivity type source active region 310.

[0205] The source electrode layer 800 is formed by deposition process to complete the fabrication of trench gate silicon carbide power devices.

[0206] This application also provides a semiconductor device, including the silicon carbide power device described in any of the above embodiments. The power device formed in this embodiment is not limited to devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs); any silicon carbide power device is within the scope of this patent.

[0207] It should be noted that the beneficial effects of the silicon carbide power device provided in this application embodiment are the same as those of the silicon carbide power device provided in the above embodiments, and will not be elaborated further in this embodiment.

[0208] The silicon carbide power devices provided in this application embodiment can be applied to vehicles, for example, to key electric drive and control components such as main drive inverters, converters, on-board chargers (OBC), and on-board charging piles. The vehicles can be electric vehicles, hybrid vehicles, or new energy vehicles.

[0209] Therefore, embodiments of this application provide a silicon carbide power device and its fabrication method, as well as a semiconductor device. An electric field shielding layer covers at least a portion of the bottom surface of the cross-section of the gate structure. This maximizes the distribution of the electric field of the gate dielectric layer onto the electric field shielding layer, thereby helping to reduce the electric field of the silicon carbide power device in the reverse blocking state, improving the reliability of the gate dielectric layer, and avoiding the problem of gate structure failure due to gate dielectric layer breakdown. This ensures the performance and reliability of the gate structure, further guaranteeing the performance and reliability of the semiconductor device. By connecting the electric field shielding layer to the source structure, the reverse bias current in the epitaxial layer is blocked as much as possible at the electric field shielding layer, forming a depletion region. This allows electrons to be depleted as much as possible at the electric field shielding layer, better shielding the electric field of the gate dielectric layer of the silicon carbide power device, thereby preventing gate dielectric layer breakdown and improving the reliability of the silicon carbide power device.

[0210] It should be noted that, in the description of the embodiments of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0211] In the description of the embodiments of this application, the term "and / or" merely indicates a relationship describing the associated objects, meaning that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the term "at least one" indicates any combination of at least two of a plurality of options, for example, including at least one of A, B, and C, which can represent any one or more elements selected from a set including communication between A, B, and C.

[0212] In the description of the embodiments of this application, the terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the term "multiple" means two or more, unless otherwise precisely specified.

[0213] In the description of the embodiments of this application, the terms "first," "second," "third," "fourth," etc. (if present) are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0214] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A silicon carbide power device, characterized in that, include: Base (100); A source structure (300) is disposed on the substrate (100); A gate structure (200) is disposed within the substrate (100), and a source structure (300) surrounds at least a portion of the side surfaces of the gate structure (200); An electric field shielding layer (400) is disposed within the substrate (100), the electric field shielding layer (400) covers the bottom of at least a portion of the cross-section of the gate structure (200), and the electric field shielding layer (400) is connected to the source structure (300).

2. The silicon carbide power device according to claim 1, characterized in that, The electric field shielding layer (400) extends to the bottom surface of the substrate (100) at a depth greater than the depth of the gate structure (200).

3. The silicon carbide power device according to claim 2, characterized in that, Along the thickness direction of the substrate (100), the electric field shielding layer (400) includes at least a first sub-electric field shielding layer (410) and a second sub-electric field shielding layer (420), wherein the first sub-electric field shielding layer (410) and the second sub-electric field shielding layer (420) are respectively disposed on both sides of at least a portion of the cross-section of the gate structure (200); In this process, at least one of the first sub-electric field shielding layer (410) and the second sub-electric field shielding layer (420) is connected to the source structure (300).

4. The silicon carbide power device according to claim 3, characterized in that, The first sub-electric field shielding layer (410) and / or the second sub-electric field shielding layer (420) cover the entire bottom surface of at least a portion of the cross-section of the gate structure (200).

5. The silicon carbide power device according to claim 4, characterized in that, The first sub-electric field shielding layer (410) and the second sub-electric field shielding layer (420) are electrically connected.

6. The silicon carbide power device according to claim 5, characterized in that, The electric field shielding layer (400) further includes a third sub-electric field shielding layer (430), which is disposed on the bottom surface of at least a portion of the cross-section of the gate structure (200).

7. The silicon carbide power device according to claim 6, characterized in that, The third sub-electric field shielding layer (430) is electrically connected to the first sub-electric field shielding layer (410) and / or the second sub-electric field shielding layer (420).

8. The silicon carbide power device according to claim 6, characterized in that, The third sub-electric field shielding layer (430) is disposed on the same cross section of the gate structure (200) as the first sub-electric field shielding layer (410) and the second sub-electric field shielding layer (420).

9. The silicon carbide power device according to any one of claims 1-8, characterized in that, The electric field shielding layer (400) has a protrusion (446) extending toward the bottom surface of the substrate (100); Along a direction perpendicular to the substrate (100), the protrusion (446) is opposite to the gate structure (200).

10. The silicon carbide power device according to claim 9, characterized in that, The protrusion (446) includes a main body (441) and an extension (442); Along a direction perpendicular to the substrate (100), the main body (441) is opposite to the gate structure (200), and the main body (441) covers the bottom surface of the gate structure (200); The extension (442) is connected to the side of the main body (441) and extends toward the source structure (300); wherein the extension (442) also covers at least a portion of the side of the gate structure (200) and is connected to the source structure (300).

11. The silicon carbide power device according to claim 10, characterized in that, The number of the extensions (442) includes two, and the two extensions (442) are located on opposite sides of the main body (441).

12. The silicon carbide power device according to claim 11, characterized in that, In the same main body (441), two extensions (442) are arranged opposite each other, parallel to the plane of the base (100) and along the second direction; or, in the same main body (441), two extensions (442) are staggered relative to each other, parallel to the plane of the base (100) and along the second direction.

13. The silicon carbide power device according to any one of claims 10-12, characterized in that, On a plane parallel to the substrate (100), the gate structure (200) is strip-shaped and extends along a first direction; The source structure (300) includes a plurality of source portions (330), which are spaced apart along the first direction, and each source portion (330) surrounds a portion of the side surface of the gate structure (200); An electric field shielding layer (400) covering the side of the gate structure (200) extends along the bottom surface away from the substrate (100) and extends between adjacent source portions (330).

14. The silicon carbide power device according to claim 13, characterized in that, The electric field shielding layer (400) located between adjacent source portions (330) is connected to at least one of the two adjacent source portions (330).

15. The silicon carbide power device according to claim 14, characterized in that, The electric field shielding layer (400) located between any adjacent source electrode portions (330) has a strip shape in the orthographic projection onto the substrate (100).

16. The silicon carbide power device according to claim 14, characterized in that, The electric field shielding layer (400) located between any adjacent source electrode portions (330) has a bent shape in the orthographic projection of the substrate (100).

17. The silicon carbide power device according to claim 16, characterized in that, The electric field shielding layer (400) located between any two adjacent source poles (330) includes a plurality of shielding extension segments (444) and shielding connection segments (445) in the orthographic projection shape of the substrate (100). Two adjacent shielding extension segments (444) are connected by the shielding connection segments (445), and any two adjacent shielding extension segments (444) are staggered in the second direction. The second direction and the first direction intersect each other.

18. The silicon carbide power device according to claim 17, characterized in that, The electric field shielding layers (400) located on both sides of the gate structure (200) are arranged in a centrally symmetrical manner with respect to the gate structure (200); Alternatively, the electric field shielding layer (400) located on both sides of the gate structure (200) is arranged symmetrically with respect to the gate structure (200).

19. The silicon carbide power device according to any one of claims 14-18, characterized in that, The gate structure (200) includes a plurality of gate structures (200), which are spaced apart along a second direction; The electric field shielding layer (400) covers at least a portion of the cross-section of the entire gate structure (200).

20. The silicon carbide power device according to claim 19, characterized in that, Each of the gate structures (200) includes a gate body (230) and a gate protrusion (240), the gate body (230) extending along the first direction and the gate protrusion (240) protruding at least one side of the gate body (230) along the second direction.

21. The silicon carbide power device according to any one of claims 1-8, characterized in that, The source structure (300) includes a second conductivity type source active region (310) and a first conductivity type source region (320); Along the thickness direction of the substrate (100), the second conductivity type source active region (310) is disposed on the substrate (100), and the first conductivity type source region (320) is disposed on the second conductivity type source active region (310).

22. The silicon carbide power device according to any one of claims 1-8, characterized in that, The silicon carbide power device further includes a source electrode layer (800), which is disposed on the source structure (300) and connected to the source structure (300).

23. The silicon carbide power device according to claim 22, characterized in that, The silicon carbide power device further includes a second conductivity type ohmic contact layer (600), and the source electrode layer (800) and the source structure (300) are connected through the second conductivity type ohmic contact layer (600).

24. The silicon carbide power device according to claim 23, characterized in that, The second type of conductive ohmic contact layer (600) is disposed within the electric field shielding layer (400); The electric field shielding layer (400) is connected to the source structure (300) through the second conductivity type ohmic contact layer (600) and the source electrode layer (800).

25. The silicon carbide power device according to any one of claims 1-8, characterized in that, The substrate (100) includes a substrate (110) and a first conductivity type epitaxial layer (120), the first conductivity type epitaxial layer (120) being disposed on the substrate (110).

26. The silicon carbide power device according to any one of claims 1-8, characterized in that, The gate structure (200) includes a gate (210) and a gate dielectric layer (220), the gate dielectric layer (220) covering the bottom and side surfaces of the gate (210).

27. A method for fabricating a silicon carbide power device, characterized in that, include: Provide a base; A source structure is formed, wherein the source structure is disposed on the substrate; An electric field shielding layer and a gate structure are formed within the substrate, the source structure surrounds at least a portion of the side surface of the gate structure, the electric field shielding layer covers at least a portion of the bottom cross-section of the gate structure, and the electric field shielding layer is connected to the source structure.

28. The method for fabricating a silicon carbide power device according to claim 27, characterized in that, The steps for forming the source structure include: A source electrode structure material layer is formed, wherein the source electrode structure material layer is disposed on the substrate; A first mask layer having a plurality of first mask openings is formed on the source structure material layer, the plurality of first mask openings being arranged at intervals along a second direction, and each first mask opening extending along a first direction; wherein the first direction and the second direction intersect each other; The source structure material layer and part of the substrate exposed in the first mask opening are removed to form a gate trench; wherein the remaining source structure material layer constitutes the source structure; Remove the first mask layer.

29. The method for fabricating a silicon carbide power device according to claim 28, characterized in that, The steps of forming the electric field shielding layer and the gate structure include: A second mask layer is formed, which fills the gate trench and covers the top surface of the source structure; The second mask layer is patterned to form a plurality of second mask openings; the plurality of second mask openings are spaced apart along the first direction, and each second mask opening extends along the second direction; wherein the second mask opening exposes a portion of the gate trench; Using the second mask layer as a mask, an electric field shielding layer is formed at least on the inner wall of the exposed gate trench through an ion implantation process; Remove the second mask layer; A gate structure is formed, wherein the gate structure is disposed within the gate trench.

30. The method for fabricating a silicon carbide power device according to claim 29, characterized in that, The step of forming the gate trench includes: Through multiple etching processes, multi-level gate trenches are formed in the substrate; wherein, along the direction pointing to the bottom surface of the substrate, the diameter of the gate trenches gradually decreases.

31. The method for fabricating a silicon carbide power device according to claim 30, characterized in that, The step of providing the substrate includes: Provide substrate; An epitaxial layer of a first conductivity type is formed, and the first conductivity type epitaxial layer is disposed on the substrate.

32. A semiconductor device, characterized in that, Includes the silicon carbide power device according to any one of claims 1-26.

Images