Patterning process for improving climbing coverage of metal electrode of semiconductor device
By employing LOR photoresist and oxygen plasma Descum processes in semiconductor device manufacturing, controllable undercut morphologies are formed, solving the problems of poor metal electrode coverage and inaccurate morphology transfer. This achieves stable metal electrode coverage and improved device performance, meeting the demands for miniaturization and high frequency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUJIAN FULIAN INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2026-01-23
- Publication Date
- 2026-04-24
AI Technical Summary
In the semiconductor device manufacturing process, poor metal electrode coverage makes it prone to cracks, the process is complex and the morphology transfer is inaccurate, which limits the device performance and integration, and cannot meet the requirements of miniaturization and high frequency.
By employing LOR photoresist and oxygen plasma descum technology, a controllable undercut morphology is formed, and the PI layer is etched to create an optimized step structure, simplifying the photolithography process, avoiding defocusing techniques, and achieving stable coverage of the metal electrode.
It significantly improves the coverage and interconnect reliability of metal electrodes, simplifies the process flow, increases production yield and device performance, and breaks through the limitations of integration and high-frequency performance.
Smart Images
Figure CN121924809A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically to a patterning process for improving the ramp coverage of metal electrodes in semiconductor devices. Background Technology
[0002] In the fabrication of gallium arsenide (GaAs) semiconductor devices, especially high-performance radio frequency devices such as pHEMTs, it is often necessary to form multilayer metal electrode interconnect structures. To achieve insulation, passivation, or reduction of parasitic capacitance between electrodes, polyimide (PI) is commonly used as the interlayer dielectric.
[0003] A typical existing manufacturing process is as follows: First, a first metal electrode is fabricated on a substrate. Then, a layer of polyimide (PI) is coated and cured on the entire wafer surface. Next, a first photoresist layer is coated on the PI layer. The window area for exposing the first metal electrode is defined by a first photolithography process. After development, a descum process is performed, typically using oxygen plasma to etch away the residual PI film at the bottom of the window, completely exposing the contact surface of the first metal electrode. Then, the first photoresist layer is removed. Afterward, a second photoresist layer is coated on the PI layer and a second photolithography process is performed to define the interconnect window and the body pattern of the second metal electrode. The second metal electrode is deposited by vapor deposition or sputtering. Finally, the second photoresist layer and the metal on it are removed by a lift-off process, completing the patterning of the second metal electrode and realizing the electrical connection between the second metal electrode and the first metal electrode.
[0004] However, existing technologies have the following drawbacks:
[0005] Poor metal coverage can easily lead to cracks: The steep sidewalls of the PI window formed by the first photolithography and Descum process are close to 90 degrees. During the second metal electrode deposition, the insufficient coverage at the step corners leads to excessive thinning, breakage, and cracking of the metal film, which increases interconnect resistance, affects the long-term reliability of the device, and is prone to causing open circuit failure.
[0006] The process is complex and relies on the difficult-to-control Defocus technology: To improve the above problems, the existing process uses Defocus optical technology to try to make the sidewalls of the photoresist pattern sloped. However, this method has a narrow process window, poor controllability, and is affected by many factors such as the performance of the lithography machine and the exposure dose, resulting in poor repeatability and consistency. Excessive Defocus can easily lead to defects such as the critical dimension CD deviating from the design value and incomplete pattern development, reducing the production yield. At the same time, a lot of time and cost are required for process parameter debugging and optimization, increasing the process development cost.
[0007] Inaccurate morphology transfer: The slope formed on the photoresist layer by the Defocus technology cannot be transferred to the PI layer with high fidelity and accuracy after subsequent Descum oxygen plasma etching because the etching selectivity ratio of polyimide (PI) to photoresist is not infinite and the isotropic etching characteristics will cause morphology distortion. As a result, the slope morphology of the photoresist cannot be transferred to the PI layer with high fidelity and accuracy. In the end, the sidewall morphology of the PI layer is not ideal.
[0008] Limitations on device performance and miniaturization: Metal cracks and high interconnect resistance issues force designers to increase the interconnect window area or adopt conservative designs, which restricts the improvement of device integration and the optimization of radio frequency performance, and fails to meet the development requirements of miniaturization, high frequency and high reliability of semiconductor devices. Summary of the Invention
[0009] To address the problems of poor metal coverage, easy cracking, complex processes, inaccurate morphology transfer, and limited device performance in the existing semiconductor device metal electrode manufacturing process, this invention provides a patterned process to improve the ramp-up coverage of semiconductor device metal electrodes, thereby optimizing the sidewall morphology of the PI window, improving metal electrode coverage, simplifying the process, and enhancing device performance and integration.
[0010] The technical solution of the present invention is as follows:
[0011] A patterning process for improving the ramp coverage of metal electrodes in semiconductor devices includes the following steps:
[0012] Step 1: Coat the PI layer on the first metal electrode with LOR photoresist and perform soft baking;
[0013] Step 2: Coat the first photoresist layer on the LOR photoresist, and perform soft baking, exposure and development in sequence to form a photolithographic pattern structure. The unexposed area of the LOR photoresist dissolves to form an undercut morphology.
[0014] Step 3: Use the oxygen plasma Descum process to etch the PI layer until the first photoresist layer is completely removed, opening the window from the PI layer to the first metal electrode;
[0015] Step 4: Continue etching the PI layer using the oxygen plasma Descum process until the LOR photoresist is completely removed, forming a PI step, and then remove the remaining photoresist;
[0016] Step 5: Coat the second photoresist layer on the PI layer and perform photolithography to deposit the second metal electrode. Complete the patterning of the second metal electrode through a lift-off process to achieve electrical connection between the second metal electrode and the first metal electrode.
[0017] Preferably, in step 1, the LOR photoresist coating is performed using a spin coater or a spin coater with the following parameters: low-speed spreading 500-1000 rpm for 5-10 seconds; high-speed spinning 1500-3500 rpm for 30-60 seconds; and the soft drying equipment is a hot plate with a temperature of 150-200℃ and a time of 60-120 seconds.
[0018] Preferably, in step 2, the material of the first photoresist layer is AZ1505 photoresist or AZ5214 photoresist, and the coating equipment is a spin coater or a spin coater with the following parameters: low speed spreading 500-1000 rpm for 5-10 seconds; high speed spinning 3000-5000 rpm for 30-45 seconds.
[0019] The softening equipment is a hot plate with a temperature of 95-110℃ and a time of 60-90 seconds;
[0020] The exposure equipment is a contact or proximity lithography machine or a stepper lithography machine, with a light source wavelength of 365nm and an exposure energy of 150mJ / cm². 2 ;
[0021] The developing equipment is a developing machine, the developing solution is a 0.26N tetramethylammonium hydroxide solution, the developing time is 60 seconds, and the developing temperature is 22±2℃.
[0022] Preferably, the etching equipment in steps 3 and 4 is a reactive ion etching machine, and the etching parameters are: gas O2 of 50-100 sccm, power of 100-200W, pressure of 100-200mTorr, and total etching time of 600 seconds; the etching rate ratio of oxygen plasma to PI and LOR photoresist is set to 1.
[0023] Preferably, in step 4, the removal of residual photoresist is carried out by: using a wet method to remove the adhesive, soaking in a pure NMP solution at 60-80℃ for 10-30 minutes, performing low-power intermittent ultrasound at 40-60℃, rinsing with acetone and isopropanol sequentially for 2-3 minutes, and drying with high-purity nitrogen; the ultrasound power is 100-150W, and the ultrasound mode is 10 seconds of ultrasound followed by a 20-second pause.
[0024] Preferably, in step 5, the second metal electrode is Ti / Pt / Au, and half of its total thickness is greater than the thickness of the PI layer, with the thickness of the PI layer being 1.5-2.5 μm.
[0025] Preferably, in step 3, the thickness of the first photoresist layer is equal to the thickness of the PI layer.
[0026] Preferably, in step 4, the thickness of the LOR photoresist is equal to 1 / 2 the thickness of the PI layer.
[0027] Preferably, the semiconductor device is a gallium arsenide semiconductor device, including a pHEMT high-performance radio frequency device.
[0028] Preferably, the PI layer can be replaced with a PBO layer or a BCB layer.
[0029] Compared with the prior art, the present invention has the following beneficial effects:
[0030] 1. Eliminates metal cracks, significantly improving interconnect reliability and electrical performance:
[0031] By using processes such as LOR (Lead-of-Row) to form a controllable undercut structure, the mask function is achieved, significantly reducing the ramp height of the second metal electrode. This eliminates the need for the second metal electrode to cover steep sidewalls when climbing over PI steps after metallization. This fundamentally avoids excessive thinning, fracture, and cracking of the metal film at step corners. The result is:
[0032] Significantly reduces interconnect resistance, improving device RF performance and current transport capability.
[0033] It fundamentally improves the long-term reliability of devices and eliminates the risk of circuit open-circuit failure caused by metal cracks under current stress and thermal stress.
[0034] 2. Simplify the process flow and improve process controllability and repeatability:
[0035] This invention abandons the difficult-to-control Defocus technique and adopts a more direct and stable method, such as normal photoresist patterning, to define the PI window morphology. This brings the following benefits:
[0036] Wider process window: The sensitivity of process results to exposure equipment parameters is greatly reduced.
[0037] Excellent repeatability and consistency: process fluctuations within and between batches are significantly reduced, and production yield is effectively guaranteed.
[0038] Reduced process development and debugging costs: No need for complex and time-consuming Defocus parameter optimization, shortening the R&D cycle and production preparation time.
[0039] 3. Overcoming limitations in device performance and integration:
[0040] By eliminating metal cracks and reducing interconnect resistance, designers can employ smaller interconnect windows and more aggressive design rules. This directly leads to:
[0041] Increasing device integration helps achieve device miniaturization and higher-density interconnects.
[0042] Optimized high-frequency performance: Smaller interconnect windows and lower contact resistance help reduce parasitic capacitance and resistance, thereby improving the device's cutoff frequency and maximum oscillation frequency.
[0043] Enhanced design flexibility: Opens up new possibilities for the design of high-performance, high-reliability gallium arsenide RF devices.
[0044] 4. Avoid pattern defects and further improve production yield:
[0045] By eliminating the defocus step, defects such as incomplete pattern development ("not developed") caused by excessive defocusing are completely avoided, making the pattern definition on the wafer surface clearer and more accurate, thereby improving the overall manufacturing yield of the final product. Attached Figure Description
[0046] Figure 1 This is a schematic diagram of the LOR photoresist and the first photoresist layer after coating in an embodiment of the present invention;
[0047] Figure 2 This is a schematic diagram of the first photoresist layer after photolithography patterning in an embodiment of the present invention;
[0048] Figure 3 This is a schematic diagram of the overall structure after step 3.
[0049] Figure 4 This is a schematic diagram of the overall structure after step 4.
[0050] Figure 5 A schematic diagram of the overall structure after the second photoresist layer is coated and the second photolithography is performed;
[0051] Figure 6 This is a graphical representation of the overall structure.
[0052] Figure 7 This is a schematic diagram of a multilayer metal electrode interconnect structure in the prior art;
[0053] In the figure: 1-first metal electrode, 2-PI layer, 3-LOR photoresist, 4-first photoresist layer, 5-second metal electrode, 6-second photoresist layer. Detailed Implementation
[0054] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.
[0055] See Figure 1-6 A patterning process for improving the ramp coverage of metal electrodes in semiconductor devices includes the following steps:
[0056] Step 1: Coat LOR photoresist 3 onto the PI layer 2 on the first metal electrode 1 and perform soft baking;
[0057] Step 2: Coat the first photoresist layer 4 on the LOR photoresist 3, and perform soft baking, exposure and development in sequence to form a photolithographic pattern structure. The unexposed area of the LOR photoresist 3 dissolves to form an undercut morphology.
[0058] Step 3: Use the oxygen plasma Descum process to etch the PI layer 2 until the first photoresist layer 4 is completely removed, opening the window from the PI layer 2 to the first metal electrode 1;
[0059] Step 4: Continue etching the PI layer 2 using the oxygen plasma Descum process until the LOR photoresist 3 is completely removed, forming a PI step, and then remove the remaining photoresist;
[0060] Step 5: Coat the second photoresist layer 6 on the PI layer 2 and perform photolithography to deposit the second metal electrode 5. Complete the patterning of the second metal electrode 5 through a lift-off process to achieve electrical connection between the second metal electrode 5 and the first metal electrode 1.
[0061] In one embodiment of the present invention, during production, the PI thickness on the first electrode is a, in μm; all subsequent thicknesses are in μm.
[0062] The PI photoresist can be replaced with a PBO photoresist or a BCB photoresist, with the same process as in the embodiment.
[0063] a. Coat a LOR photoresist 3 with a thickness of b on the PI layer 2;
[0064] LOR photoresist 3 coating is applied using a spin coater or spin coater with the following parameters: low-speed spread 500-1000 rpm for 5-10 seconds; high-speed spread 1500-3500 rpm for 30-60 seconds; and hot plate drying at 150-200℃ for 60-120 seconds.
[0065] LOR stands for Lift-Off Resist. Unlike standard photoresist, the unexposed areas of LOR photoresist 3 exhibit a relatively fast and stable dissolution rate in the developer. However, the dissolution rate of the exposed areas becomes extremely fast.
[0066] b. Then coat the first photoresist layer 4 with a thickness of c, as shown. Figure 1 The first photoresist is patterned using photolithography, as follows: Figure 2 In particular, in this embodiment, the photoresist exposure no longer uses defocus technology, so the photoresist sidewalls are not very slanted, which is a major difference from the background technology.
[0067] Unexposed areas of LOR will also dissolve, forming an undercut shape;
[0068] The material of the first photoresist layer 4 is AZ1505 photoresist or AZ5214 photoresist;
[0069] The coating equipment is a spin coater or a spin coater, with the following parameters: low-speed spread 500-1000 rpm for 5-10 seconds;
[0070] Spread the coating at high speed (3000-5000 rpm) for 30-45 seconds.
[0071] The softening equipment is a hot plate, with a temperature of 95-110℃ and a time of 60-90 seconds;
[0072] The exposure equipment is a contact or proximity lithography machine or a stepper lithography machine, with a light source wavelength of 365nm and an exposure energy of 150mJ / cm². 2 ;
[0073] The developing equipment is a developing machine, the developing solution is a 0.26N tetramethylammonium hydroxide solution, the developing time is 60 seconds, and the developing temperature is 22±2℃.
[0074] c. Etch PI using the Descum process (usually using oxygen plasma). In this embodiment, the etching rate of oxygen plasma on PI layer 2 is equal to the etching rate of photoresist, and under this premise, the thickness a of PI layer 2 is set to be equal to the thickness c of the first photoresist layer 4.
[0075] When the thickness of the first photoresist layer 4 on the first electrode is etched away, the window from the PI layer 2 to the first metal electrode 1 opens, such as... Figure 3 ;
[0076] The etching equipment is a reactive ion etching machine, and the etching parameters are: gas O2 of 50-100 sccm, power of 100-200W, pressure of 100-200mTorr, and total etching time of 600 seconds; the etching rate ratio of oxygen plasma to PI and LOR photoresist 3 is set to 1.
[0077] d. Continue etching PI layer 2 using the Descum process (usually using oxygen plasma). In this embodiment, the etching rate of PI layer 2 by oxygen plasma is 1, and the etching rate of LOR photoresist 3 is 1. Under this premise, the thickness of LOR photoresist 3 is set to b = 1 / 2 * a (thickness of PI layer 2); the etching parameters are the same as above.
[0078] Completely etch the LOR photoresist 3 on the first electrode, and etch the thickness b into the PI step height;
[0079] The subsequent photoresist removal process involves removing the low-point LOR photoresist 3 and the first photoresist layer 4. Specifically, the sample is immersed in pure NMP solution at 60-80℃ for 10-30 minutes.
[0080] 2. Low-power intermittent ultrasound at 40-60℃ (10 seconds of ultrasound followed by a 20-second pause); ultrasound power 100-150W;
[0081] 3. Immerse the wafer in fresh acetone and isopropanol for 2-3 minutes each to replace and remove residual NMP and dissolved organic matter;
[0082] 4. Dry with high-purity nitrogen gas.
[0083] Final structure as follows Figure 4 As shown.
[0084] e. Then, the second electrode layer is fabricated. A second photoresist layer 6 is coated again on the PI layer 2, and a second photolithography is performed. Next, a second metal electrode 5 is deposited by evaporation or sputtering. The second metal electrode 5 can be made of Ti / Pt / Au, and half of the total thickness of the second metal electrode 5 is greater than the thickness of the PI layer 2. The thickness of the PI layer 2 is 1.5-2.5 μm. Figure 5 As shown.
[0085] Finally, the second photoresist layer 6 and its metal are removed by a stripping process, completing the patterning of the second metal electrode 5, and enabling the second metal electrode 5 to be electrically connected to the first metal electrode 1 through an interconnect window, such as... Figure 6 ;
[0086] In a preferred embodiment of the present invention, a = 2 μm, b = 1 μm, c = 2 μm. This combination is achieved by combining the etching selectivity of the oxygen plasma on the first photoresist layer and the PI layer with a value of 1, and the etching selectivity ratio of the oxygen plasma on the PI layer and the LOR photoresist 3 with a value of 1, which can form the morphology shown in the schematic diagram.
[0087] Furthermore, in this invention, the standardized definitions of terms are as follows:
[0088] Polyimide (PI) represents polyimide;
[0089] Polybenzoxazole (PBO) represents polybenzoxazole;
[0090] Benzocyclobutene (BCB) represents benzocyclobutene;
[0091] Critical Dimension (CD) indicates the critical dimension;
[0092] Pseudomorphic High Electron Mobility Transistor (pHEMT) represents a pseudomorphic high electron mobility transistor;
[0093] Lift-Off Resist (LOR) indicates the removal of photoresist;
[0094] Lift-Off refers to the peeling method.
[0095] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A patterning process for improving the ramp coverage of metal electrodes in semiconductor devices, characterized in that, Includes the following steps: Step 1: Coat the PI layer on the first metal electrode with LOR photoresist and perform soft baking; Step 2: Coat the first photoresist layer on the LOR photoresist, and perform soft baking, exposure and development in sequence to form a photolithographic pattern structure. The unexposed area of the LOR photoresist dissolves to form an undercut morphology. Step 3: Use the oxygen plasma Descum process to etch the PI layer until the first photoresist layer is completely removed, opening the window from the PI layer to the first metal electrode; Step 4: Continue etching the PI layer using the oxygen plasma Descum process until the LOR photoresist is completely removed, forming a PI step, and then remove the remaining photoresist; Step 5: Coat the second photoresist layer on the PI layer and perform photolithography to deposit the second metal electrode. Complete the patterning of the second metal electrode through a lift-off process to achieve electrical connection between the second metal electrode and the first metal electrode.
2. The patterning process for improving the ramp-up coverage of metal electrodes in semiconductor devices according to claim 1, characterized in that, In step 1, LOR photoresist coating is performed using a spin coater or spin coater with the following parameters: low-speed spread 500-1000 rpm for 5-10 seconds; high-speed spin coat 1500-3500 rpm for 30-60 seconds; and the soft drying equipment is a hot plate at a temperature of 150-200℃ for 60-120 seconds.
3. The patterning process for improving the ramp-up coverage of metal electrodes in semiconductor devices according to claim 1, characterized in that, In step 2, the material of the first photoresist layer is AZ1505 photoresist or AZ5214 photoresist, and the coating equipment is a spin coater or a spin coater with the following parameters: low speed spreading 500-1000 rpm for 5-10 seconds; high speed spinning 3000-5000 rpm for 30-45 seconds. The softening equipment is a hot plate with a temperature of 95-110℃ and a time of 60-90 seconds; The exposure equipment is a contact or proximity lithography machine or a stepper lithography machine, with a light source wavelength of 365nm and an exposure energy of 150mJ / cm². 2 ; The developing equipment is a developing machine, the developing solution is a 0.26N tetramethylammonium hydroxide solution, the developing time is 60 seconds, and the developing temperature is 22±2℃.
4. The patterning process for improving the ramp-up coverage of metal electrodes in semiconductor devices according to claim 1, characterized in that, In steps 3 and 4, the etching equipment is a reactive ion etching machine, and the etching parameters are: gas O2 of 50-100 sccm, power of 100-200W, pressure of 100-200mTorr, and total etching time of 600 seconds; the etching rate ratio of oxygen plasma to PI and LOR photoresist is set to 1.
5. The patterning process for improving the ramp coverage of metal electrodes in semiconductor devices according to claim 1, characterized in that, In step 4, the remaining photoresist is removed by a wet method, soaking in a pure NMP solution at 60-80℃ for 10-30 minutes, followed by low-power intermittent ultrasound at 40-60℃, rinsing with acetone and isopropanol for 2-3 minutes in sequence, and drying with high-purity nitrogen. The ultrasound power is 100-150W, and the ultrasound mode is 10 seconds of ultrasound followed by a 20-second pause.
6. The patterning process for improving the ramp-up coverage of metal electrodes in semiconductor devices according to claim 1, characterized in that, In step 5, the second metal electrode is Ti / Pt / Au, and half of its total thickness is greater than the thickness of the PI layer, which is 1.5-2.5 μm thick.
7. The patterning process for improving the ramp coverage of metal electrodes in semiconductor devices according to claim 1, characterized in that, In step 3, the thickness of the first photoresist layer is equal to the thickness of the PI layer.
8. The patterning process for improving the ramp-up coverage of metal electrodes in semiconductor devices according to claim 1, characterized in that, In step 4, the thickness of the LOR photoresist is equal to 1 / 2 the thickness of the PI layer.
9. The patterning process for improving the ramp coverage of metal electrodes in semiconductor devices according to claim 1, characterized in that, The semiconductor device is a gallium arsenide semiconductor device, including a pHEMT high-performance radio frequency device.
10. The patterning process for improving the ramp coverage of metal electrodes in semiconductor devices according to claim 1, characterized in that, The PI layer can be replaced with a PBO layer or a BCB layer.