TVS device based on LDPMOS and Trench NMOS processes and preparation method thereof

Abstract

The invention discloses a TVS (Transient Voltage Suppressor) device based on LDPMOS (Layered Doped P-channel Metal Oxide Semiconductor) and Trench NMOS (N-channel Metal Oxide Semiconductor) processes and a preparation method thereof, which belong to the technical field of semiconductor devices, and are characterized in that the LDPMOS, the Trench NMOS and the TVS are synchronously integrated on the same chip by improving and fusing the LDPMOS and Trench NMOS processes, and a cascade trigger protection circuit is formed by utilizing specific interconnection. According to the TVS device, the extremely low unit area dynamic resistance of the Trench NMOS is used as a main discharge channel of electrostatic discharge current, compared with a traditional TVS device, the clamping coefficient can be reduced to 1.1 or below, compared with an SCR structure TVS, the latch risk of the SCR structure is avoided, and the electrostatic protection capacity and reliability of the device are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a TVS device based on LDPMOS and Trench NMOS processes and its fabrication method. Background Technology

[0002] Transient voltage suppressors (TVS) are key devices widely used for electrostatic discharge (ESD) protection at integrated circuit ports. Traditional TVS devices mainly employ a planar PN junction diode structure. This traditional structure has the following drawbacks: First, its dynamic resistance is relatively high, leading to a significant increase in clamping voltage (Vclamp) under high-current ESD events. The clamping factor (defined as the ratio of clamping voltage to operating voltage) is generally between 1.2 and 1.4, making it difficult to effectively protect the circuit. Second, its junction capacitance is relatively large, which can affect the integrity of high-speed signal lines.

[0003] To reduce the clamping factor, TVS devices using a silicon controlled rectifier (SCR) structure have been proposed. While SCR-structured TVS devices can achieve lower dynamic resistance and clamping voltage, they introduce new problems: the trigger voltage is typically high, and they are prone to latch-up. Once latch-up occurs, even if the external ESD pulse disappears, the device will remain in a low-resistance conducting state, leading to abnormal power supply to the protected circuit or even burnout. The ESD design window (the safe range between the operating voltage and the device breakdown voltage / trigger voltage) is difficult to optimize. Therefore, existing TVS devices cannot effectively reduce the clamping factor without affecting other performance characteristics (low trigger voltage, no latch-up risk, etc.). Summary of the Invention

[0004] The purpose of this invention is to overcome the problems of the prior art and to provide TVS devices based on LDPMOS and Trench NMOS processes and their fabrication methods.

[0005] The objective of this invention is achieved through the following technical solution: a TVS device based on LDPMOS and Trench NMOS processes, the method comprising the following steps: S1: Grow an epitaxial layer of the first conductivity type on a heavily doped substrate of the first conductivity type; S2: A field oxygen layer is formed on the surface of the epitaxial layer; S3: In the LDPMOS region, the field oxide layer is selectively etched, and heavy doped ions of the first conductivity type are implanted and diffused to form a deep body region that penetrates the epitaxial layer. At the same time, a first oxide layer is generated on the surface of the deep body region. S4: In the LDPMOS region, the field oxide layer is selectively etched, and in the Trench NMOS region and TVS region, the field oxide layer is etched. At the same time, second conductivity type ions are implanted and diffused to form a first well region extending to the epitaxial layer. Meanwhile, a second oxide layer is grown on the surface of the first well region. S5: In the LDPMOS region, the field oxide layer is etched, and ions of the first conductivity type are implanted and diffused to form a second well region extending to the epitaxial layer. At the same time, a third oxide layer is generated on the surface of the second well region. S6: In the Trench NMOS region and TVS region, the second oxide layer is selectively etched, and heavy doped ions of the first conductivity type are implanted and diffused to form a first implantation region extending to the first well region. At the same time, a fourth oxide layer is grown on the surface of the first implantation region. S7: Remove the surface oxide layer in all regions and grow a fifth oxide layer on the surface of all regions; selectively etch the fifth oxide layer in the TrenchNMOS region and the gate resistor region and extend it to the outer extension layer to form a first trench; S8: A sixth oxide layer is formed on the surface of the first trench, and polysilicon is deposited and etched. A first polysilicon layer is formed on the sixth oxide layer in the first trench to obtain the gate of Trench NMOS, the gate resistor of Trench NMOS and the gate resistor of LDPMOS. S9: A seventh oxide layer is generated on the surface of all regions. In the LDPMOS region, the fifth oxide layer and the seventh oxide layer are selectively etched to form a second trench. An eighth oxide layer is formed on the surface of the second trench. S10: In the LDPMOS region, polysilicon is deposited and etched on the surface of the eighth oxide layer in the second trench to form a second polysilicon layer on the eighth oxide layer in the second trench, thereby obtaining the gate of the LDPMOS. S11: A ninth oxide layer is generated on the surface of all regions. In the LDPMOS region, Trench NMOS region and TVS region, the ninth oxide layer, the seventh oxide layer and the fifth oxide layer are selectively etched. Heavy doped ion implantation of the second conductivity type is performed to form a second implantation region extending to the first well region and the second well region. At the same time, a tenth oxide layer is formed on the surface of the second implantation region. S12: Selectively etch the fifth, seventh, ninth, and tenth oxide layers to form contact holes on the epitaxial layer; S13: Deposit a metal layer in the contact hole and etch it by photolithography to form the source, gate, and drain of LDPMOS, the anode and cathode of TVS, and the source, gate, and drain of Trench NMOS; Connect the drain of the LDPMOS to the gate resistor and gate of the Trench NMOS. Connect the cathode of the TVS to the gate resistor and gate of the LDPMOS. Connect the gate resistor of the LDPMOS to the source and drain of the LDPMOS. Connect the anode of the TVS to the source and gate resistor of the Trench NMOS.

[0006] In one example, before forming the sixth oxide layer in step S8, the method further includes: forming a first sacrificial oxide layer in the first trench and etching the first sacrificial oxide layer; Before forming the eighth oxide layer in step S9, the method further includes: forming a second sacrificial oxide layer in the second trench and etching away the second sacrificial oxide layer.

[0007] In one example, in step S12, a contact hole is formed on the epitaxial layer, thereby exposing the deep body region and a portion of the second injection region located on both sides of the deep body region in the LDPMOS region, exposing the second injection region and a portion of the first injection region located on both sides of the second injection region in the Trench NMOS region, and exposing the first injection region and the second injection region in the TVS region.

[0008] In one example, in step S13, in the LDPMOS region, the deep body region, the middle portion of the second injection region, and a portion of the ninth oxide layer are the source contact regions of the LDPMOS, and the edge portion of the second injection region and a portion of the ninth oxide layer are the drain contact regions of the LDPMOS; in the Trench NMOS region, the second injection region, the middle portion of the first injection region, and the ninth oxide layer are the source contact regions of the Trench NMOS, and the drain of the Trench NMOS is led out from the substrate; in the TVS region, the first injection region and a portion of the ninth oxide layer are the cathode contact regions of the TVS, and the second injection region and a portion of the ninth oxide layer are the anode contact regions of the TVS.

[0009] In one example, in step S13, an interconnect metal layer is formed using a metal interconnect process.

[0010] It should be further noted that the technical features corresponding to the above examples can be combined or replaced to form new technical solutions.

[0011] The present invention also includes a TVS device based on LDPMOS and Trench NMOS processes, fabricated using the method described above based on any one or more of the above examples, comprising: LDPMOS, Trench NMOS and TVS are integrated on the same semiconductor chip; The LDPMOS region, Trench NMOS region and TVS region share a heavily doped substrate with a first conductivity type and an epitaxial layer with a first conductivity type located on the substrate. The deep body region located in the LDPMOS region and penetrating the epitaxial layer; The first well region of the second conductivity type is located in the epitaxial layer of the LDPMOS region, Trench NMOS region, and TVS region. The second well region of the first conductivity type is located in the epitaxial layer of the LDPMOS region; The first implantation region of the first conductivity type is located in the first well region of the Trench NMOS region and the TVS region; The second doped second implantation region of the second conductivity type is located in the LDPMOS region, Trench NMOS region, and TVS region; The fifth, seventh and ninth oxide layers are located in the LDPMOS region, the Trench NMOS region and the TVS region; the eighth oxide layer is located in the LDPMOS region; and the sixth oxide layer is located in the Trench NMOS region. The Trench NMOS gate and the gate resistance of the Trench NMOS located in the first trench of the Trench NMOS region; The LDPMOS gate and the LDPMOS gate resistance located in the second trench of the LDPMOS region; An interconnect metal layer is used to connect the drain of the LDPMOS to the gate resistor and gate of the Trench NMOS, the cathode of the TVS to the gate resistor and gate of the LDPMOS, the gate resistor of the LDPMOS to the source and drain of the LDPMOS, and the anode of the TVS to the source and gate resistor of the Trench NMOS.

[0012] In one example, in the LDPMOS region: The deep body region is located in the middle region, and second trap regions are located on both sides of the deep body region. The first trap region is located outside the second trap regions. The second injection region is located between the deep body region and the second well region, and within the first well region; A fifth oxide layer, a seventh oxide layer, and a ninth oxide layer are sequentially disposed above the second injection region between a portion of the first well region, a portion of the second well region, the deep body region, and the second well region, from bottom to top. A second polysilicon layer is formed in the second trench formed by the fifth oxide layer and the seventh oxide layer, serving as the LDPMOS gate. The second polysilicon layer is isolated from the epitaxial layer by the eighth oxide layer below. The deep body region, the middle part of the second injection region, and part of the ninth oxide layer are the source contact regions of the LDPMOS, while the edge part of the second injection region and part of the ninth oxide layer are the drain contact regions of the LDPMOS.

[0013] In one example, in the Trench NMOS region: The second injection region is located in the center of the first well region, with the second injection region located on both sides of the middle first injection region, and the edge first injection region located at the edge of the first well region. The first polysilicon layer, which serves as the gate of the Trench NMOS, is located in the first trench between the two first injection regions and is isolated from the sidewalls and bottom of the second trench by the sixth oxide layer surrounding the first polysilicon layer. The first injection area in the middle, the first trench, and the first injection area at the edge are provided with a fifth oxide layer, a seventh oxide layer, and a ninth oxide layer from bottom to top, and a seventh oxide layer that penetrates the fifth oxide layer is provided above the first trench; The second injection region, the middle part of the first injection region, and the ninth oxide layer constitute the source contact region of the Trench NMOS, and the drain of the Trench NMOS is led out from the substrate.

[0014] In one example, in the TVS area: The first injection region and the second injection region are spaced apart in the first well region; The fifth oxide layer, the seventh oxide layer, and the ninth oxide layer are sequentially stacked and cover the areas outside the first injection region and the second injection region; The first injection region serves as the cathode contact region of the diode, and the second injection region serves as the anode contact region of the diode.

[0015] In one example, the interconnect metal layer is a single-layer structure, and is electrically connected to the underlying second injection region, first injection region, and deep body region through contact holes.

[0016] It should be further noted that the technical features corresponding to the above examples can be combined or replaced to form new technical solutions.

[0017] Compared with the prior art, the beneficial effects of the present invention are: TVS devices fabricated using improved Trench NMOS and LDPMOS processes exhibit lower dynamic resistance per unit area compared to traditional TVS devices. This lower dynamic resistance serves as the primary discharge current channel, resulting in a slower increase in the TVS clamping voltage as the current increases, thus reducing the clamping factor to below 1.1 and significantly lowering the device clamping factor. Furthermore, based on the MOSFET turn-on principle, the TVS avoids the inherent risks of high trigger voltage and latch-up effects in SCR-structured TVS devices, thereby optimizing the ESD design window and ensuring the safety and reliability of protection actions. Additionally, the fabrication of TVS devices using improved LDPMOS and Trench NMOS processes offers good compatibility with existing semiconductor manufacturing platforms, high fabrication efficiency, and low cost. Attached Figure Description

[0018] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. The accompanying drawings are provided to provide a further understanding of the present application and constitute a part of the present application. The same reference numerals are used in these drawings to denote the same or similar parts. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application.

[0019] Figure 1 A flowchart illustrating a method provided as an example of the present invention; Figure 2 This is a schematic diagram of the device structure for steps S1-S2 provided in an example of the present invention; Figure 3 This is a schematic diagram of the LDPMOS region structure of the device in step S3 of an example of the present invention; Figure 4 This is a schematic diagram of the LDPMOS region structure of the device in step S4 of an example of the present invention; Figure 5 This is a schematic diagram of the Trench NMOS region structure of the device in step S4 of this invention, provided as an example. Figure 6 This is a schematic diagram of the TVS region structure of the device in step S4 of an example of the present invention; Figure 7 This is a schematic diagram of the LDPMOS region structure of the device provided in step S5 of the present invention; Figure 8 This is a schematic diagram of the Trench NMOS region structure of the device in step S6 of this invention, provided as an example. Figure 9 This is a schematic diagram of the TVS region structure of the device in step S6 of an example of the present invention; Figure 10This is a schematic diagram of the LDPMOS region structure of the device provided in step S7 of the present invention; Figure 11 This is a schematic diagram of the Trench NMOS region structure of the device in step S7 of this invention, provided as an example. Figure 12 This is a schematic diagram of the TVS region structure of the device provided in steps S7-S8 of the present invention; Figure 13 This is a schematic diagram of the gate resistor structure for steps S7-S8 provided in an example of the present invention; Figure 14 This is a schematic diagram of the LDPMOS region structure of the device provided in steps S9-S10 of this invention; Figure 15 This is a schematic diagram of the Trench NMOS region structure of the device in step S9 of this invention, provided as an example. Figure 16 This is a schematic diagram of the TVS region structure of the device in step S9 of an example of the present invention; Figure 17 This is a schematic diagram of the gate resistor structure for step S9 provided in an example of the present invention; Figure 18 This is a schematic diagram of the LDPMOS region structure of the device provided in step S11 of an example of the present invention; Figure 19 This is a schematic diagram of the Trench NMOS region structure of the device provided in step S11 of this invention; Figure 20 This is a schematic diagram of the TVS region structure of the device provided in step S11 of an example of the present invention; Figure 21 This is a schematic diagram of the gate resistor structure for step S11 provided in an example of the present invention; Figure 22 This is a schematic diagram of the LDPMOS region structure of the device provided in steps S12-S13 of the present invention; Figure 23 This is a schematic diagram of the Trench NMOS region structure of the device provided in steps S12-S13 of the present invention; Figure 24 This is a schematic diagram of the TVS region structure of the device provided in steps S12-S13 of the present invention; Figure 25 This is a schematic diagram of the gate resistor structure for steps S12-S13 provided as an example of the present invention; Figure 26 This invention provides an example of the structural regions and top metal layout diagrams obtained after fabrication; Figure 27 The schematic diagram of the device circuit provided is an example of the present invention. Detailed Implementation

[0020] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] In the description of this invention, it should be noted that the directions or positional relationships indicated by terms such as "middle," "upper," "lower," "inner," and "outer" are based on the directions or positional relationships shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the use of ordinal numbers (e.g., "first and second," "first to ninth," etc.) is for distinguishing objects and is not limited to this order, and should not be construed as indicating or implying relative importance.

[0022] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connection" should be interpreted broadly, for example, referring to direct connection or indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0023] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0024] In one example, such as Figure 1 As shown, a method for fabricating TVS devices based on LDPMOS and Trench NMOS processes can integrate laterally diffused PMOS (LDPMOS), trench NMOS (Trench NMOS), and TVS on the same semiconductor chip. The method includes the following steps: S1: As Figure 2 As shown, an epitaxial layer (N-EPI) of the first conductivity type is grown on a heavily doped N-type substrate (N-sub) of the first conductivity type.

[0025] Optionally, the substrate material can be any one of Si, diamond, SiC, sapphire, and GaN; in this example, it is a silicon substrate. A lightly doped N-type epitaxial layer is grown on the substrate using chemical vapor deposition (CVD) or epitaxial growth techniques.

[0026] S2: As Figure 2 As shown, a field oxygen layer is formed on the surface of the epitaxial layer.

[0027] Preferably, a field oxide layer is formed on the epitaxial layer using thermal oxidation or thin film processes for isolation between devices.

[0028] S3: As Figure 3 As shown, in the LDPMOS region, the field oxide layer is selectively etched, and heavy doped ions of the first conductivity type are implanted and diffused to form a deep body region that penetrates the epitaxial layer. At the same time, a first oxide layer is generated on the surface of the deep body region.

[0029] Preferably, photolithography and etching processes are used, with photoresist as a mask, to etch the field oxide layer, and ion implantation and diffusion processes are employed to form a deep N region extending from the surface to the substrate. + (area), and the first oxide layer is generated simultaneously.

[0030] S4: As Figure 4 As shown, in the LDPMOS region, the field oxide layer is selectively etched, and second conductivity type ions are implanted and diffused to form a first well region extending to the epitaxial layer, while a second oxide layer is grown on the surface of the first well region. At the same time, such as Figure 5-6 As shown, in the Trench NMOS region and TVS region, the field oxide layer is etched, and ions of the second conductivity type are implanted and diffused to form a first well region extending to the epitaxial layer, while a second oxide layer is grown on the surface of the first well region.

[0031] Preferably, in the LDPMOS region, the field oxide layer and the first oxide layer are used as barrier layers. The field oxide layer is selectively etched using photolithography and etching processes, and the first well region (P-Well region) is formed through ion implantation and diffusion processes, while the second oxide layer is generated simultaneously.

[0032] In the Trench NMOS and TVS regions, the field oxide layer is etched using photolithography and etching processes, and the first well region (P-Well region) is formed through ion implantation and diffusion processes, while the second oxide layer is generated simultaneously.

[0033] S5: As Figure 7 As shown, in the LDPMOS region, the field oxide layer is etched, and ions of the first conductivity type are implanted and diffused to form a second well region extending to the epitaxial layer. At the same time, a third oxide layer is generated on the surface of the second well region.

[0034] Preferably, the first oxide layer and the second oxide layer are used as barrier layers, the field oxide layer is etched using photolithography and etching processes, and the second well region (N-Well region) is formed through phosphorus ion implantation and diffusion processes, while the third oxide layer is generated simultaneously.

[0035] S6: As Figures 8-9As shown, in the Trench NMOS region and TVS region, the second oxide layer is selectively etched, and heavy doped ions of the first conductivity type are implanted and diffused to form a first implantation region extending to the first well region. At the same time, a fourth oxide layer is grown on the surface of the first implantation region.

[0036] Preferably, the first oxide layer, the second oxide layer, and the third oxide layer are used as barrier layers. The second oxide layer of the Trench NMOS region and the TVS region is selectively etched using photolithography and etching processes. Then, the first implantation region (NMOS region) is formed through ion implantation and diffusion processes. + (Region) and the fourth oxide layer.

[0037] S7: As Figures 10-13 As shown, the surface oxide layer of all regions is removed, and a fifth oxide layer is grown on the surface of all regions; in the Trench NMOS region and the gate resistor region, the fifth oxide layer is photolithographically etched and selectively etched and extended to the outer extension layer to form the first trench.

[0038] Specifically, an etching process is used to remove the first, second, third, and fourth oxide layers. Then, a fifth oxide layer is regrown using a thin-film process. The fifth oxide layer is then photolithographically etched and selectively etched, extending to the outer extension layer to form the first trench. The etching can employ reactive ion etching (RIE) or deep trench etching (DTE) techniques. The gate resistor region is a specific area on the semiconductor chip defined for forming the Trench NMOS gate resistor.

[0039] S8: As Figure 11 , 13 As shown, a sixth oxide layer is formed on the surface of the first trench, and polysilicon is deposited and etched. A first polysilicon layer is formed on the sixth oxide layer in the first trench to obtain the gate of the Trench NMOS and the gate resistor of the Trench NMOS.

[0040] Preferably, for the Trench NMOS region and the gate resistor region, a first sacrificial oxide layer is formed on the surface of the first trench using a thermal oxidation process, and the first sacrificial oxide layer is etched. Then, a gate oxide layer (sixth oxide layer) is grown, and polysilicon is deposited to completely fill the first trench and cover the chip surface. Then, the polysilicon on the surface is etched away, leaving only polysilicon in the first trench to form a first polysilicon layer (first Poly). The first polysilicon layer is used as the trench gate structure (the gate of the Trench NMOS). At the same time, the trench gate structure is patterned to extend and form the gate resistor of the Trench NMOS and the gate resistor of the DPMOS in a specific region.

[0041] Before growing the formal gate oxide in the first trench, adding the step of forming and removing the first sacrificial oxide layer can effectively repair the etching damage on the silicon surface, remove impurities, and thus improve the fabrication reliability of the sixth oxide layer (Trench NMOS gate oxide).

[0042] S9: As Figures 14-17 As shown, a seventh oxide layer is generated on the surface of all regions. In the LDPMOS region, the fifth oxide layer and the seventh oxide layer are selectively etched to form a second trench. A sacrificial oxygen layer is formed in the second trench and then etched away to remove the sacrificial oxygen. An eighth oxide layer is formed on the surface of the second trench.

[0043] Preferredly, a seventh oxide layer is formed on the surface of all regions of the device using a thin-film process. For the LDPMOS region, the fifth and seventh oxide layers are etched using photolithography and etching processes. A second sacrificial oxide layer is formed using thermal oxidation and then etched away. Finally, an eighth oxide layer (thin gate oxide) is formed using thermal oxidation. By adding the step of forming and removing the second sacrificial oxide layer before growing the formal gate oxide in the second trench, etching damage on the silicon surface can be effectively repaired, impurities removed, and the reliability of the eighth oxide layer (LDPMOS gate oxide) improved.

[0044] S10: As Figure 14 As shown, in the LDPMOS region, polysilicon is deposited and etched on the surface of the eighth oxide layer in the second trench, and a second polysilicon layer is formed on the eighth oxide layer in the second trench, thus obtaining the gate of the LDPMOS and the gate resistor of the LDPMOS.

[0045] Preferably, polysilicon is deposited on the surface of the eighth oxide layer using a thin film process, and the polysilicon is etched to form a planar polysilicon gate (second polysilicon layer, i.e., second Poly) in the LDPMOS region.

[0046] S11: As Figures 18-21 As shown, a ninth oxide layer is generated on the surface of all regions. In the LDPMOS region, TrenchNMOS region and TVS region, the ninth oxide layer, the seventh oxide layer and the fifth oxide layer are selectively etched. Heavy doped ion implantation of the second conductivity type is performed to form a second implantation region extending to the first well region and the second well region. At the same time, a tenth oxide layer is formed on the surface of the second implantation region.

[0047] Preferably, a ninth oxide layer is formed in the LDPMOS region, Trench NMOS region, TVS region, and gate resistor surface using thin film technology. The fifth, seventh, and ninth oxide layers are used as barrier layers. A second implantation region (P) is formed in the epitaxial N-well and P-well regions using photolithography, etching, and ion implantation processes. + (Injection zone), and simultaneously generate the tenth oxide layer.

[0048] S12: As Figures 22-25 As shown, the fifth, seventh, ninth, and tenth oxide layers are selectively etched to form contact holes on the epitaxial layer.

[0049] Preferably, the fifth oxide layer, the seventh oxide layer, the ninth oxide layer and the tenth oxide layer are etched using photolithography and etching processes to form contact holes on the epitaxial layer.

[0050] Preferably, contact holes are formed on the epitaxial layer, thereby exposing the deep body region and a portion of the second injection region on both sides of the deep body region in the LDPMOS region, exposing the second injection region and a portion of the first injection region on both sides of the second injection region in the Trench NMOS region, and exposing the first injection region and the second injection region in the TVS region, which facilitates subsequent device interconnection.

[0051] S13: As Figures 22-26 As shown, a metal layer (MET) is deposited in the contact hole, and photolithography is used to form the source, gate, and drain of LDPMOS, the anode and cathode of TVS, and the source, gate, and drain of Trench NMOS.

[0052] like Figures 22-26 As shown, in the LDPMOS region, the deep body region, the middle portion of the second injection region, and part of the ninth oxide layer constitute the source contact region of the LDPMOS, while the edge portion of the second injection region and part of the ninth oxide layer constitute the drain contact region of the LDPMOS. In the Trench NMOS region, the second injection region, the middle portion of the first injection region, and the ninth oxide layer constitute the source contact region of the Trench NMOS, and the drain of the Trench NMOS region is led out from the substrate. In the TVS region, the first injection region and part of the ninth oxide layer constitute the cathode contact region of the TVS, while the second injection region and part of the ninth oxide layer constitute the anode contact region of the TVS.

[0053] Preferably, a metal layer, such as an aluminum-copper alloy or copper, is deposited in the contact area by physical vapor deposition (PVD, such as sputtering), followed by photolithography and etching to form an interconnect metal layer. The drain of the LDPMOS is then connected to the gate resistor (R1) and gate of the Trench NMOS, the cathode of the TVS is connected to the gate resistor (R2) and gate of the LDPMOS, the gate resistor of the LDPMOS is connected to the source of the LDPMOS and the drain of the Trench NMOS, and the anode of the TVS is connected to the source of the Trench NMOS and the gate resistor of the Trench NMOS.

[0054] Preferably, the interconnecting metal layers are formed using a single-layer metal interconnect process, which is low-difficulty and easy to implement.

[0055] At this time, the circuit works as follows: when a surge occurs, the TVS turns on, current flows through R1, the LDPMOS turns on, current flows through R2, the voltage across R2 increases, causing the Trench NMOS to turn on, and a large amount of current is released through the Trench NMOS. Since the Trench NMOS has a very small dynamic resistance, as the current increases, the clamping voltage increases slowly, thus keeping the total clamping voltage at a low value, which can reduce the clamping coefficient to below 1.1.

[0056] This invention also includes a TVS device based on LDPMOS and Trench NMOS processes, which is fabricated using the methods described above. Figures 22-25 As shown, the device includes: LDPMOS, Trench NMOS and TVS are integrated on the same semiconductor chip; The LDPMOS region, Trench NMOS region and TVS region share a heavily doped N-type substrate with a first conductivity type and an epitaxial layer of the first conductivity type on the substrate. Located in the LDPMOS region and penetrating the deep body region (Deep N) of the epitaxial layer + district); The first well region (P-Well region) of the second conductivity type is located in the epitaxial layer of LDPMOS region, Trench NMOS region, and TVS region. The second well region (N-Well region) of the first conductivity type is located in the epitaxial layer of the LDPMOS region. The first heavily doped first implantation region (N) of the first conductivity type is located in the first well region of the Trench NMOS region and TVS region. + area); The second heavily doped second implantation region (P) of the second conductivity type is located in the LDPMOS region, Trench NMOS region, and TVS region. + area); The fifth, seventh and ninth oxide layers are located in the LDPMOS region, the Trench NMOS region and the TVS region; the eighth oxide layer is located in the LDPMOS region; and the sixth oxide layer is located in the Trench NMOS region. The Trench NMOS gate and the gate resistance of the Trench NMOS located in the first trench of the Trench NMOS region; The LDPMOS gate and the LDPMOS gate resistance located in the second trench of the LDPMOS region; An interconnect metal layer is used to connect the drain of the LDPMOS to the gate resistor and gate of the Trench NMOS, the cathode of the TVS to the gate resistor and gate of the LDPMOS, the gate resistor of the LDPMOS to the source and drain of the LDPMOS, and the anode of the TVS to the source and gate resistor of the Trench NMOS.

[0057] Preferably, such as Figure 22 As shown, in the LDPMOS region: The deep body region is located in the middle region, and second trap regions are located on both sides of the deep body region. The first trap region is located outside the second trap regions. The second injection region is located between the deep body region and the second well region and within the first well region. The first well region, the second well region, and the second injection region all extend from the surface of the epitaxial layer to the interior of the epitaxial layer. A fifth oxide layer, a seventh oxide layer, and a ninth oxide layer are sequentially disposed above the second implantation region between a portion of the first well region, a portion of the second well region, the deep body region, and the second well region. A second polysilicon layer is formed in the second trench formed between the fifth oxide layer and the seventh oxide layer, serving as the gate of the LDPMOS. The second polysilicon layer is isolated from the epitaxial layer by the eighth oxide layer below. The deep body region, the middle part of the second injection region, and part of the ninth oxide layer are the source contact region of the LDPMOS, and the edge part of the second injection region and part of the ninth oxide layer are the drain contact region of the LDPMOS. Metal layers are deposited in the source contact region and the drain contact region to form the source and drain of the LDPMOS.

[0058] Preferably, such as Figure 23 As shown, in the Trench NMOS region: The second injection region is located in the center of the first well region, with the second injection region located on both sides of the middle first injection region, and the edge first injection region located at the edge of the first well region. The first polysilicon layer, which serves as the gate of the Trench NMOS, is located in the first trench between the two first injection regions and is isolated from the sidewalls and bottom of the second trench by the sixth oxide layer surrounding the first polysilicon layer. The first injection area in the middle, the first trench, and the first injection area at the edge are provided with a fifth oxide layer, a seventh oxide layer, and a ninth oxide layer from bottom to top, and a seventh oxide layer that penetrates the fifth oxide layer is provided above the first trench; The second injection region, the middle part of the first injection region, and the ninth oxide layer constitute the source contact region of the Trench NMOS. The drain of the Trench NMOS is led out from the substrate, and a metal layer is deposited in the source contact region to form the source of the Trench NMOS.

[0059] Preferably, such as Figure 24 As shown, in the TVS area: The first injection region and the second injection region are spaced apart in the first well region; The fifth oxide layer, the seventh oxide layer, and the ninth oxide layer are sequentially stacked and cover the areas outside the first injection region and the second injection region; The first injection region serves as the cathode contact region of the diode, and the second injection region serves as the anode contact region of the diode. Metal layers are deposited in the cathode contact region and the anode contact region to form the cathode and anode of the TVS.

[0060] Preferably, the interconnecting metal layer is a single-layer structure, and is electrically connected to the lower second injection region, first injection region, and deep body region through contact holes.

[0061] like Figure 27 As shown, when the device is working, when a forward electrostatic discharge pulse arrives, the TVS diode is forward-biased, and current flows through R1, turning on the LDPMOS. The drain voltage of the LDPMOS drops and is coupled to the gate of the Trench NMOS through R2, turning on the Trench NMOS. A large amount of current is released through the Trench NMOS. Since the Trench NMOS has a very small dynamic resistance, the clamping voltage increases slowly as the current increases, thus keeping the total clamping voltage constant at a relatively stable value and reducing the clamping coefficient of the device.

[0062] This example device integrates LDPMOS, Trench NMOS, and TVS diodes on a single chip and constructs specific interconnects to apply the low dynamic resistance characteristics of Trench NMOS to ESD protection, successfully reducing the clamping coefficient to below 1.1 and solving the problem of insufficient protection capability of traditional TVS diodes.

[0063] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. A method for fabricating a TVS device based on LDPMOS and Trench NMOS processes, characterized in that, Includes the following steps: S1: Grow an epitaxial layer of the first conductivity type on a heavily doped substrate of the first conductivity type; S2: A field oxygen layer is formed on the surface of the epitaxial layer; S3: In the LDPMOS region, the field oxide layer is selectively etched, and heavy doped ions of the first conductivity type are implanted and diffused to form a deep body region that penetrates the epitaxial layer. At the same time, a first oxide layer is generated on the surface of the deep body region. S4: In the LDPMOS region, the field oxide layer is selectively etched, and in the Trench NMOS region and TVS region, the field oxide layer is etched. At the same time, second conductivity type ions are implanted and diffused to form a first well region extending to the epitaxial layer. Meanwhile, a second oxide layer is grown on the surface of the first well region. S5: In the LDPMOS region, the field oxide layer is etched, and ions of the first conductivity type are implanted and diffused to form a second well region extending to the epitaxial layer. At the same time, a third oxide layer is generated on the surface of the second well region. S6: In the Trench NMOS region and TVS region, the second oxide layer is selectively etched, and heavy doped ions of the first conductivity type are implanted and diffused to form a first implantation region extending to the first well region. At the same time, a fourth oxide layer is grown on the surface of the first implantation region. S7: Remove the surface oxide layer in all regions and grow a fifth oxide layer on the surface of all regions; selectively etch the fifth oxide layer in the Trench NMOS region and the gate resistor region and extend it to the outer extension layer to form a first trench; S8: A sixth oxide layer is formed on the surface of the first trench, and polysilicon is deposited and etched. A first polysilicon layer is formed on the sixth oxide layer in the first trench to obtain the gate of Trench NMOS, the gate resistor of Trench NMOS and the gate resistor of LDPMOS. S9: A seventh oxide layer is generated on the surface of all regions. In the LDPMOS region, the fifth oxide layer and the seventh oxide layer are selectively etched to form a second trench. An eighth oxide layer is formed on the surface of the second trench. S10: In the LDPMOS region, polysilicon is deposited and etched on the surface of the eighth oxide layer in the second trench to form a second polysilicon layer on the eighth oxide layer in the second trench, thereby obtaining the gate of the LDPMOS. S11: A ninth oxide layer is generated on the surface of all regions. In the LDPMOS region, Trench NMOS region and TVS region, the ninth oxide layer, the seventh oxide layer and the fifth oxide layer are selectively etched. Heavy doped ion implantation of the second conductivity type is performed to form a second implantation region extending to the first well region and the second well region. At the same time, a tenth oxide layer is formed on the surface of the second implantation region. S12: Selectively etch the fifth, seventh, ninth, and tenth oxide layers to form contact holes on the epitaxial layer; S13: Deposit a metal layer in the contact hole and etch it by photolithography to form the source, gate, and drain of LDPMOS, the anode and cathode of TVS, and the source, gate, and drain of Trench NMOS; Connect the drain of the LDPMOS to the gate resistor and gate of the Trench NMOS. Connect the cathode of the TVS to the gate resistor and gate of the LDPMOS. Connect the gate resistor of the LDPMOS to the source and drain of the LDPMOS. Connect the anode of the TVS to the source and gate resistor of the Trench NMOS.

2. The method for fabricating a TVS device based on LDPMOS and Trench NMOS processes according to claim 1, characterized in that, Before forming the sixth oxide layer in step S8, the method further includes: forming a first sacrificial oxide layer in the first trench and etching the first sacrificial oxide layer; Before forming the eighth oxide layer in step S9, the method further includes: forming a second sacrificial oxide layer in the second trench and etching away the second sacrificial oxide layer.

3. The method for fabricating a TVS device based on LDPMOS and Trench NMOS processes according to claim 1, characterized in that, In step S12, a contact hole is formed on the epitaxial layer, thereby exposing the deep body region and a portion of the second injection region located on both sides of the deep body region in the LDPMOS region, exposing the second injection region and a portion of the first injection region located on both sides of the second injection region in the Trench NMOS region, and exposing the first injection region and the second injection region in the TVS region.

4. The method for fabricating a TVS device based on LDPMOS and Trench NMOS processes according to claim 1, characterized in that, In step S13, in the LDPMOS region, the deep body region, the middle portion of the second injection region, and part of the ninth oxide layer are the source contact regions of the LDPMOS, and the edge portion of the second injection region and part of the ninth oxide layer are the drain contact regions of the LDPMOS; in the Trench NMOS region, the second injection region, the middle portion of the first injection region, and the ninth oxide layer are the source contact regions of the Trench NMOS, and the drain of the Trench NMOS is led out from the substrate; in the TVS region, the first injection region and part of the ninth oxide layer are the cathode contact regions of the TVS, and the second injection region and part of the ninth oxide layer are the anode contact regions of the TVS.

5. The method for fabricating a TVS device based on LDPMOS and Trench NMOS processes according to claim 1, characterized in that, In step S13, an interconnected metal layer is formed using a metal interconnect process.

6. A TVS device based on LDPMOS and Trench NMOS processes, characterized in that, The device is prepared according to the method of any one of claims 1-5, comprising: LDPMOS, Trench NMOS and TVS are integrated on the same semiconductor chip; The LDPMOS region, Trench NMOS region and TVS region share a heavily doped substrate with a first conductivity type and an epitaxial layer with a first conductivity type located on the substrate. The deep body region located in the LDPMOS region and penetrating the epitaxial layer; The first well region of the second conductivity type is located in the epitaxial layer of the LDPMOS region, Trench NMOS region, and TVS region. The second well region of the first conductivity type is located in the epitaxial layer of the LDPMOS region; The first implantation region of the first conductivity type is located in the first well region of the Trench NMOS region and the TVS region; The second doped second implantation region of the second conductivity type is located in the LDPMOS region, Trench NMOS region, and TVS region; The fifth, seventh and ninth oxide layers are located in the LDPMOS region, the Trench NMOS region and the TVS region; the eighth oxide layer is located in the LDPMOS region; and the sixth oxide layer is located in the Trench NMOS region. The Trench NMOS gate and the gate resistance of the Trench NMOS located in the first trench of the Trench NMOS region; The LDPMOS gate and the LDPMOS gate resistance located in the second trench of the LDPMOS region; An interconnect metal layer is used to connect the drain of the LDPMOS to the gate resistor and gate of the Trench NMOS, the cathode of the TVS to the gate resistor and gate of the LDPMOS, the gate resistor of the LDPMOS to the source and drain of the LDPMOS, and the anode of the TVS to the source and gate resistor of the Trench NMOS.

7. The TVS device based on LDPMOS and Trench NMOS processes according to claim 6, characterized in that, In the LDPMOS region: The deep body region is located in the middle region, and second trap regions are located on both sides of the deep body region. The first trap region is located outside the second trap regions. The second injection region is located between the deep body region and the second well region, and within the first well region; A fifth oxide layer, a seventh oxide layer, and a ninth oxide layer are sequentially disposed above the second injection region between a portion of the first well region, a portion of the second well region, the deep body region, and the second well region, from bottom to top. A second polysilicon layer is formed in the second trench formed by the fifth oxide layer and the seventh oxide layer, serving as the LDPMOS gate. The second polysilicon layer is isolated from the epitaxial layer by the eighth oxide layer below. The deep body region, the middle part of the second injection region, and part of the ninth oxide layer are the source contact regions of the LDPMOS, while the edge part of the second injection region and part of the ninth oxide layer are the drain contact regions of the LDPMOS.

8. The TVS device based on LDPMOS and Trench NMOS processes according to claim 6, characterized in that, In the TrenchNMOS region: The second injection region is located in the center of the first well region, with the second injection region located on both sides of the middle first injection region, and the edge first injection region located at the edge of the first well region. The first polysilicon layer, which serves as the gate of the Trench NMOS, is located in the first trench between the two first injection regions and is isolated from the sidewalls and bottom of the second trench by the sixth oxide layer surrounding the first polysilicon layer. The first injection area in the middle, the first trench, and the first injection area at the edge are provided with a fifth oxide layer, a seventh oxide layer, and a ninth oxide layer from bottom to top, and a seventh oxide layer that penetrates the fifth oxide layer is provided above the first trench; The second injection region, the middle part of the first injection region, and the ninth oxide layer constitute the source contact region of the Trench NMOS, and the drain of the Trench NMOS is led out from the substrate.

9. The TVS device based on LDPMOS and Trench NMOS processes according to claim 6, characterized in that, In the TVS area: The first injection region and the second injection region are spaced apart in the first well region; The fifth oxide layer, the seventh oxide layer, and the ninth oxide layer are sequentially stacked and cover the areas outside the first injection region and the second injection region; The first injection region serves as the cathode contact region of the diode, and the second injection region serves as the anode contact region of the diode.

10. The TVS device based on LDPMOS and Trench NMOS processes according to claim 6, characterized in that, The interconnect metal layer is a single-layer structure, and it is electrically connected to the second injection region, the first injection region, and the deep body region below through contact holes.

Images