Back contact battery and photovoltaic module

Abstract

The invention relates to a back contact battery and a photovoltaic module, and relates to the field of photovoltaic technology. The back contact cell includes a substrate, a first doped layer, a second doped layer, and a conductive layer. The substrate comprises a backlight surface, the backlight surface comprises a first area and a second area, and the edge of the second area adjacent to the first area is provided with an overlapping area; the first doping layer is arranged in the first region and the overlapping region, and the doping type of the first doping layer is different from that of the substrate; the second doping layer is arranged in the second region, and the doping type of the second doping layer is the same as that of the substrate; the conductive layer is arranged on the sides, away from the substrate, of the first doped layer and the second doped layer; the conductive layer is provided with an isolation groove, the isolation groove comprises a second groove body, the first area comprises a first fine grid area, the second area comprises a second main grid area, and the second groove body is arranged in the second main grid area and located on the side, connected with the first fine grid area, of the second main grid area. The hot spot risk can be effectively reduced, and the battery conversion efficiency loss is reduced.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a back contact battery and photovoltaic module. Background Technology

[0002] The back-contact battery has all the positive and negative electrodes arranged in an interdigital pattern on the back of the battery, so that there are no metal electrode grid lines on the front of the battery, thus achieving 100% unobstructed light-receiving surface. Summary of the Invention

[0003] Therefore, it is necessary to provide a back-contact battery and photovoltaic module to address the problem of hot spot effect easily generated by back-contact batteries.

[0004] To achieve the above objectives, the technical solution adopted in this application is as follows:

[0005] In a first aspect, embodiments of this application provide a back contact battery, comprising:

[0006] The substrate includes a light-receiving surface and a backlighting surface disposed opposite to each other. The backlighting surface includes at least one first region and at least one second region. The second region has an overlapping area adjacent to the edge of the first region.

[0007] A first doped layer is disposed in the first region and the overlapping region, wherein the doping type of the first doped layer is different from that of the substrate;

[0008] A second doped layer is disposed in the second region, and the doping type of the second doped layer is the same as that of the substrate;

[0009] A conductive layer is disposed on the side of the first doped layer and the second doped layer opposite to the substrate;

[0010] The conductive layer has an isolation groove, the isolation groove includes a second groove body, the first region includes a plurality of first fine gate regions, the second region includes at least one second main gate region; at least one side of the second main gate region is connected to the first fine gate region, the second groove body is disposed in the second main gate region and is located on the side where the second main gate region is connected to the first fine gate region.

[0011] In one embodiment of the first aspect, the isolation groove further includes a first groove body disposed between the first region and the second region.

[0012] In one embodiment of the first aspect, the first region further includes at least one first main gate region, and the second region further includes a plurality of second fine gate regions;

[0013] Both the first main gate region and the second main gate region are parallel to the first direction, and both the first fine gate region and the second fine gate region are parallel to the second direction;

[0014] There is an angle between the first direction and the second direction.

[0015] In one embodiment of the first aspect, one end of the first fine gate region is connected to the first main gate region, and the other end faces the second main gate region; one end of the second fine gate region is connected to the second main gate region, and the other end faces the first main gate region.

[0016] Along the first direction, a second fine gate region is provided between two adjacent first fine gate regions.

[0017] In one embodiment of the first aspect, along the second direction, two first fine gate regions located on the same straight line are disposed opposite to each other on both sides of the second main gate region, and two second fine gate regions located on the same straight line are disposed opposite to each other on both sides of the second main gate region. One side of the second main gate region is connected to one of the first fine gate regions, and the other side is spaced apart from the other first fine gate region. A portion of the first groove is disposed at the interval between the second main gate region and the first fine gate region.

[0018] In one embodiment of the first aspect, one side of the second main gate region is connected to all the first fine gate regions located on the same side, and the other side is spaced apart from all the first fine gate regions located on the same side.

[0019] In one embodiment of the first aspect, a plurality of first fine gate regions located on the same side of the second main gate region are alternately connected to or spaced from the second main gate region.

[0020] In one embodiment of the first aspect, each of the second fine gate regions is distributed on both sides of the second main gate region, and any two of the second fine gate regions on both sides of the second main gate region are not located on the same straight line in the second direction; along the second direction, the second main gate region is located on both sides of the same straight line, one side is connected to the second fine gate region, and the other side is connected to the first fine gate region; the side of the second main gate region connected to the first fine gate region is provided with the second groove, and the second groove is located in the second main gate region.

[0021] In one embodiment of the first aspect, along the second direction, the width of the second main gate region is W1, the width of the second slot is W2, the distance between the second slot and the first fine gate region is W3, and satisfies: 5%≤W2 / W1≤20%, 1%≤W3 / W1≤10%.

[0022] In one embodiment of the first aspect, along the second direction, the width of the first main gate region is W4, and satisfies: 1000um≤W4+W1≤2000um, 50%≤W1 / W4≤80%.

[0023] In one embodiment of the first aspect, along the first direction, the width of the first fine gate region is L1, the width of the second fine gate region is L2, and satisfies: 600um≤L1+L2≤1000um, 30%≤L2:L1≤80%.

[0024] In one embodiment of the first aspect, both the light-receiving surface of the substrate and the first region are textured with a velvety surface.

[0025] In one embodiment of the first aspect, the back contact battery further includes a first passivation layer, an antireflection layer, a second passivation layer, and a tunneling oxide layer. The first passivation layer is disposed on the light-receiving surface of the substrate. The antireflection layer is disposed on the side of the first passivation layer away from the substrate. The tunneling oxide layer is disposed in the second region. The second doped layer is disposed on the side of the tunneling oxide layer away from the substrate. The second passivation layer is disposed in the first region and the overlapping region, and is partially deposited on the side of the second doped layer away from the tunneling oxide layer.

[0026] Secondly, embodiments of this application also provide a photovoltaic module, including the back contact battery described in any of the above embodiments.

[0027] Compared to related technologies, the beneficial effects of this application are: This application provides a back-contact battery and photovoltaic module, by setting the isolation trench as a first trench and a second trench, and making the first... tank Located between the first and second regions, the second tank is set within the second region, which effectively reduces the risk of hot spots and lowers the battery conversion efficiency loss. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a back contact battery in related technologies;

[0030] Figure 2 This is a cross-sectional structural diagram of the back contact battery in some embodiments of this application;

[0031] Figure 3 for Figure 2 A partially enlarged structural diagram;

[0032] Figure 4 This is a schematic diagram of the back surface structure of the back contact battery in some embodiments of this application. Figure 1 ;

[0033] Figure 5 This is a schematic diagram of the back surface structure of the back contact battery in some embodiments of this application. Figure 2 ;

[0034] Figure 6 This is a schematic diagram of the back surface structure of the back contact battery in some embodiments of this application. Figure 3 ;

[0035] Figure 7 This is a schematic diagram of the back surface structure of the back contact battery in some embodiments of this application. Figure 4 ;

[0036] Figure 8 The following are schematic diagrams of the structure of photovoltaic modules in some embodiments of this application;

[0037] Figure 9 This is a schematic flowchart of the preparation method in some embodiments of this application.

[0038] Explanation of reference numerals in the attached figures:

[0039] 1. P-region; 2. N-region; 3. Isolation region; 4. Transparent conductive film;

[0040] 1000. Photovoltaic modules;

[0041] 100. Back contact cell; 110. Substrate; 111. Light-receiving surface; 112. Backlighting surface; 1121. First region; 11211. First main grid region; 11212. First fine grid region; 1122. Second region; 11221. Overlapping region; 11222. Second fine grid region; 11223. Second main grid region; 120. First doped layer; 130. Second doped layer; 140. Conductive layer; 150. Isolation trench; 151. First trench body; 152. Second trench body; 160. Second passivation layer; 170. Antireflection layer; 180. First passivation layer; 190. Tunneling oxide layer;

[0042] 200, solder strip; 300, cover plate; 400, encapsulating adhesive;

[0043] y, the first direction; x, the second direction. Detailed Implementation

[0044] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0045] In the description of this application, it should be understood that if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0046] Furthermore, where the term "and / or" appears, "and / or" merely describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. Where the terms "first" and "second" appear, these terms are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" can explicitly or implicitly include at least one of those features. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0047] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0048] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0049] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0050] Hybrid BC batteries combine the passivation contact technology of TOPCon batteries with the back contact and grid-free technology of BC batteries. (See also...) Figure 1 As shown, in related technologies, the isolation region 3 of the hybrid BC battery is located between the N region 2 and the P region 1 to reduce leakage and improve battery conversion efficiency. However, this method results in the loss of a large area of ​​the transparent conductive film 4. The transparent conductive film 4 itself has sheet resistance, and after the current is generated from various points in the battery, it needs to flow laterally through the transparent conductive film 4 to reach the main grid electrode. The area loss of the transparent conductive film 4 is equivalent to reducing the cross-sectional area for current flow and forcing the current to take a longer, narrower path, which leads to a significant decrease in the fill factor, a reduction in output power, and a decrease in battery conversion efficiency. Moreover, the resistance of the transparent conductive film 4 increases at the isolation region 3, and the heat generated when the current flows through it is most concentrated, leading to a hot spot effect.

[0051] See Figure 2As shown, to improve the above-mentioned problems, embodiments of this application provide a back contact battery 100. The back contact battery 100 includes a substrate 110, a first doped layer 120, a second doped layer 130, and a conductive layer 140. An isolation trench 150 is formed in the conductive layer 140 to separate the first doped layer 120 and the second doped layer 130, avoiding short circuits between different electrodes. The conductive layer 140 is disposed on the side of the first doped layer 120 and the second doped layer 130 away from the substrate 110 to connect with the electrodes and realize the current output of the back contact battery 100. The isolation trench 150 is formed in the conductive layer 140, and part of the isolation trench 150 is disposed between the first region 1121 and the second region 1122, and part of the isolation trench 150 is disposed within the second region 1122, so as to uniformly form a reverse leakage region and reduce the hot spot effect of the back contact battery 100.

[0052] Continue reading Figure 3 As shown, the substrate 110 includes a light-receiving surface 111 and a backlight surface 112 disposed opposite to each other. The backlight surface 112 includes at least one first region 1121 and at least one second region 1122. The second region 1122 has an overlapping region 11221 adjacent to the edge of the first region 1121. A first doped layer 120 is disposed in the first region 1121 and the overlapping region 11221. The first doped layer 120 has a different doping type than the substrate 110. A second doped layer 130 is disposed in the second region 1122. The second doped layer 130 has the same doping type as the substrate 110. A conductive layer 140 is disposed on the side of the first doped layer 120 and the second doped layer 130 away from the substrate 110.

[0053] For example, substrate 110 is a silicon substrate, which may contain doped elements of either N-type or P-type. N-type elements may be group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), while P-type elements may be group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In). For instance, when substrate 110 is a P-type substrate, the doped element type is P-type. Similarly, when substrate 110 is an N-type substrate, the doped element type is N-type.

[0054] The substrate 110 has a light-receiving surface 111 and a back-lighting surface 112. The light-receiving surface 111 is the front side of the substrate 110, and the back-lighting surface 112 is the back side of the substrate 110. During the operation of back-contacting the battery 100, the light-receiving surface 111 faces the sunlight, and correspondingly, the back-lighting surface 112 faces away from the sunlight. It is understood that the light-receiving surface 111 and the back-lighting surface 112 are only relative concepts, and in some cases, the back-lighting surface 112 can also receive light.

[0055] The positive and negative electrodes of the back contact battery 100 are both located on the backlight surface 112 to avoid the electrodes blocking light, eliminate all metal grid lines blocking the light on the front side, and maximize the photocurrent. The first region 1121 and the second region 1122 are respectively provided with positive and negative electrodes. When the first region 1121 has a positive electrode, the second region 1122 has a corresponding negative electrode; conversely, when the first region 1121 has a negative electrode, the second region 1122 has a corresponding positive electrode. Through etching and other processes, the first region 1121 and the second region 1122 have a stepped structure, with the second region 1122 protruding compared to the first region 1121.

[0056] The first doped layer 120 is a doped amorphous silicon layer, and the doping type is different from that of the substrate 110. That is, when the substrate 110 is an N-type substrate, the first doped layer 120 is a P-type doped amorphous silicon layer; when the substrate 110 is a P-type substrate, the first doped layer 120 is an N-type doped amorphous silicon layer.

[0057] The first doped layer 120 can be any one or any multiple layers of a hydrogenated amorphous silicon layer (a-Si:H), a hydrogenated nanocrystalline silicon layer (nc-Si:H), and a hydrogenated nanocrystalline silicon oxide layer (nc-SiOx:H). The type of doping element in the amorphous silicon layer is not limited. Taking a p-type amorphous silicon layer as an example, the p-type doped amorphous silicon layer can be a p-type hydrogenated amorphous silicon layer (a-Si:H(p)), a p-type hydrogenated nanocrystalline silicon layer (nc-Si:H(p)), or a p-type hydrogenated nanocrystalline silicon oxide layer (nc-SiOx:H(p)); alternatively, the p-type doped amorphous silicon layer can also be a stacked structure of a p-type hydrogenated amorphous silicon layer, a p-type hydrogenated nanocrystalline silicon layer, and a p-type hydrogenated nanocrystalline silicon oxide layer sequentially stacked on the back side of the substrate 110.

[0058] The second doped layer 130 is doped polysilicon, and the doping type is the same as that of the substrate 110. That is, when the substrate 110 is an N-type substrate, the second doped layer 130 is N-type polysilicon; when the substrate 110 is a P-type substrate, the second doped layer 130 is P-type polysilicon.

[0059] In this specific embodiment, the substrate 110 is an N-type substrate, the first doped layer 120 is a P-type doped amorphous silicon layer, and the second doped layer 130 is an N-type polycrystalline silicon layer. The first doped layer 120 is deposited in the first region 1121 and partially deposited at the edge of the second region 1122, so that the edges of the first region 1121 and the second region 1122 are conductive. The second doped layer 130 is deposited in the second region 1122 and covers the first doped layer 120. Within the second region 1122, the overlapping area of ​​the first doped layer 120 and the second doped layer 130 is the overlap region 11221, so as to form a PN junction in the overlap region 11221 to realize current conduction.

[0060] The transparent conductive layer 140 has a film thickness of 100nm-110nm, a sheet resistance of 40Ω / □-100Ω / □, and an electron mobility of 20cm² / (V·s)-50cm² / (V·s). It possesses high transparency and high conductivity, allowing most sunlight, such as visible and near-infrared light, to pass through, thus enabling the backlight surface 112 to absorb light, reducing optical losses, and effectively collecting current and transmitting it laterally to the electrodes. In the first region 1121, the transparent conductive layer 140 effectively bridges the high-resistivity amorphous silicon passivation layer and the metal electrode to achieve efficient current output. The material used to fabricate the transparent conductive layer 140 can be ITO (indium tin oxide), FTO (fluorine-doped tin oxide), AZO (aluminum-doped zinc oxide), BZO (boron-doped zinc oxide), IO:H (hydrogen-doped indium oxide), etc., and the specific material can be selected according to design requirements; no specific limitation is made here.

[0061] Continue reading Figures 4 to 7 As shown, the isolation groove 150 includes a first groove 151 and a second groove 152. The first groove 151 is disposed between the first region 1121 and the second region 1122, and the second groove 152 is disposed within the second region 1122.

[0062] For example, the isolation groove 150 can be a groove structure formed in the transparent conductive layer 140 by etching or other processes, so as to physically isolate the transparent conductive layer 140 between the positive and negative electrodes, thereby avoiding short circuit problems between the positive and negative electrodes. And by setting the second groove 152 in the second region 1122, the risk of hot spots can be effectively reduced.

[0063] See again Figure 2 As shown, the back contact battery 100 further includes a first passivation layer 180, an antireflection layer 170, a second passivation layer 160, and a tunneling oxide layer 190. The first passivation layer 180 is disposed on the light-receiving surface 111 of the substrate 110, and the antireflection layer 170 is disposed on the side of the first passivation layer 180 away from the substrate 110. The tunneling oxide layer 190 is disposed in the second region 1122, and the second doped layer 130 is disposed on the side of the tunneling oxide layer 190 away from the substrate 110. The second passivation layer 160 is disposed in the first region 1121 and the overlapping region 11221, and is partially deposited on the side of the second doped layer 130 away from the tunneling oxide layer 190.

[0064] For example, the first passivation layer 180 can effectively reduce carrier recombination. The material used to prepare it can be silicon oxide, aluminum oxide, silicon nitride, amorphous silicon, etc. The specific material can be reasonably selected according to actual needs, and no specific limitation is made here.

[0065] The antireflection layer 170 can increase light capture and reduce optical loss. Its preparation materials can be silicon nitride, titanium dioxide, niobium oxide, etc. The specific materials can be selected according to actual needs, and no specific limitation is made here.

[0066] Optionally, the second passivation layer 160 is intrinsic amorphous silicon, which has an extreme passivation effect, low surface recombination rate, can achieve extremely high open-circuit voltage, does not have parasitic absorption, and does not affect the generation of photogenerated carriers. Of course, in other embodiments, the second passivation layer 160 may also be one or more of alumina, silicon dioxide, silicon nitride, etc., and no specific limitation is made here.

[0067] The tunneling oxide layer 190 can cause an asymmetric shift in the energy band on the back side of the substrate 110, making the barrier for majority carriers lower than that for minority carriers. Therefore, majority carriers can more easily tunnel through the tunneling oxide layer 190 to be transported to the doped polycrystalline silicon layer, while minority carriers have difficulty passing through the tunneling oxide layer 190 to achieve selective transport of carriers.

[0068] Furthermore, the tunneling oxide layer 190 also serves as a chemical passivation agent. Specifically, due to the presence of interface state defects at the interface between the substrate 110 and the tunneling oxide layer 190, the interface state density on the back side of the substrate 110 is relatively high. This increased interface state density promotes the recombination of photogenerated carriers, thereby reducing the fill factor, short-circuit current, and open-circuit voltage of the solar cell, ultimately resulting in a lower photoelectric conversion efficiency. The tunneling oxide layer 190, through saturating the dangling bonds on the back side of the substrate 110, provides chemical passivation, thereby reducing the defect state density on the back side of the substrate 110 and consequently reducing the number of recombination centers on the surface of the substrate 110, thus lowering the carrier recombination rate.

[0069] In this embodiment of the disclosure, the material of the tunneling oxide layer 190 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or magnesium fluoride.

[0070] In some embodiments, the first region 1121 includes a plurality of first fine gate regions 11212 and at least one first main gate region 11211, and the second region 1122 includes a plurality of second fine gate regions 11222 and at least one second main gate region 11223. Both the first main gate region 11211 and the second main gate region 11223 are parallel to a first direction y, and both the first fine gate region 11212 and the second fine gate region 11222 are parallel to a second direction x. At least one side of the second main gate region 11223 is connected to the first fine gate region 11212. A second slot 152 is disposed within the second main gate region 11223 and located on the side where the second main gate region 11223 connects to the first fine gate region 11212.

[0071] For example, the first direction y is the length direction of the main grid, and the second direction x is the length direction of the fine grid, and the first direction y and the second direction x are perpendicular to each other. The first main grid region 11211 is used to arrange the P-region main grid, the first fine grid region 11212 is used to arrange the P-region fine grid, the second main grid region 11223 is used to arrange the N-region main grid, and the second fine grid region 11222 is used to arrange the N-region fine grid, so as to collect the current of the solar cell through the main grid and the fine grid and output it.

[0072] Understandably, the first main gate area is a pre-defined area for setting the P-region main gate, and its actual size can be larger than the projected area of ​​the P-region main gate. The second main gate area is a pre-defined area for setting the N-region main gate, and its actual size can be larger than the projected area of ​​the N-region main gate. The first fine gate area is a pre-defined area for setting the P-region fine gate, and its actual size can be larger than the projected area of ​​the P-region fine gate. The second fine gate area is a pre-defined area for setting the N-region fine gate, and its actual size can be larger than the projected area of ​​the N-region fine gate.

[0073] In some embodiments, one end of the first fine gate region 11212 is connected to the first main gate region 11211, and the other end faces the second main gate region 11223. One end of the second fine gate region 11222 is connected to the second main gate region 11223, and the other end faces the first main gate region 11211. Along the first direction y, a second fine gate region 11222 is provided between two adjacent first fine gate regions 11212, and similarly, a first fine gate region 11212 is also provided between two adjacent second fine gate regions 11222.

[0074] For example, the first region 1121 and the second region 1122 are distributed alternately in an interdigitated pattern, and a first region 1121 is provided on both sides of the second region 1122. By providing a second groove 152 in the second main gate region 11223, the risk of hot spots is effectively reduced.

[0075] In one embodiment of the first aspect, each first fine gate region 11212 and each second fine gate region 11222 are respectively distributed on both sides of the first main gate region 11211;

[0076] Along the second direction x, two first fine gate regions 11212 located on the same straight line are disposed opposite each other on both sides of the second main gate region 11223. One side of the second main gate region 11223 is connected to one of the first fine gate regions 11212, and the other side is spaced apart from the other first fine gate region 11212. A portion of the first groove 151 is disposed at the interval between the second main gate region 11223 and the first fine gate region 11212.

[0077] See Figure 4As shown, in some embodiments, second grooves 152 are provided on both sides of the second main grid region 11223. However, this method removes a large area of ​​transparent conductive layer 140 from the second main grid region 11223, resulting in a significant loss in battery conversion efficiency.

[0078] In this application, when both sides of the second main grid region 11223 are connected to a first fine grid region 11212, the second main grid region 11223 is provided with a second groove 152 on only one side, so as to reduce the risk of hot spots and improve the problem of excessive battery conversion efficiency loss.

[0079] Continue reading Figure 5 As shown, in some embodiments, one side of the second main gate region 11223 is connected to all the first fine gate regions 11212 located on the same side, and the other side is spaced apart from all the first fine gate regions 11212 located on the same side.

[0080] For example, the second slot 152 is only disposed on the same side of the second main gate region 11223, while the other side of the second main gate region 11223 is only occupied by the first slot 151. The side of the second main gate region 11223 with the second slot 152 has multiple first slots 151 and multiple second slots 152, with each first slot 151 distributed between a corresponding second fine gate region 11222 and the first region 1121. For example, if the second fine gate region 11222 has a rectangular structure, one side of the second fine gate region 11222 is connected to the second main gate region 11223, and the first slots 151 are distributed in a U-shape on the other three sides of the second fine gate region 11222 that are not connected to the second main gate region 11223. A second slot 152 located within the second main gate region 11223 is connected between two adjacent first slots 151 to reduce the risk of hot spots.

[0081] Continue reading Figure 6 As shown, in some embodiments, a plurality of first fine gate regions 11212 located on the same side of the second main gate region 11223 are alternately connected to or spaced apart from the second main gate region 11223.

[0082] For example, along the first direction y, the second slot 152 is disposed on the left side of the second main gate region 11223 corresponding to the first row of first fine gate regions 11212 in the first direction; the second slot 152 is disposed on the right side of the second main gate region 11223 corresponding to the second row of first fine gate regions 11212 in the second direction; the second slot 152 is disposed on the left side of the second main gate region 11223 corresponding to the third row of first fine gate regions 11212 in the second direction; the second slot 152 is disposed on the right side of the second main gate region 11223 corresponding to the fourth row of first fine gate regions 11212 in the second direction; and so on. Following this pattern, the second slots 152 on the same side are alternately distributed. By alternating the arrangement of the second slots 152, the reverse leakage area can be avoided from being located only on one side of the second main gate region 11223, further improving battery conversion efficiency.

[0083] It should be noted that the left and right directional terms in the above embodiments are only used in the context of... Figure 6 This description is for reference only and is not intended to limit the actual distribution in practical applications. In real-world scenarios, it can refer to any of the four cardinal directions (front, back, left, right) to meet design requirements.

[0084] Continue reading Figure 7 As shown, in some embodiments, each first fine gate region 11212 and each second fine gate region 11222 are alternately distributed on both sides of the second main gate region 11223. Along the second direction x, one side of the second main gate region 11223 is connected to the second fine gate region 11222, and the other side is connected to the first fine gate region 11212. A second groove 152 is provided on the side where the second main gate region 11223 connects to the first fine gate region 11212, and the second groove 152 is located within the second main gate region 11223.

[0085] For example, if the second fine grid area 11222 is distributed in a Z-shaped structure, then one side of the second main grid area 11223 is connected to the second fine grid area 11222, and the other side is provided with a second groove 152, which is connected to the first fine grid area 11212. Similarly, the second groove 152 can be alternately arranged to improve the battery conversion efficiency.

[0086] See Figure 6 As shown, in some embodiments, along the second direction x, the width of the second main gate region 11223 is W1, the width of the second groove 152 is W2, and the distance between the second groove 152 and the first fine gate region 11212 is W3, and satisfies: 5%≤W2 / W1≤20%, 1%≤W3 / W1≤10%.

[0087] For example, through the above design, the width of the isolation groove 150 is reasonably selected. This effectively avoids the problem of insufficient prevention of short circuits between the P and N regions when the isolation groove 150 is too narrow, preventing serious leakage and the collapse of the battery's fill factor and open-circuit voltage. At the same time, it avoids the increase of ineffective non-power-generating areas when the isolation groove 150 is too wide, preventing a decrease in the battery's short-circuit current and overall efficiency. This helps to balance the reverse breakdown voltage and operating efficiency corresponding to the back contact battery 100, thereby reducing the risk of hot spots and minimizing battery conversion efficiency loss.

[0088] In some embodiments, along the second direction x, the width of the first main gate region 11211 is W4, and satisfies: 1000um≤W4+W1≤2000um, 50%≤W1 / W4≤80%.

[0089] For example, the width W4 of the first main gate region 11211 can be 600μm-700μm, the width W1 of the second main gate region 11223 can be 400μm-500μm, the width W2 of the isolation groove 150 can be 50μm-150μm, and the distance W3 between the second groove 152 and the first fine gate region 11212 can be 5μm-50μm.

[0090] The main grid located in the first main grid region 11211 collects the hole current collected from all the fine grids located in the first fine grid region 11212, and the main grid located in the second main grid region 11223 collects the electron current collected from all the fine grids located in the second fine grid region 11222. Since the hole mobility is much lower than the electron mobility, the above design achieves global optimization of hole collection and conduction, balancing the resistance loss on the interconnect ribbon 200 and reducing the overall series resistance. This not only balances the resistance inside the cell but also balances the resistance loss on the solder ribbon 200 in the module interconnection process, thereby maximizing the reduction of the overall cell series resistance, improving the fill factor and final output power. It also further reduces the risk of hot spots while minimizing cell conversion efficiency loss.

[0091] In some embodiments, along the first direction y, the width of the first fine gate region 11212 is L1, and the width of the second fine gate region 11222 is L2, satisfying: 600um≤L1+L2≤1000um, 30%≤L2:L1≤80%.

[0092] For example, the width L1 of the first fine grid region 11212 can be 400μm-600μm, and the width L2 of the second fine grid region 11222 can be 300μm-400μm. By setting these parameters, the P-region has a larger cross-sectional area and a shorter current conduction path, balancing the total resistance of current conduction from the P-region and N-region to the main grid. This effectively reduces the overall series resistance of the battery, improves the fill factor, and directly increases the maximum output power.

[0093] In some embodiments, the light-receiving surface 111 and the first region 1121 of the substrate 110 are both provided with a velvety surface.

[0094] For example, by applying a textured surface to the light-receiving surface 111, light can be reflected multiple times on the surface, greatly increasing the chance of light entering the battery, improving short-circuit current, reducing optical loss, and broadening the response spectrum.

[0095] The textured surface of the first region 1121 increases internal light reflection, enhances the optical path, and prevents some photons from directly exiting the cell and causing loss. Some photons can be reflected back into the cell for secondary or even multiple absorptions, greatly increasing the effective propagation distance of light in silicon.

[0096] See Figure 8 As shown, embodiments of this application also provide a photovoltaic module 1000, including the back contact cell 100, solder ribbon 200, encapsulating adhesive 400 and cover plate 300 in any of the above embodiments.

[0097] For example, the photovoltaic module 1000 is used to convert received light energy into electrical energy. Two adjacent back contact cells 100 are electrically connected by solder strips 200. Two cover plates 300 are provided and located on the upper and lower sides of the photovoltaic module 1000 respectively. Encapsulating adhesive 400 is filled between the two cover plates 300 to encapsulate and fix the cell string formed by the electrical connection of the back contact cells 100.

[0098] This embodiment has the back contact battery 100 of any of the above embodiments, and therefore has all the beneficial effects of the back contact battery 100 of any of the above embodiments, which will not be described in detail here.

[0099] See Figure 9 As shown, embodiments of this application also provide a method for preparing a back contact battery 100, applicable to the back contact battery 100 in any of the above embodiments. The preparation method includes:

[0100] S10, polished after cleaning the silicon wafer.

[0101] Specifically, in this embodiment, the silicon wafer is an N-type doped silicon wafer. After selecting the desired doped silicon wafer, a wet chemical cleaning is performed to remove surface organic contaminants, the native oxide layer, some metal contaminants, particulate contaminants, and metal ions. After cleaning, it is rinsed with ultrapure water to avoid recontamination. Finally, it is dried using a dryer to prevent water residue.

[0102] S20, a tunneling oxide layer 190 and polysilicon are sequentially deposited on the surface of a silicon wafer, and the polysilicon is subjected to type I doping.

[0103] Specifically, an ultrathin layer of silicon dioxide is deposited on the surface of a silicon wafer, with a thickness controlled between 1.2 nm and 1.5 nm. This can significantly reduce the surface defect state density of the silicon wafer, lower the surface recombination rate, and create a quantum tunneling effect, allowing charge carriers to pass through the silicon wafer via quantum tunneling.

[0104] Polycrystalline silicon is vapor-deposited on the surface of the tunneling oxide layer 190, and then subjected to type I doping. Understandably, the doping type of the polycrystalline silicon is the same as that of the silicon wafer. In this specific embodiment, the silicon wafer is N-type, and type I refers to N-type doping.

[0105] S30, remove the tunneling oxide layer 190 and polysilicon from the front and back first regions 1121 of the silicon wafer, and remove a portion of the silicon wafer from the first region 1121.

[0106] Specifically, processes such as laser ablation or wet etching can be used to remove the tunneling oxide layer 190 and polysilicon on the front side of the silicon wafer, and to remove the tunneling oxide layer 190 and polysilicon in the first region 1121 on the back side, while retaining the tunneling oxide layer 190 and the second doped layer 130 in the second region 1122. Furthermore, a portion of the thickness of the silicon wafer in the first region 1121 is removed, making the first region 1121 recessed compared to the second region 1122. This facilitates subsequent metal gate line printing and avoids the gate lines simultaneously contacting the P and N regions due to misalignment.

[0107] S40, a textured surface is formed on the front side and the first region 1121 of the silicon wafer, and the borosilicate glass in the second region 1122 of the silicon wafer is removed.

[0108] Specifically, a silicon wafer is placed in a tank containing an etching solution to create a micron-scale pyramid-shaped uneven structure on the surface of the silicon wafer, and the borosilicate glass in the second region 1122 is removed by acid washing.

[0109] Understandably, when the silicon wafer is a monocrystalline silicon substrate 110, the etching solution used is an alkaline solution such as NaOH, KOH, or TMAH; when the silicon wafer is a polycrystalline silicon substrate 110, the etching solution used is an acidic solution such as HF or HNO3.

[0110] S50, a first passivation layer 180 and an antireflection layer 170 are deposited on the front side of the silicon wafer.

[0111] Specifically, processes such as PECVD (Plasma enhanced chemical vapor deposition) and ALD (Atomic layer deposition) can be used to sequentially deposit aluminum oxide and silicon nitride on the front side of the silicon wafer to form the first passivation layer 180 and the antireflection layer 170.

[0112] S60, a second passivation layer 160 and a second doped type of polysilicon are deposited on the back side of the silicon wafer.

[0113] Specifically, using the PECVD process, an intrinsic amorphous silicon layer (ia-Si:H) and a P-type heavily doped amorphous silicon layer are deposited on the back side of the silicon wafer to form a second passivation layer 160 and a first doped layer 120.

[0114] S70, remove the second passivation layer 160 and the second doped type polysilicon from the second region 1122.

[0115] Specifically, patterning is performed using methods such as laser ablation or mask etching to selectively remove a portion of the second passivation layer 160 and the first doped layer 120 in the second region 1122, while retaining the second passivation layer 160 and the first doped layer 120 at the edge of the second region 1122.

[0116] S80, a transparent conductive layer 140 is deposited on the back side of the silicon wafer, and an isolation trench 150 is formed.

[0117] Specifically, a transparent conductive material is deposited on the surfaces of the first doped layer 120 and the second doped layer 130 to obtain a transparent conductive layer 140. The transparent conductive material can be ITO (indium tin oxide), SCOT (galvanic zinc oxide), etc. Then, a laser etching process is used to etch along the edge between the second fine gate region 11222 and the first region 1121 to form a first trench 151. A second trench 152, communicating with the first trench 151, is etched on one side of the second main gate region 11223, ultimately obtaining an isolation trench 150. Finally, metal electrodes are deposited on the transparent conductive layers 140 of the first region 1121 and the second region 1122 to obtain the positive and negative electrodes of the back contact battery 100, respectively.

[0118] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A back-contact battery, characterized in that, include: The substrate includes a light-receiving surface and a backlighting surface disposed opposite to each other. The backlighting surface includes at least one first region and at least one second region. The second region has an overlapping area adjacent to the edge of the first region. A first doped layer is disposed in the first region and the overlapping region, wherein the doping type of the first doped layer is different from that of the substrate; A second doped layer is disposed in the second region, and the doping type of the second doped layer is the same as that of the substrate; A conductive layer is disposed on the side of the first doped layer and the second doped layer opposite to the substrate; The conductive layer has an isolation groove, the isolation groove includes a second groove body, the first region includes a plurality of first fine gate regions, the second region includes at least one second main gate region; at least one side of the second main gate region is connected to the first fine gate region, the second groove body is disposed in the second main gate region and is located on the side where the second main gate region is connected to the first fine gate region.

2. The back contact battery according to claim 1, characterized in that, The isolation groove also includes a first groove body, which is disposed between the first region and the second region.

3. The back contact battery according to claim 1, characterized in that, The first region further includes at least one first main gate region, and the second region further includes a plurality of second fine gate regions; Both the first main gate region and the second main gate region are parallel to the first direction, and both the first fine gate region and the second fine gate region are parallel to the second direction; There is an angle between the first direction and the second direction.

4. The back contact battery according to claim 3, characterized in that, One end of the first fine gate region is connected to the first main gate region, and the other end faces the second main gate region; one end of the second fine gate region is connected to the second main gate region, and the other end faces the first main gate region. Along the first direction, a second fine gate region is provided between two adjacent first fine gate regions.

5. The back contact battery according to claim 3, characterized in that, Along the second direction, two first fine grid areas located on the same straight line are disposed opposite to each other on both sides of the second main grid area, and two second fine grid areas located on the same straight line are disposed opposite to each other on both sides of the second main grid area. One side of the second main grid area is connected to one of the first fine grid areas, and the other side is spaced apart from the other first fine grid area; a portion of the first groove is disposed at the interval between the second main grid area and the first fine grid area.

6. The back contact battery according to claim 5, characterized in that, One side of the second main gate area is connected to all the first fine gate areas located on the same side, and the other side is spaced apart from all the first fine gate areas located on the same side.

7. The back contact battery according to claim 5, characterized in that, Multiple first fine gate regions located on the same side of the second main gate region are alternately connected to or spaced from the second main gate region.

8. The back contact battery according to claim 3, characterized in that, Each of the second fine gate areas is distributed on both sides of the second main gate area. Any two second fine gate areas on both sides of the second main gate area are not located on the same straight line in the second direction. Along the second direction, the second main gate area is located on both sides of the same straight line, with one side connected to the second fine gate area and the other side connected to the first fine gate area. The second groove is provided on the side of the second main gate area connected to the first fine gate area, and the second groove is located in the second main gate area.

9. The back contact battery according to claim 3, characterized in that, Along the second direction, the width of the second main gate area is W1, the width of the second slot is W2, the distance between the second slot and the first fine gate area is W3, and satisfies: 5%≤W2 / W1≤20%, 1%≤W3 / W1≤10%.

10. The back contact battery according to claim 9, characterized in that, Along the second direction, the width of the first main gate region is W4, and satisfies: 1000um≤W4+W1≤2000um, 50%≤W1 / W4≤80%.

11. The back contact battery according to claim 3, characterized in that, Along the first direction, the width of the first fine gate region is L1, and the width of the second fine gate region is L2, satisfying: 600um≤L1+L2≤1000um, 30%≤L2:L1≤80%.

12. The back contact battery according to claim 1, characterized in that, Both the light-receiving surface of the substrate and the first region are textured with a velvety surface.

13. The back contact battery according to claim 1, characterized in that, The back contact battery further includes a first passivation layer, an antireflection layer, a second passivation layer, and a tunneling oxide layer. The first passivation layer is disposed on the light-receiving surface of the substrate. The antireflection layer is disposed on the side of the first passivation layer away from the substrate. The tunneling oxide layer is disposed in the second region. The second doped layer is disposed on the side of the tunneling oxide layer away from the substrate. The second passivation layer is disposed in the first region and the overlapping region, and is partially deposited on the side of the second doped layer away from the tunneling oxide layer.

14. A photovoltaic module, characterized in that, Includes the back contact battery as described in any one of claims 1 to 13.

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