Stress coordinated regulation and control and low-damage manufacturing method and system for ultrathin TOPCon battery

Abstract

The invention relates to the technical field of high-efficiency crystalline silicon solar cell manufacturing, in particular to a stress coordinated regulation and low-damage manufacturing method and system for an ultrathin TOPCon cell, and the method comprises the steps: providing a crystalline silicon wafer; preparing a passivation contact precursor structure on the back surface; a composite transmission system is adopted, a silicon wafer is fixed to a high-temperature transmission station through electrostatic adsorption, and a non-high-temperature station is supported and fixed through a micro-dot matrix; annealing the doped amorphous silicon layer, and crystallizing the doped amorphous silicon layer into a polycrystalline silicon layer; respectively depositing stress-coordinated silicon nitride covering layers on the front surface and the back surface to balance the intrinsic stress of the polycrystalline silicon layer; finally, optimized sintering treatment is carried out, the peak temperature is lower than that of a conventional PERC battery, a slow cooling area is arranged, and through optimized transmission, thin film deposition, annealing and sintering processes, the manufacturing efficiency and the yield of the ultrathin TOPCon battery are improved, physical damage in the transmission process is reduced, the fragment rate is reduced, the thin film stress is effectively balanced, and the stability of the battery is ensured.

Description

Technical Field

[0001] This invention relates to the field of high-efficiency crystalline silicon solar cell manufacturing technology, and in particular to a stress-coordinated control and low-damage manufacturing method and system for ultra-thin TOPCon cells. Background Technology

[0002] TOPCon (Tunneling Oxide Passivated Contact) cells are a type of high-efficiency crystalline silicon solar cell that uses an ultrathin tunneling oxide layer and amorphous or nanocrystalline silicon layers as passivation contact structures to improve charge collection efficiency on the silicon wafer surface. Compared to traditional PERC cells, this technology offers performance advantages, particularly in reducing carrier recombination and increasing open-circuit voltage. Ultrathin TOPCon cells refer to silicon wafers with a thickness of less than 80 micrometers, and some even as low as 50 micrometers. This technological trend helps reduce material costs, but it also makes the cells more susceptible to breakage and warping during manufacturing, especially in high-temperature processes such as thin-film deposition and annealing. Therefore, controlling the stress generated during manufacturing to avoid damage to the ultrathin silicon wafer is crucial for improving the manufacturing yield of ultrathin TOPCon cells.

[0003] In existing technologies, the manufacturing of ultrathin TOPCon cells mainly focuses on three aspects: thin film deposition, annealing, and silicon wafer transport technology. However, existing technologies still have some problems that limit further optimization of ultrathin TOPCon cells. First, during the multilayer film deposition process, the difference in thermal expansion coefficients between different layers can easily lead to stress mismatch, which in turn causes warping and cracking of the silicon wafer, especially on ultrathin silicon wafers. Second, during the annealing process, the volume shrinkage and lattice changes that accompany the conversion of amorphous silicon to polycrystalline silicon generate huge internal stresses. Existing annealing processes have failed to effectively control the heating rate, leading to stress accumulation and increasing the breakage rate. Finally, traditional silicon wafer transport methods mostly use negative pressure adsorption, which can easily damage the precision structure on the back of the silicon wafer during high-temperature processes, affecting the passivation effect and potentially causing crack propagation. Therefore, existing technologies have failed to effectively solve the stress control problem in the manufacturing process of ultrathin TOPCon cells, and a new solution is urgently needed to reduce the breakage rate and improve cell performance.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the general background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] This invention provides a method and system for stress synergistic control and low-damage manufacturing of ultrathin TOPCon batteries, thereby effectively solving the problems in the prior art.

[0006] To achieve the above objectives, the technical solution adopted by this invention is: a method for stress synergistic regulation and low-damage manufacturing of ultra-thin TOPCon batteries, comprising the following steps: We provide crystalline silicon wafers with a thickness of less than 80 micrometers; A passivation contact precursor structure is prepared on the back side of the crystalline silicon wafer, the passivation contact precursor structure comprising at least an ultrathin tunneling oxide layer and a doped amorphous silicon layer; A composite transmission system is used to transport the crystalline silicon wafer. The composite transmission system is used to fix the crystalline silicon wafer by electrostatic adsorption at transmission stations involving high-temperature processes, and by micro-matrix support at non-high-temperature transmission stations. The doped amorphous silicon layer is annealed to crystallize it into a polycrystalline silicon layer, forming a complete passivation contact structure. On the back side of the silicon wafer with the passivated contact structure and on the front side of the crystalline silicon wafer, a back cover layer and a front cover layer with opposite stress states are deposited respectively. The stress of the back cover layer and the front cover layer works synergistically to balance the intrinsic stress of the polycrystalline silicon layer. The crystalline silicon wafer with completed electrode printing is subjected to sintering treatment. The sintering treatment adopts an optimized sintering temperature profile. The peak temperature of the sintering temperature profile is lower than that of conventional PERC cells, and a slow cooling zone is set in the cooling stage.

[0007] Furthermore, the use of a composite transmission system for transmission specifically includes: Determine whether the current transmission path of the crystalline silicon wafer involves a high-temperature process; If the transmission path involves a high-temperature process such as annealing or sintering, the electrostatic adsorption unit of the composite transmission system is activated to fix and transmit the crystalline silicon wafer with non-contact electrostatic force. If the transmission path does not involve the high-temperature process, the micro-matrix support unit of the composite transmission system is activated, and the crystalline silicon wafer is contacted and supported by a number of tiny bumps on its surface for transmission. The tiny bumps are configured to contact only the edge region or dicing region of the crystalline silicon wafer.

[0008] Furthermore, the electrostatic adsorption unit is activated at least during the transfer process before the crystalline silicon wafer is loaded into the annealing equipment and before it is loaded into the sintering equipment.

[0009] Furthermore, the annealing treatment performed on the doped amorphous silicon layer specifically includes: The first step is annealing, in which the crystalline silicon wafer carrying the passivated contact precursor structure is annealed at a temperature of 500°C to 600°C for a first preset time, so that the doped amorphous silicon layer partially crystallizes. The second step, annealing, involves heating the crystalline silicon wafer after the first step annealing at a rate of 10°C / second to 25°C / second from the temperature of the first step annealing to a temperature of 800°C to 900°C, and maintaining this temperature at a second preset time to complete the final crystallization of the doped amorphous silicon layer and the activation of the dopant, thus forming the polycrystalline silicon layer.

[0010] Furthermore, the back cover layer is a silicon nitride layer with tensile stress, and the front cover layer is a silicon nitride layer with compressive stress.

[0011] Furthermore, the tensile stress value of the back cover layer is controlled between 50 MPa and 300 MPa, and the compressive stress value of the front cover layer is controlled between 150 MPa and 400 MPa.

[0012] Furthermore, the peak temperature of the sintering temperature curve is 730°C to 780°C, and the cooling rate of the sintering temperature curve from the peak temperature to the slow cooling zone is controlled at 30°C / second to 60°C / second.

[0013] Furthermore, the slow cooling zone specifically refers to a constant-temperature slow cooling platform with a duration between 60 and 150 seconds, set within a temperature range of 450°C to 550°C during the cooling stage.

[0014] Furthermore, before preparing the doped amorphous silicon layer, an intrinsic amorphous silicon layer or a nanocrystalline silicon layer is first deposited on the tunneling oxide layer as a stress buffer layer.

[0015] The present invention also includes a stress-coordinated regulation and low-damage manufacturing system for ultrathin TOPCon batteries, the system comprising: A silicon wafer supply unit for supplying crystalline silicon wafers with a thickness of less than 80 micrometers; A back-side structure fabrication unit is used to fabricate a passivation contact precursor structure on the back side of the crystalline silicon wafer, wherein the passivation contact precursor structure includes at least an ultrathin tunneling oxide layer and a doped amorphous silicon layer. A composite transmission unit is used to transmit the crystalline silicon wafer using a composite transmission system. The composite transmission system is used to fix the crystalline silicon wafer by electrostatic adsorption at transmission stations involving high-temperature processes, and by micro-matrix support at non-high-temperature transmission stations. The annealing unit is used to anneal the doped amorphous silicon layer to crystallize it into a polycrystalline silicon layer and form a complete passivation contact structure. A stress deposition unit is used to deposit a back cover layer and a front cover layer with opposite stress states on the back side of the silicon wafer on which the passivation contact structure is formed and on the front side of the crystalline silicon wafer, respectively. The stress synergy between the back cover layer and the front cover layer is used to balance the intrinsic stress of the polycrystalline silicon layer. The sintering unit is used to sinter the crystalline silicon wafer after electrode printing is completed. The sintering process adopts an optimized sintering temperature profile. The peak temperature of the sintering temperature profile is lower than that of conventional PERC cells, and a slow cooling zone is set in the cooling stage.

[0016] The beneficial effects of this invention are as follows: By innovatively optimizing the transport, thin film deposition, annealing, and sintering processes, the manufacturing efficiency and yield of ultra-thin TOPCon cells are improved; by adopting a composite transport system, combined with electrostatic adsorption and micro-lattice support technology, damage to the passivation contact structure on the back of the silicon wafer is avoided by the traditional negative pressure adsorption method, fundamentally reducing the fragmentation rate caused by physical damage during the transport process; at the same time, in the co-design of thin film deposition and stress, a stress balancing strategy for the front and back cover layers is adopted, reducing the risk of warping and cracking caused by stress mismatch of multilayer films, and ensuring the stability of the ultra-thin silicon wafer during the annealing and sintering process.

[0017] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a stress-coordinated control and low-damage manufacturing method for ultrathin TOPCon batteries. Figure 2 This is a flowchart illustrating the transmission process using a composite transmission system. Figure 3 This is a flowchart illustrating the annealing process performed on the doped amorphous silicon layer. Figure 4 This is a schematic diagram of a stress-coordinated control and low-damage manufacturing system for ultra-thin TOPCon batteries. Detailed Implementation

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] Example 1: like Figures 1 to 3 As shown, this application provides a method for stress synergistic control and low-damage manufacturing of ultrathin TOPCon batteries, the method comprising: S10: Provides crystalline silicon wafers with a thickness of less than 80 micrometers; S20: A passivation contact precursor structure is prepared on the back side of a crystalline silicon wafer. The passivation contact precursor structure includes at least an ultrathin tunneling oxide layer and a doped amorphous silicon layer. S30: A composite transport system is used to transport crystalline silicon wafers. The composite transport system is used to fix crystalline silicon wafers by electrostatic adsorption in transport stations involving high-temperature processes; and to fix crystalline silicon wafers by micro-matrix support in non-high-temperature transport stations. S40: Annealing the doped amorphous silicon layer to crystallize it into a polycrystalline silicon layer, forming a complete passivation contact structure; S50: On the back side of the silicon wafer with passivated contact structure and on the front side of the crystalline silicon wafer, a back capping layer and a front capping layer with opposite stress states are deposited respectively. The stress synergy of the back capping layer and the front capping layer is used to balance the intrinsic stress of the polycrystalline silicon layer. S60: The crystalline silicon wafer with completed electrode printing is sintered. The sintering process uses an optimized sintering temperature profile. The peak temperature of the sintering temperature profile is lower than that of conventional PERC cells, and a slow cooling zone is set in the cooling stage.

[0023] First, a crystalline silicon wafer with a thickness of less than 80 micrometers is provided, ensuring good surface flatness and low impurity content. Next, an ultrathin tunneling oxide layer and a doped amorphous silicon layer are fabricated on the back side of the silicon wafer using low-pressure chemical vapor deposition (LPCVD) technology, with the phosphorus-doped amorphous silicon layer having a thickness of 15 nm. Then, the silicon wafer is transported through a composite transport system. In the high-temperature process, electrostatic adsorption is used to fix the silicon wafer, avoiding physical damage to the back structure. In the non-high-temperature process, a micro-lattice support method is used to fix the silicon wafer, further reducing the contact area on the silicon wafer surface and protecting the front structure. During the annealing process, a two-step annealing method is adopted. First, pre-crystallization is performed at a low temperature, followed by crystallization at a high temperature. The heating rate is controlled to ensure uniform heating and avoid stress abrupt changes. After annealing, a silicon nitride layer is deposited on the back of the silicon wafer, and tensile stress is set to counteract the tensile stress of the polycrystalline silicon layer. On the front, a silicon nitride layer with compressive stress is deposited to achieve stress balance. Finally, the silicon wafer after electrode printing enters the sintering process. An optimized sintering temperature profile is adopted, and a slow cooling zone is set to reduce stress concentration during the cooling process, thereby improving the manufacturing efficiency and yield of ultra-thin TOPCon cells.

[0024] By innovatively optimizing transport, thin film deposition, annealing, and sintering processes, the manufacturing efficiency and yield of ultra-thin TOPCon cells are improved. By employing a composite transport system combined with electrostatic adsorption and micro-lattice support technology, damage to the passivation contact structure on the back of the silicon wafer is avoided by traditional negative pressure adsorption methods, fundamentally reducing the breakage rate caused by physical damage during transport. Simultaneously, in thin film deposition and stress synergistic design, a stress balancing strategy for the front and back capping layers is adopted, reducing the risk of warping and cracking caused by multilayer film stress mismatch, ensuring the stability of the ultra-thin silicon wafer during annealing and sintering. Furthermore, by optimizing the annealing and sintering processes, using a two-step annealing and low-temperature sintering curve, excessive stress generated in high-temperature processes is avoided, thereby reducing damage caused by stress accumulation. This method, while reducing the breakage rate, may also further improve the open-circuit voltage and overall electrical performance of the cell. Compared with existing technologies, this invention can improve the manufacturing yield of ultra-thin TOPCon cells and reduce production costs while ensuring cell performance.

[0025] As a preferred embodiment of the above, in step S30, such as Figure 2 As shown, a composite transmission system is used for transmission, specifically including: S31: Determine whether the current transmission path of the crystalline silicon wafer involves high-temperature processes; S32: If the transmission path involves high-temperature processes such as annealing or sintering, the electrostatic adsorption unit of the composite transmission system is activated to fix and transmit the crystalline silicon wafer with non-contact electrostatic force. S33: If the transmission path does not involve high-temperature processes, the micro-matrix support unit of the composite transmission system is activated, which contacts and supports the crystalline silicon wafer through several tiny bumps on its surface for transmission. The tiny bumps are configured to contact only the edge region or dicing region of the crystalline silicon wafer.

[0026] Specifically, the first step is to determine whether the current transmission path involves high-temperature processes. High-temperature processes generally refer to processes such as annealing or sintering of the silicon wafer. These processes may cause thermal stress or physical damage to the ultra-thin silicon wafer. Therefore, an automated judgment system can automatically identify whether a process involves high temperatures based on different process stages and make corresponding adjustments to the transmission method. The judgment process is carried out through a visual recognition system or a sensor system. The sensor can detect the process temperature of the current transmission path and then decide whether to activate the electrostatic adsorption unit or the micro-array support unit. If the current transmission path involves high-temperature processes, such as annealing or sintering, the electrostatic adsorption unit in the composite transmission system is activated. The working principle of the electrostatic adsorption unit is through an electric field. The silicon wafer is non-contactly fixed to the transmission unit, thus avoiding damage caused by physical contact. In specific implementation, the electrostatic adsorption unit consists of a set of electrodes that generate a uniform electric field on the silicon wafer surface, fixing the wafer to the chuck by electrostatic force. The advantage of this method lies in its non-contact nature, making it particularly suitable for the transmission of ultra-thin silicon wafers in high-temperature processes, reducing physical damage caused by traditional clamping or negative pressure adsorption. If the current transmission path does not involve high-temperature processes, a micro-lattice support unit in the composite transmission system is used. The micro-lattice support unit consists of multiple tiny bumps that contact and support the silicon wafer at the edge or dicing area for transmission. Specifically, the micro-lattice support consists of several tiny bumps disposed on the surface of the transmission unit. The transport system consists of bumps, typically made of wear-resistant, low-friction materials such as specialty ceramics, polymers, or surface-treated metals. The bumps are usually micrometer-sized, with their height and density optimized to ensure stable support while minimizing contact area with the silicon wafer. These bumps are formed on the surface of the transport unit using processes such as precision machining, photolithography, or micro-injection molding. The bumps are precisely configured so that they contact only the edge or scriber areas of the silicon wafer when supporting it. The edge area refers to the outermost non-cell active area of ​​the silicon wafer, while the scriber area refers to the non-active area reserved during wafer manufacturing for subsequent cutting. To achieve precise positioning, the transport system... Typically, a high-precision visual positioning system or mechanical limiting mechanism is integrated to ensure that the bump array is always aligned with the edge or scriber area of ​​the silicon wafer during pick-and-place. Through the above technical solution, the bumps of the micro-array support are configured to contact only the edge or scriber area of ​​the crystalline silicon wafer, effectively avoiding contact between the support points and the active area of ​​the ultrathin crystalline silicon wafer. This reduces the risk of mechanical damage, surface contamination, or stress concentration to the ultrathin crystalline silicon wafer during non-high-temperature transport. Given the inherent fragility of ultrathin crystalline silicon wafers, precise support is crucial for maintaining the integrity of the wafer, thereby ensuring the smooth progress of subsequent processes, improving the yield and final performance of the cells, and achieving low-damage manufacturing of ultrathin TOPCon cells.

[0027] In the manufacturing process of ultrathin TOPCon cells, the transfer and fixation of crystalline silicon wafers at different process stages are crucial, especially when high-temperature processes are involved. It is necessary to ensure that the silicon wafers are stable and undamaged. Although the composite transfer system can select different fixation methods according to the process temperature, in actual operation, how to accurately activate electrostatic adsorption before the critical high-temperature process to minimize stress concentration and deformation of the silicon wafer during the transfer process is still a problem that needs careful consideration.

[0028] In response, in step S32, the electrostatic adsorption unit is activated at least during the transfer process before loading the crystalline silicon wafers into the annealing equipment and before loading them into the sintering equipment. Specifically, by activating electrostatic adsorption during the transfer process before the annealing and sintering processes, it can be ensured that the ultrathin crystalline silicon wafers are always in a stable, non-mechanically contacted fixed state before entering these two critical high-temperature processing stages. The control system of the composite transfer system is interlocked with the main control system of the production line. When the silicon wafers enter the loading station of the annealing furnace or sintering furnace, the system automatically moves the end effector of the transfer robot. The device switches and activates to electrostatic chuck mode. The uniform adsorption force provided by electrostatic adsorption effectively avoids stress concentration, scratches, or electrode pattern damage that may be caused by traditional mechanical clamping. This is especially important for ultra-thin silicon wafers with a thickness of less than 80 micrometers, which are more fragile. Activating this non-contact fixing method before annealing can prevent the silicon wafer from deforming during high-temperature transport; activating it before sintering can protect the printed electrode pattern. Precise activation timing reduces the breakage rate and defect generation of ultra-thin silicon wafers during high-temperature transport, thereby improving the yield and performance stability of the battery.

[0029] As a preferred embodiment of the above, in step S40, as Figure 3 As shown, the annealing treatment performed on the doped amorphous silicon layer specifically includes: S41: The first step of annealing is to anneal the crystalline silicon wafer carrying the passivation contact precursor structure at a temperature of 500°C to 600°C for a first preset time, so that the doped amorphous silicon layer partially crystallizes. S42: The second annealing process involves heating the crystalline silicon wafer after the first annealing to a temperature of 800°C to 900°C at a heating rate of 10°C / second to 25°C / second, and maintaining this temperature for a second preset time. This completes the final crystallization of the doped amorphous silicon layer and the activation of the dopant, forming a polycrystalline silicon layer. In this embodiment, the first annealing is performed within a temperature range of 500°C to 600°C. During this stage, the annealing time is controlled to be 30 to 60 seconds, with the goal of crystallizing the doped amorphous silicon layer. Separate crystallization: After the first annealing step, the target crystallinity is controlled between 30% and 60%, which can be characterized by the change in the full width at half maximum (FWHM) of the characteristic peaks of amorphous silicon in the Raman spectrum. This process also begins to eliminate some of the stress introduced by the doping process. To avoid over-crystallization, the annealing time should not be too long, ensuring that the amorphous silicon layer retains certain amorphous characteristics after annealing, preparing for the second annealing step. This second annealing step should employ a precise temperature control system, rapidly heating to the set temperature while ensuring the annealing atmosphere is nitrogen or a nitrogen-oxygen mixture to prevent surface defects on the silicon wafer. Oxidation phenomenon; the second annealing temperature is set between 800°C and 900°C, with the goal of completing the final crystallization of the amorphous silicon layer and activating the dopant to form a stable n-type polycrystalline silicon layer. The heating rate of the second annealing should be controlled between 10°C / second and 25°C / second. This heating rate ensures temperature uniformity during annealing and prevents thermal stress on the silicon wafer due to excessive temperature fluctuations, thereby reducing the breakage rate. During this process, the atmosphere of the silicon wafer should still be controlled in nitrogen or a nitrogen-oxygen mixture, which helps to further eliminate oxidants generated during the doping process and ensure the purity and crystal quality of the silicon wafer surface. Through the two-step annealing process, the crystallization process of the doped amorphous silicon layer can be effectively controlled. The first step, low-temperature annealing, partially crystallizes the amorphous silicon layer, effectively reducing the thermal stress generated during crystallization. The second step, high-temperature annealing, completes the final crystallization of the amorphous silicon layer and activates the dopant to form a stable polycrystalline silicon layer. The entire process, by controlling the temperature and heating rate, avoids stress accumulation caused by excessively rapid temperature changes, thereby reducing the breakage rate of the silicon wafer.

[0030] In this embodiment, in step S50, the back cover layer is a silicon nitride layer with tensile stress, and the front cover layer is a silicon nitride layer with compressive stress. Specifically, the back cover layer is configured as a silicon nitride layer with tensile stress. Silicon nitride is a dielectric thin film material widely used in the semiconductor field. Its film stress can be precisely controlled by deposition process parameters. When used as a back cover layer, by adjusting the gas flow ratio in processes such as plasma-enhanced chemical vapor deposition (PECVD), such as the ratio of silane to ammonia, radio frequency power, and deposition temperature, a silicon nitride film with specific tensile stress can be prepared. This tensile stress can effectively counteract the intrinsic compressive stress generated during the crystallization process of the polycrystalline silicon layer, thereby reducing the overall stress imbalance of the silicon wafer. Simultaneously, the front cover layer is configured as a silicon nitride layer with compressive stress. Similar to the back cover layer, the silicon nitride film of the front cover layer can also be precisely controlled by adjusting the chemical vapor deposition process parameters. To achieve the desired compressive stress, for example, by optimizing the ratio of silicon source gas to nitrogen source gas, or by adjusting the deposition temperature and power, a silicon nitride layer with specific compressive stress can be achieved. In addition to providing compressive stress to coordinate with the back cover layer for stress regulation, the front cover layer usually also has anti-reflection and surface passivation functions, further improving the photoelectric conversion efficiency of the battery. By specifically defining the back cover layer as a silicon nitride layer with tensile stress and the front cover layer as a silicon nitride layer with compressive stress, a clear and controllable stress regulation scheme is provided. As a thin film material, the stress state of silicon nitride can be precisely controlled through deposition process parameters, thereby ensuring that the back and front cover layers can generate the expected tensile and compressive stresses. This specific stress synergy can effectively offset the intrinsic stress generated by the polycrystalline silicon layer in the ultrathin crystalline silicon wafer, reduce the risk of warping and cracking of the silicon wafer during subsequent high-temperature processing, and improve the mechanical stability of the battery.

[0031] The tensile stress of the back cover layer is controlled between 50 MPa and 300 MPa, while the compressive stress of the front cover layer is controlled between 150 MPa and 400 MPa. The tensile stress of the back cover layer refers to the force within it resisting tensile deformation. Its presence helps to offset the intrinsic compressive stress that may exist in the polycrystalline silicon layer, thereby reducing the overall deformation of the silicon wafer. Precisely controlling this tensile stress within the range of 50 MPa to 300 MPa aims to ensure effective balance of internal stress within the silicon wafer, while preventing wafer cracking or film delamination due to excessive stress. This tensile stress value can be achieved by adjusting thin film deposition process parameters. For example, in plasma-enhanced chemical vapor deposition, the internal stress state of the film can be precisely controlled by optimizing parameters such as the flow ratio of silane to ammonia, deposition temperature, RF power, or chamber pressure. For instance, appropriately increasing the silane flow rate or decreasing the ammonia flow rate generally helps to form a film with tensile stress. Meanwhile, the compressive stress of the front cover layer refers to the force within it resisting compressive deformation, which is related to the stress of the back cover layer. The synergistic effect of tensile stress further refines the stress distribution across the entire silicon wafer, controlling the compressive stress value between 150MPa and 400MPa. This aims to provide sufficient compressive stress to effectively synergize with the tensile stress on the back side, jointly offsetting the intrinsic stress of the polycrystalline silicon layer and ensuring good flatness of the ultrathin silicon wafer during subsequent high-temperature processing, preventing warping and breakage. This compressive stress value can also be achieved by adjusting the deposition process parameters. This achieves refined synergistic control of the intrinsic stress of the polycrystalline silicon layer in ultrathin TOPCon cells. The tensile stress of the back cover layer and the compressive stress of the polycrystalline silicon layer cancel each other out, while the compressive stress of the front cover layer further provides auxiliary support, working together on the entire silicon wafer to form a stable stress balance system. Precise stress control avoids warping, cracking, or breakage of the ultrathin silicon wafer due to stress mismatch, significantly improving the mechanical stability of ultrathin crystalline silicon wafers with a thickness of less than 80 micrometers in subsequent high-temperature processes such as sintering, effectively reducing the breakage rate, and ensuring the yield rate of the cells during manufacturing and the reliability of the final product.

[0032] As a preferred embodiment, in step S60, the peak temperature of the sintering temperature curve is 730°C to 780°C, which aims to provide an optimized thermal treatment window for the ultrathin TOPCon cell. This temperature range ensures good ohmic contact between the metal particles in the electrode paste and the silicon wafer surface, promotes dopant activation, and optimizes the interface characteristics between the passivation layer and the metal electrode. Simultaneously, it avoids excessive thermal stress on ultrathin silicon wafers with a thickness of less than 80 micrometers caused by excessively high temperatures in traditional sintering processes. Excessively high peak temperatures can lead to silicon wafer deformation, microcrack formation, and even affect the stability of the passivation contact structure. Therefore, setting this peak temperature is crucial for balancing the battery's electrical performance with the mechanical integrity of the ultrathin silicon wafer. The cooling rate from the peak temperature to the slow cooling zone in the sintering temperature curve is controlled at 30°C / second to 60°C / second. This cooling rate can be achieved by controlling the airflow or heat dissipation power of the cooling section of the sintering furnace, thereby effectively managing the thermal stress borne by the ultrathin silicon wafer during the rapid cooling phase. An excessively rapid cooling rate can cause significant thermal stress to form inside the silicon wafer. Temperature gradients, and the resulting thermal stress, can easily cause silicon wafer warping, microcracks, or even breakage. Conversely, excessively slow cooling rates can lead to over-reaction at the metal-silicon interface, affecting the battery's electrical performance. By precisely controlling the peak temperature of the sintering temperature curve within an optimized range of 730℃ to 780℃, the overall thermal load on the ultrathin crystalline silicon wafer during high-temperature sintering is effectively reduced. This avoids structural damage to the silicon wafer and degradation of the passivation layer due to excessively high temperatures, while ensuring good ohmic contact between the electrodes and the silicon wafer. Furthermore, by controlling the cooling rate from the peak temperature to the slow cooling zone within a specific range of 30℃ / second to 60℃ / second, thermal stress during the rapid cooling phase of the silicon wafer can be effectively managed, preventing mechanical damage such as warping and microcracks caused by excessively rapid cooling. This improves the mechanical integrity and production yield of the ultrathin TOPCon battery, while ensuring its electrical performance. The refined temperature curve control, while ensuring sintering effectiveness, minimizes damage to the ultrathin silicon wafer, enhancing the battery's reliability and stability.

[0033] In this embodiment, in step S60, the slow cooling zone specifically refers to: during the cooling stage, a constant-temperature slow cooling platform with a duration between 60 and 150 seconds is set within a temperature range of 450°C to 550°C. Specifically, the slow cooling zone refers to maintaining the crystalline silicon wafer within a relatively constant temperature range during the cooling stage of the sintering process to slow down its temperature drop rate, thereby reducing thermal stress. This constant-temperature slow cooling platform is typically achieved by precisely controlling the temperature range or transport speed of the sintering furnace. For example, one or more areas with independent temperature control are set in the cooling section of the sintering furnace. When the silicon wafer enters these areas, the furnace temperature is maintained within a preset constant temperature range. Alternatively, the residence time of the silicon wafer in a specific temperature range can be adjusted. This allows for slow cooling. By setting up a constant-temperature slow-cooling platform with a specific temperature range and duration during the cooling stage of the sintering process, the cooling rate of the ultrathin crystalline silicon wafer can be effectively controlled. Within the temperature range of 450℃ to 550℃, the thermal stress inside the silicon wafer can be fully and uniformly released, avoiding mechanical damage caused by excessive instantaneous temperature differences due to rapid cooling, such as wafer warping or cracking. At the same time, the appropriate slow-cooling time, 60 to 150 seconds, ensures that the stress between key layers such as the passivation contact structure and the capping layer is effectively and synergistically regulated, thereby maintaining the integrity and stability of the battery structure, reducing the risk of damage to the ultrathin silicon wafer after high-temperature processing, and improving the electrical performance and manufacturing yield of the battery.

[0034] In step S20, before preparing the doped amorphous silicon layer, an intrinsic amorphous silicon layer or a nanocrystalline silicon layer is deposited on the tunneling oxide layer as a stress buffer layer. The stress buffer layer has a thickness of 2-10 nanometers and achieves carrier transport through the quantum tunneling effect while providing excellent surface passivation. Due to its extremely thin characteristics, the tunneling oxide layer is very sensitive to stress generated by subsequent deposition processes. Any excessive stress may damage its structural integrity, thereby affecting the open-circuit voltage and fill factor of the battery. The intrinsic amorphous silicon layer refers to an undoped amorphous silicon thin film. Its disordered atomic structure gives it a certain degree of flexibility, which can effectively absorb and disperse the mechanical stress generated by subsequent deposition layers. The stress buffer layer is preferably deposited continuously in the same low-pressure chemical vapor deposition equipment as the doped amorphous silicon layer. Specifically, after growing the tunneling oxide layer, silane gas is introduced into the reaction chamber, but a phosphorus source is not introduced. An intrinsic amorphous silicon layer of 2-10 nm thickness is deposited at 500-550 °C, followed by the deposition of a doped amorphous silicon layer using a phosphorus source. By depositing an intrinsic amorphous silicon layer or nanocrystalline silicon layer on the tunneling oxide layer as a stress buffer layer, this buffer layer can effectively absorb and disperse the mechanical stress generated during the preparation of the doped amorphous silicon layer, reducing the risk of damage to the ultrathin tunneling oxide layer that may be caused by direct deposition, ensuring its structural integrity and excellent passivation performance. At the same time, the presence of the stress buffer layer also alleviates the warping or breakage problem caused by stress accumulation during the subsequent high-temperature annealing and sintering of the ultrathin crystalline silicon wafer, thereby improving the mechanical stability, process yield and final electrical performance of the ultrathin TOPCon cell.

[0035] The technical solution is as follows: Firstly, a composite transmission system is provided.

[0036] For the sensitive structure on the back of TOPCon, an innovative approach combining electrostatic adsorption and front micro-matrix support is adopted. Electrostatic adsorption: In the transfer of high-temperature processes (such as annealing and sintering), electrostatic chucks are used. This is a non-contact (or extremely low contact pressure) fixing method. The silicon wafer is firmly adsorbed by electrostatic force, which completely avoids the physical pressure and contamination of the back structure by the negative pressure chuck. It is especially suitable for TOPCon structures with precision films on the back.

[0037] Front-side micro-matrix support: In non-high-temperature environments, the surface of the transmission unit is designed with a tiny array of bumps. These bumps only contact the most robust edge area or dicing area of ​​the silicon wafer, minimizing the contact area with the effective area of ​​the cell, thereby avoiding indentations or stress concentrations on the front-side grid lines or anti-reflection film.

[0038] Secondly, stress-coordinated design is proposed.

[0039] Backside stress buffer and capping layer design: Before depositing the doped amorphous silicon layer, an extremely thin intrinsic amorphous silicon / nanocrystalline silicon layer is deposited as a stress buffer layer, which can relax the stress of the subsequent polycrystalline silicon layer. At the same time, the backside silicon nitride capping layer is deposited in a tensile stress state, which can partially offset the inherent strong tensile stress of the polycrystalline silicon layer.

[0040] Front-side stress matching design: The front-side silicon nitride antireflection layer is deposited in a strong compressive stress state. By precisely controlling the stress matching between the front (compressive stress) and the back (achieving near-neutral or micro-tensile stress through design), the entire silicon wafer is stress-balanced like a "sandwich", reducing overall warpage and making it more stable and less prone to breakage during transmission.

[0041] Thirdly, optimize the annealing and sintering processes.

[0042] Two-step annealing method: The crystallization process of amorphous silicon is divided into two steps. First, it is partially crystallized and its structure is relaxed at a lower temperature (~550℃). Then, it is rapidly heated to the target temperature for final crystallization and doping activation. This "preheating" process avoids the severe thermal shock and stress change caused by directly heating from room temperature to high temperature. At the same time, the heating rate is strictly controlled to prevent stress accumulation caused by excessively rapid heating.

[0043] Low-temperature sintering and slow cooling: Considering the sensitivity of the TOPCon structure to high temperatures, the peak sintering temperature is appropriately reduced (e.g., 750℃) to reduce the thermal budget. At the same time, a slow cooling platform is set in the critical temperature range of the cooling stage (about 500℃) to allow sufficient time for the stress between the metal electrode and silicon, as well as between the various film layers, to relax.

[0044] Example 2: Manufacturing an N-type TOPCon battery with a thickness of 65 micrometers 1. Prepare silicon wafers: Provide N-type Czochralski single-crystal silicon wafers with a thickness of 65±3 micrometers.

[0045] 2. Preliminary treatment of the front and back sides: Perform routine steps such as front boron diffusion and removal of the back PN junction.

[0046] 3. Fabrication of the back-side TOPCon structure: A tunneling silicon oxide layer of approximately 1.5 nm is grown on the back side of the silicon wafer through thermal oxidation.

[0047] An intrinsic amorphous silicon stress buffer layer of approximately 5 nm and a phosphorus-doped amorphous silicon layer of approximately 100 nm were sequentially deposited using LPCVD.

[0048] 4. Composite Transmission and Annealing: A robotic arm equipped with electrostatic adsorption is used to transfer silicon wafers from the LPCVD furnace to the rapid annealing furnace.

[0049] The RTP process involves two steps of annealing: first, pre-crystallization is performed by holding the temperature at 580°C for 30 seconds, and then final crystallization and propagation are performed by increasing the temperature to 850°C at a rate of 15°C / second and holding for 15 seconds. The annealing atmosphere is a nitrogen-oxygen mixture.

[0050] 5. Depositional overburden and stress regulation: A silicon nitride layer of approximately 80 nm was deposited on the crystallized polycrystalline silicon back surface using PECVD. By adjusting the deposition power and gas pressure, the stress of this layer was controlled at approximately +150 MPa (tensile stress).

[0051] On the front side of the silicon wafer, a silicon oxide / silicon nitride stack is deposited by PECVD, wherein the stress of the silicon nitride layer is controlled at around -300 MPa (compressive stress).

[0052] 6. Electrode printing and optimized sintering: Complete the screen printing on both the front and back sides.

[0053] The optimized curve was executed in the sintering furnace: peak temperature 755℃, during the cooling stage, a slow cooling plateau was set at 500℃ for 120 seconds, and then it was allowed to cool naturally to room temperature.

[0054] Comparative example: Using the same 65-micron silicon wafer, the standard TOPCon process employs conventional negative pressure transmission, one-step high-temperature annealing (directly 850°C), and no stress co-design.

[0055] result: The batch produced using the method of this invention has a total breakage rate of 4.2% from silicon wafer to finished battery. The comparative example has a total breakage rate as high as 22.8%. Furthermore, due to the reduction in stress and the improvement in passivation effect, the average open-circuit voltage (Voc) of the battery prepared by this invention is 1-2 mV higher than that of the comparative example.

[0056] Example 2: This invention also includes a stress-coordinated regulation and low-damage manufacturing system for ultra-thin TOPCon batteries, such as... Figure 4 As shown, the system includes: A silicon wafer supply unit for supplying crystalline silicon wafers with a thickness of less than 80 micrometers; The back-side structure fabrication unit is used to fabricate a passivation contact precursor structure on the back side of a crystalline silicon wafer. The passivation contact precursor structure includes at least an ultrathin tunneling oxide layer and a doped amorphous silicon layer. A composite transmission unit is used to transport crystalline silicon wafers using a composite transmission system. The composite transmission system is used to fix crystalline silicon wafers in transmission stations involving high-temperature processes using electrostatic adsorption; and to fix crystalline silicon wafers in non-high-temperature transmission stations using a micro-matrix support method. The annealing unit is used to anneal the doped amorphous silicon layer to crystallize it into a polycrystalline silicon layer and form a complete passivation contact structure. The stress deposition unit is used to deposit back capping layers and front capping layers with opposite stress states on the back side of a silicon wafer with passivated contact structures and on the front side of a crystalline silicon wafer, respectively. The stress synergy between the back capping layer and the front capping layer is used to balance the intrinsic stress of the polycrystalline silicon layer. The sintering unit is used to sinter the crystalline silicon wafers after electrode printing. The sintering process adopts an optimized sintering temperature profile, the peak temperature of which is lower than that of conventional PERC cells, and a slow cooling zone is set in the cooling stage.

[0057] The adjustment system described above in this invention can effectively realize stress synergistic regulation and low-damage manufacturing method for ultra-thin TOPCon batteries. The technical effects it can achieve are as described in the above embodiments, and will not be repeated here.

[0058] Similarly, the above-mentioned optimization schemes for the system can also achieve the optimization effects corresponding to the methods in Embodiment 1, which will not be repeated here.

[0059] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and accompanying drawings are merely exemplary illustrations of the application as defined herein, and are to be considered as covering any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from its scope. Thus, if such modifications and modifications fall within the scope of this application and its equivalents, this application intends to include such modifications and modifications.

Claims

1. A method for stress synergistic regulation and low-damage manufacturing of ultrathin TOPCon batteries, characterized in that, The method includes: We provide crystalline silicon wafers with a thickness of less than 80 micrometers; A passivation contact precursor structure is prepared on the back side of the crystalline silicon wafer, the passivation contact precursor structure comprising at least an ultrathin tunneling oxide layer and a doped amorphous silicon layer; A composite transmission system is used to transport the crystalline silicon wafer. The composite transmission system is used to fix the crystalline silicon wafer by electrostatic adsorption at transmission stations involving high-temperature processes, and by micro-matrix support at non-high-temperature transmission stations. The doped amorphous silicon layer is annealed to crystallize it into a polycrystalline silicon layer, forming a complete passivation contact structure. On the back side of the silicon wafer with the passivated contact structure and on the front side of the crystalline silicon wafer, a back cover layer and a front cover layer with opposite stress states are deposited respectively. The stress of the back cover layer and the front cover layer works synergistically to balance the intrinsic stress of the polycrystalline silicon layer. The crystalline silicon wafer with completed electrode printing is subjected to sintering treatment. The sintering treatment adopts an optimized sintering temperature profile. The peak temperature of the sintering temperature profile is lower than that of conventional PERC cells, and a slow cooling zone is set in the cooling stage.

2. The stress-coordinated control and low-damage manufacturing method for ultra-thin TOPCon batteries according to claim 1, characterized in that, The use of a composite transmission system for transmission specifically includes: Determine whether the current transmission path of the crystalline silicon wafer involves a high-temperature process; If the transmission path involves a high-temperature process such as annealing or sintering, the electrostatic adsorption unit of the composite transmission system is activated to fix and transmit the crystalline silicon wafer with non-contact electrostatic force. If the transmission path does not involve the high-temperature process, the micro-matrix support unit of the composite transmission system is activated, and the crystalline silicon wafer is contacted and supported by a number of tiny bumps on its surface for transmission. The tiny bumps are configured to contact only the edge region or dicing region of the crystalline silicon wafer.

3. The stress synergistic control and low-damage manufacturing method for ultra-thin TOPCon batteries according to claim 2, characterized in that, The electrostatic adsorption unit is activated at least during the transfer process before the crystalline silicon wafer is loaded into the annealing equipment and before it is loaded into the sintering equipment.

4. The stress-coordinated control and low-damage manufacturing method for ultra-thin TOPCon batteries according to claim 1, characterized in that, The annealing process performed on the doped amorphous silicon layer specifically includes: The first step is annealing, in which the crystalline silicon wafer carrying the passivated contact precursor structure is annealed at a temperature of 500°C to 600°C for a first preset time, so that the doped amorphous silicon layer partially crystallizes. The second step, annealing, involves heating the crystalline silicon wafer after the first step annealing at a rate of 10°C / second to 25°C / second from the temperature of the first step annealing to a temperature of 800°C to 900°C, and maintaining this temperature at a second preset time to complete the final crystallization of the doped amorphous silicon layer and the activation of the dopant, thereby forming the polycrystalline silicon layer.

5. The stress-coordinated control and low-damage manufacturing method for ultra-thin TOPCon batteries according to claim 1, characterized in that, The back cover layer is a silicon nitride layer with tensile stress, and the front cover layer is a silicon nitride layer with compressive stress.

6. The method for stress synergistic regulation and low-damage manufacturing of ultra-thin TOPCon batteries according to claim 5, characterized in that, The tensile stress value of the back cover layer is controlled between 50 MPa and 300 MPa, and the compressive stress value of the front cover layer is controlled between 150 MPa and 400 MPa.

7. The method for stress synergistic regulation and low-damage manufacturing of ultra-thin TOPCon batteries according to claim 1, characterized in that, The peak temperature of the sintering temperature curve is 730°C to 780°C, and the cooling rate of the sintering temperature curve from the peak temperature to the slow cooling zone is controlled at 30°C / second to 60°C / second.

8. The method for stress synergistic regulation and low-damage manufacturing of ultra-thin TOPCon batteries according to claim 1, characterized in that, The slow cooling zone specifically refers to a constant-temperature slow cooling platform with a duration of 60 to 150 seconds set within a temperature range of 450°C to 550°C during the cooling stage.

9. The method for stress synergistic regulation and low-damage manufacturing of ultra-thin TOPCon batteries according to claim 1, characterized in that, Before preparing the doped amorphous silicon layer, an intrinsic amorphous silicon layer or a nanocrystalline silicon layer is first deposited on the tunneling oxide layer as a stress buffer layer.

10. A stress-coordinated control and low-damage manufacturing system for ultra-thin TOPCon batteries, characterized in that, The system includes: A silicon wafer supply unit for supplying crystalline silicon wafers with a thickness of less than 80 micrometers; A back-side structure fabrication unit is used to fabricate a passivation contact precursor structure on the back side of the crystalline silicon wafer, wherein the passivation contact precursor structure includes at least an ultrathin tunneling oxide layer and a doped amorphous silicon layer. A composite transmission unit is used to transmit the crystalline silicon wafer using a composite transmission system. The composite transmission system is used to fix the crystalline silicon wafer by electrostatic adsorption at transmission stations involving high-temperature processes, and by micro-matrix support at non-high-temperature transmission stations. The annealing unit is used to anneal the doped amorphous silicon layer to crystallize it into a polycrystalline silicon layer and form a complete passivation contact structure. A stress deposition unit is used to deposit a back cover layer and a front cover layer with opposite stress states on the back side of the silicon wafer on which the passivation contact structure is formed and on the front side of the crystalline silicon wafer, respectively. The stress synergy between the back cover layer and the front cover layer is used to balance the intrinsic stress of the polycrystalline silicon layer. The sintering unit is used to sinter the crystalline silicon wafer after electrode printing is completed. The sintering process adopts an optimized sintering temperature profile. The peak temperature of the sintering temperature profile is lower than that of conventional PERC cells, and a slow cooling zone is set in the cooling stage.

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