Flip-chip LED chip and method for manufacturing the same
By designing interdigitated electrodes and a refined insulating layer sidewall structure in flip-chip LEDs, the problem of poor electrode coating effect was solved, improving chip reliability and light emission uniformity, and achieving uniform current distribution and improved light extraction efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JIANGXI ZHAO CHI SEMICON CO LTD
- Filing Date
- 2026-03-25
- Publication Date
- 2026-05-29
AI Technical Summary
In the circular or polygonal structure of conventional flip-chip LEDs, there are a large number of electrodes and a large height difference between the N-type conductive steps and the P-type semiconductor layer, which leads to a poor electrode coating effect and reduces the reliability of the LED chip.
A flip-chip LED structure was designed, in which P-type electrodes and N-type electrodes are distributed in an interdigitated manner. The first N-type electrode includes a first sub-N-type electrode and a second sub-N-type electrode. The tilt angle is α=β, the tilt angle of the insulating layer sidewall is γ=δ, and the height of the insulating layer is H1=H2. By refining the electrode distribution and the insulating layer design, the electrode adhesion is improved and the interface stress concentration is reduced.
It improves the coverage of the electrodes, avoids metal stripping, enhances the reliability and light emission uniformity of the chip, and improves the uniformity of current spread and light extraction efficiency.
Smart Images
Figure CN121924911B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of optoelectronic manufacturing technology, and in particular to a flip-chip LED and its fabrication method. Background Technology
[0002] Flip-chip LEDs are widely used due to their advantages such as back-emitting light, good solderability, high thrust, and high reliability. The light-emitting structure of a conventional flip-chip LED is quadrilateral. In recent years, with the application of LEDs in automotive lights, flashlights, and other fields, there has been a growing need to manufacture irregularly shaped LED chips such as round and polygonal ones.
[0003] For flip-chip LEDs with circular or polygonal structures, there are a large number of electrodes on the chip edges. Due to the large height difference between the N-type conductive steps and the P-type semiconductor layer at the edges, the electrode coating effect is often worse, and the reliability of the LED chip is reduced. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a flip-chip LED with high reliability.
[0005] Accordingly, the present invention also provides a method for preparing the above-mentioned flip-chip LED.
[0006] To solve the above-mentioned technical problems, the present invention provides a flip-chip LED, comprising: a substrate, an epitaxial layer, a reflective layer, a first insulating layer, a P-type electrode, an N-type electrode, a second insulating layer, a P-type pad layer and an N-type pad layer stacked on the substrate;
[0007] The epitaxial layer includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer sequentially stacked on the substrate. A light-emitting structure, an isolation trench, and an N-type conductive step are formed on the epitaxial layer. The N-type conductive step is disposed on one side of the light-emitting structure and exposes the N-type semiconductor layer. The isolation trench is disposed around the light-emitting structure and exposes the substrate.
[0008] The P-type electrode and the N-type electrode are arranged in an interdigitated pattern, and the electrode located on the outermost side of the light-emitting structure is the first N-type electrode; the first N-type electrode includes a first sub-N-type electrode and a second sub-N-type electrode; the first sub-N-type electrode is located above the N-type conductive step, and the second sub-N-type electrode is located above the P-type semiconductor layer;
[0009] The first sub-N-type electrode has a first sidewall on the side near the isolation trench, and the inclination angle of the first sidewall is α; the second sub-N-type electrode has a second sidewall on the side near the edge of the P-type semiconductor layer, and the inclination angle of the second sidewall is β.
[0010] α=β.
[0011] As an improvement to the above technical solution, the first insulating layer below the first sub-N-type electrode has a third sidewall, which is located between the light-emitting structure and the isolation groove, and the inclination angle of the third sidewall is γ.
[0012] The first insulating layer below the second sub-N-type electrode has a fourth sidewall, which is disposed near the edge of the P-type semiconductor layer, and the inclination angle of the fourth sidewall is δ.
[0013] γ=δ.
[0014] As an improvement to the above technical solution, the distance between the bottom edge of the third sidewall and the top edge of the sidewall of the isolation groove is L1;
[0015] The distance between the bottom edge of the fourth sidewall and the top edge of the P-type semiconductor layer is L2;
[0016] L1=L2.
[0017] As an improvement to the above technical solution, the height of the third sidewall is H1, and the height of the fourth sidewall is H2;
[0018] H1=H2.
[0019] As an improvement to the above technical solution, the value of γ ranges from 30° to 60°; and / or
[0020] The value of L1 ranges from 4μm to 6μm; and / or
[0021] The value of H1 ranges from 2000 Å to 3000 Å.
[0022] As an improvement to the above technical solution, the N-type electrode includes a first N-type electrode, an N-type connecting portion, and a plurality of N-type cross sub-ports; the first N-type electrode and the N-type cross sub-ports are electrically connected through the N-type connecting portion;
[0023] The P-type electrode includes a P-type cross sub-section and a P-type connecting section; multiple P-type cross sub-sections are electrically connected through the P-type connecting section;
[0024] The N-type cross sub-section and the P-type cross sub-section are arranged in an intersecting manner.
[0025] As an improvement to the above technical solution, the reflective layer includes a metal reflective layer and a protective layer sequentially stacked on the P-type semiconductor layer;
[0026] The metal reflective layer is an Ag metal layer with a thickness of 1200 Å to 2000 Å; the protective layer includes alternating Ti and Ni layers with a period of 2 to 3, the thickness of a single Ti layer is 500 Å to 1000 Å, and the thickness of a single Ni layer is 500 Å to 1000 Å.
[0027] Both the N-type electrode and the P-type electrode have a Cr / Al / Ti / Ni / Ti / Ni / Ti / Cu / Cr / Ti stacked structure, with the thicknesses of each layer being 30Å~50Å, 1200Å~2000Å, 1000Å~2000Å, 1000Å~2000Å, 1000Å~2000Å, 1000Å~2000Å, 1000Å~2000Å, 5000Å~8000Å, 500Å~1000Å, and 30Å~50Å.
[0028] As an improvement to the above technical solution, the orthogonal projection of the light-emitting structure on the substrate is circular.
[0029] Accordingly, the present invention also discloses a method for fabricating a flip-chip LED, which includes the following steps:
[0030] (1) An epitaxial layer is formed on a substrate, the epitaxial layer comprising an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially stacked on the substrate;
[0031] (2) Etching forms an N-type conductive step that exposes the N-type semiconductor layer, forming a light-emitting structure disposed on the substrate;
[0032] (3) Etching forms isolation grooves;
[0033] (4) A reflective layer is formed on the P-type semiconductor layer on top of the light-emitting structure to obtain the first intermediate;
[0034] (5) A first insulating layer is formed on the first intermediate body, and a first conductive via and a second conductive via are formed on the first insulating layer located above the light-emitting structure, and a third conductive via is formed on the first insulating layer above the N-type conductive step;
[0035] (6) A third sidewall and a fourth sidewall are formed on the first insulating layer to obtain a second intermediate;
[0036] (7) Form a P-type electrode and an N-type electrode on the second intermediate to obtain a third intermediate;
[0037] (8) A second insulating layer is formed on the third intermediate, and a fourth conductive via is formed to expose the P-type electrode and a fifth conductive via is formed to expose the N-type electrode;
[0038] (9) A P-type pad layer and an N-type pad layer are formed on the second insulating layer;
[0039] The N-type electrode is electrically connected to the N-type semiconductor layer through the first conductive via and the third conductive via, and the P-type electrode is electrically connected to the P-type semiconductor layer through the second conductive via.
[0040] The P-type electrode and the N-type electrode are arranged in an interdigitated pattern, and the electrode located on the outermost side of the light-emitting structure is the first N-type electrode; the first N-type electrode includes a first sub-N-type electrode and a second sub-N-type electrode; the first sub-N-type electrode is located above the N-type conductive step, and the second sub-N-type electrode is located above the P-type semiconductor layer;
[0041] The first sub-N-type electrode has a first sidewall corresponding to the third sidewall on the side near the isolation trench, and the inclination angle of the first sidewall is α; the second sub-N-type electrode has a second sidewall corresponding to the fourth sidewall on the side near the edge of the P-type semiconductor layer, and the inclination angle of the second sidewall is β.
[0042] α=β.
[0043] As an improvement to the above technical solution, step (7) includes the following steps:
[0044] (7.1) A photoresist layer is formed on the second intermediate using negative photoresist;
[0045] (7.2) Expose and develop the photoresist layer to remove the photoresist layer in the preset area, and form a first inclined opening above the third sidewall and a second inclined opening above the fourth sidewall; the inclination angle of the first inclined opening is the same as the inclination angle of the second inclined opening.
[0046] (7.3) Formation of metal stacks;
[0047] (7.4) Peel off the remaining photoresist layer and the metal stack above it to form N-type electrode and P-type electrode.
[0048] Implementing this invention has the following beneficial effects:
[0049] In one embodiment of the present invention, the flip-chip LED includes a substrate, an epitaxial layer, a reflective layer, a first insulating layer, a P-type electrode, an N-type electrode, a second insulating layer, a P-type pad layer, and an N-type pad layer. The P-type and N-type electrodes are arranged in an interdigitated pattern, and the electrode located on the outermost side of the light-emitting structure is the first N-type electrode. The first N-type electrode includes a first sub-N-type electrode and a second sub-N-type electrode. The first sub-N-type electrode is located above the N-type conductive step, and the second sub-N-type electrode is located above the P-type semiconductor layer. The first sub-N-type electrode has a first sidewall on the side near the isolation trench, and the inclination angle of the first sidewall is α. The second sub-N-type electrode has a second sidewall on the side near the edge of the P-type semiconductor layer, and the inclination angle of the second sidewall is β; α=β. Based on this, both the first and second sub-N-type electrodes can be well coated, improving electrode adhesion and avoiding metal peeling at various points; it also reduces microcracks caused by interface stress concentration, thereby significantly enhancing the reliability of the flip-chip LED. Attached Figure Description
[0050] Figure 1 This is a top view of the substrate structure after step (3) in one embodiment of the present invention;
[0051] Figure 2 yes Figure 1 A sectional view along line AA.
[0052] Figure 3 This is a top view of the first intermediate obtained in step (4) of an embodiment of the present invention;
[0053] Figure 4 yes Figure 3 Sectional view along line BB;
[0054] Figure 5 This is a top view of the structure of the first intermediate after step (5);
[0055] Figure 6 yes Figure 5 A cross-sectional view along the CC line;
[0056] Figure 7 This is a top view of the second intermediate obtained in step (6) of one embodiment of the present invention;
[0057] Figure 8 yes Figure 7 A sectional view along the DD line;
[0058] Figure 9 This is a top view of the third intermediate obtained in step (7) of one embodiment of the present invention;
[0059] Figure 10 yes Figure 9 A sectional view along the EE line;
[0060] Figure 11 This is a top view of a flip-chip structure in one embodiment of the present invention;
[0061] Figure 12 yes Figure 11 Sectional view along the FF line;
[0062] In the figure, 100 is the substrate, 210 is the N-type semiconductor layer, 220 is the light-emitting layer, 230 is the P-type semiconductor layer, 240 is the light-emitting structure, 250 is the N-type conductive step, 260 is the isolation trench, 300 is the reflective layer, 400 is the first insulating layer, 410 is the first insulating portion, 420 is the second insulating portion, 430 is the third sidewall, 440 is the third insulating portion, 450 is the fourth insulating portion, 460 is the fourth sidewall, 470 is the first conductive via, and 480 is the second... Conductive vias: 490 is the third conductive via; 500 is a P-type electrode; 510 is a P-type cross sub-part; 520 is a P-type connector; 600 is an N-type electrode; 610 is the first N-type electrode; 611 is the first sub-N-type electrode; 6111 is the first sidewall; 612 is the second sub-N-type electrode; 6121 is the second sidewall; 620 is the N-type cross sub-part; 630 is the N-type connector; 700 is the second insulating layer; 810 is the N-type pad layer; and 820 is the P-type pad layer. Detailed Implementation
[0063] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It is hereby declared that the directional terms such as up, down, left, right, front, back, inside, and outside used in this text are based solely on the accompanying drawings and are not intended to specifically limit the invention.
[0064] Please see Figure 2 , Figure 11 , Figure 12 An embodiment of the present invention provides a flip-chip LED, which includes a substrate 100, an epitaxial layer, a reflective layer 300, a first insulating layer 400, a P-type electrode 500, an N-type electrode 600, a second insulating layer 700, a P-type pad layer 820, and an N-type pad layer 810.
[0065] Please refer to Figure 1 , Figure 2In the vertical direction (i.e., the thickness direction of the substrate 100), the epitaxial layer includes an N-type semiconductor layer 210, a light-emitting layer 220, and a P-type semiconductor layer 230 sequentially stacked on the substrate 100. A light-emitting structure 240, an isolation trench 260, and an N-type conductive step 250 are formed on the epitaxial layer. The isolation trench 260 is used to divide the substrate 100 and the epitaxial layer to form multiple flip-chip LEDs. The isolation trench 260 is disposed around the light-emitting structure 240, and the bottom of the isolation trench 260 exposes the substrate 100. The N-type conductive step 250 is disposed on one side of the light-emitting structure 240, exposing the N-type semiconductor layer 210. Specifically, one or more N-type conductive steps 250 may be provided in each flip-chip LED. Preferably, in some embodiments, each flip-chip LED includes multiple N-type conductive steps 250, which are evenly distributed around the light-emitting structure 240. The N-type conductive steps 250 are used to form electrical connections with the N-type electrode 600 and the N-type pad layer 810. The light-emitting structure 240 is used to emit light. Its top is a P-type semiconductor layer 230, which is used to form an electrical connection with the P-type electrode 500 and the P-type pad layer 820. The light-emitting structure 240 is also provided with a plurality of through holes etched to the N-type semiconductor layer 210, which are used to electrically connect the N-type electrode 600 located on the light-emitting structure 240 to the N-type semiconductor layer 210.
[0066] Specifically, the substrate 100 is a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited to these. The N-type semiconductor layer 210 can be an N-type GaAs layer, an N-type GaN layer, or an N-type AlGaN layer, but is not limited to these. The light-emitting layer 220 can be an InGaN-GaN type multiple quantum well layer, an InGaN-AlGaN type multiple quantum well layer, an AlGaN-AlGaN type multiple quantum well layer, or an AlGaInP-AlGaInP type multiple quantum well layer, but is not limited to these. The P-type semiconductor layer 230 can be a P-type GaN layer, a P-type AlGaInP layer, or a P-type AlGaN layer, but is not limited to these. Preferably, in some embodiments, the substrate 100 is a sapphire substrate, the N-type semiconductor layer 210 is an N-type GaN layer, the light-emitting layer 220 is an InGaN-GaN type multiple quantum well layer, and the P-type semiconductor layer 230 is a P-type GaN layer.
[0067] Please see Figure 3 , Figure 4A reflective layer 300 is disposed above the P-type semiconductor layer 230 on top of the light-emitting structure 240. It reflects the light emitted by the light-emitting layer 220, allowing light to exit from the substrate 100 side. The reflective layer 300 can be a metallic reflective layer or a DBR reflective layer, but is not limited to these. Preferably, in some embodiments, the reflective layer 300 includes a sequentially stacked metallic reflective layer and a protective layer. The metallic reflective layer is one or more of Ag, Au, and Al layers, but is not limited to these. The protective layer is one or more of Ni metal layers, TiW alloy layers, and PtPd alloy layers, but is not limited to these. More preferably, the metallic reflective layer is an Ag metal layer with a thickness of 1200 Å to 2000 Å; the protective layer includes alternately stacked Ti and Ni layers with a period number of 2 to 3, a single Ti layer thickness of 500 Å to 1000 Å, and a single Ni layer thickness of 500 Å to 1000 Å.
[0068] Please see Figure 5 , Figure 6 The first insulating layer 400 covers the isolation trench 260, the N-type conductive step 250, the light-emitting structure 240, and the reflective layer 300 above the light-emitting structure 240. The first insulating layer 400 forms a second conductive via 480 above the light-emitting structure 240 exposing the reflective layer 300, and a third conductive via 490 above the N-type conductive step 250. The second conductive via 480 is used to electrically connect the P-type electrode 500 to the P-type semiconductor; the third conductive via 490 is used to electrically connect the N-type electrode 600 to the N-type conductive step 250. Preferably, the first insulating layer 400 located on the light-emitting structure 240 also has a plurality of first conductive vias 470 exposing the N-type semiconductor layer 210, which are used to electrically connect the N-type electrode 600 located above the light-emitting structure 240 to the N-type semiconductor layer 210.
[0069] Specifically, the first insulating layer 400 is a SiO2 layer or a SiN layer. x The first insulating layer 400 is a multilayer structure composed of one or more of the following: an Al2O3 layer, but is not limited thereto. The thickness of the first insulating layer 400 is 6000 Å to 12000 Å. Preferably, in some embodiments, the thickness of the first insulating layer 400 is 6000 Å to 10000 Å.
[0070] Please see Figure 9 , Figure 10Both the P-type electrode 500 and the N-type electrode 600 are disposed above the first insulating layer 400. The N-type electrode 600 is electrically connected to the N-type semiconductor layer 210 through the first conductive via 470 and the third conductive via 490, and the P-type electrode 500 is electrically connected to the P-type semiconductor layer 230 through the second conductive via 480. Specifically, both the P-type electrode 500 and the N-type electrode 600 are common single-layer or multilayer metal structures in the art, and for example, they can be made of one or more of Cr, Al, Ti, Pt, Ni, Au, Cu, and Ag, but are not limited thereto. Preferably, in some embodiments, both the P-type electrode 500 and the N-type electrode 600 are Cr / Al / Ti / Ni / Ti / Ni / Ti / Cu / Cr / Ti stacked structures, with the thicknesses of each layer being 30Å~50Å, 1200Å~2000Å, 1000Å~2000Å, 1000Å~2000Å, 1000Å~2000Å, 1000Å~2000Å, 5000Å~8000Å, 500Å~1000Å, and 30Å~50Å.
[0071] Specifically, the P-type electrode 500 and N-type electrode 600 are arranged in an interdigitated pattern, with the intersecting area covering the top of the light-emitting structure 240. This arrangement significantly improves the uniformity of current distribution and light extraction efficiency. More specifically, the outermost electrode of the light-emitting structure 240 is the first N-type electrode 610, which includes a first sub-N-type electrode 611 and a second sub-N-type electrode 612. The first sub-N-type electrode 611 is located above the N-type conductive step 250 and is electrically connected to the N-type conductive step 250 through a third conductive via 490. The second sub-N-type electrode 612 is located above the P-type semiconductor layer 230 and is connected to the N-type semiconductor layer 210 through a first conductive via 470. This multi-path connection method improves the uniformity of current distribution and enhances luminous efficiency.
[0072] For more details, please refer to Figure 9 , Figure 10 The first sub-N-type electrode 611 has a first sidewall 6111 on the side near the isolation trench 260, with an inclination angle of α. The second sub-N-type electrode 612 has a second sidewall 6121 on the side near the edge of the P-type semiconductor layer 230, with an inclination angle of β, where α = β. This design ensures good coating for both the first sub-N-type electrode 611 and the second sub-N-type electrode 612, improving electrode adhesion and preventing metal peeling. It also reduces microcracks caused by interface stress concentration, thereby significantly enhancing the reliability of the flip-chip LED.
[0073] Please see Figure 11 , Figure 12The second insulating layer 700 covers the P-type electrode 500, the N-type electrode 600, and the first insulating layer 400. A fourth conductive via exposing the P-type electrode 500 and a fifth conductive via exposing the N-type electrode 600 (not shown in the figure) are formed on the second insulating layer 700. Specifically, the second insulating layer 700 is a SiO2 layer or a SiN layer. x The structure is a multilayer structure consisting of one or more of the following: an Al2O3 layer, but is not limited thereto. The thickness of the second insulating layer 700 is 5000 Å to 12000 Å.
[0074] The P-type pad layer 820 and the N-type pad layer 810 are both located above the second insulating layer 700. More specifically, the P-type pad layer 820 and the N-type pad layer 810 are both located above the second insulating layer 700 to ensure that the pad layers are at the same height, further enhancing the reliability of the flip-chip LED. The P-type pad layer 820 is electrically connected to the P-type electrode 500 through a fourth conductive via. The N-type pad layer 810 is electrically connected to the N-type electrode 600 through a fifth conductive via.
[0075] Specifically, the P-type pad layer 820 and the N-type pad layer 810 are common metal pad structures in the art, such as a stacked structure composed of one or more of Ti, Sn, Ni, and Au, but are not limited thereto. Preferably, both the P-type pad layer 820 and the N-type pad layer 810 are Ti / Al / Ni / Au stacked structures, with the thicknesses of each layer being 1000Å~2000Å, 5000Å~10000Å, 10000Å~15000Å, and 200Å~2000Å, respectively.
[0076] Preferably, please refer to Figure 7 , Figure 8 In some embodiments, the first insulating layer 400 below the first sub-N-type electrode 611 has a third sidewall 430 located between the light-emitting structure 240 and the isolation trench 260, with an inclination angle of γ. The first insulating layer 400 below the second sub-N-type electrode 612 has a fourth sidewall 460 located near the edge of the P-type semiconductor layer 230, with an inclination angle of δ and γ=δ. Based on this, similar support structures can be provided for the first sidewall 6111 and the second sidewall 6121, thereby ensuring that the inclination angles of the first sidewall 6111 and the second sidewall 6121 are consistent, making their coating performance more consistent, and making their stress changes more consistent during later use, thus improving the reliability of the flip-chip LED.
[0077] It should be noted that all angles in this application refer to the angles relative to the plane containing the substrate 100.
[0078] More specifically, the first insulating layer 400 includes a first insulating portion 410 and a second insulating portion 420 connected to each other. The first insulating portion 410 is located below the first sub-N-type electrode 611, and the second insulating portion 420 extends from the sidewall of the first sub-N-type electrode 611 to the bottom of the isolation groove 260. The height of the second insulating portion 420 is less than the height of the first insulating portion 410, so that a third sidewall 430 is formed at the transition between the first insulating portion 410 and the second insulating portion 420.
[0079] Correspondingly, the first insulating layer 400 also includes a third insulating portion 440 and a fourth insulating portion 450 connected to each other. The third insulating portion 440 is located below the second sub-N type electrode 612, and the fourth insulating portion 450 extends from the sidewall of the second sub-N type electrode 612 to the bottom of the isolation groove 260. The height of the fourth insulating portion 450 is also less than that of the third insulating portion 440, and the transition between the two forms a fourth sidewall 460.
[0080] Further, please refer to Figure 8 The distance between the bottom edge of the third sidewall 430 and the top edge of the sidewall of the isolation trench 260 is L1, and the distance between the bottom edge of the fourth sidewall 460 and the top edge of the P-type semiconductor layer 230 is L2, where L1 = L2. Based on this, the distance between the first edge of the first sub-N-type electrode 611 and the isolation trench 260, and the distance between the second edge of the second sub-N-type electrode 612 and the isolation trench 260, can be effectively controlled. This ensures that the first sub-N-type electrode 611 and the second sub-N-type electrode 612 maintain high consistency in current spread, light extraction, stress distribution, and thermal management, effectively improving the luminous uniformity and reliability of the flip-chip LED.
[0081] Furthermore, please refer to Figure 8 The height of the third sidewall 430 is H1, which is the height difference between the first insulating part 410 and the second insulating part 420. The height of the fourth sidewall 460 is H2, which is the height difference between the third insulating part 440 and the fourth insulating part 450. Since H1 = H2, this ensures high consistency in morphology, thermal conductivity, and stress control of the insulating structures on both sides, further improving the reliability of the flip-chip LED.
[0082] Specifically, in some embodiments, the values of γ and δ range from 30° to 60°. This angle range ensures the morphology controllability of the insulating layer sidewalls during photolithography and etching processes, while also taking into account the electrode coverage integrity and thermal stress control. For example, γ and δ are 35°, 40°, 45°, 50°, or 55°, but are not limited to these. More preferably, the values of γ and δ range from 30° to 45°.
[0083] Specifically, in some implementations, the values of L1 and L2 range from 4μm to 6μm, exemplarily 4.2μm, 4.6μm, 5.0μm, 5.4μm, or 5.8μm, but are not limited thereto. Preferably, they are 4.5μm to 5.5μm.
[0084] Specifically, in some implementations, the values of H1 and H2 range from 2000 Å to 3000 Å. If H1 and H2 are too small, it is difficult to form effective sidewall regulation; if they are too large, it is easy to cause uneven insulation layer coverage and weakened insulation performance. For example, H1 and H2 are 2200 Å, 2400 Å, 2600 Å, or 2800 Å, but are not limited to these. Preferably, the values of H1 and H2 range from 2400 Å to 2800 Å.
[0085] Preferably, in some embodiments, the N-type electrode 600 includes a first N-type electrode 610, an N-type connecting portion 630, and a plurality of N-type intersecting portions 620. The first N-type electrode 610 and the N-type intersecting portions 620 are electrically connected through the N-type connecting portion 630. Correspondingly, the P-type electrode 500 includes a P-type intersecting portion 510 and a P-type connecting portion 520; the plurality of P-type intersecting portions 510 are electrically connected through the P-type connecting portion 520. The N-type intersecting portions 620 and the P-type intersecting portions 510 are arranged in a cross configuration, and can be arranged in a strip-like staggered distribution or a grid-like interlocking layout. For example, the N-type intersecting portions 620 and the P-type intersecting portions 510 can have a structure similar to a triangle, a quadrilateral, a pentagon, or a circle in the top view, but are not limited thereto. It should be noted that a key concept of this application is to fabricate a flip-chip LED with a circular cross-section for the light-emitting structure 240. Its current distribution differs significantly from that of traditional square LED chips. By finely controlling the distribution of the N-type electrode 600 and the P-type electrode 500, the current can be uniformly diffused in the circular light-emitting area, thereby improving luminous efficiency, luminous uniformity, and device reliability.
[0086] Preferably, in some embodiments, the orthographic projection of the light-emitting structure 240 on the substrate 100 is a circle, but it can also be other polygons, such as a regular hexagon or a regular octagon, but is not limited thereto.
[0087] Accordingly, the present invention also discloses a method for preparing a flip-chip LED, which specifically includes the following steps:
[0088] (1) An epitaxial layer is formed on the substrate 100;
[0089] Specifically, an epitaxial layer is obtained by sequentially forming an N-type semiconductor layer 210, a light-emitting layer 220, and a P-type semiconductor layer 230 on a substrate 100 using methods such as MOCVD, MBE, and PVD.
[0090] (2) Etching forms an N-type conductive step 250 that exposes the N-type semiconductor layer 210, forming a light-emitting structure 240 disposed on the substrate 100;
[0091] Specifically, a mask (photoresist layer or SiO2 layer) can be formed on the epitaxial layer first, and then the P-type semiconductor layer 230, the light-emitting layer 220 and the N-type semiconductor layer 210 of a predetermined thickness in the predetermined area can be removed by wet etching or dry etching to form an N-type conductive step 250 and a light-emitting structure 240, but it is not limited to this.
[0092] Specifically, the N-type conductive steps 250 are distributed around the light-emitting structure 240, preferably in a ring shape, and the spacing between the multiple N-type conductive steps 250 is uniform.
[0093] (3) Etching to form isolation grooves 260;
[0094] Specifically, a mask (photoresist layer or SiO2 layer) can be formed on the exposed N-type semiconductor layer 210 first, and then a portion of the N-type semiconductor layer 210 and the substrate 100 can be removed by wet etching or dry etching to form an isolation trench 260.
[0095] Specifically, the isolation groove 260 is arranged around the light-emitting structure 240, preferably in an annular shape.
[0096] (4) A reflective layer 300 is formed on the P-type semiconductor layer 230 on the top of the light-emitting structure 240 to obtain the first intermediate;
[0097] Specifically, the reflective layer 300 can be obtained by forming a metal stack through electron beam evaporation or PVD processes, but is not limited to these methods.
[0098] Preferably, in some embodiments, a photoresist layer is first formed using a negative photoresist, then the photoresist layer on top of the light-emitting structure 240 is removed by exposure and development, then multiple metals are sequentially deposited by electron beam evaporation to form a reflective layer 300, then the metals located on the photoresist layer are removed by blue film stripping, and finally the photoresist layer is removed.
[0099] (5) A first insulating layer 400 is formed on the first intermediate body, and a first conductive through hole 470 and a second conductive through hole 480 are formed on the first insulating layer 400 located above the light-emitting structure 240, and a third conductive through hole 490 is formed on the first insulating layer 400 above the N-type conductive step 250.
[0100] Specifically, in some implementations, a first insulating layer 400 is formed by PECVD, and then a first conductive via 470, a second conductive via 480, and a third conductive via 490 are formed by photolithography etching.
[0101] (6) A third sidewall 430 and a fourth sidewall 460 are formed on the first insulating layer 400 to obtain a second intermediate;
[0102] Specifically, a photoresist layer is first formed on the first insulating layer 400, then the photoresist layer in a predetermined area is removed by exposure and development, and then a portion of the first insulating layer 400 is removed by wet etching or dry etching, thus forming the first insulating portion 410, the second insulating portion 420, the third insulating portion 440, and the fourth insulating portion 450. The transition between the first insulating portion 410 and the second insulating portion 420 forms the third sidewall 430, and the transition between the third insulating portion 440 and the fourth insulating portion 450 forms the fourth sidewall 460.
[0103] (7) A P-type electrode 500 and an N-type electrode 600 are formed on the second intermediate to obtain a third intermediate;
[0104] Specifically, metal stacks can be formed through electron beam evaporation or PVD processes to obtain P-type electrode 500 and N-type electrode 600, but are not limited to these methods.
[0105] Preferably, in some embodiments, step (7) includes the following steps:
[0106] (7.1) A photoresist layer is formed on the second intermediate using negative photoresist;
[0107] (7.2) Expose and develop the photoresist layer, remove the photoresist layer in the preset area, and form a first inclined opening above the third sidewall 430 and a second inclined opening above the fourth sidewall 460.
[0108] The first inclined opening has the same inclination angle as the second inclined opening. Based on this, a first sidewall 6111 and a second sidewall 6121 with the same inclination angle can be formed.
[0109] (7.3) Formation of metal stacks;
[0110] (7.4) Peel off the remaining photoresist layer and the metal stack above it to form an N-type electrode 600 and a P-type electrode 500.
[0111] (8) A second insulating layer 700 is formed on the third intermediate, and a fourth conductive via exposing the P-type electrode 500 and a fifth conductive via exposing the N-type electrode 600 are formed.
[0112] Specifically, the second insulating layer 700 can be formed through processes such as ALD, PECVD, and LPCVD, and then the fourth and fifth conductive vias can be etched, but it is not limited to these.
[0113] Preferably, in some embodiments, a SiO2 layer is first formed on the second intermediate by PECVD as the second insulating layer 700. Then, a photoresist layer is formed on the second insulating layer 700, and the second insulating layer 700 in a predetermined area is exposed by exposure and development. Then, a fourth conductive via and a fifth conductive via are formed by etching.
[0114] (9) A P-type pad layer 820 and an N-type pad layer 810 are formed on the second insulating layer 700;
[0115] Specifically, metal stacks can be formed through electron beam evaporation or PVD processes to obtain P-type pad layer 820 and N-type pad layer 810, but are not limited to these.
[0116] Preferably, in some embodiments, a photoresist layer is first formed in the second insulating layer 700, the fourth conductive via, and the fifth conductive via. Then, the photoresist layer in the preset area is removed by exposure and development. Then, a metal stack is deposited by electron beam evaporation to form a P-type pad layer 820 and an N-type pad layer 810. Then, the metal on the photoresist layer is removed by blue film stripping.
[0117] Preferably, in some embodiments, the method for preparing flip-chip LEDs further includes: splitting the wafer obtained in step (9) along the isolation trench 260, and then obtaining flip-chip LEDs by testing and sorting.
[0118] The present invention will be further described below with reference to specific embodiments:
[0119] Examples 1-5
[0120] This embodiment provides a flip-chip LED, which includes: a substrate, an epitaxial layer, a reflective layer, a first insulating layer, a P-type electrode, an N-type electrode, a second insulating layer, a P-type pad layer and an N-type pad layer stacked on the substrate;
[0121] The substrate is a sapphire substrate. The epitaxial layer includes an N-type semiconductor layer (N-type GaN layer), a light-emitting layer (InGaN-GaN type multiple quantum well layer) and a P-type semiconductor layer (P-type GaN layer) stacked sequentially on the substrate. A light-emitting structure, an isolation trench and an N-type conductive step are formed on the epitaxial layer. The orthographic projection of the light-emitting structure on the substrate is circular. The N-type conductive steps are uniformly spaced around the light-emitting structure and expose the N-type semiconductor layer. The isolation trench is arranged around the light-emitting structure and exposes the substrate.
[0122] The reflective layer is positioned above the P-type semiconductor layer at the top of the light-emitting structure, and includes a metal reflective layer and a protective layer stacked sequentially. The metal reflective layer is an Ag layer with a thickness of 1500 Å; the protective layer consists of alternating Ti and Ni layers with a period of 3, a single Ti layer with a thickness of 800 Å, and a single Ni layer with a thickness of 850 Å.
[0123] The first insulating layer covers the isolation trench, the N-type conductive step, the light-emitting structure, and the reflective layer above the light-emitting structure. The first insulating layer forms a second conductive via above the light-emitting structure that exposes the reflective layer, a first conductive via that exposes the N-type semiconductor layer, and a third conductive via above the N-type conductive step. The first insulating layer is a SiO2 layer with a thickness of 8000 Å.
[0124] More specifically, the first insulating layer includes an interconnected first insulating portion and a second insulating portion. The first insulating portion is located below the first sub-N-type electrode, and the second insulating portion extends from the sidewall of the first sub-N-type electrode to the bottom of the isolation trench. This forms a third sidewall at the transition between the first and second insulating portions. The third sidewall has an inclination angle of γ and a height of H1. The distance between the bottom edge of the third sidewall and the top edge of the sidewall of the isolation trench is L1. The second insulating portion is formed by an etching thinning process.
[0125] The first insulating layer also includes a third insulating portion and a fourth insulating portion that are interconnected. The third insulating portion is located below the second sub-N-type electrode, and the fourth insulating portion extends from the sidewall of the second sub-N-type electrode to the bottom of the isolation trench. The height of the fourth insulating portion is also less than that of the third insulating portion, and the transition between the two forms a fourth sidewall. The tilt angle of the fourth sidewall is δ, its height is H2, and the distance between the bottom edge of the fourth sidewall and the top edge of the P-type semiconductor layer is L2. The fourth insulating portion is formed by an etching thinning process.
[0126] The N-type electrode includes a first sub-N-type electrode, an N-type connecting portion, and multiple N-type cross sub-ports. The first N-type electrode and the N-type cross sub-ports are electrically connected through the N-type connecting portion. The P-type electrode includes a P-type cross sub-port and a P-type connecting portion; multiple P-type cross sub-ports are electrically connected through the P-type connecting portion. The N-type cross sub-ports and P-type cross sub-ports are arranged in a cross configuration. Both the N-type and P-type electrodes are Cr / Al / Ti / Ni / Ti / Ni / Ti / Cu / Cr / Ti stacked structures, with layer thicknesses of 50 Å, 1400 Å, 1200 Å, 1500 Å, 1400 Å, 1500 Å, 1500 Å, 6500 Å, 750 Å, and 45 Å, respectively.
[0127] The second insulating layer covers the P-type electrode, the N-type electrode, and the first insulating layer. A fourth conductive via exposing the P-type electrode and a fifth conductive via exposing the N-type electrode are formed on the second insulating layer. Specifically, the second insulating layer is a SiO2 layer with a thickness of 11000 Å.
[0128] The P-type pad layer and the N-type pad layer are both located above the second insulating layer. Both the P-type pad layer and the N-type pad layer include a Ti / Al / Ni / Au stack structure, and the thicknesses of each layer are 1400Å, 8000Å, 14000Å, and 1500Å, respectively.
[0129] The specific values of γ, δ, H1, H2, L1, and L2 in each embodiment are shown in the table below:
[0130]
[0131] Comparative Example 1
[0132] This comparative example provides a flip-chip LED, which differs from Example 1 in that:
[0133] The first insulating layer is not etched to thin it, i.e., the third and fourth sidewalls are not formed. The N-type and P-type electrodes are directly fabricated on the first insulating layer.
[0134] Examples 1-5 were used to test the flip-chip LED in Comparative Example 1. Specifically, a reliability aging test was conducted in an environment of 85%RH and 85°C. Every 72 hours, a -10V voltage was applied to test the current value. If the current value was less than 0.1μA, the chip was considered to have failed, and the current time point was recorded as the failure time point. The specific test results are shown in the table below:
[0135]
[0136] A comparison of Example 1 and Comparative Example 1 shows that forming third and fourth sidewalls with the same tilt angle on the first insulating layer can significantly delay the aging failure time point and improve reliability. A comparison of Examples 1-3 shows that jointly controlling the distance between the third sidewall and the isolation trench, the distance between the fourth sidewall and the edge of the P-type semiconductor layer, and the height of the third / fourth sidewall can further improve the reliability of the flip-chip.
[0137] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.
Claims
1. A flip-chip LED, characterized in that, include: Substrate, an epitaxial layer, a reflective layer, a first insulating layer, a P-type electrode, an N-type electrode, a second insulating layer, a P-type pad layer, and an N-type pad layer stacked on the substrate; The epitaxial layer includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer sequentially stacked on the substrate. A light-emitting structure, an isolation trench, and an N-type conductive step are formed on the epitaxial layer. The N-type conductive step is disposed on one side of the light-emitting structure and exposes the N-type semiconductor layer. The isolation trench is disposed around the light-emitting structure and exposes the substrate. The P-type electrode and the N-type electrode are arranged in an interdigitated pattern, and the electrode located on the outermost side of the light-emitting structure is the first N-type electrode; the first N-type electrode includes a first sub-N-type electrode and a second sub-N-type electrode; the first sub-N-type electrode is located above the N-type conductive step, and the second sub-N-type electrode is located above the P-type semiconductor layer; The first sub-N-type electrode has a first sidewall on the side near the isolation trench, and the inclination angle of the first sidewall is α; the second sub-N-type electrode has a second sidewall on the side near the edge of the P-type semiconductor layer, and the inclination angle of the second sidewall is β; α=β; The first insulating layer below the first sub-N-type electrode has a third sidewall, which is located between the light-emitting structure and the isolation trench, and the inclination angle of the third sidewall is γ; the first insulating layer below the second sub-N-type electrode has a fourth sidewall, which is disposed close to the edge of the P-type semiconductor layer, and the inclination angle of the fourth sidewall is δ; γ=δ; The distance between the bottom edge of the third sidewall and the top edge of the sidewall of the isolation trench is L1; the distance between the bottom edge of the fourth sidewall and the top edge of the P-type semiconductor layer is L2; L1 = L2; The height of the third sidewall is H1, and the height of the fourth sidewall is H2; H1 = H2.
2. The flip-chip LED as described in claim 1, characterized in that, The value of γ ranges from 30° to 60°; and / or The value of L1 ranges from 4μm to 6μm; and / or The value of H1 ranges from 2000 Å to 3000 Å.
3. The flip-chip LED as described in claim 1, characterized in that, The N-type electrode includes a first N-type electrode, an N-type connecting portion, and a plurality of N-type cross sub-ports; the first N-type electrode and the N-type cross sub-ports are electrically connected through the N-type connecting portion; The P-type electrode includes a P-type cross sub-section and a P-type connecting section; multiple P-type cross sub-sections are electrically connected through the P-type connecting section; The N-type cross sub-section and the P-type cross sub-section are arranged in an intersecting manner.
4. The flip-chip LED as described in claim 1, characterized in that, The reflective layer includes a metal reflective layer and a protective layer sequentially stacked on the P-type semiconductor layer; The metal reflective layer is an Ag metal layer with a thickness of 1200 Å to 2000 Å; the protective layer includes alternating Ti and Ni layers with a period of 2 to 3, the thickness of a single Ti layer is 500 Å to 1000 Å, and the thickness of a single Ni layer is 500 Å to 1000 Å. Both the N-type electrode and the P-type electrode have a Cr / Al / Ti / Ni / Ti / Ni / Ti / Cu / Cr / Ti stacked structure, with the thicknesses of each layer being 30Å~50Å, 1200Å~2000Å, 1000Å~2000Å, 1000Å~2000Å, 1000Å~2000Å, 1000Å~2000Å, 1000Å~2000Å, 5000Å~8000Å, 500Å~1000Å, and 30Å~50Å.
5. The flip-chip LED as described in any one of claims 1 to 4, characterized in that, The orthographic projection of the light-emitting structure onto the substrate is a circle.
6. A method for fabricating a flip-chip LED as described in any one of claims 1 to 5, characterized in that, Includes the following steps: (1) An epitaxial layer is formed on a substrate, the epitaxial layer comprising an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially stacked on the substrate; (2) Etching forms an N-type conductive step that exposes the N-type semiconductor layer, forming a light-emitting structure disposed on the substrate; (3) Etching forms isolation grooves; (4) A reflective layer is formed on the P-type semiconductor layer on top of the light-emitting structure to obtain the first intermediate; (5) A first insulating layer is formed on the first intermediate body, and a first conductive via and a second conductive via are formed on the first insulating layer located above the light-emitting structure, and a third conductive via is formed on the first insulating layer above the N-type conductive step; (6) A third sidewall and a fourth sidewall are formed on the first insulating layer to obtain a second intermediate; (7) Form a P-type electrode and an N-type electrode on the second intermediate to obtain a third intermediate; (8) A second insulating layer is formed on the third intermediate, and a fourth conductive via is formed to expose the P-type electrode and a fifth conductive via is formed to expose the N-type electrode; (9) A P-type pad layer and an N-type pad layer are formed on the second insulating layer; The N-type electrode is electrically connected to the N-type semiconductor layer through the first conductive via and the third conductive via, and the P-type electrode is electrically connected to the P-type semiconductor layer through the second conductive via. The P-type electrode and the N-type electrode are arranged in an interdigitated pattern, and the electrode located on the outermost side of the light-emitting structure is the first N-type electrode; the first N-type electrode includes a first sub-N-type electrode and a second sub-N-type electrode; the first sub-N-type electrode is located above the N-type conductive step, and the second sub-N-type electrode is located above the P-type semiconductor layer; The first sub-N-type electrode has a first sidewall corresponding to the third sidewall on the side near the isolation trench, and the inclination angle of the first sidewall is α; the second sub-N-type electrode has a second sidewall corresponding to the fourth sidewall on the side near the edge of the P-type semiconductor layer, and the inclination angle of the second sidewall is β. α=β。 7. The method for fabricating a flip-chip LED as described in claim 6, characterized in that, Step (7) includes the following steps: (7.1) A photoresist layer is formed on the second intermediate using negative photoresist; (7.2) Expose and develop the photoresist layer to remove the photoresist layer in the preset area, and form a first inclined opening above the third sidewall and a second inclined opening above the fourth sidewall; the inclination angle of the first inclined opening is the same as the inclination angle of the second inclined opening. (7.3) Formation of metal stacks; (7.4) Peel off the remaining photoresist layer and the metal stack above it to form N-type electrode and P-type electrode.