A method of processing a heavily doped substrate silicon wafer and an epitaxial wafer formed thereby

Abstract

This invention relates to the field of semiconductor manufacturing technology, specifically disclosing a method for processing heavily doped substrate silicon wafers and the epitaxial wafers formed therefrom. This invention adjusts the process steps of traditional processing methods for heavily doped substrate silicon wafers with a composite back-sealing structure of "polysilicon + silicon dioxide". After the polysilicon layer is deposited on the substrate, edge polishing is performed first to remove polysilicon from the chamfered surface, followed by the deposition of the silicon dioxide layer. This process optimization ensures that the junction between the flat back surface and the chamfered surface of the substrate is always completely covered by the silicon dioxide layer, avoiding polysilicon deposition and protrusion formation during epitaxy caused by exposure of monocrystalline silicon. This invention effectively solves problems such as lithography machine vacuum alarms and defocus defects caused by back edge protrusions in existing processes, significantly improving the flatness of the epitaxial wafer and the manufacturing yield for end customers.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, specifically relating to a processing method for a heavily doped substrate silicon wafer and an epitaxial wafer formed therefrom, particularly relating to an edge processing method for a heavily doped substrate silicon wafer with a back-sealing structure. Background Technology

[0002] Currently, MOS products typically use heavily doped silicon wafers as substrates for their monocrystalline silicon epitaxial wafers. Due to the high doping concentration of heavily doped silicon, dopants within the substrate diffuse outwards under high-temperature conditions during epitaxial growth or subsequent high-temperature wafer fabrication processes, resulting in self-doping and severely impacting device performance. To suppress dopant diffusion, the industry commonly grows a back-sealing layer on the back side of the heavily doped silicon substrate. To simultaneously suppress diffusion and enhance gettering capability, a composite back-sealing structure of "polysilicon (Poly) + silicon dioxide (LTO)" is widely adopted. In this structure, the polysilicon layer enhances gettering, while the silicon dioxide layer acts as a diffusion barrier.

[0003] The existing standard process for fabricating heavily doped substrate silicon wafers with a "Poly+LTO" composite back-sealing structure mainly includes the following key steps:

[0004] 1) Polycrystalline silicon deposition: A polycrystalline silicon layer is grown on a heavily doped monocrystalline silicon wafer that has been polished on both sides; in this step, the polycrystalline silicon layer is formed on both the back and front sides of the monocrystalline silicon wafer.

[0005] 2) Silica deposition: LTO thin film is grown on the polycrystalline silicon layer on the back side of a heavily doped monocrystalline silicon wafer.

[0006] 3) HF etching: Removes the LTO layer at a certain distance from the edge on the back chamfered surface, such as... Figure 1 This diagram illustrates the back-sealing structure of the heavily doped substrate silicon wafer after the edge polishing step in the existing process. Region A on the chamfered back face is the LTO layer area (0.2 mm in the diagram) on the chamfered back face after HF etching, located a certain width from the edge. The LTO film in region A may fall off during epitaxy and subsequent processes, causing defects on the front side of the epitaxial wafer. Therefore, after growing the LTO film, the LTO film in region A is removed using HF etching.

[0007] 4) Edge polishing: Remove the polysilicon exposed in region A of the chamfered surface due to LTO etching. Since polysilicon has a lower density than monocrystalline silicon, it is easy for the polysilicon to fall off during subsequent processing when the substrate wafer comes into contact with the clamping device. Therefore, after removing the LTO from region A of the substrate on the back chamfered surface, edge polishing is required to remove the polysilicon from region A of the chamfered surface.

[0008] 5) Single-sided polishing and cleaning: This step removes the polysilicon layer on the front side, followed by cleaning to obtain the heavily doped substrate silicon wafer with the above-mentioned "Poly+LTO" composite back-sealing structure.

[0009] During the edge polishing process described above, when removing the polysilicon from region A of the substrate, the polishing operation simultaneously removes both the back chamfered surface and the back flat surface (e.g., Figure 1 The LTO and polysilicon layers at the boundary of the C region, where Figure 1 Region B, which is the junction of the back chamfered surface and the back flat surface (region C), is directly exposed as monocrystalline silicon after edge polishing.

[0010] Therefore, during the silicon epitaxial wafer formation process on the heavily doped substrate silicon wafer prepared by the above process, the trichlorosilane (TCS) gas, which serves as the silicon source, not only reacts on the front side of the substrate but also partially diffuses to the back side. Since region B lacks LTO coverage and contains exposed monocrystalline silicon, polycrystalline silicon will deposit there, creating a raised area that protrudes above region C on the back side of the substrate, resulting in an uneven back side of the formed epitaxial wafer. During wafer fabrication at the client end, this raised area on the back side of the epitaxial wafer (region B) causes the silicon epitaxial wafer to be uneven on the lithography machine, leading to vacuum alarms or poor defocusing during lithography, severely impacting wafer processing efficiency and product yield.

[0011] The existing process has the above-mentioned inherent defects, and there is an urgent need to develop a processing method for heavily doped substrate silicon wafers: to ensure that the B region on the back edge of the substrate is always completely covered by the LTO layer, and to avoid polysilicon deposition and protrusions on the back edge during epitaxy. Summary of the Invention

[0012] To overcome the aforementioned shortcomings of the prior art, this invention aims to solve the technical problem of how to avoid the formation of protrusions on the back side of heavily doped substrates due to polysilicon deposition after epitaxial growth. A method for processing heavily doped substrate silicon wafers is provided, which ensures that the B region on the back side edge of the substrate is always completely covered by the LTO layer, avoiding polysilicon deposition and protrusions on the back side edge during epitaxy, thereby improving the flatness of the back side of the epitaxial wafer and ensuring the smooth progress of the photolithography process.

[0013] To achieve the above-mentioned objectives, the present invention adopts the following technical solution.

[0014] A method for processing heavily doped substrate silicon wafers, the method comprising the following steps in sequence:

[0015] Step 1), provide a double-sided polished heavily doped monocrystalline silicon wafer.

[0016] Step 2), Polycrystalline silicon deposition: A polycrystalline silicon layer is deposited on the back side of the heavily doped monocrystalline silicon wafer; in this step, the polycrystalline silicon layer is simultaneously formed on the front side of the heavily doped monocrystalline silicon wafer. Preferably, the thickness of the polycrystalline silicon layer is approximately 7200~8800 Å.

[0017] Step 3), edge polishing: The heavily doped monocrystalline silicon wafer with a polycrystalline silicon layer deposited is edge polished to remove the polycrystalline silicon on its chamfered surface.

[0018] Step 4), Silica deposition: A silicon dioxide layer, i.e., an LTO layer, is deposited on the back side of the heavily doped monocrystalline silicon wafer after edge polishing. Preferably, the thickness of the LTO layer is approximately 4000~5000 Å.

[0019] Step 5), HF etching: HF etching is performed on the heavily doped single-crystal silicon wafer with a silicon dioxide layer deposited on the back side to remove the LTO layer in the edge region from the outermost edge to a predetermined width from the edge on the back chamfered surface, as in Example 1, removing the LTO layer in the edge region approximately 0.2 mm from the edge on the back chamfered surface. The predetermined width is preferably 0.1~0.4 mm.

[0020] Step 6), Single-sided polishing and cleaning: The heavily doped monocrystalline silicon wafer etched by HF is polished on one side to remove the polycrystalline silicon layer on its front side, followed by cleaning to obtain the heavily doped substrate silicon wafer with a "Poly+LTO" composite back-sealing structure. The removal amount by single-sided polishing is 1.5~3μm thick.

[0021] The present invention also provides an epitaxial wafer, which is formed by a silicon epitaxial growth process using a heavily doped silicon wafer prepared by the above-described processing method as the epitaxial substrate. Preferably, the silicon epitaxial growth process is carried out at atmospheric pressure and a temperature of 1100~1200℃, and the thickness of the grown epitaxial layer is 20~50μm, and the resistivity of the epitaxial layer is 0.1~10 ohm·cm.

[0022] Compared to heavily doped substrate silicon wafers processed using existing methods, the back-sealing structure of the heavily doped substrate silicon wafer produced by this invention remains a typical poly+LTO structure. The core improvement lies in optimizing the polysilicon processing steps on the back chamfered surface. This invention places edge polishing after polysilicon layer growth and before LTO layer growth. After edge polishing, before LTO layer growth, the polysilicon on the back chamfered surface of the silicon wafer is removed. This ensures that after HF etching within a predetermined width from the edge of the chamfered surface, no polysilicon will be exposed, and except for the area within the predetermined edge width where LTO is stripped, the other back areas maintain complete LTO coverage. Since the Si generated by the reduction reaction of trichlorosilane (TCS) gas with H2 during epitaxial growth does not deposit on silicon dioxide, polysilicon deposition and protrusions will not occur at the interface between the back chamfered surface and the flat back surface during epitaxy, fundamentally eliminating the generation of back edge protrusions.

[0023] The beneficial technical effects of the present invention are as follows:

[0024] Completely eliminate backside protrusions: Through process optimization, the integrity of the silicon dioxide layer in the edge area of ​​the backside of the substrate is ensured, and there are no silicon absorption protrusions after epitaxial growth, significantly improving the flatness of the backside.

[0025] Improving client manufacturing yield: The flat back surface avoids vacuum alarms and defocus defects in lithography machines, significantly improving the production efficiency and product yield of client wafer processing.

[0026] High process compatibility and low cost: This invention only adjusts the existing process flow sequence without introducing any new special equipment or expensive materials. It is easy to implement and does not increase additional production costs. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the back seal structure of the heavily doped substrate silicon wafer after edge polishing using existing processes.

[0028] Figure 2 This is a schematic diagram of the back seal structure of the heavily doped substrate silicon wafer prepared by the processing method of the present invention.

[0029] Figure 3 This is a 2D microscope image of the back side of a heavily doped substrate epitaxial wafer prepared using the processing method of the present invention in Example 1.

[0030] Figure 4 The image shows a 3D microscope image and test diagram of the back side of a heavily doped substrate epitaxial wafer prepared using the processing method of the present invention in Example 1.

[0031] Figure 5 This is a 2D microscope image of the heavily doped substrate epitaxial wafer prepared in Comparative Example 1.

[0032] Figure 6 The image shows a 3D microscope photograph and test pattern of the back side of the heavily doped substrate epitaxial wafer prepared using existing processing methods in Comparative Example 1. Detailed Implementation

[0033] Compared to existing processes, this invention ensures that after the LTO layer is etched on the back chamfered surface of the substrate from the outermost edge to a predetermined width, the junction between the substrate's back chamfered surface and the flat surface remains completely covered by the silicon dioxide layer by placing the edge polishing step before silicon dioxide layer deposition. Since the Si generated by the reduction reaction of trichlorosilane (TCS) gas with H2 during epitaxial growth does not deposit on the silicon dioxide, the generation of back edge protrusions is fundamentally eliminated. Figure 2 This is a schematic diagram of the back seal structure of the heavily doped substrate silicon wafer processed using the method of the present invention in various embodiments, and... Figure 1 As in the figure: Area A is the edge region within a predetermined width from the edge, i.e., the area where LTO is etched by HF. This predetermined width is preferably 0.1~0.4mm, and the figure shows 0.2mm in Example 1; and Figure 1 Similar to the previous diagram, region B in the figure represents the boundary between the chamfered surface and the flat surface on the back side of the substrate, while region C represents the flat surface area on the back side of the substrate. As can be seen in the figure, except for region A where LTO has been removed, the rest of the back side is completely covered by LTO, including region B, which would form a protrusion during epitaxy in existing processes. Figure 2 The middle part was also completely covered.

[0034] The present invention will be further described in detail below with reference to embodiments, but the scope of protection of the present invention is not limited thereto.

[0035] Example 1

[0036] Prepare polished wafers: Prepare heavily doped double-sided polished silicon wafers with a thickness of 725~775μm. In this embodiment, a 12-inch heavily doped double-sided polished monocrystalline silicon wafer with a thickness of 750μm and a diameter of 300mm is used.

[0037] Deposition of polycrystalline silicon layer: Using low-pressure chemical vapor deposition, silane gas is introduced at 670°C and low pressure to grow a polycrystalline silicon layer with a thickness of about 8000 Å on the back side of a heavily doped monocrystalline silicon wafer. The polycrystalline silicon layer is also formed simultaneously on the front side of the silicon wafer.

[0038] Edge polishing: The heavily doped monocrystalline silicon wafer is edge polished for 70 seconds to completely remove the polycrystalline silicon layer deposited on the chamfered surface.

[0039] Depositing a silicon dioxide layer: Using atmospheric pressure chemical vapor deposition, silane reacts with oxygen at 400°C and atmospheric pressure to grow a silicon dioxide layer with a thickness of approximately 4500 Å on the back side of a heavily doped single-crystal silicon wafer.

[0040] HF etching: Selective etching is performed on the chamfered area on the back of the silicon wafer using hydrofluoric acid solution to remove the silicon dioxide layer with a width of about 0.2 mm from the outermost diameter.

[0041] Single-sided polishing: The front side of the heavily doped monocrystalline silicon wafer is polished on one side, with a removal amount of about 2μm, to remove the polycrystalline silicon layer on the front side. Then it is cleaned to obtain a heavily doped substrate silicon wafer with a "Poly+LTO" structure.

[0042] Epitaxial growth: Silicon epitaxial growth is performed on the heavily doped substrate silicon wafer prepared above. Under normal pressure and 1150°C, an epitaxial layer with a thickness of 20 μm and a resistivity of 10 Ω·cm is grown on the front side of the substrate to obtain the heavily doped substrate epitaxial wafer of this embodiment.

[0043] The edge of the back side of the epitaxial wafer prepared in this embodiment was observed using a 2D microscope, such as... Figure 3 As shown, at position B, the junction of the chamfered surface and the back side, the edge shows the color of the LTO layer, proving that the edge is covered by LTO and there is no abnormal silicon absorption. Figure 4 This is a 3D microscope image of the back side of the heavily doped substrate epitaxial wafer prepared in this embodiment. In the figure, A represents the back chamfered area, B represents the boundary area between the back chamfered area and the back flat surface, and C represents the back flat surface area. As can be seen from the figure, area B is flat and smooth without any protrusions, which confirms the effect of the present invention.

[0044] Example 2

[0045] Prepare the polishing wafer: Prepare a 300mm heavily doped double-sided polished silicon wafer with a thickness of 725μm.

[0046] Deposition of polycrystalline silicon layer: Low-pressure chemical vapor deposition is used to grow a polycrystalline silicon layer with a thickness of about 7200 Å on the back side of a heavily doped monocrystalline silicon wafer under low-pressure conditions of 665°C and silane gas. The polycrystalline silicon layer is also formed simultaneously on the front side of the silicon wafer.

[0047] Edge polishing: The heavily doped monocrystalline silicon wafer is edge polished for 60 seconds to ensure complete removal of the polycrystalline silicon layer deposited on the chamfered surface.

[0048] Depositing a silicon dioxide layer: Using atmospheric pressure chemical vapor deposition, silane reacts with oxygen at 395°C and atmospheric pressure to grow a silicon dioxide layer with a thickness of approximately 4000 Å on the back side of a heavily doped single-crystal silicon wafer.

[0049] HF etching: Selective etching is performed on the chamfered area on the back of the silicon wafer using hydrofluoric acid solution to remove a silicon dioxide layer approximately 0.1 mm from the outermost diameter.

[0050] Single-sided polishing: The front side of the heavily doped monocrystalline silicon wafer is polished on one side, with a removal amount of about 1.5μm, to remove the polycrystalline silicon layer on the front side. Then it is cleaned to obtain a heavily doped substrate silicon wafer with a "Poly+LTO" structure.

[0051] Epitaxial growth: Silicon epitaxial growth was performed on the heavily doped substrate silicon wafer prepared above. Under normal pressure and 1100℃, an epitaxial layer with a thickness of 30μm and a resistivity of 0.5Ω·cm was grown on the front side of the substrate.

[0052] 3D microscopy revealed that the epitaxial wafer in region B on the back side (the junction of the surface area and the flat back side) prepared in this embodiment exhibited the same smooth and even surface as in Example 1, without any protrusions. This demonstrates that even with adjustments to the polysilicon layer thickness, the process sequence of this invention effectively ensures the integrity of the back silicon dioxide layer and prevents protrusions.

[0053] Example 3

[0054] Prepare the polishing wafer: Prepare a 300mm heavily doped double-sided polished silicon wafer with a thickness of 775μm.

[0055] Deposition of polycrystalline silicon layer: Using low-pressure chemical vapor deposition, silane gas is introduced at 675°C and low pressure to grow a polycrystalline silicon layer with a thickness of about 8800 Å on the back side of a heavily doped monocrystalline silicon wafer. The polycrystalline silicon layer is also formed simultaneously on the front side of the silicon wafer.

[0056] Edge polishing: The heavily doped monocrystalline silicon wafer is edge polished for 80 seconds to ensure complete removal of the polycrystalline silicon layer deposited on the chamfered surface.

[0057] Depositing a silicon dioxide layer: Using atmospheric pressure chemical vapor deposition, silane reacts with oxygen at 405°C and atmospheric pressure to grow a silicon dioxide layer with a thickness of approximately 5000 Å on the back side of a heavily doped single-crystal silicon wafer.

[0058] HF etching: Selective etching is performed on the chamfered area on the back of the silicon wafer using hydrofluoric acid solution to remove the silicon dioxide layer with a width of approximately 0.4 mm from the outermost diameter.

[0059] Single-sided polishing: The front side of the heavily doped monocrystalline silicon wafer is polished on one side, with a removal amount of about 3μm, to remove the polycrystalline silicon layer on the front side. Then it is cleaned to obtain a heavily doped substrate silicon wafer with a "Poly+LTO" structure.

[0060] Epitaxial growth: Silicon epitaxial growth was performed on the heavily doped substrate silicon wafer prepared above. Under normal pressure and 1200℃ conditions, an epitaxial layer with a thickness of 50μm and a resistivity of 0.1Ω·cm was grown on the front side of the substrate.

[0061] Testing revealed that the B region on the back side of the epitaxial wafer prepared in this embodiment was also smooth and flat. Even at higher epitaxial growth temperatures and with a thicker epitaxial layer, no polysilicon deposition occurred in the B region because the back edge area was well protected by a thicker silicon dioxide layer, demonstrating the reliability of this invention under more stringent process conditions.

[0062] Example 4

[0063] In this embodiment, the steps of preparing the substrate, depositing a polycrystalline silicon layer, edge polishing, depositing a silicon dioxide layer, HF etching, and single-sided polishing are all performed with parameters as described in Example 1 to obtain a heavily doped substrate silicon wafer.

[0064] Epitaxial growth: Epitaxy was performed on the prepared heavily doped silicon substrate. Under normal pressure and 1170℃, an epitaxial layer with a thickness of 40μm and a resistivity of 5Ω·cm was grown on the front side of the substrate.

[0065] 3D microscopy tests show that regardless of the target thickness of the epitaxial layer (range 20-50 μm) or the target resistivity (range 0.1 Ω·cm to 10 Ω·cm), this invention effectively prevents backside protrusions by ensuring the integrity of the silicon dioxide layer at the backside edge. Various embodiments demonstrate the broad adaptability of this invention to different product specifications.

[0066] Comparative Example 1

[0067] Prepare polished wafers: Prepare double-sided polished monocrystalline silicon wafers, the same as in Example 1.

[0068] Deposit a polycrystalline silicon layer: Deposit the same polycrystalline silicon layer as in Example 1.

[0069] First, a silicon dioxide layer is deposited: using the same process as in Example 1, a silicon dioxide layer with a thickness of approximately 4500 Å is grown on the back side of the silicon wafer.

[0070] HF etching: Same as in Example 1, remove the silicon dioxide layer with a width of 0.2 mm on the back chamfered surface.

[0071] Edge polishing: The silicon wafer undergoes edge polishing for 70 seconds to remove the polysilicon exposed after HF etching. This step inevitably removes some of the polysilicon at the junction of the flat back surface and the chamfered surface. Figure 1 Silicon dioxide and polycrystalline silicon in region B.

[0072] Single-sided polishing and cleaning: The same single-sided polishing and cleaning process as in Example 1 was used to prepare the heavily doped substrate silicon wafer with the "Poly+LTO" structure in this comparative example.

[0073] Epitaxial growth: Epitaxial growth is performed on the heavily doped substrate silicon wafer obtained in the above steps. The epitaxial growth parameters in this step are the same as those in Example 1, and the heavily doped substrate epitaxial wafer of this comparative example is obtained.

[0074] The back edge of the heavily doped substrate epitaxial wafer prepared in this comparative example was observed using a 2D microscope. Figure 5 As shown, at position B, where the back side meets the front side, there is a partial LTO defect, indicating that the LTO has been removed, and some silicon absorption can be seen in the defective LTO area. Figure 6 The figures show 3D microscopic images and test results of the back side of the heavily doped substrate epitaxial wafer prepared in this comparative example. In the figures, A represents the chamfered area of ​​the back side, B represents the boundary between the chamfered area and the flat surface of the back side, and C represents the flat surface area of ​​the back side. As can be seen from the figures, region B on the back side of the epitaxial wafer prepared in this comparative example has a significant protrusion, with a width of approximately 11.3 μm and a height of approximately 2.8 μm. Compared with the smooth and flat region B in the examples, this demonstrates that the present invention effectively solves the technical problem of back side edge protrusion by adjusting the process sequence.

[0075] The above embodiments are intended to illustrate the essential content of the present invention, but are not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of protection of the present invention.

Claims

1. A method for processing heavily doped substrate silicon wafers, characterized in that, The processing method includes the following steps in sequence: Step (1): Provide a double-sided polished heavily doped monocrystalline silicon wafer; Step (2): Deposit a polycrystalline silicon layer on the back side of the heavily doped monocrystalline silicon wafer; Step (3): Polish the edges of the heavily doped monocrystalline silicon wafer on which the polycrystalline silicon layer is deposited to remove the polycrystalline silicon on its chamfered surface. Step (4): Deposit a silicon dioxide layer on the back side of the heavily doped monocrystalline silicon wafer after edge polishing; Step (5): Etch the heavily doped single-crystal silicon wafer on which the silicon dioxide layer is deposited to remove the silicon dioxide layer on the back chamfered surface with a predetermined width from the edge; the predetermined width is 0.1 mm to 0.4 mm, so that the junction of the back chamfered surface and the back flat surface is completely covered by the silicon dioxide layer. Step (6): Polish one side of the etched heavily doped single-crystal silicon wafer to remove the polycrystalline silicon layer on its front side, and clean it to obtain the heavily doped substrate silicon wafer.

2. The method for processing a heavily doped substrate silicon wafer according to claim 1, characterized in that, The polycrystalline silicon layer is grown using low-pressure chemical vapor deposition and has a thickness of 7200 Å to 8800 Å.

3. The method for processing a heavily doped substrate silicon wafer according to claim 1, characterized in that, The silica layer is grown using atmospheric pressure chemical vapor deposition and has a thickness of 4000 Å to 5000 Å.

4. The method for processing a heavily doped substrate silicon wafer according to claim 1, characterized in that, The etching is a wet etching process using hydrofluoric acid solution.

5. The method for processing a heavily doped substrate silicon wafer according to claim 1, characterized in that, The material removal on the front side of the single-sided polishing is 1.5 μm to 3 μm.

6. A heavily doped substrate epitaxial wafer, characterized in that, The epitaxial wafer is formed by epitaxial growth using a heavily doped silicon wafer prepared by any one of the processing methods described in claims 1 to 5 as the substrate.

7. The heavily doped substrate epitaxial wafer according to claim 6, characterized in that, The epitaxial wafer includes: A heavily doped substrate silicon wafer, wherein the back side of the heavily doped substrate silicon wafer has a composite back-sealing structure consisting of a polycrystalline silicon layer and a silicon dioxide layer covering the polycrystalline silicon layer; An epitaxial layer formed on the front side of the heavily doped silicon substrate; Wherein, there is no protrusion formed by polysilicon deposition during the epitaxial growth process at the junction of the back chamfered surface and the back flat surface of the epitaxial wafer, and the junction is completely covered by the silicon dioxide layer.

8. The heavily doped substrate epitaxial wafer according to claim 7, characterized in that, The thickness of the epitaxial layer is 20 μm to 50 μm.

9. The heavily doped substrate epitaxial wafer according to claim 7, characterized in that, The resistivity of the epitaxial layer is from 0.1 Ω·cm to 10 Ω·cm.

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