Chip copper interconnection layer deplating recovery method and system, electronic equipment and medium

Abstract

The invention provides a chip copper interconnection layer deplating recovery method and system, electronic equipment and a medium, and the method comprises the steps: recognizing an active reaction boundary dissolved by a copper interconnection layer in real time, and dynamically dividing a microelectrode array into a core deplating region, an edge inhibition region and an isolation region according to the active reaction boundary; a forward dissolving electric field is applied to the core deplating area to efficiently remove a copper material, meanwhile, a reverse restraining electric field is applied to the edge restraining area to actively restrain transverse etching of the side wall, the isolation area avoids interference on a non-target area through a passive or high-resistance state, and therefore localized precise regulation and control of the deplating process are achieved. According to the invention, the uncontrollable erosion of the side wall of the micron-sized copper circuit is obviously reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method, system, electronic device, and medium for stripping and recycling copper interconnect layers on a chip. Background Technology

[0002] In the semiconductor manufacturing and advanced packaging fields, the copper interconnect layers of chips often require stripping during recycling or repair. Currently, the commonly used stripping methods in the industry are mainly based on wet chemical etching or bulk electrochemical dissolution.

[0003] However, existing stripping methods inevitably cause excessive erosion of the sidewalls of copper circuits with linewidths only on the micrometer scale, altering the width of the designed pattern. In other words, current technologies struggle to effectively remove copper material while maintaining the original dimensions and geometry of the micrometer-scale circuit pattern. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, this application provides a method, system, electronic device, and medium for stripping and recovering copper interconnect layers from a chip. The specific technical solution is as follows: In its first part, this application proposes a method for stripping and recovering copper interconnect layers on a chip. The method involves applying an electric field to the copper interconnect layer of the chip to be stripped using a microelectrode array to perform the stripping. The method includes: Step S1: Obtain real-time electrochemical state information of the surface of the copper interconnect layer to be deplated on the chip; Step S2: Based on the real-time electrochemical state information and the preset graphic information of the copper interconnect layer to be stripped, identify the active reaction boundary of the current copper interconnect layer to be stripped. Step S3: Based on the active reaction boundary, dynamically divide the microelectrode units in the microelectrode array into a core deplating area, an edge suppression area, and an isolation area; Step S4: Apply a positive dissolution electric field to the microelectrode unit located in the core deplating area, apply a reverse suppression electric field to the microelectrode unit located in the edge suppression area, and set the microelectrode unit located in the isolation area to a passive or high-resistivity state. Step S5: Repeat steps S1 to S4 to update the active reaction boundary, and dynamically partition and apply an electric field to the microelectrode array according to the updated active reaction boundary until the plating is removed.

[0005] In one embodiment, "step S3, dynamically dividing the microelectrode units in the microelectrode array into a core deplating region, an edge suppression region, and an isolation region according to the active reaction boundary" includes: Based on the boundary of the active reaction; The microelectrode unit that covers the undissolved area behind the normal of the active reaction boundary and corresponds to the undissolved area of ​​the copper interconnect layer to be deplated is defined as the core deplating area; The microelectrode units located within a predetermined range of the lateral edge of the active reaction boundary are divided into the edge suppression region; The remaining microelectrode units in the microelectrode array that are not included in the core deplating area and the edge suppression area are designated as the isolation area.

[0006] In one embodiment, "step S4, applying a positive dissolution electric field to the microelectrode unit located in the core stripping zone, applying a reverse suppression electric field to the microelectrode unit located in the edge suppression zone, and setting the microelectrode unit located in the isolation zone to a passive or high-resistivity state" includes: An adjustable pulse voltage waveform is independently applied to each microelectrode unit assigned to the core stripping zone to form the positive dissolution electric field; wherein, at least one parameter of the pulse voltage waveform is adjusted in real time according to the local current density at each microelectrode unit to maintain a constant dissolution current density. An inhibition voltage is applied to each microelectrode unit that is assigned to the edge inhibition region to form the reverse inhibition electric field; wherein, an inhibition voltage of a corresponding amplitude is set for each microelectrode unit according to the distance between each microelectrode unit and the active reaction boundary, and the amplitude of the inhibition voltage is negatively correlated with the distance; All microelectrode units assigned to the isolation region are set to a passive or high-resistivity state.

[0007] In one embodiment, the microelectrode array integrates multiple micropotential sensors 21. "Step S1, acquiring real-time electrochemical state information of the surface of the copper interconnect layer to be stripped from the chip," includes: The two-dimensional potential distribution spectrum covering the area of ​​the copper interconnect layer to be deplated is obtained by scanning through multiple micro potential sensors 21, which serves as real-time electrochemical state information.

[0008] In one embodiment, "step S2, based on the real-time electrochemical state information and the preset graphic information of the copper interconnect layer to be stripped, identifies the active reaction boundary of the current dissolution of the copper interconnect layer to be stripped," includes: The obtained two-dimensional potential distribution spectrum is spatially registered with the preset graphic information of the copper interconnect layer to be deplated; The registered two-dimensional potential distribution map is compared with the preset graphic information, and the boundary between the dissolved and undissolved areas of the copper interconnect layer to be deplated is identified based on the potential difference. Image edge extraction processing is performed on the boundary, and the extracted continuous edge lines are defined as the active reaction boundary of the current copper interconnect layer to be deplated and dissolved.

[0009] In one embodiment, steps S1 to S4 form a closed-loop control cycle, wherein the closed-loop control cycle is less than or equal to 1 millisecond.

[0010] In one embodiment, step S4 further includes: Fresh electrolyte is continuously supplied to the reaction region between the copper interconnect layer to be deplated and the microelectrode array, while reaction waste liquid containing copper ions is discharged simultaneously. Real-time monitoring of the dissolution current information of the microelectrode unit in the core stripping zone; The flow rate of the fresh electrolyte is dynamically adjusted based on the dissolved current information to maintain a stable mass transport state at the reaction interface.

[0011] Part Two: This application proposes a chip copper interconnect layer stripping and recycling system for implementing any of the chip copper interconnect layer stripping and recycling methods described above. The system includes: The microelectrode array module includes multiple microelectrode units; The sensing module, integrated in the microelectrode array module, is used to acquire real-time electrochemical state information of the surface of the copper interconnect layer to be deplated on the chip. The control module is communicatively connected to both the microelectrode array module and the sensing module, and is configured as follows: Based on the real-time electrochemical state information and the preset graphic information of the copper interconnect layer to be stripped, the active reaction boundary of the current copper interconnect layer to be stripped is identified. Based on the active reaction boundary, dynamic partitioning instructions and electric field control instructions are generated. The dynamic partitioning instructions are used to dynamically divide the multiple microelectrode units into a core deplating area, an edge suppression area, and an isolation area. The electric field control instructions are used to apply corresponding electric fields to the microelectrode units in the core deplating area, the edge suppression area, and the isolation area. As the stripping process progresses, the active reaction boundary is periodically updated, and the dynamic partitioning command and the electric field control command are updated accordingly.

[0012] Part Three, this application proposes an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements any of the methods described above.

[0013] Part Four, this application proposes a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in any of the preceding descriptions.

[0014] This application has at least the following beneficial effects: This application effectively overcomes the problem of excessive sidewall erosion caused by existing wet chemical etching or overall electrochemical dissolution by employing a microelectrode array to apply an electric field and combining real-time electrochemical state information with preset pattern information for dynamic feedback control. Specifically, this application identifies the active reaction boundary of copper interconnect layer dissolution in real time and dynamically divides the microelectrode array into a core stripping region, an edge suppression region, and an isolation region accordingly, thereby achieving localized and precise control of the stripping process. Specifically, a positive dissolution electric field is applied to the core stripping region to efficiently remove copper material, while a reverse suppression electric field is applied to the edge suppression region to actively suppress lateral etching of the sidewalls, and the isolation region avoids interference with non-target areas through a passive or high-resistivity state.

[0015] This application utilizes dynamic control across distinct zones and fields to ensure the stripping process strictly adheres to preset pattern boundaries, significantly reducing uncontrollable erosion of the sidewalls of micron-level copper circuits. This allows for the complete removal of the target copper layer while maximally maintaining the original design width, geometry, and dimensional accuracy of the circuitry. Furthermore, a closed-loop control mechanism based on real-time electrochemical states further enhances the controllability and adaptability of the stripping process, effectively guaranteeing the dimensional integrity of micron-level circuits and laying a high-precision process foundation for subsequent chip repair or material recycling. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic cross-sectional view of the overall structure provided in this embodiment; Figure 2 This is a schematic cross-sectional view of the overall structure provided in this embodiment; Figure 3 A schematic diagram of a chip copper interconnect layer stripping and recycling system provided in this embodiment. Figure 1 ; Figure 4 A schematic diagram of a chip copper interconnect layer stripping and recycling system provided in this embodiment. Figure 2 .

[0018] Figure label: 1-Microelectrode array module; 2-Sensing module; 3-Microfluidic module; 4-Control module; 21-Potential sensor; 22-pH sensor. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0020] In the description of this application, it should be noted that the terms "vertical", "up", "down", "horizontal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0022] like Figure 1 As shown, this embodiment proposes a chip copper interconnect layer stripping and recycling system, including a microelectrode array module 1, a sensing module 2, a microfluidic module 3, and a control module 4.

[0023] The microelectrode array module 1 includes multiple microelectrode units, which are used to generate an adjustable electric field based on the instructions of the control module 4.

[0024] For example, a microelectrode array is fabricated on a silicon oxide insulating substrate using standard semiconductor microfabrication processes (such as photolithography, metal sputtering, and electroplating). The active material of the microelectrode units is a chemically stable platinum-iridium alloy (Pt90Ir10), designed as circular point electrodes with a diameter of 5 micrometers, arranged in a hexagonal close-packed manner with a center-to-center spacing of 10 micrometers, which helps to form a more uniform initial electric field background on a macroscopic scale. Each microelectrode unit is connected to a pad at the edge of the array via an independent conductive lead, wherein the conductive lead is made of titanium nitride (TiN).

[0025] The sensing module 2 is integrated into the microelectrode array module 1. The sensing module 2 includes a potential sensor 21 and a pH sensor 22. The potential sensor 21 is used to obtain real-time electrochemical state information of the surface of the copper interconnect layer to be stripped from the chip, and the pH sensor 22 is used to obtain real-time pH value information of the surface of the copper interconnect layer to be stripped from the chip.

[0026] For example, the potential sensor 21 is a miniature Ag / AgCl reference electrode, and is distributed in the microelectrode array module 1 at a density of one potential sensor 21 embedded in the center of every 10×10 microelectrode unit regions. For example, the pH sensor 22 is an IrO2 thin film electrode, and is integrated in the microelectrode array module 1 at a density of one pH sensor 22 per 20×20 microelectrode unit regions.

[0027] For example, the microelectrode array module 1 is encapsulated in quartz glass, exposing only the electrode working surfaces and the sensor. The back side of the microelectrode array module 1 is bonded to a high-density interconnect board using flip-chip bonding technology. The high-density interconnect board integrates a high-speed analog switch matrix chip (such as the ADGS1412 series) and connects to the control module 4 through a high-speed FMC (FPGA Mezzanine Card) interface, thereby enabling independent and rapid address gating and potential control of thousands of microelectrode units, with switching times down to the nanosecond level.

[0028] The microfluidic module 3 includes a reaction chamber. This chamber creates a stable and controllable closed-loop liquid-phase reaction environment between the microelectrode array and the chip workpiece, enabling precise delivery of reactants and timely removal of products. For example, the reaction chamber includes a top cover and a microchannel base. The microchannel base is made of polydimethylsiloxane (PDMS) using soft lithography and has pre-patterned microchannels processed inside. When the microchannel base and top cover are sealed together, the microchannels form the fluid channels of the closed reaction chamber. The top cover is located above the microchannel base and supports and fixes the chip to be processed, ensuring that the copper interconnect layer to be removed from the chip faces the microchannels. The microchannels are 100 micrometers high, which helps ensure that the electrolyte flow is in a stable laminar flow state, thereby reducing the diffusion layer thickness and promoting mass transfer. The microelectrode array is located directly below the microchannel base. The surfaces of the microelectrode units in the microelectrode array are in close contact with the bottom surface of the microchannel base or precisely aligned through extremely small gaps. This allows each microelectrode unit in the microelectrode array to establish an electrochemical interaction with a corresponding local area on the copper interconnect layer to be stripped through the electrolyte medium within the microchannel. For example, a tree-like fractal porous channel structure is provided in the microchannel inlet region to ensure that the electrolyte is uniformly distributed throughout the working area.

[0029] The microfluidic module 3 also includes a pumping unit connected to the inlet and outlet fluids of the reaction chamber. The pumping unit typically comprises two precision injection pumps, used to inject fresh electrolyte into the sealed reaction chamber at a constant flow rate and to extract waste liquid containing reaction products from the sealed reaction chamber, respectively. The pumping unit communicates with the control module 4 to dynamically adjust the flow rate within the range of 0.1 to 10 µL / min based on commands from the control module 4, thereby matching the stripping reaction rate. Furthermore, a pressure monitoring unit, such as a miniature pressure sensor, is integrated within the microchannel to monitor pressure changes within the channel in real time, determining whether the flow is smooth or if there are any abnormalities such as blockages or leaks.

[0030] The control module 4 is communicatively connected to the microelectrode array module 1 and the sensing module 2. The control module 4 is configured to: identify the active reaction boundary of the copper interconnect layer to be deplated based on real-time electrochemical state information and preset graphic information of the copper interconnect layer to be deplated; generate dynamic partitioning instructions and electric field control instructions according to the active reaction boundary; the dynamic partitioning instructions are used to dynamically divide multiple microelectrode units into core deplating area, edge suppression area and isolation area; the electric field control instructions are used to apply corresponding electric fields to the microelectrode units in the core deplating area, edge suppression area and isolation area; and periodically update the active reaction boundary as the deplating process progresses, and update the dynamic partitioning instructions and electric field control instructions accordingly.

[0031] For example, control module 4 uses a Xilinx Kintex-7 series FPGA chip. The peripheral hardware of the FPGA chip includes: a multi-channel 16-bit ADC module (sampling rate ≥ 1 MSPS) for high-speed acquisition of signals from all sensors; and a multi-channel DAC module (update rate ≥ 1 MHz) for generating the complex voltage waveforms required by each microelectrode unit. Internally, the FPGA chip implements fast sequence control of the switching matrix through programmable logic resources and runs advanced control algorithms through its integrated hard-core processor system (such as an ARM Cortex-A9).

[0032] This embodiment also proposes a method for stripping and recycling copper interconnect layers on a chip, applied to the chip copper interconnect layer stripping and recycling system described above. Specifically, an electric field is applied to the copper interconnect layer of the chip to be stripped using a microelectrode array to perform the stripping. The method includes: Step S1: Obtain real-time electrochemical state information of the surface of the copper interconnect layer to be stripped from the chip. Specifically, this includes: Step S101: Clamp the chip onto the reaction chamber and initialize the control module 4; Step S102: Obtain real-time electrochemical state information of the surface of the copper interconnect layer to be stripped from the chip, and preprocess the real-time electrochemical state information.

[0033] Step S101 includes: positioning the chip with the copper interconnect layer to be stripped facing down, precisely aligning it, and mounting it on the top cover plate. After sealing the top cover plate and the microchannel base, the injection pump is started to inject a pre-prepared weakly acidic electrolyte into the sealed reaction chamber at an initial flow rate of 0.5 µL / min. The weakly acidic electrolyte can be a 0.1 M Na2SO4 solution containing 1 mM benzotriazole as a corrosion inhibitor. Simultaneously, the FPGA loads the computer-aided design (CAD) drawing file of the copper interconnect layer to be stripped from the chip and connects all microelectrode units to zero potential (virtual ground) via a switch matrix.

[0034] Step S102 includes: FPGA controlling the switch matrix to sequentially connect each integrated micro Ag / AgCl reference electrode to the ADC channel in a high-speed scanning mode to acquire high-density raw potential data. Simultaneously, all IrO2 pH sensors 22 are scanned at a lower frequency (e.g., once every 10 control cycles) to acquire sparse, localized raw pH data.

[0035] Within the FPGA's logic units, the raw potential data undergoes real-time digital filtering, while the raw pH data is subjected to median filtering to remove outliers. The processed data is then transmitted to the hard-core processor system (PS). In the PS, the potential data is used to generate a high-resolution real-time two-dimensional potential distribution map via spatial interpolation. Simultaneously, the pH data undergoes the same spatial interpolation process to generate a corresponding real-time two-dimensional pH distribution map. The real-time two-dimensional potential and pH distribution maps are perfectly aligned in spatial coordinates, together constituting the multiphysics state of the reaction interface.

[0036] Step S2: Based on real-time electrochemical state information and preset graphic information of the copper interconnect layer to be removed, identify the active reaction boundary of the current copper interconnect layer dissolution. Specifically, the FPGA performs digital image registration between the real-time two-dimensional potential distribution spectrum obtained in step S102 and the pre-loaded CAD graphic file. After registration, the two images are aligned pixel by pixel in space. A potential difference spectrum is obtained through image subtraction. In the potential difference spectrum, a significant potential gradient change band is shown between the copper interconnect layer region that has not yet started to dissolve (with good conductivity) and the region that has completely dissolved and exposed the insulating substrate (such as SiO2). The Sobel edge detection operator is applied to the potential difference spectrum to extract a continuous boundary line with a width of 1-2 pixels. This boundary line is the front where the copper dissolution reaction is currently occurring, and this boundary line is taken as the active reaction boundary. The algorithm also calculates the normal direction of each point on the boundary line (pointing to the undissolved copper layer) to obtain the precise geometry and position of the active reaction boundary.

[0037] Step S3: Based on the active reaction boundary, dynamically divide the microelectrode units in the microelectrode array into a core deplating zone, an edge suppression zone, and an isolation zone. The dynamic division is based on the active reaction boundary.

[0038] Specifically, the microelectrode units covering the undissolved bulk area of ​​the copper interconnect layer to be stripped, located behind the boundary of the active reaction, are designated as the core stripping zone. For example, using the boundary point normal direction calculated in step S2 (pointing inwards towards the copper layer, i.e., the direction of the undissolved bulk copper) as a reference, all microelectrode units within a depth range of approximately 3 to 5 micrometers from the active reaction boundary along the boundary point normal direction are selected. These microelectrode units face the copper body to be dissolved and are responsible for driving the longitudinal dissolution of the copper.

[0039] Specifically, the microelectrode units located within a predetermined range on the lateral edge of the active reaction boundary are designated as edge suppression regions. For example, using the boundary line identified in step S2 as a reference, a width of 1 to 2 micrometers is extended to both sides of the boundary line (perpendicular to the boundary normal), defining the microelectrode units falling within this strip-shaped region as edge suppression regions. This strip-shaped region corresponds to the sidewalls of the copper lines and an adjacent minimal area, used for subsequently applying a suppression electric field to protect the sidewalls.

[0040] The remaining microelectrode units in the microelectrode array that are not included in the core stripping area and edge suppression area are designated as isolation areas. These microelectrode units either correspond to areas that have been completely stripped (such as insulating substrates) or to processing areas far from the current active reaction boundary, and do not need to participate in the reaction during this control cycle.

[0041] Step S4: Apply a positive dissolution electric field to the microelectrode unit located in the core stripping zone, apply a reverse suppression electric field to the microelectrode unit located in the edge suppression zone, and set the microelectrode unit located in the isolation zone to a passive or high-resistivity state.

[0042] Specifically, an adjustable high-frequency pulsed voltage waveform is applied independently to each microelectrode unit within the core stripping zone to create a reinforced positive dissolution electric field. The initial pulse amplitude is set based on the target dissolution rate using an electrochemical kinetic model (such as the Tafel equation). Specifically, at least one parameter of the pulse voltage waveform is adjusted in real time based on the local current density at each microelectrode unit to maintain a constant dissolution current density. Specifically, the FPGA performs closed-loop regulation of the pulse voltage waveform of each microelectrode unit based on real-time feedback of the local current density, ensuring a uniform and efficient dissolution process. For example, a PID controller dynamically adjusts the duty cycle of the pulse voltage waveform of the microelectrode unit. For instance, when the local current density at a microelectrode unit is detected to be lower than a set target value, the PID controller increases its pulse duty cycle to enhance the electrochemical driving force; conversely, it decreases the duty cycle. This ensures a constant and optimal longitudinal dissolution current density throughout the entire core stripping zone, achieving uniform stripping.

[0043] In this process, a suppression voltage is applied to each microelectrode unit within the edge suppression region to create a reverse suppression electric field. The voltage is determined based on the distance between each microelectrode unit located in the edge suppression region and the boundary of the active reaction. Set a suppression voltage of appropriate amplitude for each microelectrode unit located in the edge suppression region. And suppress the amplitude of the voltage. With distance They exhibit a negative correlation, specifically determined by the following formula:

[0044] in, The suppression coefficient is, and , Preset the total width for the edge suppression region. For example, It is 2 micrometers.

[0045] This formula constructs the amplitude of the suppression voltage. With distance A negatively correlated gradient electric field makes the area immediately adjacent to the active reaction boundary ( The microelectrode unit with a suppression voltage of approximately 0 has the strongest suppression voltage (approximately 0). ), sufficient to effectively counteract the stray electric field that causes lateral erosion; as one moves away from the active reaction boundary ( (Increase), the suppression voltage decreases linearly until the outer edge of the edge suppression region ( When the value drops to zero, the reaction is precisely and gently constrained by a gradient electric field, avoiding the introduction of new inhomogeneities.

[0046] Furthermore, for each microelectrode unit located in the edge suppression region, the FPGA queries the real-time two-dimensional pH distribution map generated in step S102 or obtains the local pH value at its corresponding location based on the spatial coordinates of each microelectrode unit, either by querying the map or by bilinear interpolation. .Will Compared with the initial background pH of the electrolyte By comparison, the local pH change was obtained. For example, It is 4.5.

[0047] like , A preset threshold indicates that the localized area is experiencing severe reaction or insufficient fluid turnover, potentially exacerbating the risk of lateral erosion. In this case, the FPGA dynamically fine-tunes the suppression voltage coefficient of the microelectrode unit. ,in This is the pH feedback gain coefficient. Substitute the amplitude of the suppression voltage mentioned above With distance The formula is used to calculate the final suppression voltage. This allows for the automatic enhancement of the suppressive electric field in regions of changing chemical environments, achieving electrochemical synergistic control. For example, It is 0.2. It is 0.5.

[0048] Simultaneously, the FPGA performs a global analysis of the entire pH distribution map, calculating the average pH change at all monitoring points. .like If the value continuously exceeds a lower threshold, an instruction is generated, according to... The proportion of this increases the overall flow rate of the microfluidic system (β is the adjustment coefficient) to stabilize the reaction environment. Among these, The threshold is 0.1.

[0049] In this process, all microelectrode units assigned to the isolation zone are configured as passive or high-impedance states. Specifically, for all microelectrode units in the isolation zone, the FPGA uses a switching matrix to connect them uniformly to the FPGA's virtual ground potential and sets their internal circuitry to a high-impedance input state. This makes the microelectrode units in the isolation zone electrically passive or floating, neither actively outputting electric fields nor sensitively receiving signals, thereby completely eliminating their electric field interference to the current core reaction area and ensuring the purity and controllability of the local electric field.

[0050] Step S4 further includes: the FPGA dynamically adjusts the injection pump flow rate of the microfluidic module 3 using a PID control algorithm based on the currently estimated total dissolution rate, so as to correspondingly increase the flow rate of fresh electrolyte delivery and waste liquid discharge when the dissolution rate increases, thereby ensuring stable mass transfer at the reaction interface. The total dissolution rate is obtained by integrating the total current in the core stripping zone.

[0051] Step S5: Repeat steps S1 to S4 to update the active reaction boundary, and dynamically partition the microelectrode array and apply an electric field according to the updated active reaction boundary until the plating is removed.

[0052] Specifically, steps S1 to S4 form a closed-loop control cycle, which is less than or equal to 1 millisecond.

[0053] Specifically, when the potential characteristic value of the target stripping area (i.e., the area where the copper interconnect layer to be stripped is located) is detected to be consistent with the potential characteristic value of the substrate material (which has been pre-calibrated) and remains stable for more than a preset number of consecutive cycles, the FPGA determines that the stripping is complete. For example, the preset number of consecutive cycles is 10 cycles.

[0054] If the termination condition is not met (i.e., the potential characteristic value of the target stripping area is inconsistent with the potential characteristic value of the substrate material), the FPGA immediately starts the next control cycle. That is, after completing one cycle (about 1 millisecond) of electric field application, the FPGA automatically and without intervals repeats steps S1 to S4.

[0055] This embodiment effectively overcomes the problem of excessive sidewall erosion caused by existing wet chemical etching or overall electrochemical dissolution by employing a microelectrode array to apply an electric field and combining real-time electrochemical state information with preset pattern information for dynamic feedback control. Specifically, this embodiment identifies the active reaction boundary of copper interconnect layer dissolution in real time and dynamically divides the microelectrode array into a core stripping zone, an edge suppression zone, and an isolation zone accordingly, thereby achieving localized and precise control of the stripping process. Specifically, a positive dissolution electric field is applied to the core stripping zone to efficiently remove copper material, while a reverse suppression electric field is applied to the edge suppression zone to actively suppress lateral etching of the sidewalls, and the isolation zone avoids interference with non-target areas through a passive or high-resistivity state.

[0056] Traditional methods using macroscopic electrodes cause the electric field to diverge at the microscale, inevitably leading to lateral etching. This application fundamentally changes the way the electric field is applied by identifying the active reaction boundary in real time and dynamically dividing the microelectrode array into different functional regions accordingly, achieving ultra-high processing accuracy and extremely low lateral etching. By applying a positive dissolution electric field to drive efficient longitudinal dissolution in the core stripping region, while applying a gradient-attenuated reverse suppression electric field in the adjacent edge suppression region, a dynamic electric field barrier is actively constructed laterally at the reaction boundary, effectively counteracting stray electric field components that cause lateral dissolution. Combined with the shielding of irrelevant electric fields by the isolation region, the dissolution reaction is strictly constrained within the preset longitudinal path. Furthermore, the algorithm moves synchronously with the real-time active reaction boundary, achieving full protection of the stripping path. Experimental results show that this method can precisely control the lateral etching amount at the sub-micron level, thereby completely removing the target copper interconnect layer while maintaining the original design width, geometry, and sidewall integrity of the circuit to the maximum extent, laying a high-precision foundation for subsequent chip repair or reuse.

[0057] The core of the control logic in this application lies in comparing and making decisions based on real-time sensing data (i.e., real-time electrochemical state information) with preset chip pattern information, rather than relying on pre-programmed processing paths. This enables the control unit to automatically identify arbitrary imported copper interconnect pattern boundaries and drive the microelectrode array module 1 to perform real-time tracking processing. The adaptive working mode of dynamically dividing microelectrode units based on active reaction boundaries provided by this application allows the same system to handle circuits of different shapes and sizes without changing hardware or complex parameter tuning, significantly improving flexibility and intelligence, and demonstrating strong versatility.

[0058] The plating removal method provided in this application is performed at room temperature and pressure, and is a purely electrochemical process that does not introduce mechanical stress or significant thermal effects. This method will not damage brittle semiconductor substrates (such as silicon) and surrounding dielectric layers (such as SiO2 and SiN), fully meeting the stringent requirements of advanced semiconductor manufacturing and packaging processes for cleanliness, low stress, and low thermal budgets. It is easily integrated into existing chip repair, failure analysis, or resource recycling processes. Example 2 This embodiment proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the method described in Embodiment 1.

[0059] Example 3 This embodiment proposes a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the method described in Embodiment 1.

[0060] Those skilled in the art will understand that the modules or steps described above in this application can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby allowing them to be stored in a storage device for execution by a computing device, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0061] Note that the above description is merely a preferred embodiment and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of this application, and the scope of this application is determined by the scope of the appended claims.

[0062] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for stripping and recycling copper interconnect layers in a chip, characterized in that, The method of removing copper plating from a chip by applying an electric field to the copper interconnect layer to be removed using a microelectrode array includes: Step S1: Obtain real-time electrochemical state information of the surface of the copper interconnect layer to be deplated on the chip; Step S2: Based on the real-time electrochemical state information and the preset graphic information of the copper interconnect layer to be stripped, identify the active reaction boundary of the current copper interconnect layer to be stripped. Step S3: Based on the active reaction boundary, dynamically divide the microelectrode units in the microelectrode array into a core deplating area, an edge suppression area, and an isolation area; Step S4: Apply a positive dissolution electric field to the microelectrode unit located in the core deplating area, apply a reverse suppression electric field to the microelectrode unit located in the edge suppression area, and set the microelectrode unit located in the isolation area to a passive or high-resistivity state. Step S5: Repeat steps S1 to S4 to update the active reaction boundary, and dynamically partition and apply an electric field to the microelectrode array according to the updated active reaction boundary until the plating is removed.

2. The method for stripping and recycling copper interconnect layers in a chip according to claim 1, characterized in that, "Step S3: Based on the active reaction boundary, dynamically divide the microelectrode units in the microelectrode array into a core deplating zone, an edge suppression zone, and an isolation zone," including: Based on the boundary of the active reaction; The microelectrode unit that covers the undissolved area behind the normal of the active reaction boundary and corresponds to the undissolved area of ​​the copper interconnect layer to be deplated is defined as the core deplating area; The microelectrode units located within a predetermined range of the lateral edge of the active reaction boundary are divided into the edge suppression region; The remaining microelectrode units in the microelectrode array that are not included in the core deplating area and the edge suppression area are designated as the isolation area.

3. A method for stripping and recycling copper interconnect layers in a chip according to claim 1 or 2, characterized in that, "Step S4, applying a positive dissolution electric field to the microelectrode unit located in the core deplating area, applying a reverse suppression electric field to the microelectrode unit located in the edge suppression area, and setting the microelectrode unit located in the isolation area to a passive or high-resistivity state," includes: An adjustable pulse voltage waveform is independently applied to each microelectrode unit assigned to the core stripping zone to form the positive dissolution electric field; wherein, at least one parameter of the pulse voltage waveform is adjusted in real time according to the local current density at each microelectrode unit to maintain a constant dissolution current density. An inhibition voltage is applied to each microelectrode unit that is assigned to the edge inhibition region to form the reverse inhibition electric field; wherein, an inhibition voltage of a corresponding amplitude is set for each microelectrode unit according to the distance between each microelectrode unit and the active reaction boundary, and the amplitude of the inhibition voltage is negatively correlated with the distance; All microelectrode units assigned to the isolation region are set to a passive or high-resistivity state.

4. The method for stripping and recycling copper interconnect layers in a chip according to claim 1, characterized in that, The microelectrode array integrates multiple micropotential sensors 21. "Step S1, acquiring real-time electrochemical state information of the surface of the copper interconnect layer to be deplated on the chip," includes: The two-dimensional potential distribution spectrum covering the area of ​​the copper interconnect layer to be deplated is obtained by scanning through multiple micro potential sensors 21, which serves as real-time electrochemical state information.

5. The method for stripping and recycling copper interconnect layers in a chip according to claim 4, characterized in that, "Step S2, based on the real-time electrochemical state information and the preset graphic information of the copper interconnect layer to be stripped, identify the active reaction boundary of the current dissolution of the copper interconnect layer to be stripped," includes: The obtained two-dimensional potential distribution spectrum is spatially registered with the preset graphic information of the copper interconnect layer to be deplated; The registered two-dimensional potential distribution map is compared with the preset graphic information, and the boundary between the dissolved and undissolved areas of the copper interconnect layer to be deplated is identified based on the potential difference. Image edge extraction processing is performed on the boundary, and the extracted continuous edge lines are defined as the active reaction boundary of the current copper interconnect layer to be deplated and dissolved.

6. The method for stripping and recycling copper interconnect layers in a chip according to claim 1, characterized in that, Steps S1 to S4 form a closed-loop control cycle, which is less than or equal to 1 millisecond.

7. The method for stripping and recycling copper interconnect layers in a chip according to claim 1, characterized in that, Also includes: Fresh electrolyte is continuously supplied to the reaction region between the copper interconnect layer to be deplated and the microelectrode array, while reaction waste liquid containing copper ions is discharged simultaneously. Real-time monitoring of the dissolution current information of the microelectrode unit in the core stripping zone; The flow rate of the fresh electrolyte is dynamically adjusted based on the dissolved current information to maintain a stable mass transport state at the reaction interface.

8. A chip copper interconnect layer stripping and recycling system, characterized in that, The system for implementing the method of any one of claims 1-7 comprises: The microelectrode array module includes multiple microelectrode units; The sensing module, integrated in the microelectrode array module, is used to acquire real-time electrochemical state information of the surface of the copper interconnect layer to be deplated on the chip. The control module is communicatively connected to both the microelectrode array module and the sensing module, and is configured as follows: Based on the real-time electrochemical state information and the preset graphic information of the copper interconnect layer to be stripped, the active reaction boundary of the current copper interconnect layer to be stripped is identified. Based on the active reaction boundary, dynamic partitioning instructions and electric field control instructions are generated. The dynamic partitioning instructions are used to dynamically divide the multiple microelectrode units into a core deplating area, an edge suppression area, and an isolation area. The electric field control instructions are used to apply corresponding electric fields to the microelectrode units in the core deplating area, the edge suppression area, and the isolation area. As the stripping process progresses, the active reaction boundary is periodically updated, and the dynamic partitioning command and the electric field control command are updated accordingly.

9. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores a computer program thereon, which, when executed by a processor, implements the method as described in any one of claims 1 to 7.

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