Semiconductor device and semiconductor device manufacturing method
By introducing a less dense intermediate metal layer as a buffer layer in semiconductor devices, the stress concentration at the interface between the contact metal layer and the metal interconnect layer is alleviated, the risk of interlayer cracking is solved, electrical performance is improved, and the manufacturing process is simplified.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUNAN SANAN SEMICON CO LTD
- Filing Date
- 2024-10-11
- Publication Date
- 2026-04-24
AI Technical Summary
In existing semiconductor devices, the interlayer stress between the contact metal layer and the metal interconnect layer is relatively large, which leads to a high risk of interlayer cracking and affects electrical performance.
An intermediate metal layer is placed between the contact metal layer and the metal interconnect layer. The intermediate metal layer and the metal interconnect layer are made of the same metal and have a low density. As a buffer layer, it alleviates the stress concentration phenomenon at the interface caused by deformation.
It reduces the interlayer stress between the contact metal layer and the metal interconnect layer, lowers the risk of cracking between metal layers, ensures the electrical performance of the device, and eliminates the need for additional metal intercalation processes, requiring minimal equipment modifications and simplifying the manufacturing process.
Smart Images
Figure CN121925117A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology
[0002] Semiconductors such as silicon carbide (SiC) and gallium arsenide (GaAs) have superior properties in terms of electrical performance and chemical stability, and have a wide range of applications in new energy vehicles, automotive lighting, general lighting, electric vehicles, and 5G communication applications.
[0003] Currently, semiconductor devices typically use different types of metals as contact metal layers (such as Schottky contact metal layers or ohmic contact metal layers) and interconnect layers, respectively, and annealing is performed after the metal fabrication process. During this process, because the coefficients of thermal expansion of the metal in the contact metal layer and the metal in the interconnect layer differ significantly, they will exhibit large deformation differences during heating. This results in high interlayer stress between the contact metal layer and the interconnect layer, increasing the risk of interlayer cracking and compromising the electrical performance of the device. Summary of the Invention
[0004] This application provides a semiconductor device and a method for manufacturing a semiconductor device, which mainly solves the technical problem in the prior art that the large interlayer stress between the contact metal layer and the metal interconnect layer leads to a high risk of interlayer cracking.
[0005] To address the aforementioned technical problems, this application provides a semiconductor device, comprising:
[0006] Semiconductor substrate;
[0007] A contact metal layer is disposed on the semiconductor substrate, wherein the contact metal layer is a Schottky contact metal layer or an ohmic contact metal layer;
[0008] An intermediate metal layer is disposed on the side of the contact metal layer away from the semiconductor substrate;
[0009] A metal interconnect layer is disposed on the side of the intermediate metal layer away from the contact metal layer;
[0010] Wherein, the metal of the contact metal layer and the metal of the metal interconnect layer are dissimilar metals; the metal of the intermediate metal layer and the metal of the first metal layer are the same metals, and the density of the intermediate metal layer is less than that of the first metal layer, wherein the first metal layer is either the metal interconnect layer or the contact metal layer.
[0011] Optionally, the contact metal layer, the intermediate metal layer, and the metal interconnect layer are all single-element metal layers;
[0012] And / or,
[0013] The metal of the contact metal layer includes at least one of molybdenum, nickel, cobalt and titanium, and the metal of the metal interconnect layer includes at least one of aluminum, copper and tungsten.
[0014] And / or,
[0015] The contact metal layer is a molybdenum layer, and the metal interconnect layer is an aluminum layer.
[0016] Optionally, the first metal layer is the metal interconnect layer, the thickness of the contact metal layer is 20-200 nanometers, the thickness of the intermediate metal layer is 800-1200 nanometers, and the total thickness of the metal interconnect layer and the intermediate metal layer is 3800-4200 nanometers.
[0017] or,
[0018] The first metal layer is the contact metal layer, the thickness of the contact metal layer is 50-70 nanometers, the thickness of the intermediate metal layer is 30-50 nanometers, and the thickness of the metal interconnect layer is 3800-4200 nanometers.
[0019] Optionally, the thickness of the intermediate metal layer is less than the thickness of the first metal layer, and the thickness of the intermediate metal layer is 20%-30% of the total thickness of the intermediate metal layer and the first metal layer.
[0020] This application also provides a method for manufacturing a semiconductor device, including:
[0021] Provide a semiconductor substrate;
[0022] A contact metal layer, an intermediate metal layer, and a metal interconnect layer are formed on the semiconductor substrate;
[0023] The contact metal layer is disposed on the semiconductor substrate, and the contact metal layer is a Schottky contact metal layer or an ohmic contact metal layer; the intermediate metal layer is disposed on the side of the contact metal layer away from the semiconductor substrate; the metal interconnect layer is disposed on the side of the intermediate metal layer away from the contact metal layer; the metal of the contact metal layer and the metal interconnect layer are dissimilar metals, the metal of the intermediate metal layer and the metal of the first metal layer are the same metal, and the density of the intermediate metal layer is less than the density of the first metal layer, wherein the first metal layer is either the metal interconnect layer or the contact metal layer.
[0024] Optionally, both the intermediate metal layer and the first metal layer are formed by a deposition process, and the deposition rate of the intermediate metal layer is greater than that of the first metal layer.
[0025] Optionally, the step of forming a contact metal layer, an intermediate metal layer, and a metal interconnect layer on the semiconductor substrate includes:
[0026] A first metal of a first thickness is deposited on a first surface of the semiconductor substrate, and the semiconductor substrate on which the first metal is deposited is subjected to a first annealing process to form a contact metal layer.
[0027] A second metal of a second thickness is deposited at a first deposition rate on the surface of the contact metal layer away from the semiconductor substrate to form an intermediate metal layer;
[0028] A third thickness of the second metal is deposited on the surface of the intermediate metal layer away from the semiconductor substrate at a second deposition rate to form a metal interconnect layer, wherein the first deposition rate is greater than the second deposition rate;
[0029] After the step of forming the contact metal layer, the intermediate metal layer and the metal interconnect layer on the semiconductor substrate, the method further includes:
[0030] The semiconductor substrate on which the contact metal layer, the intermediate metal layer and the metal interconnect layer are formed is subjected to a second annealing process.
[0031] Optionally, the first deposition rate is 600-800 nm / min, and the second deposition rate is 100-200 nm / min;
[0032] And / or,
[0033] The annealing temperature of the first annealing treatment is 900-1100 degrees Celsius, and the annealing time of the first annealing treatment is 120-150 seconds; the annealing temperature of the second annealing treatment is 400-480 degrees Celsius, and the annealing time of the second annealing treatment is 120-150 seconds.
[0034] And / or,
[0035] The first thickness is 20-200 nanometers, the second thickness is 800-1200 nanometers, and the third thickness is 2800-3200 nanometers;
[0036] And / or,
[0037] The first metal is cobalt, and the second metal is aluminum.
[0038] Optionally, the step of forming a contact metal layer, an intermediate metal layer, and a metal interconnect layer on the semiconductor substrate includes:
[0039] A first metal of a fourth thickness is deposited on a first surface of a semiconductor substrate at a third deposition rate, and a first metal of a fifth thickness is deposited on the surface of the first metal of the fourth thickness away from the semiconductor substrate at a fourth deposition rate. The semiconductor substrate on which the first metal of the fourth thickness and the first metal of the fifth thickness are deposited is subjected to a third annealing process to form a contact metal layer and an intermediate metal layer, wherein the fourth deposition rate is greater than the third deposition rate.
[0040] A second metal of a sixth thickness is deposited on the surface of the intermediate metal layer opposite to the semiconductor substrate to form a metal interconnect layer;
[0041] After the step of forming the contact metal layer, the intermediate metal layer and the metal interconnect layer on the semiconductor substrate, the method further includes:
[0042] The semiconductor substrate on which the contact metal layer, the intermediate metal layer and the metal interconnect layer are formed is subjected to a fourth annealing process.
[0043] Optionally, the third deposition rate is 8-16 nm / min, and the fourth deposition rate is 50-70 nm / min;
[0044] And / or,
[0045] The annealing temperature of the third annealing process is 900-1100 degrees Celsius, and the annealing time of the third annealing process is 120-150 seconds; the annealing temperature of the fourth annealing process is 400-480 degrees Celsius, and the annealing time of the fourth annealing process is 120-150 seconds.
[0046] And / or,
[0047] The fourth thickness is 50-70 nanometers, the fifth thickness is 30-50 nanometers, and the sixth thickness is 3800-4200 nanometers;
[0048] And / or,
[0049] The first metal is cobalt, and the second metal is aluminum.
[0050] Unlike existing technologies, the beneficial effects of this application are that the semiconductor device provided by this application has an intermediate metal layer between the contact metal layer and the metal interconnect layer. The intermediate metal layer and the metal interconnect layer are made of the same metal, but the intermediate metal layer has a lower density than the metal interconnect layer, or the intermediate metal layer and the contact metal layer are made of the same metal, but the intermediate metal layer has a lower density than the contact metal layer. In this way, the intermediate metal layer can act as a buffer layer between the contact metal layer and the metal interconnect layer, which can alleviate the stress concentration phenomenon at the interface caused by deformation during heating, thereby reducing the interlayer stress between the contact metal layer and the metal interconnect layer, reducing the risk of cracking between metal layers, and better ensuring the electrical performance of the device. Moreover, the metal of the intermediate metal layer is the same metal as the metal interconnect layer and the contact metal layer, that is, the structure of the same metal with varying density not only has a better stress buffering effect than introducing another metal with a different coefficient of thermal expansion, but also does not require the introduction of an additional metal intercalation process, which has the advantages of minimal modification to production line equipment and simple process implementation. Attached Figure Description
[0051] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0052] Figure 1 This is a schematic diagram of the structure of one embodiment of the semiconductor device provided in this application.
[0053] Figure 2 This is a schematic diagram of another embodiment of the semiconductor device provided in this application.
[0054] Figure 3 This is a schematic flowchart of a semiconductor device manufacturing method provided in an embodiment of this application. Detailed Implementation
[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0056] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.
[0057] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.
[0058] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0059] The present application will now be described in detail with reference to the accompanying drawings and embodiments.
[0060] Please see Figures 1-3 , Figure 1 This is a schematic diagram of the structure of one embodiment of the semiconductor device provided in this application. Figure 2 This is a schematic diagram of another embodiment of the semiconductor device provided in this application. Figure 3 This is a schematic flowchart of a semiconductor device manufacturing method provided in an embodiment of this application.
[0061] like Figures 1-2 As shown, this application provides a semiconductor device.
[0062] Semiconductor substrate 1;
[0063] A contact metal layer 2 is disposed on the semiconductor substrate 1, and the contact metal layer 2 is a Schottky contact metal layer or an ohmic contact metal layer.
[0064] An intermediate metal layer 3 is disposed on the side of the contact metal layer 2 away from the semiconductor substrate 1;
[0065] Metal interconnect layer 4 is disposed on the side of the intermediate metal layer 3 away from the contact metal layer 2;
[0066] Wherein, the metal of the contact metal layer 2 and the metal of the metal interconnect layer 4 are dissimilar metals; the metal of the intermediate metal layer 3 and the metal of the first metal layer are the same metals, and the density of the intermediate metal layer 3 is less than that of the first metal layer, and the first metal layer is either the metal interconnect layer 4 or the contact metal layer 2.
[0067] In this embodiment, the semiconductor substrate 1 may include a semiconductor substrate and an epitaxial layer disposed on the semiconductor substrate. The semiconductor substrate may be, for example, a silicon carbide substrate or a silicon substrate. The epitaxial layer may also be a drift layer, and multiple spaced doped regions may be disposed within the epitaxial layer. The contact metal layer may be disposed on the surface of the epitaxial layer away from the semiconductor substrate, or it may be disposed on the surface of the semiconductor substrate away from the epitaxial layer; no limitation is made here.
[0068] The contact metal layer 2 may be disposed on the surface of the semiconductor substrate 1 and configured to form an ohmic contact or a Schottky contact with the semiconductor substrate 1. The contact metal layer 2 may be a single metal layer such as a molybdenum layer or a nickel layer, or it may be an alloy layer; this application does not limit the specific metal layer. The metal of the contact metal layer 2 may refer to the constituent metal of the contact metal layer. The metal of the contact metal layer 2 may include at least one of molybdenum, nickel, cobalt, and titanium. Using materials such as molybdenum, nickel, cobalt, or titanium to fabricate the contact metal layer makes it easier to form a Schottky contact or an ohmic contact.
[0069] The metal interconnect layer 4 can be disposed on the surface of the intermediate metal layer 3 away from the contact metal layer 2. The metal of the metal interconnect layer 4 can refer to the constituent metal of the metal interconnect layer 4, and the metal of the metal interconnect layer 4 can include at least one of aluminum, copper, and tungsten. Using materials such as aluminum, copper, or tungsten to make the metal interconnect layer can provide better electrical signal transmission performance. The metal interconnect layer 4 can be a single metal layer such as an aluminum layer or a tungsten layer, or it can be an alloy layer such as an aluminum-copper (AlCu) alloy layer or an aluminum-silicon-copper (AlSiCu) alloy layer; this application does not limit this.
[0070] The intermediate metal layer 3 is located between the contact metal layer 2 and the metal interconnect layer 4, and can be configured as a stress buffer layer between the contact metal layer 2 and the metal interconnect layer 4. The intermediate metal layer 3 can be a single metal layer such as an aluminum layer or a molybdenum layer, or an alloy layer such as an aluminum-copper alloy layer or an aluminum-silicon-copper alloy layer; this application does not limit the specific alloy layer. The metal in the intermediate metal layer 3 can refer to the constituent metals of the intermediate metal layer 3.
[0071] In this embodiment, the intermediate metal layer 3 can be made of the same metal material as one of the metal interconnect layer 4 and the contact metal layer 2, while being made of a different type of metal material as the other. That is, the intermediate metal layer 3 can be made of the same metal as the metal interconnect layer 4 but of a different type of metal as the contact metal layer 2, or the intermediate metal layer 3 can be made of the same metal as the contact metal layer 2 but of a different type of metal as the metal interconnect layer 4. In both of these cases, the density of the intermediate metal layer 3 is less than the density of the metal interconnect layer 4 and the contact metal layer 2, which are made of the same metal as the intermediate metal layer 3.
[0072] The semiconductor device provided in this application has an intermediate metal layer between the contact metal layer and the metal interconnect layer. The intermediate metal layer is made of the same metal as the metal interconnect layer but has a lower density than the metal interconnect layer, or the intermediate metal layer is made of the same metal as the contact metal layer but has a lower density than the contact metal layer. Because the interlayer particle spacing of the low-density metal layer is large and loose, the interparticle forces are small and the stress is small. Therefore, the intermediate metal layer can act as a buffer layer between the contact metal layer and the metal interconnect layer, which can alleviate the stress concentration phenomenon at the interface caused by deformation during heating, thereby reducing the interlayer stress between the contact metal layer and the metal interconnect layer, reducing the risk of cracking between metal layers, and better ensuring the electrical performance of the device. Moreover, the metal of the intermediate metal layer is the same metal as the metal interconnect layer and the contact metal layer. That is, the structure adopts the same metal with varying density. This not only has a better stress buffering effect than introducing another metal with a different coefficient of thermal expansion, but also does not require the introduction of an additional metal intercalation process. It has the advantages of minimal modification to production line equipment and simple process implementation.
[0073] Optionally, the contact metal layer 2, the intermediate metal layer 3, and the metal interconnect layer 4 are all single-element metal layers;
[0074] And / or,
[0075] The metal of the contact metal layer 2 includes at least one of molybdenum, nickel, cobalt and titanium, and the metal of the metal interconnect layer 4 includes at least one of aluminum, copper and tungsten.
[0076] And / or,
[0077] The contact metal layer 2 is a single molybdenum layer, and the metal interconnect layer 4 is a single aluminum layer.
[0078] In this embodiment, since the contact metal layer, intermediate metal layer, and interconnect layer are all elemental metal layers, the manufacturing process of each metal layer is simplified. Because the metal in the contact metal layer includes at least one of molybdenum, nickel, cobalt, and titanium, and the metal in the interconnect layer includes at least one of aluminum, copper, and tungsten, the reliable formation of ohmic contacts or Schottky bases is better ensured, as well as better electrical signal transmission. By setting the contact metal layer as an elemental molybdenum layer and the interconnect layer as an elemental aluminum layer, a better balance between process convenience, process operability, and superior electrical performance can be achieved.
[0079] Optionally, the first metal layer is the metal interconnect layer 4, the thickness of the contact metal layer 2 is 20-200 nanometers, the thickness of the intermediate metal layer 3 is 800-1200 nanometers, and the total thickness of the metal interconnect layer 4 and the intermediate metal layer 3 is 3800-4200 nanometers.
[0080] or,
[0081] The first metal layer is the contact metal layer 2, the thickness of the contact metal layer 2 is 50-70 nanometers, the thickness of the intermediate metal layer 3 is 30-50 nanometers, and the thickness of the metal interconnect layer 4 is 3800-4200 nanometers.
[0082] In this embodiment, when the first metal layer is the metal interconnect layer 4, that is, when the metal of the intermediate metal layer 3 and the metal of the metal interconnect layer 4 are the same metal, the contact metal layer 2 can be 20-200 nanometers (e.g., 20 nanometers, 50 nanometers, 80 nanometers, 100 nanometers, 120 nanometers, 150 nanometers, 180 nanometers or 200 nanometers), the thickness of the intermediate metal layer 3 can be 800-1200 nanometers (e.g., 800 nanometers, 900 nanometers, 950 nanometers, 1000 nanometers, 1050 nanometers, 1100 nanometers or 1200 nanometers), and the total thickness of the metal interconnect layer 4 and the intermediate metal layer 3 can be 3800-4200 nanometers (e.g., 3800 nanometers, 3900 nanometers, 3950 nanometers, 4000 nanometers, 4050 nanometers, 4100 nanometers or 4200 nanometers). When the first metal layer is a metal interconnect layer, by setting the thickness of each layer to the aforementioned value, it is possible to ensure that both the contact metal layer and the metal interconnect layer have excellent electrical performance, as well as that the intermediate metal layer has excellent stress buffering effect, thereby better balancing the performance of each layer.
[0083] When the first metal layer is the contact metal layer 2, that is, when the metal of the intermediate metal layer 3 is the same metal as the metal of the contact metal layer 2, the thickness of the contact metal layer 2 can be 50-70 nanometers (e.g., 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, or 70 nanometers), the thickness of the intermediate metal layer 3 can be 30-50 nanometers (e.g., 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, or 50 nanometers), and the thickness of the metal interconnect layer 4 can be 3800-4200 nanometers (e.g., 3800 nanometers, 3900 nanometers, 3950 nanometers, 4000 nanometers, 4050 nanometers, 4100 nanometers, or 4200 nanometers). When the first metal layer is the contact metal layer, by setting the thickness of each layer to the aforementioned values, it is possible to ensure that both the contact metal layer and the metal interconnect layer have excellent electrical performance, as well as that the intermediate metal layer has excellent stress buffering effect, thereby better balancing the performance of each layer.
[0084] Optionally, the thickness of the intermediate metal layer 3 is less than the thickness of the first metal layer.
[0085] Since the density of the first metal layer is higher than that of the middle metal layer, the electrical signal transmission effect of the metal layer is better than that of the middle metal layer. Therefore, by making the first metal layer thicker and the thickness of the middle metal layer thinner, it is possible to ensure the electrical signal transmission effect of the device while taking into account the stress performance of the device.
[0086] Optionally, the thickness of the intermediate metal layer 3 is 20%-30% of the total thickness of the intermediate metal layer 3 and the first metal layer.
[0087] By setting the thickness of the intermediate metal layer to 20%-30% of the total thickness of the intermediate metal layer and the first metal layer, a better balance between stress buffering effect and electrical performance effect can be achieved.
[0088] like Figure 3 As shown in the embodiments of this application, a semiconductor device manufacturing method is also provided, including:
[0089] Step 11: Provide a semiconductor substrate;
[0090] Step 12: Form a contact metal layer, an intermediate metal layer, and a metal interconnect layer on the semiconductor substrate;
[0091] The contact metal layer is disposed on the semiconductor substrate, and the contact metal layer is a Schottky contact metal layer or an ohmic contact metal layer; the intermediate metal layer is disposed on the side of the contact metal layer away from the semiconductor substrate; the metal interconnect layer is disposed on the side of the intermediate metal layer away from the contact metal layer; the metal of the contact metal layer and the metal interconnect layer are dissimilar metals, the metal of the intermediate metal layer and the metal of the first metal layer are the same metal, and the density of the intermediate metal layer is less than the density of the first metal layer, wherein the first metal layer is either the metal interconnect layer or the contact metal layer.
[0092] In this embodiment, the semiconductor substrate may include a semiconductor substrate and an epitaxial layer disposed on the semiconductor substrate. The semiconductor substrate may be, for example, a silicon carbide substrate or a silicon substrate. The epitaxial layer may also be a drift layer, and multiple spaced-apart doped regions may be disposed within the epitaxial layer. The contact metal layer may be disposed on the surface of the epitaxial layer away from the semiconductor substrate, or it may be disposed on the surface of the semiconductor substrate away from the epitaxial layer; no limitation is made here.
[0093] The contact metal layer can be disposed on the surface of a semiconductor substrate and configured to form an ohmic contact or a Schottky contact with the semiconductor substrate. The contact metal layer can be a single metal layer such as a molybdenum layer or a nickel layer, or an alloy layer; this application does not limit the specific metal used. The metal in the contact metal layer can refer to the constituent metal of the contact metal layer. The metal in the contact metal layer can include at least one of molybdenum, nickel, cobalt, and titanium. Using materials such as molybdenum, nickel, cobalt, or titanium to fabricate the contact metal layer makes it easier to form a Schottky contact or an ohmic contact. The contact metal layer can be formed by a deposition process (e.g., metal evaporation or metal sputtering) followed by an annealing process.
[0094] The metal interconnect layer can be a surface disposed on the intermediate metal layer away from the contact metal layer. The metal of the metal interconnect layer can refer to the constituent metals of the metal interconnect layer, and the metal can include at least one of aluminum, copper, and tungsten. Using materials such as aluminum, copper, or tungsten to fabricate the metal interconnect layer can provide better electrical signal transmission performance. The metal interconnect layer can be a single metal layer such as an aluminum layer or a tungsten layer, or an alloy layer such as an aluminum-copper (AlCu) alloy layer or an aluminum-silicon-copper (AlSiCu) alloy layer; this application does not limit this. The metal interconnect layer can be formed by a deposition process (such as metal evaporation or metal sputtering).
[0095] The intermediate metal layer is located between the contact metal layer and the metal interconnect layer, and can be configured as a stress buffer layer between the contact metal layer and the metal interconnect layer. The intermediate metal layer can be a single metal layer such as an aluminum layer or a molybdenum layer, or an alloy layer such as an aluminum-copper alloy layer or an aluminum-silicon-copper alloy layer; this application does not limit its application in this regard. The metal in the intermediate metal layer can refer to the constituent metal of the intermediate metal layer. The intermediate metal layer can be formed by a deposition process (such as a metal evaporation process or a metal sputtering process).
[0096] In the embodiments of this application, the intermediate metal layer may be made of the same metal material as one of the metal interconnect layer and the contact metal layer, while being made of a different type of metal material as the other. That is, the intermediate metal layer may be made of the same metal as the metal interconnect layer but a different type of metal as the contact metal layer, or the intermediate metal layer may be made of the same metal as the contact metal layer but a different type of metal as the metal interconnect layer. In both of these cases, the density of the intermediate metal layer is less than the density of the metal interconnect layer and the contact metal layer made of the same metal material as them.
[0097] The semiconductor device manufacturing method provided in this application forms an intermediate metal layer between a contact metal layer and a metal interconnect layer. The intermediate metal layer and the metal interconnect layer are made of the same metal, but the intermediate metal layer has a lower density than the metal interconnect layer, or the intermediate metal layer and the contact metal layer are made of the same metal, but the intermediate metal layer has a lower density than the contact metal layer. Because the interlayer particle spacing of the low-density metal layer is large and loose, the interparticle forces are small, and the stress is small, the intermediate metal layer can act as a buffer layer between the contact metal layer and the metal interconnect layer. This can alleviate the interface stress concentration caused by deformation during heating, thereby reducing the interlayer stress between the contact metal layer and the metal interconnect layer, reducing the risk of cracking between metal layers, and better ensuring the electrical performance of the device. Moreover, the metal of the intermediate metal layer is the same metal as the metal interconnect layer and the contact metal layer. That is, the structure of varying density of the same metal not only has a better stress buffering effect than introducing another metal with a different coefficient of thermal expansion, but also does not require the introduction of an additional metal intercalation process. It has the advantages of minimal modification to production line equipment and simple process implementation.
[0098] Optionally, both the intermediate metal layer and the first metal layer are formed by a deposition process, and the deposition rate of the intermediate metal layer is greater than that of the first metal layer.
[0099] In the embodiments of this application, the deposition process may specifically be a metal evaporation process or a metal sputtering process, etc.
[0100] By setting the deposition rate of the intermediate metal layer to be greater than that of the first metal layer, the orderly stacking of the lower-density intermediate metal layer and the higher-density first metal layer can be achieved by adjusting the deposition rate. This results in less process modification, simpler process implementation, and lower cost.
[0101] Optionally, the step of forming a contact metal layer, an intermediate metal layer, and a metal interconnect layer on the semiconductor substrate includes:
[0102] A first metal of a first thickness is deposited on a first surface of the semiconductor substrate, and the semiconductor substrate on which the first metal is deposited is subjected to a first annealing process to form the contact metal layer;
[0103] A second metal of a second thickness is deposited at a first deposition rate on the surface of the contact metal layer away from the semiconductor substrate to form an intermediate metal layer;
[0104] A third thickness of the second metal is deposited on the surface of the intermediate metal layer away from the semiconductor substrate at a second deposition rate to form a metal interconnect layer, wherein the first deposition rate is greater than the second deposition rate;
[0105] After the step of forming the contact metal layer, the intermediate metal layer and the metal interconnect layer on the semiconductor substrate, the method further includes:
[0106] The semiconductor substrate on which the contact metal layer, the intermediate metal layer and the metal interconnect layer are formed is subjected to a second annealing process.
[0107] In the embodiments of this application, the first surface of the semiconductor substrate can be the surface of the epitaxial layer away from the semiconductor substrate, or it can be the surface of the semiconductor substrate away from the epitaxial layer; the specific surface is not limited.
[0108] The first metal can be a single element such as molybdenum, nickel, cobalt, or titanium, or a metal alloy composed of at least one of molybdenum, nickel, cobalt, and titanium. The second metal can be a single element such as aluminum, copper, or tungsten, or a metal alloy composed of at least one of aluminum, copper, and tungsten.
[0109] The first thickness can be 20-200 nanometers (e.g., 20 nanometers, 50 nanometers, 80 nanometers, 100 nanometers, 120 nanometers, 150 nanometers, 180 nanometers, or 200 nanometers), the second thickness can be 800-1200 nanometers (e.g., 800 nanometers, 900 nanometers, 950 nanometers, 1000 nanometers, 1050 nanometers, 1100 nanometers, or 1200 nanometers), and the third thickness can be 2800-3200 nanometers (e.g., 3800 nanometers, 3900 nanometers, 3950 nanometers, 4000 nanometers, 4050 nanometers, 4100 nanometers, or 4200 nanometers). By setting the first thickness to 20-200 nanometers, the second thickness to 800-1200 nanometers, and the third thickness to 2800-3200 nanometers, the performance of each layer can be better balanced.
[0110] The deposition rate of the first metal of the first thickness can be 8-16 nm / min (e.g., 8 nm / min, 10 nm / min, 12 nm / min, 14 nm / min, or 16 nm / min). Depositing the first metal at a deposition rate of 8-16 nm / min yields a contact metal layer of better quality. The first deposition rate can be 600-800 nm / min (e.g., 600 nm / min, 650 nm / min, 700 nm / min, 750 nm / min, or 800 nm / min), and the second deposition rate can be 100-200 nm / min (100 nm / min, 120 nm / min, 150 nm / min, 180 nm / min, or 200 nm / min). By depositing the intermediate metal layer and the metal interconnect layer at the first and second deposition rates respectively, higher quality low-density intermediate metal layers and high-density metal interconnect layers can be obtained, thereby further improving electrical performance and reducing interlayer stress.
[0111] The first annealing treatment can be used to form ohmic contacts or Schottky contacts. The annealing temperature for the first annealing treatment can be 900–1100 degrees Celsius, and the annealing time can be 120–150 seconds. Annealing at a temperature of 900–1100 degrees Celsius for 120–150 seconds can better form ohmic contacts or Schottky bases, thereby obtaining a contact metal layer with superior performance.
[0112] The second annealing treatment can be used to relieve stress in the metal interconnect layer. The annealing temperature for the second annealing treatment can be 400–480 degrees Celsius, and the annealing time can be 120–150 seconds. Annealing at 400–480 degrees Celsius for 120–150 seconds can improve the stress relief effect of the metal interconnect layer, thereby further reducing the risk of interlayer cracking.
[0113] By first depositing a first metal and annealing it, then depositing a second metal at a high deposition rate, and then depositing the second metal at a low deposition rate, a contact metal layer composed of a first metal, an intermediate metal layer composed of a second metal, and a metal interconnect layer composed of a second metal are stacked sequentially on a semiconductor substrate. The manufacturing process is simple and requires minimal modification. Furthermore, by performing a second annealing process on the entire structure, stress relief can be further achieved in the metal interconnect layer, thereby further reducing the risk of interlayer cracking.
[0114] Furthermore, by performing a first annealing treatment after the first metal deposition to form ohmic or Schottky contacts, and then performing a second annealing treatment after the metal interconnect layer is formed to release stress, that is, by performing two annealing treatments to form ohmic / Schottky contacts and release stress respectively, it is possible to better take into account situations where there is a large difference in melting points between the first and second metals, such as when the melting point of the second metal is lower than the formation temperature of the ohmic or Schottky contacts while the melting point of the first metal is higher than the formation temperature of the ohmic or Schottky contacts, thus avoiding the risk of the second metal melting due to a single annealing treatment.
[0115] Of course, in some specific embodiments, when the melting points of the first metal and the second metal are not significantly different (for example, the first metal is molybdenum and the second metal is tungsten), an overall annealing process can be performed all at once after all metal layers have been deposited. In this case, the steps described above for forming the contact metal layer, the intermediate metal layer, and the metal interconnect layer on the semiconductor substrate can specifically include: depositing a first metal of a first thickness on the first surface of the semiconductor substrate; depositing a second metal of a second thickness on the surface of the first metal of the first thickness facing away from the semiconductor substrate at a first deposition rate; and depositing a second metal of a third thickness on the surface of the second metal of the second thickness facing away from the semiconductor substrate at a second deposition rate; and performing a fifth annealing process on the semiconductor substrate with the first metal of the first thickness, the second metal of the second thickness, and the third metal of the third thickness deposited thereon to form the contact metal layer, the intermediate metal layer, and the metal interconnect layer. The temperature of the fifth annealing process can be 900–1100 degrees Celsius, and the annealing time can be 120–150 seconds.
[0116] Optionally, the step of forming a contact metal layer, an intermediate metal layer, and a metal interconnect layer on the semiconductor substrate includes:
[0117] A first metal of a fourth thickness is deposited on a first surface of a semiconductor substrate at a third deposition rate, and a first metal of a fifth thickness is deposited on the surface of the first metal of the fourth thickness away from the semiconductor substrate at a fourth deposition rate. The semiconductor substrate on which the first metal of the fourth thickness and the first metal of the fifth thickness are deposited is subjected to a third annealing process to form the contact metal layer and the intermediate metal layer, wherein the fourth deposition rate is greater than the third deposition rate.
[0118] A second metal of a sixth thickness is deposited on the surface of the intermediate metal layer opposite to the semiconductor substrate to form a metal interconnect layer;
[0119] After the step of forming the contact metal layer, the intermediate metal layer and the metal interconnect layer on the semiconductor substrate, the method further includes:
[0120] The semiconductor substrate on which the contact metal layer, the intermediate metal layer and the metal interconnect layer are formed is subjected to a fourth annealing process.
[0121] In this embodiment, the third deposition rate can be 8-16 nm / min (e.g., 8 nm / min, 10 nm / min, 12 nm / min, 14 nm / min, or 16 nm / min), and the fourth deposition rate can be 50-70 nm / min (e.g., 50 nm / min, 55 nm / min, 60 nm / min, 65 nm / min, or 70 nm / min). After depositing the first metal at the third and fourth deposition rates respectively, annealing is performed to obtain the contact metal layer and the intermediate metal layer. This allows for the fabrication of a lower-density intermediate metal layer and a higher-density contact metal layer of superior quality, thereby further improving electrical performance and reducing interlayer stress. Furthermore, the deposition rate of the second metal with a sixth thickness can be 100-200 nm / min (100 nm / min, 120 nm / min, 150 nm / min, 180 nm / min, or 200 nm / min). Depositing the second metal at a deposition rate of 100-200 nm / min yields a metal interconnect layer of even better quality.
[0122] The fourth thickness can be 50-70 nanometers (e.g., 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, or 70 nanometers), the fifth thickness can be 30-50 nanometers (e.g., 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, or 50 nanometers), and the sixth thickness can be 3800-4200 nanometers (e.g., 3800 nanometers, 3900 nanometers, 4000 nanometers, 4100 nanometers, or 4200 nanometers). By setting the fourth thickness to 50-70 nanometers, the fifth thickness to 30-50 nanometers, and the sixth thickness to 3800-4200 nanometers, the performance of each layer can be better balanced.
[0123] The third annealing process can be used to form ohmic or Schottky contacts. The annealing temperature for the third annealing process can be 900–1100 degrees Celsius, and the annealing time can be 120–150 seconds. By annealing at 900–1100 degrees Celsius for 120–150 seconds, ohmic or Schottky contacts can be formed more effectively, resulting in a contact metal layer with superior performance.
[0124] The fourth annealing process can be used to relieve stress in the metal interconnect layer. The annealing temperature for the fourth annealing process can be 400–480 degrees Celsius, and the annealing time can be 120–150 seconds. By annealing at 400–480 degrees Celsius for 120–150 seconds, the stress relief effect of the metal interconnect layer can be improved, thereby further reducing the risk of interlayer cracking.
[0125] By employing a low deposition rate for the first metal, followed by a high deposition rate, and then annealing, and finally depositing the second metal, a contact metal layer, an intermediate metal layer, and a metal interconnect layer composed of the first metal are sequentially stacked on a semiconductor substrate. This process is simple and requires minimal modification. Furthermore, the final second annealing process further relieves stress in the metal interconnect layer, thereby reducing the risk of interlayer cracking. Moreover, by performing a first annealing process after two depositions of the first metal to form ohmic or Schottky contacts, and then performing a second annealing process after the formation of the metal interconnect layer to release stress, the two annealing processes respectively form ohmic / Schottky contacts and release stress. This effectively addresses situations where there is a significant difference in melting points between the first and second metals, such as when the melting point of the second metal is lower than the formation temperature of the ohmic / Schottky contact while the melting point of the first metal is higher, avoiding the risk of the second metal melting due to a single annealing process.
[0126] Of course, in some specific embodiments, when the melting points of the first metal and the second metal are not significantly different (for example, the first metal is molybdenum and the second metal is tungsten), an overall annealing process can be performed all at once after all metal layers have been deposited. In this case, the steps of forming the contact metal layer, the intermediate metal layer, and the metal interconnect layer on the semiconductor substrate described above may specifically include: depositing a first metal of a fourth thickness on the first surface of the semiconductor substrate at a third deposition rate, depositing a first metal of a fifth thickness on the surface of the fourth thickness of the first metal opposite to the semiconductor substrate at a fourth deposition rate, and depositing a second metal of a sixth thickness on the surface of the fifth thickness of the first metal opposite to the semiconductor substrate, and performing a sixth annealing process on the semiconductor substrate on which the fourth thickness of the first metal, the fifth thickness of the first metal, and the sixth thickness of the second metal have been deposited to form the contact metal layer, the intermediate metal layer, and the metal interconnect layer.
[0127] Optionally, the first metal is cobalt and the second metal is aluminum.
[0128] In this embodiment, by setting the first metal as cobalt and the second metal as aluminum, a metal stack structure can be obtained in which the contact layer is a cobalt layer, the metal interconnect layer is an aluminum layer, and the intermediate metal layer is a cobalt layer or an aluminum layer. Cobalt is more likely to form ohmic contacts or Schottky contacts, while aluminum has better electrical properties, thus better balancing process convenience, process operability, and electrical performance advantages.
[0129] For ease of understanding, the semiconductor device manufacturing method in the embodiments of this application will be illustrated below using a silicon carbide substrate as the semiconductor substrate, molybdenum (Mo) as the first metal, and aluminum (Al) as the second metal.
[0130] Example 1
[0131] A method for manufacturing a semiconductor device specifically includes the following steps:
[0132] Step 21: Provide a silicon carbide substrate.
[0133] Step 22: Deposit a 100 nm Mo metal element layer on a silicon carbide substrate using a metal sputtering process at a deposition rate of 12 nm per minute. Then, perform high-temperature annealing at a temperature of 900–1100 degrees Celsius for 120–150 seconds to form a contact metal layer.
[0134] Step 23: On the surface of the above-mentioned Mo metal elemental layer, a layer of Al metal elemental layer with a thickness of 1000 nanometers is deposited using a metal sputtering process at a deposition rate of 600-800 nanometers per minute to form an intermediate metal layer (in this step, a high deposition rate is used for metal Al deposition to obtain a low-density metal Al stress buffer layer).
[0135] Step 24: After completing Step 23 above, continue with the metal sputtering process to deposit a 3000 nm thick Al metal layer on the Al metal layer formed in Step 2, at a deposition rate of 100 nm per minute, to form a metal interconnect layer. (A low deposition rate is used in this step to deposit the Al metal to obtain a high-density Al metal interconnect layer, thereby ensuring the electrical signal transmission effect of the Al metal layer.)
[0136] Step 25: The overall structure after Al metal deposition is annealed again at a temperature of 400-480 degrees Celsius for 120-150 seconds.
[0137] The semiconductor device manufacturing method in this example achieves ordered, layered deposition of Al metal layers with varying densities by adjusting the Al metal layer deposition process during the Mo / Al metal stacking process. A homogeneous, low-density (low-stress) Al film acts as a stress buffer layer to mitigate metal layer cracking caused by stress mismatch during high-temperature annealing of the Mo / Al metal stack. Specifically, in the Al layer deposition in contact with Mo, a high deposition rate is used to obtain a low-density (low-stress) Al film. This low-density aluminum layer helps alleviate stress concentration caused by deformation at its contact with Mo during high-temperature processing. Subsequently, a low deposition rate is used to obtain a high-density Al layer to ensure the effective transmission of electrical signals within the metal interconnects.
[0138] The semiconductor device manufacturing method in this example can improve the stress and density parameters of the Al metal layer by simply adjusting the process parameters (such as deposition rate), thereby achieving orderly stacking of the metal layers and improving the interface stress between Mo and Al. Moreover, this technology does not require the introduction of other additional metal intercalation processes, and has the advantages of minimal changes to production line equipment and simple process implementation.
[0139] Example 2
[0140] A method for manufacturing a semiconductor device specifically includes the following steps:
[0141] Step 31: Provide a silicon carbide substrate.
[0142] Step 32: Deposit a 60 nm Mo metal elemental layer on a silicon carbide substrate using a metal sputtering process at a low deposition rate of 12 nm per minute; then continue to deposit a 40 nm Mo metal elemental layer using a metal sputtering process at a high deposition rate of 60 nm per minute; after the above two Mo layers are deposited, perform high-temperature annealing treatment to form a contact metal layer and an intermediate metal layer.
[0143] Step 33: On the surface of the 40 nm Mo metal elemental layer (i.e., the intermediate metal layer), deposit an Al metal elemental layer with a thickness of 4000 nm at a deposition rate of 100 nm per minute to form a metal interconnect layer.
[0144] Step 34: The overall structure after Al metal deposition is annealed again at a temperature of 400-480 degrees Celsius for 120-150 seconds.
[0145] The semiconductor device manufacturing method in this example achieves ordered, layered deposition of Mo metal layers with different densities by adjusting the Mo metal layer deposition process during the Mo / Al metal stacking process. A homogeneous, low-density Mo film acts as a stress buffer layer to mitigate metal layer cracking caused by stress mismatch during high-temperature annealing of the Mo / Al metal stack. Specifically, in the Mo layer deposition in contact with the silicon carbide substrate, a low deposition rate is used to obtain a high-density Mo layer to ensure effective electrical signal transmission as a contact metal layer. Subsequently, a high deposition rate is used to obtain a low-density Mo layer. This low-density Mo layer helps alleviate stress concentration caused by deformation at its contact with the Al layer (which serves as a metal interconnect layer) during high-temperature processing, reducing interlayer stress.
[0146] The semiconductor device manufacturing method in this example can improve the stress and density parameters of the Mo metal layer by simply adjusting the process parameters (such as deposition rate), thereby achieving orderly stacking of the metal layers and improving the interface stress between Mo and Al. Moreover, this technology does not require the introduction of other additional metal intercalation processes, and has the advantages of minimal changes to production line equipment and simple process implementation.
[0147] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalent elements of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0148] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A semiconductor device, characterized in that, include: Semiconductor substrate; A contact metal layer is disposed on the semiconductor substrate, wherein the contact metal layer is a Schottky contact metal layer or an ohmic contact metal layer; An intermediate metal layer is disposed on the side of the contact metal layer away from the semiconductor substrate; A metal interconnect layer is disposed on the side of the intermediate metal layer away from the contact metal layer; Wherein, the metal of the contact metal layer and the metal of the metal interconnect layer are dissimilar metals; the metal of the intermediate metal layer and the metal of the first metal layer are the same metals, and the density of the intermediate metal layer is less than that of the first metal layer, wherein the first metal layer is either the metal interconnect layer or the contact metal layer.
2. The semiconductor device according to claim 1, characterized in that, The contact metal layer, the intermediate metal layer and the metal interconnect layer are all single-element metal layers; And / or, The metal of the contact metal layer includes at least one of molybdenum, nickel, cobalt and titanium, and the metal of the metal interconnect layer includes at least one of aluminum, copper and tungsten. And / or, The contact metal layer is a molybdenum layer, and the metal interconnect layer is an aluminum layer.
3. The semiconductor device according to claim 1, characterized in that, The first metal layer is the metal interconnect layer, the thickness of the contact metal layer is 20-200 nanometers, the thickness of the intermediate metal layer is 800-1200 nanometers, and the total thickness of the metal interconnect layer and the intermediate metal layer is 3800-4200 nanometers. or, The first metal layer is the contact metal layer, the thickness of the contact metal layer is 50-70 nanometers, the thickness of the intermediate metal layer is 30-50 nanometers, and the thickness of the metal interconnect layer is 3800-4200 nanometers.
4. The semiconductor device according to any one of claims 1-3, characterized in that, The thickness of the intermediate metal layer is less than the thickness of the first metal layer, and the thickness of the intermediate metal layer is 20%-30% of the total thickness of the intermediate metal layer and the first metal layer.
5. A method for manufacturing a semiconductor device, characterized in that, include: Provide a semiconductor substrate; A contact metal layer, an intermediate metal layer, and a metal interconnect layer are formed on the semiconductor substrate; The contact metal layer is disposed on the semiconductor substrate, and the contact metal layer is a Schottky contact metal layer or an ohmic contact metal layer; the intermediate metal layer is disposed on the side of the contact metal layer away from the semiconductor substrate; the metal interconnect layer is disposed on the side of the intermediate metal layer away from the contact metal layer; the metal of the contact metal layer and the metal interconnect layer are dissimilar metals, the metal of the intermediate metal layer and the metal of the first metal layer are the same metal, and the density of the intermediate metal layer is less than the density of the first metal layer, wherein the first metal layer is either the metal interconnect layer or the contact metal layer.
6. The semiconductor device manufacturing method according to claim 5, characterized in that, Both the intermediate metal layer and the first metal layer are formed by a deposition process, and the deposition rate of the intermediate metal layer is greater than that of the first metal layer.
7. The semiconductor device manufacturing method according to claim 6, characterized in that, The step of forming a contact metal layer, an intermediate metal layer, and a metal interconnect layer on the semiconductor substrate includes: A first metal of a first thickness is deposited on a first surface of the semiconductor substrate, and the semiconductor substrate on which the first metal is deposited is subjected to a first annealing process to form a contact metal layer. A second metal of a second thickness is deposited at a first deposition rate on the surface of the contact metal layer away from the semiconductor substrate to form an intermediate metal layer; A third thickness of the second metal is deposited on the surface of the intermediate metal layer away from the semiconductor substrate at a second deposition rate to form a metal interconnect layer, wherein the first deposition rate is greater than the second deposition rate; After the step of forming the contact metal layer, the intermediate metal layer and the metal interconnect layer on the semiconductor substrate, the method further includes: The semiconductor substrate on which the contact metal layer, the intermediate metal layer and the metal interconnect layer are formed is subjected to a second annealing process.
8. The semiconductor device manufacturing method according to claim 6, characterized in that, The first deposition rate is 600-800 nm / min, and the second deposition rate is 100-200 nm / min; And / or, The annealing temperature of the first annealing treatment is 900-1100 degrees Celsius, and the annealing time of the first annealing treatment is 120-150 seconds; the annealing temperature of the second annealing treatment is 400-480 degrees Celsius, and the annealing time of the second annealing treatment is 120-150 seconds. And / or, The first thickness is 20-200 nanometers, the second thickness is 800-1200 nanometers, and the third thickness is 2800-3200 nanometers; And / or, The first metal is cobalt, and the second metal is aluminum.
9. The semiconductor device manufacturing method according to claim 6, characterized in that, The step of forming a contact metal layer, an intermediate metal layer, and a metal interconnect layer on the semiconductor substrate includes: A first metal of a fourth thickness is deposited on a first surface of a semiconductor substrate at a third deposition rate, and a first metal of a fifth thickness is deposited on the surface of the first metal of the fourth thickness away from the semiconductor substrate at a fourth deposition rate. The semiconductor substrate on which the first metal of the fourth thickness and the first metal of the fifth thickness are deposited is subjected to a third annealing process to form a contact metal layer and an intermediate metal layer, wherein the fourth deposition rate is greater than the third deposition rate. A second metal of a sixth thickness is deposited on the surface of the intermediate metal layer opposite to the semiconductor substrate to form a metal interconnect layer; After the step of forming the contact metal layer, the intermediate metal layer and the metal interconnect layer on the semiconductor substrate, the method further includes: The semiconductor substrate on which the contact metal layer, the intermediate metal layer and the metal interconnect layer are formed is subjected to a fourth annealing process.
10. The semiconductor device manufacturing method according to claim 9, characterized in that, The third deposition rate is 8-16 nm / min, and the fourth deposition rate is 50-70 nm / min; And / or, The annealing temperature of the third annealing process is 900-1100 degrees Celsius, and the annealing time of the third annealing process is 120-150 seconds; the annealing temperature of the fourth annealing process is 400-480 degrees Celsius, and the annealing time of the fourth annealing process is 120-150 seconds. And / or, The fourth thickness is 50-70 nanometers, the fifth thickness is 30-50 nanometers, and the sixth thickness is 3800-4200 nanometers; And / or, The first metal is cobalt, and the second metal is aluminum.