Chip, chip preparation method and chip packaging structure

Abstract

The embodiment of the invention provides a chip, a chip preparation method and a chip packaging structure, and the chip preparation method comprises the steps: providing a chip body, and forming a groove in the central region of the back surface of the chip body; depositing and forming a barrier layer on the bottom wall of the groove; forming a plurality of carbon nanotube sites distributed at intervals on the barrier layer; vertically growing compact and uniform carbon nanotubes on the carbon nanotube sites; and filling nano-silver colloid in the groove, and carrying out stepped curing on the nano-silver colloid to form a nano-silver colloid filling body wrapping the carbon nanotubes. The carbon nanotubes and the high-thermal-conductivity nano-silver colloid are integrated in the grooves, so that the thermal conductivity (exceeding a pure silicon wafer) of the groove area is remarkably improved, rapid heat dissipation is realized, and thermal stress is reduced; the nano-silver colloid filled in the groove constructs an effective thermal stress buffer area, the non-uniform thermal stress of the center of the chip is reduced, the reliability of a thermal interface material in temperature circulation of large-size heterogeneous chip packaging is remarkably improved, and therefore the overall reliability of packaging is greatly improved.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a chip, its fabrication method, and its packaging structure. Background Technology

[0002] FCBGA (Flip Chip Ball Grid Array) is a high-performance, high-density, and high-reliability semiconductor packaging technology. With its excellent electrical performance, heat dissipation capabilities, and high I / O density, it has become the preferred solution for high-end chip packaging and is widely used in fields with stringent requirements for performance, power consumption, and size. Its main applications include high-performance computing, networking and communications, data centers, automotive electronics, and consumer electronics.

[0003] The core structure of the FCBGA package consists of: a chip, a silicon-based semiconductor containing the core circuit functional areas; a substrate, a multilayer organic material substrate that enables high-density wiring and connects the chip to the motherboard; solder balls, made of tin-silver-copper alloy, serving as electrical and mechanical connection points between the package and the PCB motherboard; and a heat sink, typically made of copper or nickel-plated copper, whose key function is to enhance heat dissipation efficiency and protect the chip.

[0004] Due to chip design considerations, the asymmetrical distribution of chips on the substrate can lead to uneven stress and long heat dissipation paths at the chip center. Consequently, in temperature cycling (TC) reliability tests, the thermal interface materials (such as indium wafers) at the chip center are significantly affected by the chip's thermal stress, resulting in significant degradation of the thermal interface materials after temperature cycling. The specific challenges and reasons are as follows: Structural factors: Due to the asymmetric structure of the chip on the substrate, its mass distribution and thermal expansion characteristics differ in different directions, and the heat dissipation path at the center of the chip is long, which easily leads to the formation of a thermal center.

[0005] Problem Description: In FCBGA packaging, temperature cycling reliability testing is a crucial part of verifying product quality. The heatsink and chip are connected via a thermal interface material. An asymmetrical structure and thermal center can lead to uneven thermal stress distribution at the chip center during temperature cycling, resulting in severe degradation of the thermal interface material at its center, which is reflected in the thermal interface material coverage.

[0006] To address the aforementioned issues, it is necessary to propose a reasonably designed chip that effectively solves these problems, along with its chip fabrication method and chip packaging structure. Summary of the Invention

[0007] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a chip, a chip fabrication method thereon, and a chip packaging structure.

[0008] This disclosure provides a chip fabrication method, the method comprising: Provide a chip body, and form a trench in the central area on the back of the chip body; A barrier layer is deposited on the bottom wall of the trench to form a barrier layer; Multiple carbon nanotube sites are formed at intervals on the barrier layer; Dense and uniform carbon nanotubes are vertically grown at the carbon nanotube sites. The groove is filled with silver nanoparticles, and the silver nanoparticles are cured in a stepwise manner to form a silver nanoparticle filler that encapsulates the carbon nanotubes.

[0009] Optionally, vertically growing dense and uniform carbon nanotubes at the carbon nanotube sites includes: Plasma-enhanced chemical vapor deposition was employed, with carbon source gas introduced while maintaining stable H2 flow rate and temperature. A negative bias voltage is applied and the growth time is controlled to vertically grow dense and uniform carbon nanotubes at the carbon nanotube sites.

[0010] Optionally, the carbon source gas is C2H2, the flow rate of C2H2 is in the range of 10 sccm to 30 sccm, and the flow rate ratio of H2 to C2H2 is in the range of (8~10):1; The vertically grown carbon nanotubes have a height range of 100 μm to 200 μm.

[0011] Optionally, a trench is formed in the central region on the back side of the chip body, including: Plasma etching is performed in the central region on the back of the chip to form the trench with a width ranging from 100 μm to 200 μm, wherein the depth of the trench is less than the maximum thinning thickness of the chip. The organic matter in the trench is removed by plasma cleaning.

[0012] Optionally, a plurality of carbon nanotube sites are formed at intervals on the barrier layer, including: A plurality of uniform and dense Fe nanoparticles are formed on the barrier layer by electrochemical deposition, wherein the size of the Fe nanoparticles ranges from 5 nm to 10 nm.

[0013] Optionally, the trench is filled with nano-silver paste, comprising: The nano-silver paste was diluted with a low-boiling-point solvent to a viscosity range of 100 cP to 500 cP. The diluted nano-silver paste is filled into the groove and soaked for 5 to 10 minutes to allow the voids in the groove to drain naturally, so that the entire groove is completely filled.

[0014] Optionally, the nano-silver paste is cured in a stepwise manner, including: The solvent is slowly evaporated within a temperature range of 80℃ to 100℃. Prepolymerization is carried out within a temperature range of 120℃ to 150℃; The silver particles are sintered and solidified within a temperature range of 200℃ to 250℃.

[0015] Optionally, a barrier layer is deposited on the bottom wall of the trench, comprising: An Al2O3 barrier layer with a thickness of 10 nm to 20 nm was prepared on the bottom wall of the trench using an atomic deposition process.

[0016] Another aspect of this disclosure provides a chip fabricated using the chip fabrication method described above; the chip includes a chip, a barrier layer, a silver nanoparticle filler, and a plurality of carbon nanotubes. The back of the chip has grooves. The barrier layer is disposed on the bottom wall of the trench; Multiple carbon nanotubes are vertically spaced apart in the barrier layer; The nano-silver paste filler is filled in the trench.

[0017] Another aspect of this disclosure provides a chip packaging structure, including: substrate; A chip is flip-chip disposed on the substrate, wherein the chip is symmetrically disposed on the substrate, or the chip is asymmetrically disposed on the substrate; A thermal interface material layer is disposed on the back side of the chip; A heat dissipation cover is disposed on the thermal interface material layer, and the edge region of the heat dissipation cover is fixed to the substrate; wherein, The chip used is the one described above.

[0018] The chip, its fabrication method, and its packaging structure disclosed herein are described. The chip fabrication method integrates vertically grown carbon nanotubes and highly thermally conductive silver nanoparticles within trenches, significantly improving the thermal conductivity of the trench region (surpassing that of pure silicon wafers), enabling rapid heat dissipation and reducing thermal stress. Simultaneously, the silver nanoparticles filling the trenches construct an effective thermal stress buffer zone, reducing uneven thermal stress at the chip center and significantly improving the reliability of the thermal interface material during temperature cycling in large-size heterogeneous chip packaging. Furthermore, when the chip fabricated using this method is used in an asymmetric packaging structure, it effectively alleviates the problem of uneven thermal stress distribution during thermal cycling. This significantly reduces the performance degradation of the thermal interface material connected to the chip center due to uneven thermal stress, thereby greatly improving the overall reliability of the packaging. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of an asymmetric packaging structure in the prior art; Figure 2 This is a schematic flowchart of a chip fabrication method according to one embodiment of the present disclosure; Figures 3 to 6 This is a schematic diagram of a chip fabrication method according to another embodiment of this disclosure; Figure 7 This is a schematic diagram of a chip packaging structure according to another embodiment of the present disclosure. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0021] Figure 1 This is a common asymmetric packaging structure in existing technologies. The black dashed line represents the centerline of substrate 1, and the red dashed line represents the stress distribution curve at the center of chip 2. In asymmetric packaging structures, due to the asymmetric structure of chip 2 on substrate 1, its mass distribution and thermal expansion characteristics differ in different directions, and the heat dissipation path at the chip center is long, easily forming a hot spot. The asymmetric structure and hot spot lead to uneven thermal stress at the center of chip 2 under temperature cycling, resulting in the uneven stress distribution curve shown in the figure. Due to the uneven thermal stress at the center of chip 2, the thermal interface material degrades severely at the center, thereby reducing the thermal interface material coverage and consequently reducing the reliability of the asymmetric packaging structure.

[0022] In response to the above issues, such as Figure 2 As shown, this embodiment of the present disclosure provides a chip fabrication method S100, which specifically includes: S110 provides a chip and forms a trench in the central region on the back of the chip body.

[0023] Specifically, such as Figure 3 As shown, a chip body 110 is provided. Plasma etching is performed on the central region of the back side of the chip body to form trenches 120 with a width ranging from 100 μm to 200 μm, wherein the depth of the trenches 120 is less than the maximum thinning thickness of the chip body 110. Subsequently, plasma cleaning is used to remove organic matter from the trenches 120. The parameters for plasma etching are: O2 / Ar (4:1); 300W; 5 min.

[0024] S120, A barrier layer is deposited on the bottom wall of the trench to form a barrier layer.

[0025] like Figure 4 As shown, a barrier layer 130 is deposited on the bottom wall of the trench 120. Specifically, in this embodiment, an Al2O3 barrier layer with a thickness of 10 nm to 20 nm is prepared on the bottom wall of the trench 120 using an atomic deposition process.

[0026] In this embodiment, by forming a barrier layer on the bottom wall of the trench, the diffusion of subsequently formed carbon nanotube sites into the silicon chip can be prevented.

[0027] S130, Multiple carbon nanotube sites are formed at intervals on the barrier layer.

[0028] Specifically, a plurality of uniform and dense Fe nanoparticles are formed on the barrier layer 130 by electrochemical deposition, wherein the size of the Fe nanoparticles ranges from 5 nm to 10 nm. These Fe nanoparticles serve as the sites for the subsequent vertical growth of carbon nanotubes.

[0029] More specifically, in this embodiment, a dense and uniform carbon nanotube site is deposited at the barrier layer 130 using a chronoamperometry method (electrochemical deposition). A negative potential (reduction potential) of -1.0 V to -1.2 V (vs. Ag / AgCl) is applied to the working electrode, and the deposition time is 30 s to 60 s, thereby forming a uniform and dense layer of metallic Fe nanoparticles.

[0030] It should be noted that there are no specific restrictions on the distribution of multiple carbon nanotube sites. They can be distributed at equal intervals or at non-equal intervals. The distance between adjacent carbon nanotube sites can be set according to actual needs.

[0031] S140. Dense and uniform carbon nanotubes are vertically grown at the carbon nanotube sites.

[0032] like Figure 5 As shown, dense and uniform carbon nanotubes 140 are vertically grown at carbon nanotube sites.

[0033] The process of forming carbon nanotubes 140 can be described as follows: Plasma-enhanced chemical vapor deposition was employed, with carbon source gas introduced while maintaining stable H2 flow rate and temperature; a negative bias voltage was applied and the growth time was controlled to vertically grow dense and uniform carbon nanotubes 140 at the carbon nanotube sites.

[0034] Specifically, in this embodiment, the carbon source gas can be C2H2, the flow rate of C2H2 is in the range of 10 sccm ~ 30 sccm, the flow rate ratio of H2 to C2H2 is in the range of (8~10):1, and the height of the vertically grown carbon nanotubes is in the range of 100 μm ~ 200 μm.

[0035] Preferably, by controlling the flow ratio of H2 to C2H2 at 10:1, applying a certain negative bias voltage (-300 V) to the sample stage, and controlling the growth time at 5 min to 20 min, dense and uniform carbon nanotubes 140 with a diameter of 100 μm to 200 μm can be vertically grown on the carbon nanotube sites.

[0036] S150. Fill the trench with nano-silver paste and cure the nano-silver paste in a stepwise manner.

[0037] like Figure 6 As shown, the groove 120 is filled with nano-silver paste, and the nano-silver paste is cured in a stepwise manner to form a nano-silver paste filler 150 that encapsulates carbon nanotubes 140.

[0038] The specific process of filling the trench 120 with nano-silver paste can be as follows: First, the nano-silver paste is diluted with a low-boiling-point solvent (such as ethylene glycol ether) to a viscosity range of 100 cP to 500 cP. This dilution before curing increases the fluidity of the nano-silver paste, making it easier to fill the gaps between the dense carbon nanotubes 140.

[0039] Next, the diluted nano-silver paste is filled into the groove 120 and soaked for 5 to 10 minutes to allow the voids in the groove 120 to be naturally drained, so that the entire groove 120 is completely filled.

[0040] The specific process of step-by-step curing of nano-silver paste may include: Low-temperature solvent evaporation: The solvent is slowly evaporated within a temperature range of 80℃ to 100℃.

[0041] Medium-temperature prepolymerization: Prepolymerization is carried out in a temperature range of 120℃~150℃ to promote the expulsion of bubbles.

[0042] High-temperature sintering: Silver particles are sintered and solidified within a temperature range of 200℃~250℃.

[0043] The nano-silver paste filled in the trench 120 is cured by a step-by-step curing process to obtain the nano-silver paste filler 150, thereby obtaining... Figure 6 The chip 100 shown.

[0044] In this embodiment, by performing stepwise curing on the nano-silver paste filled in the trench, a dense, highly thermally conductive and firmly bonded nano-silver paste filler can be formed.

[0045] The chip fabrication method of this disclosure significantly improves the thermal conductivity of the trench region (surpassing that of pure silicon wafers) by integrating vertically grown carbon nanotubes and highly thermally conductive silver nanoparticles within the trench, achieving rapid heat dissipation and reducing thermal stress. Simultaneously, the silver nanoparticles filling the trenches construct an effective thermal stress buffer region, reducing uneven thermal stress at the chip center and significantly improving the reliability of the thermal interface material during temperature cycling in large-size heterogeneous chip packaging. When the chip fabricated using this method is used in an asymmetric packaging structure, it effectively alleviates the problem of uneven thermal stress distribution during thermal cycling. This significantly reduces the performance degradation of the thermal interface material connected to the chip center due to uneven thermal stress, thereby greatly improving the overall reliability of the packaging. Of course, applying the chip to a symmetric packaging structure can also effectively alleviate the problem of uneven thermal stress distribution during thermal cycling.

[0046] like Figure 6 As shown, another aspect of this disclosure provides a chip 100, which adopts the chip fabrication method S100 described above. The specific steps of the chip fabrication method S100 have been described in detail above and will not be repeated here.

[0047] like Figure 6 As shown, the chip 100 includes a chip body 110, a barrier layer 130, multiple carbon nanotubes 140, and a nano-silver paste filler 150.

[0048] A trench 120 is provided on the back side of the chip body 110; wherein the width of the trench 120 is in the range of 100 μm to 200 μm, and the depth of the trench 120 is less than the maximum thinning thickness of the chip body 110.

[0049] A barrier layer 130 is disposed on the bottom wall of the trench 120 to prevent carbon nanotubes 140 from diffusing into the silicon chip. In this embodiment, the barrier layer 130 can be an Al2O3 barrier layer with a thickness of 10 nm to 20 nm.

[0050] Multiple carbon nanotubes 140 are vertically spaced on the barrier layer 130; wherein, the height of the carbon nanotubes 140 ranges from 100 μm to 200 μm. The distribution characteristics of the multiple carbon nanotubes 140 and the distance between two adjacent carbon nanotubes 140 can be selected according to actual needs, and this embodiment does not make specific limitations.

[0051] The nano-silver paste filler 150 fills the groove 120 and encapsulates multiple carbon nanotubes 140.

[0052] The chip of this embodiment is fabricated using the chip fabrication method described in the entire text. This chip can accelerate heat dissipation, reduce thermal stress, provide a stress buffer layer, reduce uneven thermal stress at the center of the chip, and significantly improve the reliability of the thermal interface material during temperature cycling of large-size heterogeneous chip packaging.

[0053] like Figure 7 As shown, another aspect of this disclosure provides a chip packaging structure 200, including: a substrate 210, a chip 100, a thermal interface material layer 220, and a heat sink 230. The chip 100 is the chip 100 described throughout this document; its specific structural features have been described in detail above and will not be repeated here.

[0054] Chip 100 is flip-chip disposed on substrate 210, wherein chip 100 is symmetrically disposed on substrate 210 or asymmetrically disposed on substrate 210. That is to say, the chip packaging structure can be a symmetrical packaging structure or an asymmetrical packaging structure.

[0055] A thermal interface material layer 220 is disposed on the back side of the chip 100. The thermal interface material layer 220 can be made of indium foil or the like, and can be selected according to actual needs.

[0056] The heat dissipation cover 230 is disposed on the thermal interface material layer 220, and the edge area of ​​the heat dissipation cover 230 is fixed to the substrate 210.

[0057] like Figure 7 As shown, in this embodiment, the chip packaging structure 200 is an asymmetric packaging structure as an example for explanation. The black dashed line in the figure represents the center line of the substrate 210, and the red dashed line represents the stress distribution curve at the center of the chip 100. In this embodiment, the back of the chip is provided with trenches, and carbon nanotubes and highly thermally conductive silver nanoparticles are disposed within the trenches, significantly improving the thermal conductivity of the trench region (surpassing that of pure silicon wafers), achieving rapid heat dissipation, reducing thermal stress, and thus... Figure 7 The asymmetric package shown generates uniform stress at the chip center, which significantly reduces the performance degradation of the thermal interface material layer connected to the chip center due to uneven thermal stress, thereby greatly improving the overall reliability of the package.

[0058] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.

Claims

1. A chip fabrication method, characterized in that, The method includes: Provide a chip body, and form a trench in the central area on the back of the chip body; A barrier layer is deposited on the bottom wall of the trench to form a barrier layer; Multiple carbon nanotube sites are formed at intervals on the barrier layer; Dense and uniform carbon nanotubes are vertically grown at the carbon nanotube sites. The groove is filled with silver nanoparticles, and the silver nanoparticles are cured in a stepwise manner to form a silver nanoparticle filler that encapsulates the carbon nanotubes.

2. The chip fabrication method according to claim 1, characterized in that, The process of vertically growing dense and uniform carbon nanotubes at the carbon nanotube sites includes: Plasma-enhanced chemical vapor deposition was employed, with carbon source gas introduced while maintaining stable H2 flow rate and temperature. A negative bias voltage is applied and the growth time is controlled to vertically grow dense and uniform carbon nanotubes at the carbon nanotube sites.

3. The chip fabrication method according to claim 2, characterized in that, The carbon source gas is C2H2, the flow rate of C2H2 is in the range of 10 sccm ~ 30 sccm, and the flow rate ratio of H2 to C2H2 is in the range of (8~10):1; The vertically grown carbon nanotubes have a height range of 100 μm to 200 μm.

4. The chip fabrication method according to any one of claims 1 to 3, characterized in that, A trench is formed in the central region on the back of the chip body, including: Plasma etching is performed on the central region of the back side of the chip body to form the trench with a width ranging from 100 μm to 200 μm, wherein the depth of the trench is less than the maximum thinning thickness of the chip body. The organic matter in the trench is removed by plasma cleaning.

5. The chip fabrication method according to any one of claims 1 to 3, characterized in that, Multiple carbon nanotube sites are formed at intervals on the barrier layer, including: A plurality of uniform and dense Fe nanoparticles are formed on the barrier layer by electrochemical deposition, wherein the size of the Fe nanoparticles ranges from 5 nm to 10 nm.

6. The chip fabrication method according to any one of claims 1 to 3, characterized in that, The trench is filled with nano-silver paste, comprising: The nano-silver paste was diluted with a low-boiling-point solvent to a viscosity range of 100 cP to 500 cP. The diluted nano-silver paste is filled into the groove and soaked for 5 to 10 minutes to allow the voids in the groove to drain naturally, so that the entire groove is completely filled.

7. The chip fabrication method according to any one of claims 1 to 3, characterized in that, The nano-silver paste is cured in a stepwise manner, including: The solvent is slowly evaporated within a temperature range of 80℃ to 100℃. Prepolymerization is carried out within a temperature range of 120℃ to 150℃; The silver particles are sintered and solidified within a temperature range of 200℃ to 250℃.

8. The chip fabrication method according to any one of claims 1 to 3, characterized in that, A barrier layer is deposited on the bottom wall of the trench to form a barrier layer, comprising: An Al2O3 barrier layer with a thickness of 10 nm to 20 nm was prepared on the bottom wall of the trench using an atomic deposition process.

9. A chip, characterized in that, The chip fabrication method according to any one of claims 1 to 8 is adopted; the chip includes a chip body, a barrier layer, a silver nanoparticle filler, and a plurality of carbon nanotubes; The back of the chip body is provided with grooves; The barrier layer is disposed on the bottom wall of the trench; Multiple carbon nanotubes are vertically spaced apart in the barrier layer; The nano-silver paste filler is filled in the trench.

10. A chip packaging structure, characterized in that, include: substrate; A chip is flip-chip disposed on the substrate, wherein the chip is symmetrically disposed on the substrate, or the chip is asymmetrically disposed on the substrate; A thermal interface material layer is disposed on the back side of the chip; A heat dissipation cover is disposed on the thermal interface material layer, and the edge region of the heat dissipation cover is fixed to the substrate; wherein, The chip used is the chip described in claim 9.

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