Power semiconductor device and metal pad modifying and lifting method thereof
By forming a three-dimensional array of metal bumps on the surface of the metal pads of power semiconductor devices, the problem of insufficient power cycling and thermal cycling capabilities caused by small pad area is solved, and high-reliability and low-cost power device manufacturing is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIAXING SIDA MICROELECTRONICS CO LTD
- Filing Date
- 2025-12-05
- Publication Date
- 2026-04-24
AI Technical Summary
The small pad area of existing power devices results in insufficient power cycling and thermal cycling capabilities, which cannot meet the application requirements of high power density and high reliability. Furthermore, increasing the pad area or using high melting point metals in existing technologies is costly and complex.
Multiple three-dimensional metal bump arrays are formed on the surface of the metal pads of power semiconductor devices. The geometry and distribution of the metal bumps are optimized by laser-induced metal deposition and selective electrochemical etching processes to form a three-dimensional multi-level metal bump array.
Without increasing chip area, the contact area of the pads is increased, enhancing the power cycling and thermal cycling capabilities of power devices, reducing costs and simplifying the process, while meeting high reliability requirements.
Smart Images
Figure CN121925149A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power device packaging technology, and more specifically to a power semiconductor device and a method for modifying and improving its metal pads. Background Technology
[0002] Power devices are widely used in industrial motor drives, new energy vehicles, and other fields where extremely high reliability is required. The power cycle capability of power devices such as Insulated Gate Bipolar Transistors (IGBTs) and Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors (SiC MOSFETs) after packaging is a key indicator of their reliability and lifespan. During the packaging process, power devices need to be connected to external circuits via solder pads. The contact area of these pads affects the power cycle capability and thermal cycle capability of the power device. The use of new materials has led to increasingly smaller areas for power devices with the same current capability, resulting in correspondingly smaller solder pad areas. This leads to lower power cycle capability and thermal cycle capability after packaging, failing to meet the application requirements of high power density and high reliability.
[0003] To improve the power cycling and thermal cycling capabilities of power devices, existing technologies typically increase the pad area, but this increases the chip area and thus the cost. Another approach is to use high-melting-point metals as pad materials, but high-melting-point metals are expensive and the soldering process with external circuitry is more complex. Summary of the Invention
[0004] To address the above problems, the present invention aims to provide a power semiconductor device; Another objective of this invention is to provide a method for modifying and improving the metal pads of power semiconductor devices.
[0005] A power semiconductor device, comprising: Semiconductor material layer of the chip; A dielectric layer is formed above the semiconductor material layer of the chip; A metal layer is formed above the dielectric layer, with a portion of the bottom of the metal layer reaching the chip semiconductor material layer; Metal pads are formed on the metal layer, and the surface of the metal pads is formed with a three-dimensional metal bump array consisting of multiple three-dimensional metal bumps.
[0006] The power semiconductor device of the present invention further includes a passivation layer formed in a region above the metal layer, outside the metal pad region, with a portion of the bottom of the passivation layer reaching the surface of the dielectric layer; A polyimide layer is formed on the outside of the passivation layer.
[0007] The present invention discloses a power semiconductor device, wherein the metal bumps are a single-level bump structure or a three-dimensional multi-level bump structure, the metal bumps are cylindrical or conical, the height of the metal bumps is 1 micrometer to 10 micrometers, the bottom surface size of the metal bumps is 5 micrometers to 50 micrometers, and the spacing between the metal bumps is 5 micrometers to 10 micrometers.
[0008] The present invention discloses a power semiconductor device in which a plurality of metal bumps are uniformly or non-uniformly distributed over the entire area of the metal pad, or in the edge or center area of the metal pad.
[0009] The present invention discloses a power semiconductor device, wherein the metal bump comprises a titanium layer, a nickel layer and a silver layer stacked sequentially.
[0010] The present invention discloses a power semiconductor device in which multiple three-dimensional metal bumps are formed by laser-induced metal deposition process.
[0011] A method for modifying and improving the metal pads of a power semiconductor device, used in the aforementioned power semiconductor device, comprising, The surface of the metal pad is pretreated to obtain a pretreated metal pad; Multiple three-dimensional metal bumps are formed by depositing metal on the surface of the pretreated metal pads using a laser-induced metal deposition process. Selective electrochemical etching and electrochemical polishing are performed on multiple metal bumps to obtain electrochemically treated metal bumps. A three-dimensional metal bump array is obtained by applying a metal coating.
[0012] The method for modifying and improving the metal pads of power semiconductor devices according to the present invention includes a laser power of 100W-300W and a scanning speed of 100mm / min-500mm / min in the laser-induced metal deposition process, wherein the height of the metal bump is 1 micrometer to 10 micrometers, the bottom surface size of the metal bump is 5 micrometers to 50 micrometers, and the spacing between the metal bumps is 5 micrometers to 10 micrometers.
[0013] The method for modifying and improving the metal pads of power semiconductor devices according to the present invention uses a phosphoric acid-sulfuric acid mixed solution as the electrolyte for electrochemical etching and electrochemical polishing, with a voltage of 5-10V, a current density of 10-50mA / cm2, an etching time of 1min to 3min, and a metal coating thickness of 0.5μm to 2μm.
[0014] The method for modifying and improving the metal pads of power semiconductor devices according to the present invention further includes, after the step of obtaining a three-dimensional metal bump array by metal plating: Determine whether the parameters of the three-dimensional metal bump array are reasonable. The parameters include geometric morphology, electrical performance, interface and material properties. If they are reasonable, continue to build a three-dimensional multi-level metal bump array. If they are not reasonable, adjust the laser-induced metal deposition process to make the parameters meet the requirements, and then continue to build a three-dimensional multi-level metal bump array. The construction of the three-dimensional multi-level metal bump array is carried out through the following steps: a layer of photoresist is spin-coated on the top of the three-dimensional metal bump array, and a secondary pattern is defined on the top surface of each primary bump; selective metal deposition technology is used to grow metal only in the area of the secondary pattern, and this process is repeated to form a three-dimensional multi-level metal bump array.
[0015] Beneficial effects: This invention provides a novel power semiconductor device that forms metal bumps on the surface of metal pads, thereby increasing the contact area of the pads without increasing the chip area, thus improving the power cycling capability and thermal cycling capability of the power device, while taking into account cost and process feasibility. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of a power semiconductor device of the present invention, showing a pad structure with increased contact area; Figure 2 This is a cross-sectional view of the power semiconductor device of the present invention after sintering; Figure 3 This is a cross-sectional view of the power semiconductor device of the present invention after wire bonding. Detailed Implementation
[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0018] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0019] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.
[0020] Reference Figure 1 A power semiconductor device, comprising: Semiconductor material layer 1 of the chip; Dielectric layer 2 is formed above semiconductor material layer 1 of the chip; Metal layer 3 is formed above dielectric layer 2, with part of the bottom of the metal layer reaching the chip semiconductor material layer 1; Metal pad 6, metal pad region 7 formed on metal layer 3, and a three-dimensional metal bump array composed of multiple three-dimensional metal bumps formed on the surface of metal pad 6.
[0021] This invention provides a novel power semiconductor device that forms metal bumps on the surface of metal pads or contact surfaces. This increases the contact area of the pads without increasing the chip area, thereby improving the power cycling capability and thermal cycling capability of the power device. This meets the application requirements of high power density and high reliability, while also taking into account cost and process feasibility.
[0022] A power semiconductor device of the present invention further includes a passivation layer 4 formed in the area above the metal pad region of the metal layer 3, and the bottom of a portion of the passivation layer 4 reaches the surface of the dielectric layer 2. A polyimide layer 5 is formed on the outside of the passivation layer 4.
[0023] The present invention discloses a power semiconductor device in which the metal bumps can be a single-level bump structure, more preferably a three-dimensional multi-level bump structure, and can be cylindrical, conical or other suitable shapes. The height of the metal bumps is 1 micrometer to 10 micrometers, preferably 1 micrometer to 5 micrometers, the bottom surface size of the metal bumps is 5 micrometers to 50 micrometers, and the spacing between the metal bumps is 5 micrometers to 10 micrometers.
[0024] In a power semiconductor device of the present invention, multiple metal bumps may be uniformly or non-uniformly distributed over the entire area of a metal pad, or the multiple metal bumps may be uniformly or non-uniformly distributed over a portion of the metal pad, such as the edge or center area. By optimizing the distribution area of the metal bumps, the power cycling capability and thermal cycling capability of the power device can be improved.
[0025] The present invention discloses a power semiconductor device in which the metal bumps can be composed of multiple layers of metal materials, such as sequentially stacked titanium, nickel, and silver layers, or they can be composed of conventional metal layer materials. By adopting a multilayer metal material structure, the soldering reliability between the metal bumps and external circuits can be further improved. Using conventional metal layer materials does not lead to an increase in cost.
[0026] A method for modifying and improving the metal pads of a power semiconductor device, used in the aforementioned power semiconductor device, includes the following steps: The surface of the metal pads is pretreated to obtain pretreated metal pads; Multiple three-dimensional metal bumps are formed by depositing metal on the surface of pretreated metal pads using a laser-induced metal deposition process. Selective electrochemical etching and electrochemical polishing were performed on multiple metal bumps to obtain electrochemically treated metal bumps. A three-dimensional metal bump array is obtained by applying a metal coating.
[0027] In the back-end process of chip manufacturing of power semiconductor devices, this invention uses an additive-subtractive composite process, including the synergistic process of laser-induced metal deposition (LIMD) and selective electrochemical etching, to form three-dimensional metal bumps, thereby forming metal pads with uneven surfaces on the power device. After subsequent sintering, packaging, or bonding, the contact area between the metal connection and the metal layer of the chip is increased.
[0028] In a preferred embodiment, the surface of the metal pad is pretreated by cleaning, etching, or chemical treatment to improve the deposition activity of the metal pad surface.
[0029] The additive-subtractive composite process of this invention includes using laser-induced metal deposition to deposit metal to form a preliminary three-dimensional structure, and then using selective electrochemical etching to precisely etch the deposited metal to remove excess material, ultimately constructing three-dimensional metal bumps. The laser-induced metal deposition process of this invention uses nanoscale metal powder as the metal source, with a laser power of 100W-300W and a scanning speed of 100mm / min-500mm / min.
[0030] The height of the metal bumps ranges from 1 micrometer to 10 micrometers, the bottom surface size of the metal bumps ranges from 5 micrometers to 50 micrometers, and the spacing between the metal bumps ranges from 5 micrometers to 10 micrometers.
[0031] The height, width, and spacing of the metal bumps in this invention are carefully designed to ensure that while increasing the contact area, the contact resistance remains essentially stable. This structure effectively disperses thermomechanical stress and reduces stress concentration points, thereby improving the reliability and stability of the device during power cycling.
[0032] The present invention discloses a method for modifying and improving the metal pads of power semiconductor devices. The electrolyte used for electrochemical etching and electrochemical polishing is a phosphoric acid-sulfuric acid mixed solution, with a voltage of 5-10V, a current density of 10-50mA / cm², and an etching time of 1-3 minutes. Selective electrochemical etching is performed on the three-dimensional metal bumps to remove metal particles at the bump tips, resulting in a smooth bump surface. A metal plating layer is then applied to the surface of the three-dimensional metal bumps to improve their corrosion resistance and conductivity. An electroless nickel plating process is used, and the plating thickness is 0.5 micrometers to 2 micrometers.
[0033] The method for modifying and improving the metal pads of power semiconductor devices according to the present invention further includes, after the step of obtaining a three-dimensional metal bump array by metal plating: Determine whether the parameters of the three-dimensional metal bump array are reasonable. The parameters can include geometric morphology, electrical performance, interface and material properties. If they are reasonable, continue to build three-dimensional multi-level metal bumps. If they are not reasonable, adjust the laser-induced metal deposition process to meet the requirements, and then continue to build three-dimensional multi-level metal bumps. Once the basic 3D metal bump array is deemed suitable, a more refined secondary structure is built on top of it to form a 3D multi-level metal bump array. The construction of the 3D multi-level metal bump array involves the following steps: A layer of photoresist is spin-coated onto the top of the suitable 3D metal bump array. Using higher resolution photolithography or direct writing technology, smaller and denser secondary patterns are defined on the top surface of each primary bump. Selective metal deposition technology is used to grow metal only in the areas of the secondary patterns. The same metal material as the primary bumps can be deposited, or different metals (such as nickel or gold) can be selected to meet specific functions (such as enhanced oxidation resistance). This process is repeated as needed to form a 3D multi-level metal bump array.
[0034] like Figure 2 As shown, after the formation of the three-dimensional, undulating, multi-level metal bumps in the metal pad region 7, sintering and encapsulation are performed. The undulating three-dimensional bumps increase the contact area between the sintered encapsulation metal layer and the chip metal pads. If the power semiconductor device uses wire bonding encapsulation, the contact area between the bonding wire 8 and the chip's metal pads 6 will also increase, such as... Figure 3 As shown, this improves power cycling capability while maintaining a substantially constant contact resistance. The power cycling capability of power semiconductor devices using this invention is more than three times that of conventional planar pads, with increased contact area while maintaining a substantially constant contact resistance.
[0035] The description and accompanying drawings provide typical embodiments of specific structures for specific implementations. Other modifications are possible based on the spirit of the invention. While the above-described invention presents preferred embodiments, these are not intended to be limiting.
[0036] For those skilled in the art, various changes and modifications will undoubtedly be apparent after reading the above description. Therefore, the appended claims should be construed as covering all changes and modifications that encompass the true intent and scope of the invention. Any and all equivalent scope and content within the scope of the claims should be considered to remain within the intent and scope of the invention.
Claims
1. A power semiconductor device, characterized in that, include: Semiconductor material layer of the chip; A dielectric layer is formed above the semiconductor material layer of the chip; A metal layer is formed above the dielectric layer, with a portion of the bottom of the metal layer reaching the chip semiconductor material layer; Metal pads are formed on the metal layer, and the surface of the metal pads is formed with a three-dimensional metal bump array consisting of multiple three-dimensional metal bumps.
2. The power semiconductor device according to claim 1, characterized in that, It also includes a passivation layer formed in the area above the metal layer, outside the metal pad area, with a portion of the bottom of the passivation layer reaching the surface of the dielectric layer; A polyimide layer is formed on the outside of the passivation layer.
3. A power semiconductor device according to claim 1, characterized in that, The metal bumps are a single-level bump structure or a three-dimensional multi-level bump structure. The metal bumps are cylindrical or conical. The height of the metal bumps is 1 micrometer to 10 micrometers. The bottom surface size of the metal bumps is 5 micrometers to 50 micrometers. The spacing between the metal bumps is 5 micrometers to 10 micrometers.
4. A power semiconductor device according to claim 1, characterized in that, The multiple metal bumps are evenly or non-evenly distributed over the entire area of the metal pad, or the multiple metal bumps are evenly or non-evenly distributed over the edge or center area of the metal pad.
5. A power semiconductor device according to claim 1, characterized in that, The metal bumps consist of layers of titanium, nickel, and silver stacked sequentially.
6. A power semiconductor device according to claim 1, characterized in that, Multiple three-dimensional metal bumps are formed using a laser-induced metal deposition process.
7. A method for modifying and improving the metal pads of a power semiconductor device, characterized in that, For the power semiconductor device according to any one of claims 1-6, comprising, The surface of the metal pad is pretreated to obtain a pretreated metal pad; Multiple three-dimensional metal bumps are formed by depositing metal on the surface of the pretreated metal pads using a laser-induced metal deposition process. Selective electrochemical etching and electrochemical polishing are performed on multiple metal bumps to obtain electrochemically treated metal bumps. A three-dimensional metal bump array is obtained by applying a metal coating.
8. The method for modifying and improving the metal pads of a power semiconductor device according to claim 7, characterized in that, The laser power of the laser-induced metal deposition process is 100W-300W, the scanning speed is 100mm / min-500mm / min, the height of the metal bumps is 1 micrometer to 10 micrometers, the bottom surface size of the metal bumps is 5 micrometers to 50 micrometers, and the spacing between the metal bumps is 5 micrometers to 10 micrometers.
9. The method for modifying and improving the metal pads of a power semiconductor device according to claim 7, characterized in that, The electrolyte for electrochemical etching and electrochemical polishing is a phosphoric acid-sulfuric acid mixed solution, the voltage is 5-10V, the current density is 10-50mA / cm2, the etching time is 1min to 3min, and the coating thickness of the metal coating is 0.5μm to 2μm.
10. The method for modifying and improving the metal pads of a power semiconductor device according to claim 7, characterized in that, After the step of obtaining a three-dimensional metal bump array by metal coating, the following steps are also included: Determine whether the parameters of the three-dimensional metal bump array are reasonable. The parameters include geometric morphology, electrical performance, interface and material properties. If they are reasonable, continue to build a three-dimensional multi-level metal bump array. If they are not reasonable, adjust the laser-induced metal deposition process to make the parameters meet the requirements, and then continue to build a three-dimensional multi-level metal bump array. The construction of the three-dimensional multi-level metal bump array is carried out through the following steps: a layer of photoresist is spin-coated on the top of the three-dimensional metal bump array, and a secondary pattern is defined on the top surface of each primary bump; selective metal deposition technology is used to grow metal only in the area of the secondary pattern, and this process is repeated to form a three-dimensional multi-level metal bump array.