Semiconductor packaging structure

Abstract

A semiconductor packaging structure comprises a substrate, an image sensing chip, a metal wire, a cover body, a first sealing glue layer and a solder ball array. The image sensing chip is located on the upper surface of the substrate. The two ends of the metal wire are electrically connected with the image sensing chip and the upper contact points on the upper surface of the substrate respectively. The lower surface of the cover body is connected with the first cover body side face of the cover body, and a first cover body included angle larger than 90 degrees is formed between the lower surface of the cover body and the first cover body side face. The first sealing glue layer laterally encapsulates the substrate, the metal wire, the image sensing chip and the cover body and exposes a part of the upper surface of the image sensing chip, and an air chamber is defined among the first sealing glue layer, the lower surface of the cover body and the part of the exposed upper surface of the image sensing chip. The solder ball array comprises a plurality of solder balls, and each solder ball is electrically connected with a lower contact point on the lower surface of the substrate individually.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging structure, and more particularly to a semiconductor packaging structure for an image sensing chip. Background Technology

[0002] Please refer to Figure 1 , Figure 1 This is a schematic cross-sectional view of a known semiconductor package structure 1. Figure 1 The semiconductor package structure 1 mainly includes a substrate 10, a solder ball array 11 (including solder balls 110), an image sensor chip 12, a cover 13, intermediates 14, metal lines 16, and encapsulating layers 17 and 18. The intermediates 14 are typically disposed on both sides of the image sensor chip 12, and the cover 13 is disposed on the two intermediates 14, so that the image sensor chip 12, the two intermediates 14, and the cover 13 define a gas chamber 15. The encapsulating layers 17 and 18 laterally encapsulate both sides of the two intermediates 14 and the cover 13. The configuration of the substrate 10, the solder ball array 11 (and its solder balls 110), and the metal lines 16 can be referred to... Figure 1 This will not be elaborated further here. Summary of the Invention

[0003] However, in such Figure 1 In the known semiconductor package structure 1, the lateral encapsulation of the encapsulating layer 17 (or even the encapsulating layer 18) will be limited by the setting of the intermediate material 14, which will result in encapsulation defects and thus affect the overall yield and reliability of the semiconductor package structure 1.

[0004] In addition, in such Figure 1 In the known semiconductor package structure 1, the air chamber 15 has a relatively large volume, thus retaining a significant amount of air within it. Since the cover 13, encapsulating layers 17 and 18, and substrate 10 are all non-permeable components, when the semiconductor package structure 1 undergoes subsequent heat treatment processes (such as reflow soldering), the air inside the air chamber 15 will expand due to heat, creating a pressure difference between the interior and exterior of the air chamber 15. This pressure difference can lead to adhesion failure between the cover 13 and the encapsulating layers 17 and 18, thereby affecting the overall yield and reliability of the semiconductor package structure 1.

[0005] In view of this, some embodiments propose a semiconductor package structure comprising a substrate, an image sensor chip, a plurality of metal lines, a cover, a first encapsulating layer, and a solder ball array. The substrate has an upper surface, a lower surface, and traces located between the upper and lower surfaces. The upper surface has a plurality of upper contact points, and the lower surface has a plurality of lower contact points, the upper contact points being electrically connected to the lower contact points via traces. The image sensor chip is located on the upper surface of the substrate. One end of each metal line is electrically connected to the image sensor chip, and the other end of each metal line is electrically connected to the upper surface of the substrate. The cover has a lower surface and a first cover side surface, the lower surface of the cover being connected to the first cover side surface, and a first cover angle greater than 90 degrees is formed between the lower surface of the cover and the first cover side surface. The first encapsulating layer laterally encapsulates the substrate, the metal lines, the image sensor chip, and the cover, and exposes a portion of the upper surface of the image sensor chip, and a chamber is defined between the first encapsulating layer, the lower surface of the cover, and the exposed portion of the upper surface of the image sensor chip. The solder ball array comprises multiple solder balls, each of which is electrically connected to a lower contact point of the substrate.

[0006] In some embodiments, the cover further has a second cover side. The second cover side is connected to the first cover side. A second cover angle is formed between the lower surface of the cover and the second cover side, and the second cover angle is less than or equal to the first cover angle. Attached Figure Description

[0007] The invention can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 A schematic cross-sectional view of a known semiconductor packaging structure;

[0009] Figure 2 This is a cross-sectional view of the semiconductor packaging structure of the first embodiment;

[0010] Figures 3A to 3F For example Figure 2 A cross-sectional schematic diagram of a semi-finished semiconductor packaging structure;

[0011] Figure 4A This is a cross-sectional structural diagram of a semi-finished cover body according to some embodiments;

[0012] Figures 4B to 4C This is a cross-sectional structural diagram of the cover in some embodiments;

[0013] Figures 5A to 5C This is a cross-sectional structural diagram of a semi-finished cover body according to some embodiments;

[0014] Figure 5D This is a cross-sectional structural diagram of the cover body in some embodiments;

[0015] Figure 6 This is a cross-sectional view of the semiconductor packaging structure of the second embodiment; and

[0016] Figure 7 This is a cross-sectional structural diagram of the cover in some embodiments.

[0017] In the attached figures, the following labels are used:

[0018] 1: Semiconductor packaging structure;

[0019] 10:Substrate;

[0020] 11: Solder ball array;

[0021] 110: Welding ball;

[0022] 12: Image sensing chip;

[0023] 13: Cover;

[0024] 14: Intermediate goods;

[0025] 15: Air chamber;

[0026] 16: Metal wire;

[0027] 17, 18: Sealing layer;

[0028] 2a, 2b: Semiconductor packaging structure;

[0029] 20:Substrate;

[0030] 200: (of the substrate) upper surface;

[0031] 201: Upper contact point;

[0032] 202: Wiring;

[0033] 203: Lower contact point;

[0034] 204: (Substrate) Lower surface;

[0035] 21: Solder ball array;

[0036] 210: Welding ball;

[0037] 22: Image sensing chip;

[0038] 23: Cover;

[0039] 230: (The lower surface of the cover);

[0040] 231: Side view of the first cover;

[0041] 232: Side view of the second cover;

[0042] 25: Air chamber;

[0043] 26: Metal wire;

[0044] 27: First sealant layer;

[0045] 270: (The upper surface of the first sealant layer);

[0046] 271: First sealant side;

[0047] 28: Second sealant layer;

[0048] 280: (The upper surface of the second sealant layer);

[0049] 281: Second sealant side;

[0050] 30: Material of the cover;

[0051] 31: Cover;

[0052] 310: (The lower surface of the cover);

[0053] 311: Side of the cover;

[0054] 32: First colloid;

[0055] 33: Second colloid;

[0056] 34: First cutting tool;

[0057] 340: First cutting edge;

[0058] 40: Cover material;

[0059] 41: Second cutting tool;

[0060] 410: Second cutting edge;

[0061] 42: Third cutting tool;

[0062] 420: Third cutting face;

[0063] θ0,θ0': Angle between the covers;

[0064] θ1,θ1': Angles between the first cover bodies;

[0065] θ2,θ2': Angles between the second cover bodies;

[0066] θ3,θ3': The included angle of the first sealant application;

[0067] θ4,θ4': The included angle of the second sealant;

[0068] X: The X-axis of the coordinate system;

[0069] Y: The y-axis of the coordinate system;

[0070] Z: The Z-axis of the coordinate system. Detailed Implementation

[0071] Please refer to Figure 2 and Figure 3E , Figure 2 This is a cross-sectional view of the semiconductor packaging structure 2a in the first embodiment; Figure 3E For example Figure 2 A schematic cross-sectional view of the semi-finished semiconductor package structure 2a. Figure 2 A semiconductor package structure 2a includes a substrate 20, an image sensor chip 22, multiple metal lines 26, a cover 23, a first encapsulating layer 27, and a solder ball array 21. In one cross-section (e.g., Figure 2 and Figure 3E In the YZ plane, the substrate 20 has an upper surface 200, a lower surface 204, and a trace 202 located between the upper surface 200 and the lower surface 204. The upper surface 200 of the substrate 20 has a plurality of upper contact points 201, and the lower surface 204 of the substrate 20 has a plurality of lower contact points 203. Each upper contact point 201 is individually electrically connected to at least one of the plurality of lower contact points 203 through the trace 202. The image sensing chip 22 is located on the upper surface 200 of the substrate 20. One end of each metal line 26 is electrically connected to the image sensing chip 22, and the other end of each metal line 26 is electrically connected to at least one of the plurality of upper contact points 201. The cover 23 has an upper surface (not shown), a lower surface 230, and a first cover side surface 231. The lower surface 230 of the cover 23 is connected to the first cover side surface 231, and there is a first cover angle θ1, θ1' between the lower surface 230 and the first cover side surface 231 (e.g., ...). Figure 2 or Figure 3E The first cover angles θ1 and θ1' refer to the angles formed between the lower surface 230 of the cover 23 and the first cover side surfaces 231 on both sides of the cover 23, respectively. The first cover angles θ1 and θ1' can be the same or different angles, but both are greater than 90 degrees. The first encapsulating layer 27 laterally encapsulates the substrate 20, the metal line 26, the image sensor chip 22, and the cover 23, and exposes a portion of the upper surface of the image sensor chip 22 (not shown). An air chamber 25 is defined between the first encapsulating layer 27, the lower surface 230 of the cover 23, and the exposed portion of the upper surface of the image sensor chip 22. The solder ball array 21 includes a plurality of solder balls 210, and each solder ball 210 is individually electrically connected to at least one of the plurality of lower contact points 203 of the substrate 20.

[0072] Therefore, in some embodiments, by setting the upper surface of the cover 23 to be wider than the lower surface 230 of the cover 23 (i.e., wider at the top and narrower at the bottom), the cover 23 will be snapped onto the image sensing chip 22, without the need for further configuration such as... Figure 1 The intermediate 14, thereby avoiding known encapsulation defects between the sealant layer 17 (or even the sealant layer 18) and the intermediate 14 and / or the cap 13; at the same time, in some embodiments, the height of the air chamber 15 (i.e., the height of the air chamber 15 at...) can also be effectively controlled. Figure 1 The dimension in the Z direction is reduced to the height of the air chamber 25 (i.e., the air chamber 25 is at...). Figure 2 The dimensions in the Z direction are used to prevent the adhesion between the cover 13 and the encapsulating layers 17 and 18 from failing due to pressure differences caused by subsequent processes, thereby affecting the yield and reliability of the overall semiconductor package structure 1. In other words, in some embodiments, the yield and reliability of the overall semiconductor package structure 2a can be maintained at a better (or even better) level without being affected.

[0073] Furthermore, due to such Figure 1 The cover 13 can be used to transmit light. Once the light enters the air chamber 15, it is reflected back and forth within the air chamber 15 by the surrounding environment (e.g., the lower surface of the cover 13 (not shown) and the intermediate objects 14 on both sides of the air chamber 15), thereby causing unnecessary interference to the image sensing chip 12. For example, the light transmitted within the air chamber 15 may produce unwanted glare due to further reflection or transmission to the intermediate objects 14 and / or the cover 13.

[0074] Conversely, in some embodiments, by means of Figure 2 The cover 23 is designed to be wider at the top and narrower at the bottom, which alters the light transmission path within the cover 23 due to reflection from the side 231 of the first cover, thereby reducing the probability of light transmission into the air chamber 25 and avoiding unnecessary interference caused by light traveling back and forth within the air chamber 25. Furthermore, in some embodiments, even if light further transmits into the air chamber 25, the semiconductor package structure 2a does not require additional features such as... Figure 1 The intermediate material 14 is used to prevent the light from being reflected or transmitted to the intermediate material 14, thus avoiding unnecessary glare. At the same time, since the light from the two sides of the air chamber 25 will no longer be transmitted or transmitted into the first sealing layer 27, the light from the two sides of the air chamber 25 will be confined to the air chamber 25, thereby more effectively avoiding unnecessary glare.

[0075] Additionally, in some embodiments, by means of Figure 2The cover 23 is designed to be wider at the top and narrower at the bottom. Therefore, there is no need to provide a separate, known shielding layer on the lower surface 230 of the cover 23. This saves the processing time and cost required for setting a shielding layer and effectively avoids unnecessary glare. In some embodiments, the shielding layer is made of photoresist, black ink, or other black adhesive.

[0076] Please refer to Figure 2 and Figure 3F , Figure 3F For example Figure 2 A schematic cross-sectional view of the semi-finished semiconductor package structure 2a. Figure 2 The cover 23 also has a second cover side 232, which is connected to the first cover side 231, and the lower surface 230 of the cover 23 and the second cover side 232 have a second cover angle θ2, θ2' (e.g., ...). Figure 3F The second cover angles θ2 and θ2' refer to the angles formed between the lower surface 230 of the cover 23 (e.g., a virtual plane or dashed line parallel to the lower surface 230) and the second cover side surfaces 232 on both sides of the cover 23, respectively. The second cover angles θ2 and θ2' can be the same or different angles, but they are both less than or equal to the corresponding first cover angles θ1 and θ1' (e.g., ...). Figure 2 For example, the included angle θ2 of the second cover is less than or equal to the included angle θ1 of the first cover located on the same side of the cover 23. For example, the included angles θ2 and θ2' of the second cover are both 90 degrees (e.g., Figure 2 and Figure 3F And both are smaller than the corresponding first cover angles θ1 and θ1' (e.g.) Figure 2 Therefore, in some embodiments, the two sides of the cover 23 can be respectively through a first cover side 231 and a second cover side 232 that are not coplanar. This can change the light transmission path inside the cover 23 due to the reflection of the first cover side 231 and the second cover side 232, thereby further reducing the probability of light transmission to the air chamber 25, and thus avoiding unnecessary interference caused by light transmission back and forth in the air chamber 25, such as glare.

[0077] Please refer to Figure 2 and Figure 3F In some embodiments, the semiconductor package structure 2a further includes a second encapsulating layer 28, which is located on the first encapsulating layer 27 and laterally encapsulates the cover body 23. For example, in Figure 2The first sealing layer 27 is lateral to the first cover side 231 of the cover 23, and the second sealing layer 28 is lateral to the second cover side 232 of the cover 23. Therefore, in some embodiments, by setting the first cover side 231 and the second cover side 232, the light transmission path inside the cover 23 can be changed due to the reflection of the first cover side 231 and the second cover side 232, thereby reducing the probability of light transmission to the air chamber 25, and thus avoiding unnecessary interference caused by light transmitting back and forth in the air chamber 25, such as glare.

[0078] The following is passed Figure 2 and Figures 3A to 3F The specific implementation and fabrication process of semiconductor packaging structure 2a are illustrated.

[0079] Please refer to Figure 3A , Figure 3A For example Figure 2 A cross-sectional view of a semi-finished semiconductor package structure 2a is shown. The substrate 20 has an opposing upper surface 200 and a lower surface 204. The upper surface 200 is provided with a plurality of upper contact points 201, and the lower surface 204 is provided with a plurality of lower contact points 203. The substrate 20 also has a plurality of traces 202 to selectively electrically connect a portion of the upper contact points 201 to a portion of the lower contact points 203. In other words, a single upper contact point 201 can be electrically connected to one or more lower contact points 203 via traces 202, and a single lower contact point 203 can also be electrically connected to one or more upper contact points 201 via traces 202. Therefore, those skilled in the art will understand that the configuration of the upper contact points 201, traces 202, and lower contact points 203 of the present invention is not limited to the drawings in this case (e.g., Figure 3A and Figure 2 The configuration illustrated herein is subject to adjustment according to various requirements and is covered by this invention. In some embodiments, the substrate 20 is a laminated material composed of multiple layers of glass fiber composite material. In other embodiments, the substrate 20 is a ceramic substrate made of silicon nitride (Si3N4), alumina (Al2O3), aluminum nitride (AlN), zirconium oxide (ZrO2), zirconium oxide-toughened alumina (ZTA), and beryllium oxide (BeO).

[0080] Please refer to Figure 3A The image sensing chip 22 has an active surface (e.g., Figure 3A The upper surface of the image sensing chip 22 and the back surface (e.g., the upper surface of the image sensing chip 22) and the back surface (e.g., the back surface of the image sensing chip 22) Figure 3A The lower surface of the image sensor chip 22). The image sensor chip 22 faces upward with its active surface facing upward and is held together by a die-attach adhesive (e.g., Figure 3AThe image sensor chip 22 is bonded to the upper surface 200 of the substrate 20 using an adhesive between its lower surface and the upper surface 200 of the substrate 20. The active surface of the image sensor chip 22 may include an image sensing area (e.g., Figure 3A The middle portion of the upper surface of the image sensing chip 22 and multiple solder joints (e.g., the middle portion of the upper surface of the image sensing chip 22) and the multiple solder joints located around the image sensing area. Figure 3A The image sensing chip 22 is located on two sides of its upper surface. These solder joints allow the image sensing chip 22 to be electrically connected to external circuitry. In some embodiments, these solder joints are located on opposite sides of the image sensing area (e.g., on both sides). Figure 3A (both sides of the upper surface of the image sensing chip 22).

[0081] Please continue to refer to this. Figure 3A The metal wire 26 is electrically connected to the image sensor chip 22 and the upper surface 200 of the substrate 20 by wire bonding. For example, one end of the metal wire 26 is bonded to at least one of the solder joints of the image sensor chip 22, and the other end of the metal wire 26 is bonded to at least one of the multiple upper contact points 201 of the substrate 20.

[0082] Please refer to Figure 3B , Figure 3B For example Figure 2 A cross-sectional view of the semi-finished semiconductor packaging structure 2a is shown. The cover 31 has an upper surface (not shown), a lower surface 310, and cover side surfaces 311. The lower surface 310 of the cover 31 connects to the cover side surfaces 311, and there are cover angles θ0 and θ0' between the lower surface 310 and the cover side surfaces 311. The cover angles θ0 and θ0' refer to the angles formed between the lower surface 310 of the cover 31 and the cover side surfaces 311 on both sides of the cover 31, respectively. The cover angles θ0 and θ0' can be the same or different angles, but both are greater than 90 degrees. In some embodiments, the cover angles θ0 and θ0' correspond to the first cover angles θ1 and θ1', respectively (e.g., ...). Figure 2 The cover 23 is configured such that its two sides are fitted together and snapped into the first sealing layer 27 (e.g., Figure 2 For example, the included angle θ0 of the cover is equal to or slightly greater than the included angle θ1 of the first cover, and the included angle θ0' of the cover is equal to or slightly greater than the included angle θ1' of the first cover. In some embodiments, the cover 31 is made of glass, and its transmittance relative to visible light is greater than 90%. The cover 31 can be obtained, for example, by a preparation method described later in detail.

[0083] Please refer to Figure 3BThe cover 31 is fixed to the active surface of the image sensor chip 22 (e.g., the image sensing area of ​​the image sensor chip 22) by a second adhesive 33. For example, the second adhesive 33 is applied between the lower surface 310 of the cover 31 and the active surface of the image sensor chip 22. In some embodiments, the second adhesive 33 is a hydrosol that can be removed with water or various aqueous solutions. In other embodiments, the second adhesive 33 is double-sided tape, foam adhesive, or a combination thereof, which can be removed with organic solvents or other physical methods (e.g., peeling). The thickness of the second adhesive 33 can be adjusted according to different needs and is not limited. Based on this, the cover 31 can be fixed to the image sensor chip 22 by the second adhesive 33, and the cover 31 and the image sensor chip 22 can be protected from damage; in addition, in subsequent processes, the cover 31 can be quickly separated from the image sensor chip 22 by removing the second adhesive 33, thereby shortening the process time and cost.

[0084] Please continue to refer to this. Figure 3B In some embodiments, the cover 31 is further coated with a first colloid 32. For example, the first colloid 32 is coated on the lower surface 310 and the side surface 311 of the cover 31, so that the cover 31 coated with the first colloid 32 is fixed to the active surface of the image sensing chip 22 by a second colloid 33. In some embodiments, the first colloid 32 is made of polyimide (PI), which can be removed with organic solvents. In other embodiments, the first colloid 32 is made of hydrosol, which can be removed with water or various aqueous solutions. In still other embodiments, the first colloid 32 is double-sided tape, foam adhesive, or a combination thereof, which can be removed with organic solvents or other physical methods (e.g., peeling). In still other embodiments, the material of the first colloid 32 coated on the lower surface 310 of the cover 31 is different from the material of the first colloid 32 coated on the side surface 311 of the cover 31. Furthermore, the first colloid 32 and the second colloid 33 can be made of the same or different materials, without limitation; for example, both can be hydrosols, or the first colloid 32 can be polyimide and the second colloid 33 can be hydrosol. The thickness of the first colloid 32 can be adjusted according to different needs, without limitation. Based on this, by setting the first colloid 32, the cover 31 can be fixed to the image sensing chip 22 and the first encapsulating layer 27 (e.g., Figure 3C (Details to follow) It can also protect the cover 31 from damage; in addition, in subsequent processes, by removing the first adhesive 32, the cover 31 can be quickly separated from the image sensing chip 22 (or the second adhesive 33) and the first encapsulating layer 27, thereby shortening the process time and cost.

[0085] Please refer to Figure 3C , Figure 3C For example Figure 2 A schematic cross-sectional view of the semi-finished semiconductor package structure 2a. Figure 3CThe first encapsulating layer 27 laterally encapsulates the substrate 20, metal line 26, image sensor chip 22, cover 31, die bond adhesive, first adhesive 32, and second adhesive 33. Furthermore, the first encapsulating layer 27 tightly encapsulates the surface contours of the cover 31, the first adhesive 32, and the second adhesive 33 on both sides, so that the surface contours of the first encapsulating layer 27 match the surface contours of the cover 31, the first adhesive 32, and the second adhesive 33. The material of the first encapsulating layer 27 can be, for example, a material with a low melting point or glass transition temperature (e.g., below the temperature that would damage the image sensor chip 22), so that the first encapsulating layer 27 can remain in a liquid adhesive state and have fluidity during filling, and can be made to follow the surface contours of each component to be encapsulated (e.g., cover 31, first adhesive 32, and second adhesive 33) as much as possible through, for example, dispensing. In some embodiments, the first sealant layer 27 is made of a material with low light transmittance in the visible light range, such as a material containing epoxy resin.

[0086] Please refer to Figure 3C and Figure 3D , Figure 3D For example Figure 2 A cross-sectional view of a semi-finished semiconductor packaging structure 2a. In some embodiments, the surface contour of the cured first encapsulant layer 27 matches the surface contours of the two sides of the cover 31, the two sides of the first adhesive 32, and the two sides of the second adhesive 33. In some embodiments, the cured first encapsulant layer 27 has an upper surface 270, a lower surface (not shown), and a first encapsulant side surface 271. The upper surface 270 of the first encapsulant layer 27 is connected to the first encapsulant side surface 271, and there is a first encapsulant angle θ3, θ3' between the upper surface 270 and the first encapsulant side surface 271. The first encapsulant angle θ3, θ3' refers to the angle formed between the upper surface 270 of the first encapsulant layer 27 and the first encapsulant side surfaces 271 on both sides of the first encapsulant layer 27, and the first encapsulant angles θ3 and θ3' can be the same or different angles, but both are greater than 90 degrees. In some embodiments, the first encapsulant angle θ3 and the first encapsulant angle θ3' (e.g. Figure 3D ) respectively correspond to the included angle θ0 and included angle θ0' of the cover (e.g. Figure 3C ) configuration to enable, for example Figure 2 or Figure 3E The cover 23 is fitted onto the first sealing layer 27 on both sides; for example, the included angle θ0 of the cover is equal to or slightly greater than the included angle θ3 of the first sealing layer, and the included angle θ0' of the cover is equal to or slightly greater than the included angle θ3' of the first sealing layer.

[0087] For example, the first sealant angle θ3 of the first sealant layer 27 after curing (e.g.) Figure 3D ) equal to or slightly less than the included angle θ0 of the enclosure (e.g. Figure 3C ), the first sealant angle θ3' (e.g. Figure 3D ) equal to or slightly less than the included angle θ0' of the enclosure (e.g. Figure 3C Based on this, in Figure 3D When further removal such as Figure 3C When the cover 31, the first colloid 32, and the second colloid 33 expose a portion of the upper surface of the image sensing chip 22 (e.g., the image sensing area of ​​the active surface of the image sensing chip 22), the result is as follows: Figure 3D The surface profile of the first sealing side 271 can be roughly the same as the surface profile of the cover side 311.

[0088] Please refer to Figure 3C and Figure 3D In some embodiments, the upper surface 270 of the cured first sealant layer 27 is horizontal and parallel to the upper surface 200 of the substrate 20. In other embodiments, the upper surface 270 of the cured first sealant layer 27 is inclined, for example, the thickness of the first sealant layer 27 (i.e., as shown in the figure) Figure 3D The dimension in the Z direction decreases in the direction away from the cover 23; that is, in these embodiments, the upper surface 270 of the first sealant layer 27 can be configured as follows: Figure 1 The upper surface of the sealing layer 17. In some other embodiments, the upper surface 270 of the first sealing layer 27 is coplanar with the upper surface of the cover 31 (e.g., Figure 3C For example, the first sealant layer 27 can be thinned by chemical mechanical polishing until the upper surface of the cover 31 is exposed to the upper surface 270 of the first sealant layer 27.

[0089] Please refer to Figure 3E , for removal such Figure 3C After the cover 31 is installed, the cover 23 is snapped onto the first sealing layer 27 and positioned approximately corresponding to the cover 31, so that an air chamber 25 is defined between the first sealing layer 27, the lower surface 230 of the cover 23, and a portion of the exposed upper surface of the image sensing chip 22 (e.g., the image sensing area exposing the active surface of the image sensing chip 22). The cover 23 can be obtained, for example, by a preparation method described later in detail. In some embodiments, the air chamber 25 is a sealed space.

[0090] Please refer to Figure 3E In some embodiments, the surface profile of the cover 23 attached to the first sealant layer 27 (e.g., the surface profile of its first cover side 231) matches the surface profile of the first sealant side 271. For example, the first cover angle θ1 of the first sealant layer 27 is equal to or slightly greater than the first sealant angle θ3', and the first cover angle θ1' is equal to or slightly greater than the first sealant angle θ3'. Based on this, in Figure 3EWhen the cover 23 is further attached to the first sealing layer 27 so that the cover 23, the first sealing layer 27 and a portion of the exposed upper surface of the image sensing chip 22 (e.g., the image sensing area of ​​the active surface of the image sensing chip 22) define the air chamber 25, the surface profile of the first sealing side 271 obtained can be approximately the same as the surface profile of the cover 23 (e.g., the surface profile of its first cover side 231).

[0091] In some embodiments, since such settings have been configured as follows Figure 3E The cover 23 means that there is no need to set up another cover such as Figure 1 The intermediate 14, thus avoiding the intermediate 14 from being used with, for example Figure 1 Encapsulation defects can be generated between the encapsulation layers 17 (or even the encapsulation layers 18), thereby avoiding affecting the overall yield and reliability of the semiconductor package structure 1.

[0092] Furthermore, in some embodiments, since the cover 23 is already provided, there is no need to provide another such cover. Figure 1 The intermediate 14 is therefore no longer limited by the intermediate 14 and its process, so as... Figure 3E The air chamber 25 will be reduced as much as possible. Therefore, in some embodiments, even if the semiconductor package structure 2a subsequently undergoes other heat treatment processes, the air in the air chamber 25 has been significantly reduced, thus preventing the cover 23 from merging with the first encapsulating layer 27 (or even with the layer described later). Figure 3F The adhesion between the second encapsulant layer 28 and the adhesive layer fails, thereby providing an overall semiconductor package structure 2a with maintained or better yield and reliability.

[0093] Please refer to Figure 3E and Figure 3F In some embodiments, the cover 23 further has a second cover side 232, which is connected to the first cover side 231, and the lower surface 230 of the cover 23 and the second cover side 232 have a second cover angle θ2, θ2' (e.g., ...). Figure 3F The specific implementation of the second cover side 232 and the included angles θ2 and θ2' of the second cover can be referred to the foregoing and will not be described in detail here. The cover 23 and its first cover side 231 and second cover side 232 can be obtained, for example, by the preparation method described later, which will be described in detail later. In some embodiments, the upper surface of the cover 23 is higher than the upper surface 270 of the first sealing layer 27. In some embodiments, such as Figure 3E The upper surface 270 of the first sealant layer 27 is located at the height of the connection between the first cover side 231 and the second cover side 232, so as to expose the second cover side 232.

[0094] Please refer to Figure 3FIn some embodiments, the second sealant layer 28 is located on the first sealant layer 27 and laterally encapsulates the cover 23 and the first sealant layer 27. Furthermore, the second sealant layer 28 tightly encapsulates the cover 23 by following the surface contours of both sides (e.g., the second cover side 232 of the cover 23), so that the surface contours of the second sealant layer 28 match the surface contours of both sides of the cover 23. The material of the second sealant layer 28 may be, for example, a material with a low melting point or glass transition temperature (e.g., below the temperature that would cause the first sealant layer 27 to melt or deteriorate), so that the second sealant layer 28 remains in a liquid gel state and has fluidity when covering the first sealant layer 27, without causing the first sealant layer 27 to melt or deteriorate, and so that after curing, the second sealant layer 28 follows the surface contours of each element to be encapsulated (e.g., the cover 23 (e.g., the second cover side 232) and the first sealant layer 27) as closely as possible. In some embodiments, the second sealant layer 28 is made of a material with low light transmittance in the visible light range, such as a material containing a thermosetting sealant.

[0095] In some embodiments, the surface contour of the cured second sealant layer 28 matches the surface contours of the two sides of the cover 23. In some embodiments, the cured second sealant layer 28 has an upper surface 280, a lower surface (not shown), and a second sealant side surface 281. The upper surface 280 of the second sealant layer 28 is connected to the second sealant side surface 281, and there is a second sealant angle θ4, θ4' between the upper surface 280 and the second sealant side surface 281. The second sealant angle θ4, θ4' refers to the angle formed between the upper surface 280 of the second sealant layer 28 and the second sealant side surfaces 281 on both sides of the second sealant layer 28, and the second sealant angles θ4 and θ4' can be the same or different angles, but both are greater than 90 degrees. In some embodiments, the second sealant angle θ4 and the second sealant angle θ4' (e.g., Figure 3F ) respectively correspond to the included angle θ2 of the second cover and the included angle θ2' of the second cover (e.g. Figure 3F The surface profiles of the two sides of the cover 23 (e.g., the surface profile of its second cover side 232) are configured to match the surface profile of the second sealant side 281; for example, the included angle θ2 of the second cover is equal to or slightly greater than the included angle θ4 of the second sealant, and the included angle θ2' of the second cover is equal to or slightly greater than the included angle θ4' of the second sealant. Based on this, in Figure 3F When the cover 23 is further attached to the second sealant layer 28, the surface profile of the resulting second sealant side 281 can be approximately the same as the surface profile of the cover 23 (e.g., the surface profile of its second cover side 232).

[0096] Please continue to refer to this. Figure 3FIn some embodiments, the upper surface 280 of the cured second sealant layer 28 is horizontal and parallel to the upper surface 200 of the substrate 20. In other embodiments, the upper surface 280 of the cured second sealant layer 28 is inclined, for example, the thickness of the second sealant layer 28 (i.e., as shown in the figure) Figure 3F The dimension in the Z direction decreases away from the cover 23. In some other embodiments, the upper surface 280 of the second sealant layer 28 is coplanar with the upper surface of the cover 23 (e.g., Figure 3F For example, the second sealant layer 28 and / or the cover 23 can be thinned by chemical mechanical polishing until the upper surface of the cover 23 is exposed to the upper surface 280 of the second sealant layer 28.

[0097] Please refer to Figure 2 A plurality of solder balls 210 are disposed on the lower surface 204 of the substrate 20, and the solder balls 210 are further arranged into a solder ball array 21. Each solder ball 210 can be electrically connected to at least one of the lower contact points 203 of the substrate 20. The material of the solder balls 210 can be various conductive metals, such as gold, silver, copper, tin, or any combination thereof. Thus, a structure is formed as shown in the image. Figure 2 Semiconductor packaging structure 2a.

[0098] The following is passed Figures 4A to 4C The preparation process of the cover 31 is illustrated by example.

[0099] Please refer to Figure 4A and Figure 4B , Figure 4A This is a cross-sectional structural diagram of a semi-finished cover 31 according to some embodiments; Figure 4B This is a cross-sectional structural diagram of the cover 31 in some embodiments. First, a cover material 30 is provided. The material selection of the cover material 30 is related to that of the cover 31 (e.g., Figure 3C The materials are the same, for example, the material of the cover material 30 and the cover 31 are both glass, and their light transmittance relative to visible light is greater than 90%. Next, a first cutting tool 34 is provided. The first cutting tool 34 has a lower surface (not shown) and a first cutting face 340. The lower surface of the first cutting tool 34 is connected to the first cutting face 340, and there is a first cutting angle (not shown) between the lower surface of the first cutting tool 34 and the first cutting face 340. In some embodiments, the first cutting angles on both sides of the first cutting tool 34 can be any angle, so as to be the same as the cover angles θ0 and θ0' on both sides of the corresponding cover 31 (e.g., Figure 3C For example, the included angles of the first cutter on both sides of the first cutter 34 are the same as the included angles of the corresponding cover, θ0 and θ0'. In some embodiments, the included angles of the first cutter on both sides of the first cutter 34 are the same as the included angles of the corresponding first sealing layer 27, θ3 and θ3' (e.g., ...). Figure 3DDuring the same operation time, the cover material 30 can be cut by one or more first tools 34 in a single or multi-stage manner to form the cover 31 (e.g., Figure 4B The aforementioned single-stage method refers to the process where the cover material 30 is formed into the cover 31 through only one cutting; for example, simultaneously using... Figure 4A The first cutters 34 on the left and right sides cut the cover material 30 to directly form such as Figure 4B The cover 31. The above-mentioned multi-stage method refers to the cover material 30 being cut multiple times to form the cover material 30. Figure 4B The cover 31; for example, first with such Figure 4A The first cutter 34 on the left cuts the raw material 30 of the cover, and then... Figure 4A The first cutter 34 on the right side cuts the cover material 30 to form such a shape. Figure 4B The cover 31.

[0100] Please continue to refer to this. Figure 4B The cut raw material 30 will form a cover 31 having a lower surface 310 and cover sides 311. The lower surface 310 and the cover sides 311 located on both sides of the cover 31 will have cover angles θ0 and θ0', respectively. The cover angles θ0 and θ0' can be the same or different angles. The specific implementation of the cover 31 can be referred to the aforementioned specific implementation, and will not be described in detail here.

[0101] Please refer to Figure 4C , Figure 4C This is a schematic cross-sectional view of the cover 31 in some embodiments. The first colloid 32 is further coated onto... Figure 4B The lower surface 310 of the cover 31 and the side surfaces 311 of the cover 31 located on both sides of the cover 31. The material and specific implementation of the first colloid 32 can be referred to the foregoing, and will not be described in detail here. Thus, a structure as shown can be formed. Figure 3B and Figure 3C The cover 31 and its first colloid 32.

[0102] The following is passed Figures 5A to 5D The preparation process of the cover 23 is illustrated illustratively.

[0103] Please refer to Figure 5A and Figure 5B , Figure 5A This is a cross-sectional structural diagram of a semi-finished cover 23 according to some embodiments; Figure 5B This is a cross-sectional structural diagram of a semi-finished cover 23 according to some embodiments. First, a cover material 40 is provided. The material selection of the cover material 40 is related to that of the cover 23 (e.g., Figure 3EThe materials are the same, for example, the materials of the cover material 40 and the cover 23 are both glass, and their light transmittance relative to visible light is greater than 90%. Next, a second cutter 41 is provided. The second cutter 41 has a lower surface (not shown) and a second cutting face 410. The lower surface of the second cutter 41 is connected to the second cutting face 410, and there is a second cutter angle (not shown) between the lower surface of the second cutter 41 and the second cutting face 410. In some embodiments, the second cutter angles on both sides of the second cutter 41 can be any angle, so as to be the same as the first cover angles θ1 and θ1' on both sides of the corresponding cover 23 (e.g., Figure 3E For example, the included angles of the second cutter on both sides of the second cutter 41 are the same as the included angles of the corresponding first cover, θ1 and θ1'. In some embodiments, the included angles of the second cutter on both sides of the second cutter 41 are the same as the included angles of the corresponding first sealant layer 27, θ3 and θ3' (e.g., ...). Figure 3E During the same operation time, the cover material 40 can be cut by one or more second tools 41 in a single or multi-stage manner to form the cover 23 (e.g., ...). Figure 6 ) or its semi-finished products (such as Figure 5B The aforementioned single-stage method refers to the process where the cap material 40 is formed through only one cutting operation. Figure 6 The cover 23 (details to follow) or as Figure 5B Semi-finished products; for example, synchronously as Figure 5A The second cutters 41 on the left and right sides cut the cover material 40 to form such a shape. Figure 6 The cover 23 or such Figure 5B The semi-finished product. The above-mentioned multi-stage method refers to the process where the cover material 40 is cut multiple times to form a semi-finished product. Figure 5D or Figure 6 The cover 23 (details to follow); for example, first as follows Figure 5A The second cutter 41 on the left side cuts the cover material 40, and then... Figure 5A The second cutter 41 on the right side cuts the cover material 40 to form such a shape. Figure 6 The cover 23 or such Figure 5B Semi-finished products.

[0104] Please refer to Figure 5B The raw material 40 for the cover, after being cut by the second cutter 41, will form the cover 23 or its semi-finished product. For example, such as Figure 5B The semi-finished cover 23 has a lower surface 230 and a first cover side 231. The lower surface 230 and the first cover side 231 located on both sides of the semi-finished cover 23 have first cover angles θ1 and θ1', respectively. The two first cover angles θ1 and θ1' can be the same or different angles. The specific implementation of the cover 23 and its semi-finished product can be referred to the aforementioned specific implementation, and will not be described in detail here.

[0105] Please continue to refer to this. Figure 5C , Figure 5C This is a cross-sectional structural diagram of a semi-finished cover 23 according to some embodiments. A third cutting tool 42 is also provided. The third cutting tool 42 has a lower surface (not shown) and a third cutting face 420. The lower surface of the third cutting tool 42 is connected to the third cutting face 420, and a third cutting angle (not shown) exists between the lower surface of the third cutting tool 42 and the third cutting face 420. In some embodiments, the third cutting angles on both sides of the third cutting tool 42 can be arbitrary angles, respectively the same as the second cover angles θ2 and θ2' on the corresponding sides of the cover 23 (e.g., ...). Figure 3F For example, the included angles of the third cutter 42 on both sides are the same as the corresponding included angles θ2 and θ2' of the second cover. In the same operation time, the semi-finished cover 23 can be cut by one or more third cutters 42 in a single or multi-stage manner to form the cover 23 (e.g., ...). Figure 5D or Figure 6 The aforementioned single-stage method refers to the process where the semi-finished cover 23 is formed by only one cutting operation. Figure 5D or Figure 6 The cover 23 (details to follow); for example, synchronization as... Figure 5C The third cutter 42 on the left and right sides cuts as follows Figure 5B The semi-finished product of the cover 23 is directly formed as... Figure 6 The cover 23. The above-mentioned multi-stage method refers to the process where the semi-finished cover 23 is cut multiple times to form the shape shown above. Figure 5D or Figure 6 The cover 23 (details to follow); for example, first as follows Figure 5C The third cutter on the left, 42, cuts as follows Figure 5B The semi-finished product of the cover body 23, and then as follows Figure 5C The third cutter on the right, 42, cuts as follows Figure 5B The semi-finished product of the cover 23, to form as Figure 5D or Figure 6 23. Cover body.

[0106] Please continue to refer to this. Figure 5D , Figure 5D This is a cross-sectional structural diagram of the cover 23 in some embodiments. The semi-finished cover 23, after being cut by the third cutter 42, will form a cover 23 having a lower surface 230 and a second cover side surface 232, and as shown... Figure 5D The lower surface 230 of the cover 23 (e.g., a virtual plane or dashed line parallel to the lower surface 230) and the second cover side surfaces 232 located on both sides of the cover 23 have second cover angles θ2 and θ2', respectively. The two second cover angles θ2 and θ2' can be the same or different angles, and the two second cover angles θ2 and θ2' are both less than or equal to the first cover angles θ1 and θ1', respectively. In some embodiments, such as Figure 5C and Figure 5DThe angle between the lower surface of the third cutter 42 and the third cutting face 420 is 90 degrees. Therefore, after the cover 23 is cut by the third cutter 42 (which has 90-degree angles on both sides), the second cover angles θ2 and θ2' on both sides of the cover 23 are also 90 degrees. The specific implementation of the cover 23 can be referred to the aforementioned specific implementation, and will not be detailed here. Thus, a cover as shown in the image is formed. Figure 2 or Figure 6 23. Cover body.

[0107] Please refer to Figure 2 , Figure 6 and Figure 7 , Figure 6 This is a cross-sectional view of the semiconductor packaging structure 2b in the second embodiment; Figure 7 This is a schematic cross-sectional view of the cover 23 in some embodiments. Compared to... Figure 2 Semiconductor packaging structure 2a, such as Figure 6 The main difference in the semiconductor package structure 2b lies, for example, in the angular configuration between the second cover side 232 and the first cover side 231. For instance, the included angles θ2 and θ2' of the second cover in the semiconductor package structure 2b can be greater than 90 degrees (e.g., ...). Figure 7 For example, in Figure 6 and Figure 7 The included angles θ2 and θ2' of the second cover (e.g.) Figure 7 Both are greater than 90 degrees, and the included angle between the second cover side 232 and the first cover side 231 is approximately 180 degrees. Therefore, there is no significant step difference between the second cover side 232 and the first cover side 231 (e.g., Figure 6 In some embodiments, such as Figure 6 The first cover angle θ1 is equal to the second cover angle θ2 (and / or the first cover angle θ1' is equal to the second cover angle θ2'), so as to form a cover 23 side surface without a significant step difference between the first cover side surface 231 and the second cover side surface 232. In other embodiments, such as Figure 7 The included angle θ1 of the first cover is not equal to the included angle θ2 of the second cover (and / or the included angle θ1' of the first cover is not equal to the included angle θ2' of the second cover), so as to form a cover 23 side surface with a step difference between the first cover side surface 231 and the second cover side surface 232; for example, in Figure 7 The included angle θ1 of the first cover is greater than the included angle θ2 of the second cover, and the included angle θ1' of the first cover is greater than the included angle θ2' of the second cover.

[0108] In summary, in some embodiments, by providing a cover with at least one inclined surface (such as the aforementioned first cover side) on the active surface of the image sensing chip, a gas chamber is defined by the cover, the active surface of the image sensing chip, and the encapsulating layer (such as the aforementioned first encapsulating layer). The light transmission path within the cover is altered by the reflection of the at least one inclined surface, thereby reducing the probability of light transmission into the gas chamber and avoiding unnecessary interference caused by light traveling back and forth within the gas chamber, such as glare. In other words, the semiconductor packaging structure according to some embodiments can effectively solve the glare phenomenon known to the inventors of this invention. Meanwhile, in some embodiments, since it is unnecessary to provide an intermediary and / or shielding layer between the cover and the active surface of the image sensing chip, both the process time and cost required for providing the intermediary and / or shielding layer can be saved, and unnecessary glare can be effectively avoided.

[0109] Although the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention shall be determined by the scope of the claims appended to this specification.

Claims

1. A semiconductor packaging structure, characterized in that, Include: A substrate has an upper surface, a lower surface, and traces located between the upper surface and the lower surface. The upper surface of the substrate has a plurality of upper contact points, and the lower surface of the substrate has a plurality of lower contact points. The upper contact points are electrically connected to the lower contact points through the traces. An image sensing chip is located on the upper surface of the substrate; Multiple metal lines, one end of each metal line being electrically connected to the image sensing chip, and the other end of each metal line being electrically connected to the upper contact points of the substrate; A cover has a lower surface and a first cover side surface, wherein the lower surface of the cover is connected to the first cover side surface, and a first cover angle is formed between the lower surface of the cover and the first cover side surface, wherein the first cover angle is greater than 90 degrees. A first encapsulating layer laterally encapsulates the substrate, the metal lines, the image sensor chip, and the cover, exposing a portion of the upper surface of the image sensor chip. An air chamber is defined between the first encapsulating layer, the lower surface of the cover, and the exposed portion of the upper surface of the image sensor chip. The solder ball array comprises a plurality of solder balls, each of which is individually electrically connected to the lower contact points of the substrate.

2. The semiconductor packaging structure as described in claim 1, characterized in that, The cover also has a second cover side, which is connected to the first cover side, and the lower surface of the cover and the second cover side have a second cover angle, which is less than or equal to the first cover angle.

3. The semiconductor packaging structure as described in claim 2, characterized in that, It also includes a second sealant layer, which is located on the first sealant layer and laterally encapsulates the cover.

4. The semiconductor packaging structure as described in claim 3, characterized in that, The second sealant layer laterally encapsulates the side of the second cover, and the first sealant layer laterally encapsulates the side of the first cover.

5. The semiconductor packaging structure as described in claim 1, characterized in that, The cover also has a second cover side, which is connected to the first cover side, and the lower surface of the cover and the second cover side have a second cover angle, which is equal to 90 degrees.

6. The semiconductor packaging structure as described in claim 5, characterized in that, It also includes a second sealant layer, which is located on the first sealant layer and laterally encapsulates the cover.

7. The semiconductor packaging structure as described in claim 6, characterized in that, The second sealant layer laterally encapsulates the side of the second cover, and the first sealant layer laterally encapsulates the side of the first cover.

8. The semiconductor packaging structure as described in claim 1, characterized in that, It also includes a second sealant layer, which is located on the first sealant layer and laterally encapsulates the cover.

9. The semiconductor packaging structure as described in claim 1, characterized in that, The cover has two opposing sides in a cross section, each of the two sides having a first cover side surface. The lower surface of the cover on each of the two sides has a first cover angle with the corresponding first cover side surface, and the first cover angles on the two sides are different.

10. The semiconductor packaging structure as described in claim 1, characterized in that, The cover has two opposite sides in a cross section, each of the two sides having a first cover side surface. The lower surface of the cover on each of the two sides has a first cover angle with the corresponding first cover side surface, and the first cover angles on the two sides are the same.

11. The semiconductor packaging structure as described in claim 9 or 10, characterized in that, In the cross section, each of the two sides of the cover also has a second cover side, and the second cover side on each side is connected to the corresponding first cover side. The lower surface of the cover has a second cover angle with the corresponding second cover side, and the second cover angles on the two sides are different.

12. The semiconductor packaging structure as described in claim 9 or 10, characterized in that, In the cross section, each of the two sides of the cover also has a second cover side surface, the second cover side surface on each side is respectively connected to the corresponding first cover side surface, the lower surface of the cover has a second cover angle with the corresponding second cover side surface, and the second cover angle on both sides is the same.

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