General purpose input / output (GPIO) power supply acquisition

Abstract

Systems and methods described herein correspond to power supply acquisition operations. The power management circuit (170) may receive a supply voltage from other power management circuits (152). The supply voltage may be a supply drawn from other power management circuitry (152). Further, some of the power management circuits (152) may operate as a controller power management circuit (152) to supply the supply voltage via the one or more rails, and some of the power management circuits (170) may operate as a leaf power management circuit (170) to draw the supply voltage from the one or more rails. The leaf power management circuit (170) may not include a regulator (156), thereby enabling the leaf power management circuit (170) to enter a mode of lower power than previously enabled when including the regulator (156).

Description

Background Technology

[0001] This disclosure relates to systems and methods for power management circuitry of semiconductor devices, and more particularly to general purpose inputs / outputs (GPIOs) of such power management circuitry.

[0002] Integrated circuits are found in a wide range of electronic devices, including computers, handheld devices, wearable devices, vehicles, and robots. Electronic devices can operate in various modes, such as always-on display mode, power-off mode, and normal mode. In some systems, circuit blocks designed to perform various functions can be designed to operate at different power supply levels. Power management circuitry can be included in such systems to generate and monitor varying power supply levels at power supply nodes for different circuit blocks.

[0003] Power management circuitry sometimes includes one or more power converter circuits that generate a regulated voltage level for a corresponding power supply signal based on the voltage level of the input supply signal. Such regulator circuits can employ different operations to regulate the voltage level of power nodes. For example, the power converter can be a switching regulator, a linear regulator, or another suitable regulator. However, operating these power circuits in different modes may result in one or more power converters being de-energized, which could cause general-purpose input / output (GPIO) circuitry to lose bias and / or cease operating in a blocking state. Summary of the Invention

[0004] A computer system may include multiple circuits for performing specific operations. These circuits may be fabricated on one or more substrates and may employ different supply voltage levels. A power management unit (PMU) may include multiple power converter circuits that generate regulated voltage levels for various supply signals. Such power converter circuits may be designed to maintain a constant voltage based on changes in input voltage or circuit load. As part of this operation, the PMU may include interfaces, such as general purpose inputs / outputs (IOs) that may include one or more pins, where corresponding GPIO pins may be programmed into input or output terminals. To program a GPIO pin as an input, the GPIO pin may be set to a high-impedance state (e.g., a higher impedance state, corresponding to an impedance greater than a threshold impedance), which enables sensing whether the voltage on the GPIO pin is considered a high voltage level (e.g., a "1" bit, a high logic value) or a low voltage level (e.g., a "0" bit, a low logic value). The high-impedance state may correspond to an impedance of an appropriate value (e.g., at least a threshold impedance) to prevent unwanted or unintended signals from being received via the GPIO pin (and propagating through connected circuitry).

[0005] Although the power converter circuit can maintain a constant voltage output, electronic devices can operate in various operating modes, such as always-on display mode, power-off mode, reduced power mode, and normal mode. These different operating modes may consume different amounts of power, which may cause the power converter circuit to change its operation to supply power to the circuit when in various operating modes. In fact, the PMU's GPIO can send or receive control signals, status, indications of events, etc., to transmit transitions between different operating modes, to perform test or debugging operations, etc.

[0006] In one example of a reduced power mode, the integrated circuit can operate in a hold mode. Hold mode can be used to maintain the state of one or more memory devices and / or memory caches, preserve the state, continue providing an always-on display, or continue other operations that correspond to an "auto-run" mode, which allows one or more circuits to be turned off while functionality or applications continue to be provided to the user. Similar to a power-down mode, the PMU of an electronic device can stop supplying power to one or more parts of the electronic device when operating in hold mode. However, hold mode differs from power-down mode in that a system interrupt can be generated to exit hold mode, while a system interrupt can be used to exit power-down mode (e.g., no interrupt is generated when electronic device 10 is in power-down mode).

[0007] With this in mind, entering hold mode may require disconnecting power to the regulators associated with the PMU, such as linear or low-dropout regulators (LDOs). When the regulator is de-energized, the GPIO may lose bias on its well and gate (e.g., well terminal, gate terminal). When this is lost, the GPIO may no longer hold at high impedance. Instead, the GPIO may transition to a low-impedance state, which allows unintended signals to propagate to the integrated circuit and corrupt data on the associated GPIO interface bus. In fact, when the GPIO is not in a high-impedance blocking state, signals received via the GPIO may no longer be blocked by high impedance, thus affecting chip functionality and reducing integrated circuit reliability.

[0008] Systems and methods that maintain GPIO in a high-impedance state while enabling integrated circuits to operate in a reduced-power mode are desirable. As described herein, such systems and methods may include power acquisition operations. For example, one or more PMUs may receive a supply voltage from one or more other PMUs. This supply voltage may be a power supply obtained from the one or more other PMUs. Furthermore, in some systems, one or more PMUs may operate as controller PMUs to supply a supply voltage via one or more rails, and one or more PMUs may operate as leaf PMUs to obtain a supply voltage from the one or more rails. In some systems, the respective PMUs may not switch between acquisition mode and controller mode. For a first PMU that obtains a supply voltage from a second PMU, one or more regulators of the first PMU may be disconnected from the power supply, while one or more regulators of the second PMU may remain powered on. The first PMU disconnected from the power supply may maintain a high-impedance state on the GPIO set on the first PMU because it continues to receive a supply voltage from at least one regulator of the second PMU. Attached Figure Description

[0009] A better understanding of the various aspects of this disclosure can be achieved by reading the following detailed description and referring to the accompanying drawings.

[0010] Figure 1 It is a schematic block diagram of an electronic device according to the implementation plan;

[0011] Figure 2 It is based on the implementation plan. Figure 1 A front view of a mobile phone, an example of an electronic device;

[0012] Figure 3 It is based on the implementation plan. Figure 1 A front view of a tablet device, an example of an electronic device;

[0013] Figure 4 It is based on the implementation plan. Figure 1 A front view of a laptop computer, an example of an electronic device;

[0014] Figure 5 It is based on the implementation plan. Figure 1 Front and side views of an example watch, an electronic device;

[0015] Figure 6 This is a schematic diagram illustrating the operation of an integrated circuit associated with exiting a holding mode (e.g., example, reduced power mode) according to an implementation scheme.

[0016] Figure 7This is a block diagram of a leaf power management unit (PMU) according to an implementation scheme, which is operable to obtain a supply voltage from a controller PMU based on a first coupling when in hold mode;

[0017] Figure 8 It is a timing diagram of the signal states associated with the implementation scheme and the hold mode;

[0018] Figure 9 This is a block diagram of a leaf PMU according to the implementation scheme, which is operable to obtain a supply voltage from a controller PMU based on a second coupling when in hold mode;

[0019] Figure 10 This is a block diagram of a leaf PMU according to the implementation scheme, which is operable to obtain supply voltage from the controller PMU via a third coupling when in hold mode; and

[0020] Figure 11 It is a block diagram of multiple leaf PMUs according to the implementation scheme, which are operable to obtain supply voltage from a first type of controller PMU and a second type of controller PMU based on a fourth coupling when in hold mode. Detailed Implementation

[0021] When describing elements of various embodiments of this disclosure, the articles “a,” “an,” and “the” are intended to mean one or more elements present in the elements. The terms “comprising” and “having” are intended to be included and to mean that additional elements may be present in addition to the listed elements. Additionally, it should be understood that references to “some embodiments,” “implementation,” “an embodiment,” or “an embodiment” in this disclosure are not intended to be construed as excluding the existence of additional embodiments also incorporating the cited features. Furthermore, the phrase A “based on” B is intended to mean that A is at least partially based on B. Moreover, the term “or” is intended to be inclusive (e.g., logical OR) and not exclusive (e.g., logical XOR). In other words, the phrase A “or” B is intended to mean A, B, or both A and B.

[0022] This disclosure relates to an electronic device including a power management unit (PMU). The electronic device 10 can be any suitable electronic device, such as a computer, mobile phone, portable media device, tablet computer, television, virtual reality headset, wearable device (such as a watch), vehicle and / or vehicle dashboard, etc. Figure 1 This is intended to represent an example of a particular implementation and to illustrate the types of components that may be present in electronic device 10.

[0023] Figure 1The electronic device 10 includes an electronic display 12, one or more input devices 14, one or more input / output (I / O) ports 16, a processor core complex 18 having one or more processors or processor cores, local memory 20, main memory storage device 22, network interface 24, power supply 26 (e.g., power supply unit), and power management unit (PMU) 28. Figure 1 The various components described herein may include hardware elements (e.g., circuitry), software elements (e.g., a tangible, non-transitory computer-readable medium storing executable instructions), or a combination of both hardware and software elements. It should be noted that the various depicted components may be combined into fewer components or separated into additional components. For example, local memory 20 and main memory storage device 22 may be included in a single component.

[0024] The processor core complex 18 is operatively coupled to local memory 20 and main memory storage device 22. Therefore, the processor core complex 18 can execute instructions stored in local memory 20 or main memory storage device 22 to perform operations such as generating and / or transmitting image data for display on electronic display 12. Thus, the processor core complex 18 may include one or more general-purpose microprocessors, one or more application-specific integrated circuits (ASICs), one or more field-programmable gate arrays (FPGAs), or any combination thereof.

[0025] In addition to program instructions, local memory 20 or main memory storage device 22 may store data to be processed by processor core complex 18. Therefore, local memory 20 and / or main memory storage device 22 may include one or more tangible, non-transitory computer-readable media. For example, local memory 20 may include random access memory (RAM), and main memory storage device 22 may include read-only memory (ROM), rewritable non-volatile memory such as flash memory, hard disk drive, optical disk, etc.

[0026] Network interface 24 can transmit data with another electronic device or network. For example, network interface 24 (e.g., a radio frequency system) can enable electronic device 10 to communicatively couple to a personal area network (PAN) (such as a Bluetooth network), a local area network (LAN) (such as an 802.11x Wi-Fi network), and / or a wide area network (WAN) (such as a 4G, LTE, or 5G cellular network). Power supply 26 can provide power to one or more components in electronic device 10, such as processor core complex 18 or electronic display 12. Therefore, power supply 26 can include any suitable energy source, such as a rechargeable lithium polymer (Li-poly) battery or an alternating current (AC) power converter. One or more PMUs 28 can help distribute power to various circuits of electronic device 10. Although multiple PMUs 28 may be described herein, for ease of description, these multiple PMUs 28 may sometimes be referred to as PMU 28 herein. Some of the descriptions included herein are applicable to systems having one PMU and / or systems having multiple PMUs. In addition, PMU 28 may include components that are different from each other; for example, some PMU 28 may include regulators while others may not include regulators, as further described herein.

[0027] I / O port 16 enables electronic device 10 to interface with other electronic devices. For example, when a portable storage device is connected, I / O port 16 enables processor core complex 18 to transfer data with the portable storage device. Input device 14 can enable user interaction with electronic device 10, for example, by receiving user input via buttons, keyboard, mouse, touchpad, touch sensor, etc. Input device 14 may include touch sensing components (e.g., touch control circuitry, touch sensing circuitry) in electronic display 12. Touch sensing components can receive user input by detecting the occurrence of an object touching the surface of electronic display 12 or the location of the object touching the surface of the electronic display.

[0028] The electronic device 10 can take any suitable form. Figure 2 An example of an electronic device 10 is shown, which takes the form of a handheld device 10A. The handheld device 10A can be a portable phone, media player, personal data manager, handheld gaming platform, etc. For illustrative purposes, the handheld device 10A can be a smartphone, such as any iPhone available from Apple Inc. ® model.

[0029] The handheld device 10A includes a housing 30 (e.g., a casing). The housing 30 protects internal components from physical damage or shields them from electromagnetic interference, such as by surrounding the electronic display 12. The electronic display 12 can display a graphical user interface (GUI) 32 with an array of icons. When an icon 34 is selected via the input device 14 or a touch-sensing component of the electronic display 12, an application can be launched.

[0030] The input device 14 can be accessed through an opening in the housing 30. The input device 14 enables the user to interact with the handheld device 10A. For example, the input device 14 enables the user to activate or deactivate the handheld device 10A, navigate the user interface to the home screen, navigate the user interface to a user-configurable application screen, activate voice recognition feature structures, provide volume control, or switch between vibration and ring modes.

[0031] Figure 3 Another example of a suitable electronic device 10 is shown, specifically a tablet device 10B. The tablet device 10B can be any iPad available from Apple Inc. ® model. Figure 4 Another example of a suitable electronic device 10 is shown, specifically a computer 10C. For illustrative purposes, computer 10C could be any MacBook available from Apple Inc. ® or IMAC ® model. Figure 5 Another example of a suitable electronic device 10 is shown, specifically a watch 10D. For illustrative purposes, the watch 10D can be any Apple Watch available from Apple Inc. ® Model. As depicted, the tablet device 10B, computer 10C, and watch 10D each also include an electronic display 12, an input device 14, an I / O port 16, and a housing 30. The electronic display 12 can display a GUI 32. Here, the GUI 32 displays a visualization of a clock. When the visualization is selected via the input device 14 or the touch-sensitive component of the electronic display 12, an application can be launched, such as transforming the GUI 32 into a presentation. Figure 2 and Figure 3 Icon 34 is discussed in the text.

[0032] Return to reference Figure 1 The circuitry of electronic device 10 (such as...) Figure 1The circuits illustrated may be fabricated on one or more substrates and may employ different power supply 26 voltage levels. The PMU 28 may control and / or monitor the signals supplying power from the power supply 26, which may be based on one or more voltage regulator circuits that generate regulated voltage levels to be supplied to various circuits of the electronic device 10. For example, the PMU 28 may adjust the power supplied to one or more domains (such as analog domains, digital domains, etc.). The PMU 28 may adjust the voltage levels based on the operating mode indicated by the processor core complex 18 and / or based on the expected or desired energy consumption levels of one or more different components or systems of the electronic device 10.

[0033] Such voltage regulator circuits can employ both passive circuit elements (e.g., inductors, capacitors) and active circuit elements (e.g., transistors, diodes). Different types of voltage regulator circuits can be used based on the power requirements of the load circuit, available circuit area, etc. One type of voltage regulator circuit is a buck converter circuit (e.g., a buck regulator), such as... Figures 8 to 10 The buck regulator described and discussed herein. Other regulators may be used.

[0034] In view of the foregoing, during the operation of the electronic device 10, the electronic device 10 may enter a hold mode. Figure 6 This is timing diagram 50 for operations 52 to 88 performed within time t0 to t7 associated with the hold mode of electronic device 10. This document describes example operations in conjunction with the hold mode. In actual implementations of the system, one or more of these operations may be adjusted or omitted based on the specific configuration and / or use of the system.

[0035] The hold mode can typically be an operating mode in which the analog and digital domains of electronic device 10 are disconnected from power supply 26. The analog domain can refer to the analog circuitry of electronic device 10 and / or one or more portions of the analog circuitry of electronic device 10. The digital domain can refer to the digital circuitry of electronic device 10 and / or one or more portions of the digital circuitry of electronic device 10. The analog domain can be powered solely by PMU 28 because the analog domain may have different voltage and / or current requirements relative to the digital domain. Disconnecting the analog and / or digital domains from power supply 26 reduces the amount of energy consumed by electronic device 10 compared to the amount of energy consumed in one or more other operating modes, such as normal operating mode. For example, in normal operating mode, the analog and digital domains can be connected to power supply 26. The hold mode can correspond to a duration between: t0, when power is attached to PMU 28; and time t3, when PMU 28 generates an "analog domain power-on" event to enable the analog domain. It should be noted that an event such as the “analog domain power-on” event or one of the other events described herein may correspond to an interruption that can wake up or change the operating mode of one or more circuits receiving the event.

[0036] At block 52 and at time t0, power supply 26 may be attached to PMU 28, where attachment refers to an electrical coupling that enables power supply 26 to be electrically connected to and supply power to PMU 28. In response, at block 54 and at time t1, the analog domain may provide a flag and / or event even if the analog domain is not fully powered on. In practice, power supply 26 attached to PMU 28 may power on a comparator associated with the VDD_MAIN voltage rail (e.g., the main power rail associated with the analog domain). The analog domain may provide a flag and / or event in response to the VDD_MAIN voltage rail reaching a threshold voltage level. At block 56 and at time t2, in response to the main power supply power-on, another flag may be generated by the analog domain, thereby powering on the reference generator. The operation of block 58 may be associated with enabling the analog and digital domains powered by PMU 28. In practice, at block 60, the digital logic of electronic device 10 may provide a RESET signal at block 62. The RESET signal of block 62 may correspond to Figure 8 The RESET_L signal is 112.

[0037] In response to the RESET signal, at block 62, PMU 28 can generate an "Analog Domain Power-On" event, which enables main power supply undervoltage lockout (UVLO) at block 64, enables the analog domain at block 66, and enables the digital domain at block 68. In practice, digital logic coupled to or associated with PMU 28 can enable the analog and / or digital domains in response to the "Analog Domain Power-On" event from PMU 28. The digital logic referred to herein (e.g., blocks 60, 66) can be located on or as part of the chip logic. The logic used to drive the Reset_L pin can be located separately from the chip logic. UVLO prevents the integrated circuit from being used at voltages lower than the specification voltage associated with the integrated circuit, which can be beneficial in protecting the integrated circuit from malware attacks or accidental operation. Enabling the analog domain can correspond to enabling the analog domain regulator (e.g., LDO) of the digital logic to initiate power supply to the analog domain circuitry. Figure 8 The VDD_ANA signal 108 can supply voltage to the analog domain. A VDD_ANA signal 108 with a voltage greater than or equal to a voltage threshold level of 146A can enable the analog domain. Enabling the digital domain can correspond to enabling a digital logic regulator (e.g., LDO) associated with the PMU 28 to initiate power supply to the circuitry in the digital domain. Figure 8 The VDD_DIG signal 110 can supply voltage to the digital domain. A VDD_DIG signal 110 with a voltage greater than or equal to a voltage threshold level 146B enables the digital domain. In practice, the digital domain supply voltage (e.g., VDD_DIG signal 110) can be generated from VDD_MAIN by another regulator. The voltage provided by this regulator can be substantially equal to the VDD_ANA voltage (e.g., as shown in the image). Figure 7 As illustrated, or by a negligible amount (e.g., 1% deviation or other threshold deviation), can be equal to an additional regulator powered on after the VDD_ANA regulator that generates a digital domain voltage, which may have different voltage values ​​(e.g., as shown). Figure 9 exemplified).

[0038] Further detailing the example relationship between boxes 64, 66, and 68: A digital domain can be enabled at box 68, where the VDD_ANA voltage is triggered in response to the VDD_MAIN_OK signal generated by the operation of box 54, which indicates that the VDD_MAIN power rail is supplying a threshold voltage level (e.g., Figure 8 The voltage level 120, or any suitable threshold voltage for the electronic device 10. As indicated above, the VDD_ANA voltage can be supplied based on the operation of block 66. Additionally, in response to logic detection that the bandgap has reached the threshold voltage difference (which can be obtained from...), the voltage level 120 can be supplied. Figure 8The VREF_0V6 signal (indicated by 106) enables the digital field at box 68. In some systems, such as... Figure 9 The systems described herein can enable the digital domain at block 68 based on power supplied from a second LDO, which can be triggered in response to operation at block 54 based on a first LDO associated with the analog domain (e.g., power-on based on operation at block 66). The first LDO can be triggered by the VDD_MAIN_OK signal described above. Alternatively, it can be triggered in response to logic detection that the bandgap has reached a threshold voltage difference (which can be triggered by...). Figure 8 The VREF_0V6 signal (106 indication) is used to enable the first LDO.

[0039] At box 70, the analog domain may respond to determining the regulator (e.g., LDO) of the analog domain, the regulator (e.g., LDO) of the digital domain, and / or the power supply rail (e.g., Figure 7 The PMU 28 provides a flag and / or event upon VDDIO1V2_AON being ready. In some systems, the PMU 28 may generate flags and / or events opposite to those in the analog domain, such as in response to detecting that the analog domain, digital domain, and power rails are supplied with a threshold amount of voltage, current, and / or power. In either case, a flag and / or event may be generated based on a voltage comparison with a threshold performed using one or more comparators to indicate that the regulators in the analog domain, digital domain, and / or power rails are supplying an appropriate voltage level. In response to this flag or event, at block 72, the PMU 28 may generate a “voltage ready” event for triggering at time t4. At block 74, the PMU 28 and / or electronics 10 may continue to perform additional startup operations to enter a power-on mode and / or perform other operations.

[0040] For example, at block 76, in response to the PMU 28 generating a “voltage ready” event, digital logic can provide a clock, such as an auxiliary clock, for operating one or more circuits of electronic device 10. The digital logic can be associated with a digital domain, PMU 28, etc. At block 78, PMU 28 can generate a “power-on reset digital logic” event, which can trigger a finite state machine (FSM) to advance to the state corresponding to the “power-on reset digital logic” event. In response to the “power-on reset digital logic” event, at block 80, the digital logic can enable one or more input / output (IO) devices, such as the GPIO of PMU 28. Furthermore, in response to the “power-on reset digital logic” event, at block 84, at time t5, the digital logic can provide a master clock for electronic device 10. At block 86, master clock activation can trigger PMU 28 to generate an event to allow processing operations of electronic device 10 to continue (e.g., based on the enabled master clock). At a later time, at box 88, PMU 28 may generate another event to cause electronic device 10 to set a timer and enter a power-reducing mode, such as a hold mode. The timer may be set to expire at time t7 near time t6. The power-reducing mode may end when the timer expires (e.g., at time t7), thereby causing PMU 28 to wake up again at box 90. In some cases, timer expiration allows the power-reducing mode to end in response to the finite state machine and / or when PMU 28 receives an interrupt. Box 90 may correspond to the finite state machine transitioning from power-reducing mode to a "wake-up" state.

[0041] As noted above, at box 88, electronic device 10 can enter a reduced power mode corresponding to the hold mode. The hold mode is similar to the power-off mode in that PMU 28 can stop supplying power to one or more parts of electronic device 10, but the difference is that a system interrupt can be generated to exit the hold mode (e.g., an interrupt can be not generated to wake up electronic device 10 when in power-off mode). The hold mode can be used to maintain one or more memory states and / or memory caches, maintain a state, continue providing an always-on display, or continue other operations corresponding to the "auto-run" mode, which allows one or more circuits to be turned off. In some cases, the circuits include analog and / or digital domains. To consume less power when power to a domain is cut off in hold mode, it may be desirable to turn off the regulator of PMU 28 that supplies power to that domain (e.g., disconnect the power supply to the regulator or eliminate the regulator). In some cases, the regulator is a linear regulator, low-dropout regulator (LDO), buck regulator, etc., associated with the power management operation of PMU 28. When the regulator stops receiving power from power supply 26, the bias of the general purpose input / output (GPIO) of PMU 28 may be lost, as described above, which may be undesirable. In fact, under these conditions, when the GPIO is not in a blocking state, unexpected signal spikes may be received at the GPIO, and these unexpected signal spikes may propagate to one or more parts of the electronic device 10. When the GPIO is not a secure GPIO, activity on the rail may not be blocked unless the GPIO is in a blocking state, such as having a bias on its gate and well voltages and / or the GPIO pin is pulled to a logic high level (e.g., "1"). Furthermore, when the regulator is removed from the design of PMU 28, there may be no alternative in the design to continue supplying power to the GPIO of PMU 28 to maintain the pin blocking state (e.g., bias, high impedance (Hi-Z), threshold impedance). To address this issue, a supply voltage can be obtained to maintain the blocking state of the GPIO pin. See below for reference. Figures 7 to 11 Describe the power acquisition and additional systems and methods.

[0042] In fact, Figure 7 This is a block diagram of leaf PMU 28 (e.g., leaf PMU 154), which is operable to obtain a supply voltage from controller PMU 28 (e.g., controller PMU 152) based on a first coupling when in hold mode.

[0043] In this system, leaf PMU 154 obtains two voltage supplies from leader PMU 152—one from a first always-on (AON) power rail and the other from a second always-on (AON) power rail. These two power rails can supply voltage to one or more leaf PMUs 28 during hold mode. When leaf PMU 154 is in hold mode, the GPIOs may not function, but may remain biased at a higher impedance state. In this way, if any communication occurs on the GPIO interface, the input pins used to turn off the leaf PMUs may not interfere with communication that might occur on the shared GPIO bus.

[0044] The first AON voltage supply comes from the VDDIO1V2_AON pin, which provides the first voltage on its connected rail. This first voltage can correspond to 9 volts (V), a voltage between 8V and 10V, a voltage greater than 5V, etc. In fact, although this pin is referred to herein as the "VDDIO1V2_AON pin," it should be understood that, as the name suggests, any suitable voltage, not just 1.2V, can be supplied via this pin. The voltage supplied via the VDDIO1V2_AON pin can correspond to the always-on regulator output from the leader PMU 152. Therefore, voltage can be supplied from the always-on regulator to the VDDIO1V2_AON pin via the rail. The VDDIO1V2_AON pin can also be grounded via capacitor 160C. The always-on regulator can be an always-on LDO. The always-on regulator may sometimes be used when PMU 28 is decoupled from power supply 26 (e.g., in…). Figure 6 The VDDIO1V2_AON pin is turned off and thus powered down before the operation of box 52. The VDDIO1V2_AON pin can supply voltage to the GPIOs of PMU 152 and 154, and can therefore generally be regarded as the logic level used by the GPIO when determining whether the received signal is a high logic voltage value or a low logic voltage value.

[0045] The second voltage supply originates from the VDDIO_AON pin, which provides a second voltage on its connected rail and can be grounded via capacitor 160D. Although referred to as the "second voltage supply," the VDDIO_AON voltage supply is established before the "first voltage supply" (e.g., the VDDIO1V2_AON pin). In this way, the first voltage supply can be based on the second voltage supply, as the second voltage supply powers the always-on regulator. The second voltage can correspond to 1.5V, a voltage between 1V and 2V, a voltage greater than 1V but less than 3V, etc. The first voltage can be 6 times the second voltage (e.g., V1 = 6 * V2) or another suitable integer multiple. The second voltage supply can correspond to a subdomain of digital logic, which can power the control of GPIOs used for PMU 152, 154. In some cases, the control supply for GPIOs can correspond to a logic high voltage level. The logic low voltage level can be a voltage less than 1.5V, such as 0.7V, a voltage between 0.5V and 1V, or any suitable value. In some systems, the voltage VDD_ANA supplied to the analog domain can be the same as the voltage supplied to the digital domain (e.g., Figure 8 The VDD_DIG described is the same, and therefore there may only be one always-on logic power rail shared between the analog and digital domains, such as Figure 7 As shown. Each of the VDDIO_AON, VDD_ANA, and VLDOINT pins is connected to the same VLDOINT pin, which enables the voltages and / or circuitry coupled to those pins to be internally and externally coupled to each other. Therefore, each of these connected pins is grounded via the same capacitor 160D on the controller PMU 152.

[0046] In leaf PMU 154, the VDDIO_AON pin supplies power from controller PMU 152. Additionally, in leaf PMU 154, the VDD_ANA and VLDOINT pins are coupled to receive power from the internal regulator 156A of controller PMU 152. This allows the internal regulator 156B to be shut down during hold mode (and in some cases, normal operating mode), further reducing power consumption, at least during hold mode, since the voltage supply is shared among the individual PMUs 152 and 154. In leaf PMU 154, the VDD_ANA pin is coupled to the VLDOINT pin and is grounded via capacitor 160E.

[0047] When with Figure 7 and Figure 8In contrast to the operation of the previous PMU, leaf PMU 154 may correspond to a first PMU including a GPIO that is operable in a blocking state when a threshold voltage level is received from controller PMU 152 and / or power supply 26. Leaf PMU 154 may be decoupled from power supply 26 during hold mode (e.g., between a first time and a second time) and may be coupled to power supply 26 when operating in normal non-hold mode. Controller PMU 152 may be coupled to leaf PMU 154 and provides a threshold voltage level to leaf PMU 154 when electronics 10 is in hold mode. The blocking state may correspond to the GPIO being coupled to a voltage rail supplying a logic high voltage level as a threshold voltage level. In some cases, the blocking state may correspond to the GPIO having a bias between the well and the gate, wherein the bias is based on the threshold voltage level between the well and the gate. The blocking state may protect the digital logic coupled to leaf PMU 154 from unwanted signals that may be received at the GPIO during hold mode, wherein such unwanted signals may otherwise damage the digital logic if the GPIO is not operated to maintain the blocking state. The blocking state also protects GPIO units from unwanted conduction, which could corrupt data sent to other chips on the shared GPIO bus.

[0048] Although the example shown powers both the power rail from the VDDIOV2_AON pin and the power rail from the VDDIO_AON pin, in some systems, one or only one of these power rails may be powered. For example, Figures 8 to 9 This involves systems where VDDIOV2_AON is powered but VDDIO_AON is not also powered, and Figure 10 This involves systems where VDDIO_AON is powered but VDDIOV2_AON is not. In fact, Figure 9 and Figure 10 An example is shown where a non-powered supply is driven by an associated LDO (e.g., VLDO9B is connected back to VDDIO1V2_AON).

[0049] It should be noted that each PMU 28 may include multiple devices and switching nodes, which are coupled to the regulated power supply node via inductor 158. For a given switching sequence, during different operating cycles of the voltage regulator circuit, the switching nodes may be coupled to capacitor 160 using different sets of multiple devices included in the converter circuit. As used and described herein, the switching sequence specifies the activation of one or more devices of the voltage regulator circuit during each of a plurality of cycles used during the operation of the voltage regulator circuit, and may correspond to different operating modes of the electronic device 10 and / or different operations of different circuits in the analog and / or digital domains for various operating modes of the electronic device 10.

[0050] In some embodiments, one or more PMUs in PMU 28 (e.g., leaf PMU 154, controller PMU 152) may be implemented on a single semiconductor IC (e.g., a die or chip). In some embodiments, one or more PMUs in PMU 28 may be implemented on more than a single semiconductor IC. For example, a leaf PMU (e.g., leaf PMU 154) may be implemented as a chiplet on or adjacent to a semiconductor IC that includes a controller PMU (e.g., controller PMU 152). In some embodiments, one or more PMUs in PMU 28 may be implemented as a multi-die module in a chip package, wherein one or more different dies in the multi-die module are communicatively coupled and / or electrically coupled to each other. For example, a controller PMU (e.g., controller PMU 152) and a leaf PMU (e.g., leaf PMU 154) may be packaged laterally adjacent to each other on the surface of an interposer to achieve a die-to-die connection between the controller PMU and the leaf PMU. In some implementations, one or more PMUs in PMU 28 are implemented together with a processing IC (e.g., a system-on-a-chip) in a chip package or multi-die module. In some implementations, one or more passive devices may be packaged together with one or more PMUs 28. For example, inductor 158 and / or capacitor 160 may be implemented as a small chip on or adjacent to PMU 28 (e.g., as an integrated passive device mounted on controller PMU 152).

[0051] To further explain the power acquisition and retention modes in detail Figure 8 and Figure 9 Timing diagrams and system examples are involved; for ease of discussion, they will be described together in this article. Figure 8 This is a timing diagram 100 illustrating signals 102 to 116 having various voltage values ​​associated with entering and / or exiting the hold mode, and Figure 9 This is a block diagram of leaf PMU 154, which is operable to obtain supply voltage from controller PMU 152 via a second coupling when in hold mode. This document describes example operation in conjunction with hold mode. In practical implementations, one or more of these operations may be adjusted or omitted, or additional operations may be added, depending on the specific configuration and / or use of the system.

[0052] First refer to Figure 8 In the timing diagram 100, digital logic can respond to changes in signals 102 to 116. Signals 102 to 116 are associated with electronic device 10 and can cause the analog and / or digital domains to enter and exit hold modes. Although regarding... Figure 9 Discussions were held, but Figure 8 It can be described similarly Figure 7 , Figure 9 , Figure 10 and Figure 11 The system described operates in power acquisition and retention mode.

[0053] exist Figure 8 and Figure 9 In this system, PMU 154 receives the supply voltage coupled to the rail of the VDDIO1V2_AON pin. The VDDIO1V2_AON pin is coupled to DLD09B and grounded (e.g., via capacitor 160C). Another coupling is between the VDDIO_AON, VDD_ANA, and VLDOINT pins of controller PMU 152, each grounded via capacitor 160D. Furthermore, another coupling is between the VDDIO_AON, VDD_ANA, and VLDOINT pins of PMU 154, each grounded via capacitor 160E. In this system, the digital control voltage level provided via the VDDIO1V2_AON pin can be equal to or substantially similar to the logic level of the GPIO. Conversely, since the digital control voltage level and the GPIO logic level are different voltages, Figure 7 The system may use multiple power rails.

[0054] To further illustrate the hold mode, the RESET_L signal 112 indicates when the electronic device 10 is in hold mode. The RESET_L signal 112 controls whether the electronic device 10 is in hold mode. The RESET_L signal 112 can be a low-level active signal (e.g., "0"), and the hold mode can correspond to the time during which the RESET_L signal 112 is in a low-level state. For example, timing diagram 100 corresponds to the hold mode between time 122 and time 124, and also between time 128 and time 130. The hold mode can correspond to a lower power consumption operating mode of the electronic device 10. As mentioned herein, a logic high voltage level can help identify a "1" bit and can correspond to a first voltage level, such as 1.5 volts (V), a voltage between 1V and 2V, a voltage greater than 1V but less than 3V, or any suitable voltage value. A logic low voltage level can help identify a "0" bit and can correspond to a second voltage level, such as a voltage less than 1.5V, a voltage such as 0.7V, a voltage between 0.5V and 1V, or any suitable value. A logic low voltage level may be lower than a logic high voltage level, and one or both of these logic voltage levels can be used to determine the value of a bit (e.g., to determine whether the bit is a "0" bit or a "1" bit).

[0055] The VREF_OK signal 114 can be an active high signal. The VREF_OK signal 114 can indicate that a voltage supply rail is ready to supply power to one or more power domains (e.g., one or more analog and / or digital domains). For example, the VREF_OK signal 114 can indicate that a main system voltage rail (e.g., VDD_MAIN) is ready for use by electronic device 10. The VREF_OK signal 114 state is based on the voltage level of the VDD_MAIN rail exceeding a threshold voltage 120. Figure 8 In this context, the threshold voltage 120 corresponds to 2.2 volts (V) and occurs at time 118. It should be understood that the threshold voltage 120 can be any suitable voltage, such as a value between 2V and 2.5V, a value between 1V and 3V, a value greater than 1V, etc.

[0056] The VDD_DIG signal 110 indicates the voltage of the rail supplying power to the digital voltage domain of the electronic device 10. This rail can supply power to a digital LDO or another type of digital regulator associated with the digital domain. The VDD_ANA signal 108 indicates the voltage of the rail supplying power to the analog voltage domain of the electronic device 10. This rail can supply power to an analog LDO or another type of analog regulator associated with the digital domain.

[0057] The VAON_OK signal 116 can be an active high signal. The VAON_OK signal 116 can be set to a high logic level in response to one or more power rails being ready to supply power to one or more analog and / or digital domains. For example, the VAON_OK signal 116 can indicate when one or more always-on power rails and / or LDOs are ready for use by the circuitry of the electronic device 10.

[0058] Once both the analog and digital domains are properly powered (e.g., the voltages of the corresponding rails supplying power to the respective domains exceed a voltage threshold), such as at times 126 and 132, the VAON_OK signal 116 can be operated to a logic high level and can continue to indicate when the analog and digital domains are properly powered. Therefore, at time 128, when the electronic device 10 is in hold mode 140 and the voltages of the VDD_ANA signal 108 and / or the VDD_DIG signal 110 decrease below that threshold amount, the VAON_OK signal 116 can be operated to a logic low level.

[0059] The VDD_MAIN signal 102 indicates the voltage of the main power supply (e.g., the VDD_MAIN rail) of the electronic device 10. The PREREG signal 104 indicates the voltage of the pre-regulator included in the bandgap associated with the PMU 28. The pre-regulator can follow the voltage of the VDD_MAIN rail when in bypass mode, which allows the pre-regulator to consume no current and allows the hold mode to consume relatively little power. When the electronic device exits hold mode (e.g., when the RESET_L signal is in a logic high state), the pre-regulator turns on (at time 124), causing a drop in the voltage indicated by the PREREG signal and improving the performance of the bandgap associated with the relatively high-performance power bandgap mode 138.

[0060] The VREF_0V6 signal 106 can indicate a reference voltage generated from the bandgap. A voltage can be supplied to the VREF_0V6 rail after the voltage supplied via the VDD_MAIN rail (e.g., VDD_MAIN signal 102) has reached a threshold voltage 120 (e.g., 2.2V or other suitable threshold). The portion of the VREF_0V6 signal 106 corresponding to the lower power bandgap mode 136 (associated with a hold mode) can be used to hold the output capacitor biased in the electronic device 10. This output capacitor may correspond to... Figure 7 One or more capacitors in capacitor 160. Maintaining the charge of one or more capacitors during reduced power mode reduces the total time to return to normal power mode or to restore the electronic device 10 to full power supply, because no time is spent charging the capacitors.

[0061] The hold mode can also be used to maintain a threshold voltage difference between the VDD_MAIN signal 102 and the VREF_0V6 signal 106 as a bandgap voltage. In this way, the hold mode can be used to maintain the bandgap voltage under a higher-performance bandgap mode 138. The higher-performance bandgap mode 138 enables the electronic device 10 to maintain the bandgap voltage. Compared to the lower-power bandgap mode 136, the higher-performance bandgap mode 138 corresponds to a relatively higher level of threshold calculation. The voltage difference of the maintained bandgap voltage can vary over time. In practice, maintaining a more stable or consistent voltage difference may require more circuitry and / or consume more power than is required in hold mode 140. Therefore, further power consumption reduction can be achieved by making the system more flexible in terms of the maintained bandgap voltage. The relative voltage between the VREF_0V6 signal 106 and ground can correspond to a reference voltage. The PMU 28 can generate the reference voltage independently of the VDD_ANA signal 108 and the VDD_DIG signal 110.

[0062] At some point, the electronic device 10 can be operated back to hold mode 140. For this purpose, the RESET_L signal 112 can change to a logic low level signal at time 128. Upon re-entry into hold mode, the voltages to the analog and digital domains can be reduced to zero (indicated by the decrease in the voltage values ​​of the VDD_ANA signal 108 and the VDD_DIG signal 110). The bandgap voltage can be reduced to a lower power bandgap mode 136, corresponding to an increased voltage being provided to the pre-regulator (e.g., visualized by the value of the PREREG signal 104). Since the VREF_OK signal 114 is generated in response to the VDD_MAIN signal 102 exceeding the threshold voltage 120, the VREF_OK signal 114 is maintained at a logic high voltage level during hold mode 140. However, since the digital and analog domains are de-energized when entering hold mode, the VAON_OK signal 116 is operated at a logic low voltage level until time 132; after exiting hold mode again at time 130 140, the VDD_DIG signal 110 returns to the operating on-voltage level in normal operating mode. To exit hold mode at time 130, the RESET_L signal is operated at a logic high voltage, and in response, the bandgap voltage is increased via the PREREG signal 104 for at least a portion of the duration as power is restored to the analog and digital domains via the VDD_ANA signal 108 and the VDD_DIG signal 110. In some systems, time 134 between time 130 and time 132 may be less than 4.1 milliseconds (ms), such as between 2 ms and 3.5 ms, between 1 ms and 2 ms, between 2.5 ms and 4 ms, etc. This transition time between hold mode 140 and power-up mode 142 may be relatively shorter than some system operations that do not employ one or more of the systems and methods described herein. For example, as described above, instead of restoring capacitor 160 to zero voltage charge when in hold mode 140 (which would normally correspond to power-off mode 144), maintaining the charge of one or more capacitors in capacitor 160 can reduce the power-on time when exiting hold mode 140.

[0063] Available Figure 10 Another example is shown below. Figure 10This is a block diagram of leaf PMU 154, which is operable to draw supply voltage from controller PMU 152 based on a third coupling when in hold mode. In this example, the third coupling is between the VDDIO_AON pins of the respective PMUs 152 and 154, and grounded via capacitor 160D. An additional coupling is between the VDDIO1V2_AON pin and the VLDO9B pin, which is grounded on both controller PMU 152 and leaf PMU 154 via capacitor 160C. The source voltage (e.g., the VDDIO1V2_AON pin) can be unbiased or driven by the on-chip VLDO9B, and the VLDOINT rail and / or the VDDIO_AON rail can be drawn such that the well and gate of the GPIO can be pulled up to a second voltage provided via the VDDIO_AON pin on the connected rail. VDDIO_AON is drawn between controller PMU 152 and leaf PMU 154. The VDD_ANA and VLDOINT pins can be grounded via capacitor 160E. By operating in this way, even if one or more of the VDDIO1V2_AON pins are grounded, the PMU 28 can operate the GPIO at high impedance (HI-Z) at least partially by pulling up the well and gate of the GPIO to a second voltage.

[0064] The above-described Figure 7 , Figure 9 and Figure 10 The PMU 28 can be based on a PMU 28 that can be programmed into leaf mode or controller mode. The PMU 28 can be programmed into leaf or controller mode based on data stored in a register loaded when the electronic device 10 is powered on. Furthermore, the above... Figure 7 , Figure 9 and Figure 10 The PMU 28 may include multiple leaf PMUs 154 coupled to a power supply rail of a controller PMU 152.

[0065] In some systems, PMU 28 is not configurable and may be specifically designed with regulator 156 (e.g., controller PMU) or without regulator 156 (e.g., leaf PMU). In some systems, it may be desirable to couple more than one leaf PMU 28 to one or more controller PMU 28. Sometimes, two types of controller PMU 28 may be used, with different signal combinations obtained among these controller PMU 28.

[0066] In detail, Figure 11This is a block diagram of multiple leaf PMUs 28 that are operable to obtain supply voltage from a first type of controller PMU 28 (e.g., leader controller PMU 152A) and a second type of controller PMU 28 (e.g., follower controller PMU 152B) based on a fourth coupling when in hold mode. Figure 11 Leaf PMU 28 (e.g., leaf PMU 170A, leaf PMU 170B, leaf PMU 170C, leaf PMU 170D) may be designed to omit or bypass one or more regulators 156, and thus can be considered different in this way from the reconfigurable leaf PMU 154 described above. The other pins of leaf PMU 170 may be similar to the pins of the leaf PMUs described above, and are therefore described here based on this. Leaf PMU 170 may not be able to generate its own bias and may therefore be designed to obtain its supply voltage from controller PMU 152.

[0067] A first-type controller PMU 152A may be coupled to a second-type controller PMU 152B via one or more voltage rails. The second-type controller PMU 152B may receive voltage from the first-type controller PMU 152A via one or more voltage rails. The first-type controller PMU 152A may regulate the voltage supplied via the one or more voltage rails, and / or the second-type controller PMU 152B may regulate the voltage supplied via the one or more voltage rails to adjust the voltage supplied to downstream circuitry. In some cases, the first-type controller PMU 152A may provide one or more timing or control signals to the second-type controller PMU 152B to synchronize the operation between the controllers. This allows the second-type controller PMU 152B to omit or disable one or more portions of its circuitry based on its configuration as the second-type controller PMU 152B, thereby achieving further power savings when in hold mode.

[0068] The controller PMU 152 can provide an always-on (AON) voltage supply to the connected leaf PMU 170. The leaf PMU 170 can (e.g., via a shared rail) obtain the AON voltage from the controller PMU 152 and monitor the quality of that AON voltage. The AON voltage supply can be provided on the rail from the VDDIO1V2_AON pin. The voltage can be a suitable value between 1V and 1.5V, such as 1.2V, 1.3V, etc. The leaf PMU 170 can be operated to obtain the VDDIO1V2_AON pin supply voltage in both hold mode and normal mode. Therefore, Figure 11The illustrated example shows that leaf PMU 170, when in hold mode, draws power not only from its GPIOs but also from the controller PMU 152A as its main power supply. By doing so, each leaf PMU 170 can consume less total power compared to leaf PMU 154, which continues to use regulator 156 during normal mode, and / or other PMUs 28, which may not perform power acquisition.

[0069] In fact, Figure 11 The system may include a first power management unit (PMU) (e.g., controller PMU 152A) and multiple power management units (PMUs) (e.g., leaf PMU 170), wherein each of the multiple PMUs may obtain a supply voltage from the first PMU and supply that voltage to one or more corresponding GPIO pins. The multiple PMUs may achieve this via direct coupling. Leaf PMUs 170A and 170B may be directly coupled to controller PMU 152A, controller PMU 152B may be directly coupled to controller PMU 152A, and leaf PMUs 170C and 170D may be directly coupled to controller PMU 152B. Leaf PMUs 170A through 170D may each maintain the bias of the GPIO and / or pull the GPIO to a logic high voltage level based on regulator 156A of controller PMU 152A. Each leaf PMU 170A to 170D may be without a regulator and is therefore operable to draw power supply voltage from controller PMU 152A during each operating mode of electronic device 10, such as during both hold mode and normal mode.

[0070] The technical effects described herein include systems and methods for maintaining the GPIO bias of power management circuitry (e.g., a PMU) to enhance the ability of the GPIO to protect the circuitry of the electronic device even when the electronic device is operating in hold mode. The systems and methods described herein enable a PMU to share a voltage rail with one or more other PMUs, allowing those other PMUs to acquire power. When power is acquired, the one or more other PMUs can de-energize one or more LDOs and other circuitry without causing the GPIO bias to be lost. In some cases, when acquiring power to maintain the GPIO bias is unsuitable for the electronic device, the GPIO pin can be pulled to a logic high level during hold mode, thereby enabling the GPIO to have high impedance and thus blocking unwanted signals from being transmitted to the circuitry of the electronic device, similar to how biasing blocks unwanted signals.

[0071] Based on the examples described above, a system may include a power supply, a PMU having terminals (e.g., GPIO, other types of input and / or output pins) that correspond to a bias state at least some time, wherein the PMU may be coupled to the power supply at a first time. The system may also include digital logic associated with the PMU (e.g., a leaf PMU), wherein the digital logic may be coupled to the power supply at a second time (e.g., at a second time). Figure 6 and Figure 8 (After exiting hold mode) and in response to an event generated by the PMU, the analog domain is enabled. Prior to the first time, the PMU may receive a threshold amount of power to maintain the terminal in a biased state when the PMU is decoupled from the power supply. The biased state may correspond to the voltage between the well and gate of the GPIO. The PMU may achieve this by acquiring the voltage via direct coupling to a second PMU coupled to the power supply. Both PMUs may include regulators. Hold mode may correspond to an operating mode during which the regulator in the PMU is de-energized prior to the first time, while the regulator in the second PMU remains connected to the power supply. The regulator may correspond to an LDO. In some cases, the biased state corresponds to a threshold amount of impedance at a terminal used to block signals received from at least digital logic at the terminal. The examples described herein relate to the PMU and the PMU's GPIO. It should be understood that maintaining the blocking state of one or more terminals is applicable to various circuits within an electronic device.

[0072] The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments are permissible with various modifications and alternatives. It should also be understood that the claims are not intended to be limited to the specific forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the substance and scope of this disclosure.

[0073] Furthermore, the techniques presented and claimed herein are referenced and applied to specific examples of physical and practical nature that significantly improve the art and are therefore not abstract, intangible, or purely theoretical. Additionally, if any claim appended to the end of this specification contains one or more elements designated as “means for [performing] [function]...” or “steps for [performing] [function]...”, such elements shall be interpreted in accordance with 35 USC 112(f). However, for any claim containing elements designated in any other manner, it is intended that such elements shall not be interpreted in accordance with 35 USC 112(f).

[0074] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

Claims

1. An electronic device, the electronic device comprising: A leaf power management unit (PMU) includes a general-purpose input / output (GPIO) that is capable of operating in a blocking state when a threshold voltage level is received, wherein the leaf PMU is configured to be decoupled from the power supply between a first time and a second time, and coupled to the power supply during the second time; and A controller PMU is configured to be coupled to the leaf PMU and to provide the threshold voltage level to the leaf PMU between the first time and the second time.

2. The electronic device of claim 1, wherein the blocking state corresponds to the GPIO being coupled to a voltage rail supplying a logic high voltage level as the threshold voltage level.

3. The electronic device of claim 1, wherein the blocking state corresponds to the GPIO having a bias based on the threshold voltage level between the well and the gate.

4. The electronic device of claim 3, wherein the electronic device includes digital logic configured to be coupled to the leaf PMU, wherein the bias protects signals received at the GPIO from reaching the digital logic.

5. The electronic device according to claim 1, wherein the electronic device comprises: The power source; and Digital logic configured to be coupled to the leaf PMU, wherein the digital logic is configured to enable the analog domain at the second time and in response to an event generated by the controller PMU, the leaf PMU, or both, and wherein prior to the first time, the controller PMU is configured to receive the threshold voltage level from the leaf PMU to maintain the GPIO in a bias state corresponding to the blocking state when the controller PMU is decoupled from the power supply between the first time and the second time.

6. The electronic device of claim 1, the electronic device comprising digital logic configured to be coupled to the leaf PMU, wherein the blocking state corresponds to the GPIO blocking a signal received from the digital logic via the GPIO.

7. The electronic device of claim 1, the electronic device comprising a plurality of power management units (PMUs), the plurality of power management units (PMUs) including the leaf PMU, wherein the controller PMU is configured to be coupled to each respective PMU of the plurality of PMUs via a shared rail.

8. A circuit, the circuit comprising: power supply; A power management unit (PMU) includes terminals configured to operate in a bias state at least for some time, the bias state corresponding to the voltage between the well and the gate of the terminals, wherein the PMU is configured to be coupled to the power supply at a first time. and Digital logic configured to be coupled to the PMU, wherein the digital logic is configured to enable the analog domain in response to the PMU being coupled to the power supply at a first time, wherein prior to the first time, the PMU is configured to receive a threshold amount of power to maintain the terminal in the bias state when the PMU is decoupled from the power supply.

9. The circuit of claim 8, wherein the terminals include general purpose input / output (GPIO).

10. The circuit of claim 8, wherein the digital logic is configured to operate as part of a hold mode, the hold mode enabling the maintenance of one or more states associated with the digital logic when the PMU is decoupled from the power supply.

11. The circuit of claim 10, wherein the PMU comprises a linear regulator or a low-dropout (LDO) regulator.

12. The circuit of claim 8, wherein the bias state corresponds to the impedance of a threshold amount at the terminal, the terminal being configured to block signals received from at least the digital logic at the terminal.

13. The circuit of claim 8, wherein the circuit includes a plurality of PMUs having the power management unit (PMU), wherein the terminals correspond to general purpose inputs / outputs (GPIOs), and wherein the plurality of PMUs are configured to receive the voltage supplied by the power supply via directly obtaining voltage from a second PMU, and to provide a voltage corresponding to the power of the threshold amount to maintain the GPIO in the bias state.

14. A system comprising: First power management unit (PMU); and Multiple power management units (PMUs) are configured to obtain voltage from a first PMU and provide the voltage to one or more terminals.

15. The system of claim 14, wherein a subset of the plurality of PMUs is configured to obtain the voltage from the first PMU via direct coupling to the first PMU.

16. The system of claim 14, the system comprising a second PMU, wherein a subset of the plurality of PMUs is configured to obtain the voltage from the first PMU via direct coupling to the second PMU.

17. The system of claim 14, wherein the first PMU includes a regulator for generating the voltage, and wherein a respective PMU of the plurality of PMUs maintains a general purpose input / output (GPIO) bias based on the voltage from the regulator.

18. The system of claim 14, wherein the first PMU includes a regulator for generating the voltage, and wherein the plurality of PMUs pull the voltage of one or more general purpose inputs / outputs (GPIOs) to a logic high level based on the voltage from the regulator.

19. The system of claim 14, wherein each of the plurality of PMUs corresponds to a first type, wherein the first PMU corresponds to a second type, wherein the first type does not include a regulator for powering one or more pins of the corresponding PMU, and wherein the second type includes the regulator for powering the one or more pins.

20. The system of claim 19, wherein the regulator comprises a linear regulator or a low-dropout (LDO) regulator.

21. The system of claim 14, the system comprising a chip package, wherein the chip package comprises a plurality of different dies, the plurality of different dies comprising the first PMU and the plurality of PMUs, and wherein one or more of the plurality of different dies are communicatively coupled to each other.

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