Statistical channel analysis with feedback burst error

Abstract

The application discloses a computing system configured to measure a step response of a channel in an electronic device, determine a feedback voltage added to the channel by a decision feedback equalizer in response to detecting inter-symbol interference in a received symbol, and predict signal integrity of the channel based at least in part on the step response of the channel and the feedback voltage. The computing system may utilize the predicted signal integrity to determine a probability that a feedback voltage added to the channel by the decision feedback equalizer is wrong, and determine a signal integrity of the channel based at least in part on the step response of the channel, the feedback voltage, and a probability that the feedback voltage added to the channel by the decision feedback equalizer is wrong.

Description

Technical Field

[0001] This application generally relates to electronic design automation, and more specifically, to statistical analysis of electronic circuits and transmission channels within systems, including those that provide feedback on sudden errors. Background Technology

[0002] Modern digital electronic circuits and systems can transmit or transmit sequences of binary values, commonly referred to as bit sequences or digital signals. These bit sequences can be transmitted as voltage waveforms, where the voltage amplitude of a given time period or bit corresponds to the binary logic value for the same time period. Therefore, digital signals can be represented as voltage waveforms in the signal lines and transmission paths of an electronic system. When digital signals are transmitted through circuits, various effects can cause signal degradation, often to the point of error. Errors within digital signals can be quantified by the bit error rate (BER). In many cases, the BER of a circuit or signal path is defined as the ratio of the number of erroneously received bits to the total number of bits transmitted. A crucial consideration in digital electronic design is fidelity, or the quality of signal transmission. The fidelity of an electronic system is often referred to as signal integrity. As designers have increased operating speeds and manufacturing processes have shrunk the physical size of today's modern circuits, signal integrity has become increasingly important. Currently, virtually all electronic circuit designs take signal integrity into account.

[0003] A common type of link in electronic systems—the SERDES (serializer / deserializer) link—typically operates at marginal speeds due to channel losses and impairments. Therefore, equalization schemes, such as decision feedback equalizers (DFEs), are often used to improve the signal-to-noise ratio at the receiver. The DFE used in electronic systems detects symbols received through the SERDES link and provides feedback signals to the SERDES link to eliminate inter-symbol interference associated with the detected symbols. If the DFE erroneously detects a symbol, the resulting feedback signal introduced into the SERDES link will not be able to eliminate the interference and will increase the probability of future symbol detection errors; this is commonly referred to as a DFE burst error.

[0004] Electronic designers frequently employ techniques to predict link behavior in the presence of burst errors (DFEs), such as determining the symbol error ratio (SER) or bit error ratio (BER) and selecting a forward error correction (FEC) scheme for a given channel. For example, these designers can use simulation tools to perform time-domain simulations of channels before device fabrication to identify link behavior problems. However, time-domain simulations are often so complex, computationally expensive, and time-consuming that they become impractical. These complexities and impracticalities often lead designers to attempt to use statistical simulation methods instead of time-domain simulations to determine the probability distribution describing the eye diagram, thereby enabling the prediction of BERs as low as 1e-15 to 1e-20 bits and below with minimal computational resources. However, most traditional statistical simulations cannot account for feedback from DFEs, their complexity is often superlinear relative to the length of the received symbol set, and they frequently include many simplifications, which can lead to unreliable results. Summary of the Invention

[0005] This application discloses a computational system including a channel analysis tool for performing statistical simulations on channels capable of experiencing burst errors originating from a decision feedback equalizer. The computational system can measure the step response of a channel in an electronic device, determine the correct and incorrect feedback voltages that the decision feedback equalizer can add to the channel in response to detecting inter-symbol interference in received symbols, and predict the signal integrity of the channel based at least in part on the channel's step response and the correct feedback voltage. The computational system can use the predicted signal integrity to determine the probability of an incorrect feedback voltage added to the channel by the decision feedback equalizer, and determine the channel's signal integrity based at least in part on the channel's step response, the correct feedback voltage, the incorrect feedback voltage, and the probability that the feedback voltage added to the channel by the decision feedback equalizer is incorrect. The computational system can generate an eye diagram or derive the bit error rate corresponding to the signal integrity of a channel capable of experiencing burst errors originating from the decision feedback equalizer. An embodiment of statistical simulation for a channel capable of experiencing burst errors originating from a decision feedback equalizer is described in more detail below. Attached Figure Description

[0006] Figure 1 and Figure 2 Examples of computer systems that can be used to implement various embodiments of the present invention are shown.

[0007] Figure 3A and Figure 3B An example eye diagram is shown, illustrating the signal integrity of the circuit path.

[0008] Figure 4 An example electrical system is shown.

[0009] Figure 5 Example channel analysis tools for performing statistical simulations on channels capable of experiencing burst errors in decision feedback equalizers, according to various embodiments of the present invention, are shown.

[0010] Figure 6 A flowchart is shown, illustrating the process in Figure 5 An example process for performing statistical simulation on a channel with a sudden error in the decision feedback equalizer.

[0011] Figure 7 Example step responses of channels being evaluated by statistical simulation are shown according to various examples of the present invention.

[0012] Figure 8A and Figure 8B Examples of eye diagrams and example vertical cross-sections of the eye diagrams, constructed by statistical simulation of the channels according to various examples of the present invention, are shown, illustrating the signal integrity of the circuit path.

[0013] Figure 9 Examples of symbolic state transition structures according to various embodiments of the present invention are shown for use with statistical simulation of channels capable of experiencing burst errors from decision feedback equalizers.

[0014] Figure 10 An example vertical cross section of an eye diagram for identifying sign overlap errors due to decision feedback equalization, according to various examples of the present invention, is shown. Detailed Implementation

[0015] Exemplary operating environment

[0016] The execution of various applications can be implemented using computer-executable software instructions that are executed by one or more programmable computing devices. Since these embodiments of the present invention can be implemented using software instructions, the components and operation of a general-purpose programmable computer system that can employ various embodiments of the present invention will be described first.

[0017] Various examples of the present invention can be implemented by executing software instructions using a computing device (e.g., a programmable computer). Accordingly, Figure 1An illustrative example of a computing device 101 is shown. As shown, the computing device 101 includes a computing unit 103 having a processing unit 105 and a system memory 107. The processing unit 105 can be any type of programmable electronic device for executing software instructions, but is conventionally a microprocessor. The system memory 107 may include a read-only memory (ROM) 109 and a random access memory (RAM) 111. As those skilled in the art will understand, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 can store software instructions for execution by the processing unit 105.

[0018] Processing unit 105 and system memory 107 are directly or indirectly connected to one or more peripheral devices via bus 113 or an alternative communication structure. For example, processing unit 105 or system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 115, a removable disk drive 117, an optical disk drive 119, or a flash memory card 121. Processing unit 105 and system memory 107 may also be directly or indirectly connected to one or more input devices 123 and one or more output devices 125. Input devices 123 may include, for example, a keyboard, pointing devices (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. Output devices 125 may include, for example, a monitor display, a printer, and speakers. For various examples of computer 101, one or more peripheral devices 115-125 may be integrated into the housing along with computing unit 103. Alternatively, one or more peripheral devices 115-125 may be located outside the housing of computing unit 103 and connected to bus 113 via, for example, a Universal Serial Bus (USB) connection.

[0019] In some embodiments, computing unit 103 may be directly or indirectly connected to one or more network interfaces 127 for communicating with other devices constituting the network. Network interface 127 converts data and control signals from computing unit 103 into network messages according to one or more communication protocols, such as Transmission Control Protocol (TCP) and Internet Protocol (IP). Furthermore, interface 127 may employ any suitable connection proxy (or combination of proxies) to connect to the network, including, for example, a wireless transceiver, modem, or Ethernet connection. Such network interfaces and protocols are well known in the art and will not be discussed in detail here.

[0020] It should be understood that computer 101 is merely illustrative and not intended to be limiting. Various embodiments of the invention can be implemented using one or more computing devices, including… Figure 1 The components of the computer 101 shown, or only including Figure 1 A subset of the components shown, or an alternative combination of components, including Figure 1 Components not shown. For example, various embodiments of the invention may be implemented using a multiprocessor computer, a network of multiple single-processor and / or multiprocessor computers, or some combination of both.

[0021] In some embodiments of the present invention, the processor unit 105 may have more than one processor core. Accordingly, Figure 2 An example of a multi-core processor unit 105 that can be used in various embodiments of the present invention is shown. As shown, the processor unit 105 includes a plurality of processor cores 201. Each processor core 201 includes a computing engine 203 and a memory cache 205. As known to those skilled in the art, the computing engine includes logic devices for performing various computational functions, such as fetching software instructions and then executing operations specified in the fetched instructions. These operations may include, for example, addition, subtraction, multiplication, comparing numbers, performing logical operations such as AND, OR, NOR, and XOR, and retrieving data. Each computing engine 203 can then use its corresponding memory cache 205 to quickly store and retrieve data and / or instructions for execution.

[0022] Each processor core 201 is connected to interconnect structure 207. The specific configuration of interconnect structure 207 can vary depending on the architecture of the processor unit 201. For some processor cores 201, such as the Cell microprocessors created by Sony Corporation, Toshiba Corporation, and IBM Corporation, interconnect structure 207 may be implemented as an interconnect bus. However, for other processor units 201, such as the Opteron™ and Athlon™ dual-core processors available from AMD in Sunnyvale, California, interconnect structure 207 may be implemented as a system request interface device. In any case, the processor core 201 communicates with input / output interface 209 and memory controller 211 via interconnect structure 207. Input / output interface 209 provides a communication interface between processor unit 201 and bus 113. Similarly, memory controller 211 controls the exchange of information between processor unit 201 and system memory 107. In some embodiments of the invention, processor unit 201 may include additional components, such as high-level cache memory shared by processor cores 201.

[0023] It should also be understood that Figure 1 and Figure 2 The description of the computer networks shown is provided by way of example only and is not intended to impose any limitation on the scope or functionality of alternative embodiments of the invention.

[0024] This document describes in detail methods, apparatus, and systems for analyzing circuit channels, typically designed to carry high-speed signals. The disclosed methods, apparatus, and systems can be used, for example, in printed circuit board or integrated circuit design flows to analyze signal integrity. The disclosed methods, apparatus, and systems should not be construed as limiting in any way. Rather, this disclosure is directed to all novel and non-obvious features and aspects of the various methods, apparatus, systems, and their equivalents, individually and in various combinations and sub-combinations. This disclosure is not limited to any particular aspect or feature or combination thereof, and the disclosed methods, apparatus, and systems do not require any one or more particular advantages or solve any particular problem.

[0025] Although some of the operations of the disclosed methods, apparatuses, and systems are described in a specific order for ease of presentation, it should be understood that this descriptive approach includes rearrangement unless the specific language below requires a particular order. For example, operations described sequentially may be rearranged or performed concurrently in certain circumstances. Furthermore, for brevity, the accompanying drawings may not show the various ways in which the disclosed methods, apparatuses, and systems can be used in conjunction with other methods, apparatuses, and systems. Additionally, the description sometimes uses terms such as “generate” and “determine” to describe the disclosed methods. These terms are high-level abstractions of the actual operations performed. The actual operations corresponding to these terms may vary depending on the specific implementation and are readily discernible to those skilled in the art.

[0026] Various embodiments of the present invention can be used to analyze channels to determine signal integrity. For example, traces, vias, or other interconnections between drivers and receivers in a printed circuit board layout can be evaluated. In some examples, the signal integrity of a digital circuit can be expressed as a bit error rate (BER), which can correspond to a measure of the degree of degradation a bit sequence suffers as it is transmitted through the digital circuit. In addition to the BER, the signal integrity of a channel is typically analyzed by creating an "eye" diagram. Eye diagrams can be created using a variety of techniques, such as by repeatedly sampling the digital signal on the channel using a signal measurement tool (such as an oscilloscope) and superimposing various samples onto each other, by simulating the transmission of the digital signal on the channel and superimposing the simulated digital signal, or by performing statistical simulation on the channel.

[0027] Figure 3A Eye diagram 301 is shown, while Figure 3B Eye diagram 303 is shown. (See diagram 303.) Figure 3A and Figure 3B As shown, eye diagram 301 is distortion-free, while eye diagram 303 contains distortion. Eye diagrams can exhibit distortion due to various electronic effects, such as eye diagram 303. For example, noise, timing issues, overshoot, or undershoot typically manifest as amplitude and phase errors within the eye diagram. The amount of distortion is usually quantified by the opening of the eye diagram. Figure 3A The opening angle is shown to be 305. Figure 3B An eye opening of 307 is shown. In various embodiments of the invention, a bit sequence is selected to produce the maximum eye opening in the eye diagram. In other embodiments of the invention, a bit sequence is selected to produce the minimum eye opening in the eye diagram.

[0028] Various embodiments of the present invention analyze the signal integrity of channels within electronic devices. Examples include printed circuit boards, application-specific integrated circuits (ASICs) (including mixed-signal ASICs), system-on-a-chip (SoCs), programmable logic devices (PLDs) (e.g., field-programmable gate arrays (FPGAs)), fiber optic transmission networks, and optical channels (e.g., optical channels between two components of an integrated circuit). Furthermore, this technique can also be used to evaluate the integrity of electrical carrier channels. As described above, physical electronic devices can be employed in various embodiments of the present invention. However, in various other embodiments of the present invention, examples of simulation or statistical simulation of electronic devices can be employed.

[0029] Any method or technique described herein can be executed using software comprising computer-executable instructions stored on one or more computer-readable storage devices for causing a computer to perform the method or technique. Such software may include, for example, electronic design automation (EDA) tools, such as signal integrity tools. The Hyperlynx tool, provided by Mentor Computer, Wilsonville, Oregon, is an example of a suitable software tool. In various embodiments of the invention, the software may be executed on a single computer. In other embodiments, the software may be executed on a networked computer system, for example, via the Internet, a wide area network, a local area network, a client-server network, or other such networks. For clarity, only certain selected aspects of the software-based implementations have been described. Other details well-known in the art have been omitted. For example, it should be understood that the disclosed techniques are not limited to any particular computer language, program, or computer, and that the disclosed techniques can be implemented using any commercially available computer. An exemplary computing environment has been described, but it should be understood that this environment is not limiting, and although not all possible computing environments have been described, those skilled in the art will be able to implement the invention based on the following disclosure.

[0030] Various embodiments of the present invention may use circuit design information. For example, printed circuit board layout information (such as .HYP files), device models (such as IBIS models), netlists, GDSII descriptions or HDL descriptions (such as Verilog or VHDL descriptions), or other similar layout or device design descriptions stored on one or more computer-readable storage devices. In some embodiments, the circuit to be simulated is instantiated as a SPICE or Eldo model for simulation. For presentation purposes, this disclosure sometimes refers to circuit components by their physical counterparts (e.g., drivers, channels, signals, and other such terms). However, it should be understood that any such references include not only physical components but also such circuit components and representations of signals on those components that can be used in a computer-implemented signal integrity analysis environment.

[0031] Electrical systems including the passageway

[0032] Figure 4 An exemplary electrical system 401 is shown. Figure 4 As shown, electrical system 401 includes a driver 403, a channel 405, and a buffer or receiver 407. In various embodiments of the invention, driver 403 may be a nonlinear driver. Typically, a component may exhibit nonlinear behavior when the sum of its responses is not equal to the sum of its inputs. More specifically, in a linear system, the sum of the responses to bit sequence '010' and the responses to bit sequence '001' will equal the response to bit sequence '011'. The principle of linearity is generally explained mathematically as follows: Given a function F, where Y1 = F(X1) and Y2 = F(X2), if X... s =X1+X2 then Y s =F(X s The response to the bit sequence '011' may not be equal to the sum of the responses to the bit sequences '010' and '001'. Using the same function F defined above and Y1, Y2, and X... s In a nonlinear system Y s =F(X s )≠Y1 +Y2.

[0033] like Figure 4As shown, driver 403 includes an input 409 for receiving a digital signal, or d(t). Furthermore, driver 403 and buffer 407 are connected via channel 405. When the digital signal d(t) is applied to driver 403 through input 409, a response, or voltage waveform, or V(t), is observed on channel 405. The voltage waveform V(t) is commonly referred to as the driver voltage or transmitter voltage. The response of driver 403 can be measured at point 411 in electrical system 401. Additionally, the response of the channel, or W(t), commonly referred to as the waveform or receiver voltage at the receiver, can be measured at point 413 in electrical system 401. Furthermore, as... Figure 4 As shown, driver 403, channel 405 and buffer 407 are typically connected to multiple ground terminals 415.

[0034] As mentioned above, Figure 4 The illustrative systems and other electrical systems represented herein can be actual physical devices. Therefore, the signals, voltages, and currents present in the system can be measured, for example, using an oscilloscope. However, more commonly, various embodiments of the invention are practiced in conjunction with simulation examples of electrical systems. Therefore, the signals, voltages, currents, and other values ​​present in the system can also be simulated.

[0035] Furthermore, those skilled in the art will understand that various tools exist for mathematically describing electrical systems. More specifically, various mathematical tools exist for describing the properties of electrical systems in the time and frequency domains. The formulas described herein can be further modified and transformed using available tools such as Laplace transforms or Fourier transforms. Such transformations and modifications to the methods and exemplary embodiments of the invention are all within the scope of this disclosure.

[0036] Statistical Channel Analysis with Feedback-based Sudden Errors

[0037] Figure 5 An example channel analysis tool 500, according to various embodiments of the present invention, is shown for performing statistical simulations on channels capable of experiencing burst errors of decision feedback equalizers. Figure 6 A flowchart is shown, illustrating the process in Figure 5 This document presents an example procedure for performing statistical simulation on a channel with a sudden error in a decision feedback equalizer. (Reference) Figure 5 and Figure 6In block 601, the computing system implementing channel analysis tool 500 can identify at least one step response or transition edge of a channel of an electronic device. A step response or transition edge can correspond to a channel's response to voltage signal transitions (e.g., via a low-to-high or high-to-low edge of the channel), and the step response or transition edge can electrically characterize the channel. Although the example channel analysis described below corresponds to two-level signaling, in some embodiments, channel analysis tool 500 can perform similar channel analysis for arbitrary signaling levels, such as four-level pulse amplitude modulation (PAM-4) signaling, etc.

[0038] Channel analysis tool 500 may include a step response system 510 for identifying the step response of a channel. In some embodiments, this identification is performed by conducting circuit simulation of the channel described in circuit design 501, such as using an analytical model, SPICE model, IBIS model, transistor-level model, ideal voltage source model, or other such models. In other embodiments, the step response may be measured from a test chip or other physical chip implementing the channel under consideration. In some embodiments, such as when the channel is driven by a nonlinear transmitter or driver, the channel may have multiple transition edges or step responses whose shape may be based on bits that have already been transmitted through the channel before a bit transition. The number of these previously transmitted bits that can influence the shape of the transition edge or step response may be referred to as prehistory or history depth.

[0039] Figure 7 Example step responses of channels, evaluated by statistical simulation, are shown according to various embodiments of the present invention. References Figure 7 The xy-coordinate plot has a channel voltage 701 corresponding to the y-axis and a time 702 corresponding to the x-axis. The plot shows the step response 711 of the channel over time 702, which in this example corresponds to the jump in channel voltage from a low value to a high value.

[0040] As will be described in more detail below, the statistical simulation process can identify sampling points in the step response 711 of the channel. In some embodiments, these sampling points can be periodic, corresponding to bit intervals 713-1 to 713-3 transmitted on the channel. Initial sampling can be performed after an initial offset 712, for example, its value can be set between zero and the duration of a bit interval. In some embodiments, the high-to-low step response can be... Figure 7 The low-to-high step response 711 is shown as an inverted or negative value.

[0041] Return to reference Figure 5 and Figure 6The channel analysis tool 500 may include a statistical simulation system 520 for predicting the signal integrity of the channel, for example, by determining the bit error rate 503 or by constructing a statistical eye diagram 504 through statistical simulation. In some embodiments, the statistical simulation system 520 may construct the statistical eye diagram 504 by respectively determining the probability density functions of multiple different vertical sections of the eye diagram. These probability density functions may represent transitions in the channel voltage from low to high and from high to low. When signaling of more than two levels is implemented, the probability density functions may represent the channel voltage transitions between each voltage level.

[0042] Figure 8A and Figure 8B Example eye diagrams 800 and 810 of the eye diagrams, constructed by statistical simulation of the channels according to various embodiments of the present invention, are shown, illustrating the signal integrity of the circuit path. Reference Figure 8A and Figure 8B The eye diagram 800 has a channel voltage 801 corresponding to the y-axis and a value interval 802 corresponding to the x-axis. The value interval 802 may correspond to a time period during which a value can be transmitted through the channel. The diagram illustrates signals 804 received on the channel, superimposed based on their corresponding value intervals 802. The signals 804 in the eye diagram 800 can be identified as their voltages at different times during the value intervals 802, but in some embodiments, they may also be represented as the density or frequency at which they appear at a specific time-voltage intersection, for example, by their color in the eye diagram 800.

[0043] Figure 8A The diagram also shows offset 803 to illustrate how offset 803 corresponds to a vertical section in eye diagram 810. The vertical section of eye diagram 810 may have a channel voltage 801 corresponding to the x-axis and a density 811 corresponding to the y-axis. Density 811 may correspond to the frequency or probability of the signal 804 received on the channel at different channel voltages 801. The amplitude of the signal 804 received along the y-axis in the vertical section of eye diagram 810 can be... Figure 8A The color of the received signal 804 is represented in the eye diagram. As will be discussed in more detail below, the statistical simulation system 520 can determine the probability density function for the vertical section 810 in the value interval 802 associated with the offset 803. This will identify the signal voltages at the vertical section 810 of the value interval 802 and their density or frequency at different points in the vertical section of the value interval 802.

[0044] Return to reference Figure 5 and Figure 6The statistical simulation system 520 may include a decision feedback equalizer error system 522 for receiving decision feedback equalizer taps 502, which can identify the number of symbols received on a channel that can be affected by inter-symbol interference (ISI). As described above, the symbols received on a channel can have any number of signaling levels. In some examples, the symbols received on a channel can have tail voltage levels capable of altering the voltage values ​​of one or more subsequently received symbols. The decision feedback equalizer at the receiving end of the channel can detect the reception of symbols capable of causing ISI and introduce a voltage into the channel that can eliminate or reduce ISI. In some cases, the decision feedback equalizer can correctly eliminate or reduce ISI, while in other cases, the decision feedback equalizer may incorrectly add feedback voltage, which may exacerbate ISI. The decision feedback equalizer error system 522 can set the probability, or error probability, that the decision feedback equalizer introduces correct or incorrect feedback voltage on the channel. For example, in block 602, the computational system implementing the channel analysis tool 500 can set the error probability of the decision feedback equalizer tap 502. In some embodiments, the decision feedback equalizer error system 522 may initially set the error probability to zero, meaning that the statistical simulation system 520 assumes that the decision feedback equalizer does not malfunction when a feedback voltage is introduced on the channel. In some embodiments, the decision feedback equalizer error system 522 may construct a symbol error probability matrix filled with error probabilities. The symbol error probability matrix may be arranged in a row-column format, with columns corresponding to the number of received signal levels and rows corresponding to the number of transmitted signal levels. In these embodiments, the decision feedback equalizer error system 522 may initially set the error probability of matrix entries with the same signal level to 1, while setting the error probability of other entries to 0.

[0045] The statistical simulation system 520 may include an offset system 524 for setting an offset per unit interval on the channel. The offset per unit interval may correspond to a vertical cross-section of the channel's eye diagram. For example, in block 603, a computational system implementing the channel analysis tool 500 may set the offset per unit interval on the channel. The statistical simulation system 520 may use this offset to determine various sampling points in at least one step response identified by the step response system 510. In some embodiments, sampling points may be located in unit interval increments such that each sampling point corresponds to the same vertical cross-section of the channel per unit interval.

[0046] The statistical simulation system 520 can identify sampling points in the step response of a channel. In some embodiments, these sampling points can be periodic, corresponding to unit intervals transmitted on the channel, starting after an initial offset. In some embodiments, the statistical simulation system 520 can utilize the transmit jitter distribution at each sampling point of the step response to determine the possible voltage at each sampling point in the presence of transmit jitter; this can be referred to as a vertical distribution. These vertical distributions can serve as probability density functions to identify the potential voltage at each sampling point and the probability or weight associated with each potential voltage of the step response at the corresponding sampling point.

[0047] The statistical simulation system 520 may include a transition state system 526 for constructing a symbol state transition structure that describes the symbol transition received from the channel based at least in part on the vertical voltage distribution associated with the symbol transition and the feedback voltage introduced by the decision feedback equalizer. In some examples, the symbol state transition structure may be implemented by a computing system or in a programmable hardware device.

[0048] Figure 9 Example symbolic state transition structure 900, according to various embodiments of the present invention, is shown for use with statistical simulation of channels capable of experiencing burst errors from a decision feedback equalizer. Reference Figure 9 The symbol state transition structure 900 describes serially received symbols as a set including symbol units 920-924. In this example embodiment of the symbol state transition structure 900, symbol unit 920 may correspond to the main cursor symbol, and symbol units 921-924 may correspond to subsequent cursor symbols. Although not shown, the symbol transition structure 900 may include one or more symbol units corresponding to the preceding cursor symbol or a previously received symbol (to the right of the main cursor), and may include one or more additional subsequent cursor symbol units (to the left of symbol unit 924). The main cursor symbol may correspond to the symbol currently received through the channel, while the subsequent cursor symbols may correspond to subsequently received symbols. The subsequent cursor symbols corresponding to symbol units 921-924 may correspond to symbols whose voltage levels may be affected by an error feedback voltage added to the channel by a decision feedback equalizer to eliminate or reduce the voltage tail associated with the main cursor symbol. The number of subsequent cursor symbols that may be affected by the feedback voltage added to the channel by the decision feedback equalizer may correspond to the number of decision feedback equalizer taps 905 associated with the channel.

[0049] Each symbol unit 920-924 in the symbol transfer structure 900 may have a state-based structure, as shown in reference symbol unit 921. Symbol unit 921 may include a first stage having multiple accumulators 911 and 912 for receiving probability density functions 901 and 902 corresponding to high and low states of voltage levels on the channel, respectively. The symbol transfer structure 900 includes a second stage having multiple accumulators 913 and 914 for accumulating versions of probability density functions 901 and 902 from the first stage after one or more modifications 915-918.

[0050] In some embodiments, modification 915 to the probability density function output from accumulator 911 may involve scaling the probability density function based on the probability of a symbol transitioning from a high state to another high state on the channel, while convolving the probability density function with an error feedback voltage weighted by the probability of a decision feedback voltage failing in the feedback voltage added to the channel. Modification 916 to the probability density function output from accumulator 912 may involve scaling the probability density function based on the probability of a symbol transitioning from a low state to another low state on the channel, while convolving the probability density function with an error feedback voltage weighted by the probability of a decision feedback voltage failing in the feedback voltage added to the channel. In some embodiments, modification 917 to the probability density function output from accumulator 911 may involve scaling the probability density function based on the probability of a symbol transitioning from a high state to a low state on the channel, while convolving the probability density function with both a correct feedback voltage and an error feedback voltage, both of which are complementary weighted by the probability of a decision feedback voltage failing in the feedback voltage added to the channel. In some embodiments, the modification 918 performed on the probability density function output from accumulator 912 may be scaling the probability density function based on the probability of a symbol transitioning from a low state to a high state on the channel, while convolving the probability density function with both the correct feedback voltage and the incorrect feedback voltage, which are complementary weighted by the probability that the decision feedback voltage is incorrect in the feedback voltage added to the channel. Accumulator 913 may receive the probability density functions modified by 915 and 918 and aggregate them to output probability density function 903. Accumulator 914 may receive the probability density functions modified by 916 and 917 and aggregate them to output probability density function 904.

[0051] In some implementations, accumulators 911 and 912 can convolve their respective probability density functions with an error feedback voltage, weighted by the probability of the decision feedback voltage being incorrect in the feedback voltage added to the channel, using the error probabilities in the symbol error probability matrix. Since the error probability matrix can be arranged in a row-column format, the error probabilities at corresponding intersections in the matrix can be applied to the accumulators associated with the corresponding rows and columns. After convolution, accumulators 911 and 912 can output the convolved probability density function to accumulators 913 and 914, where the structure of the symbol unit 921 undergoes any further modifications during the transition to accumulators 913 and 914. Although... Figure 9 A symbol transfer structure 900 is shown for use with statistical simulation of a channel with two-level signaling, but in some embodiments, the symbol transfer structure 900 may include additional accumulators and modifications to accommodate statistical simulation of any number of signal levels.

[0052] Return to reference Figure 5 and Figure 6 The statistical simulation system 520 may include a signal integrity system 528 for constructing a statistical eye diagram 504 using the symbolic state transition structure generated by the transition state system 526. For example, in block 604, the computational system implementing the channel analysis tool 500 may aggregate the probability density function and feedback voltage from the decision feedback equalizer for each point on the step response corresponding to that offset.

[0053] The signal integrity system 528 can initially load the first stage of the bit state transition structure with a Dirac delta function—having a voltage level corresponding to a high level in the state container associated with the '1' symbol and a voltage level corresponding to a low level in the state container associated with the '0' symbol. The signal integrity system 528 can then transfer the Dirac delta function from the state container in the first stage of the symbol state transition structure to the second stage of the symbol state transition structure, while performing the operation corresponding to the last sampling point along at least one step response (e.g., ...). Figure 7 The signal integrity system 528 can modify the sampling point 710-Q in the second stage. The signal integrity system 528 can move the probability density function obtained in the state container of the second stage to the corresponding state container in the first stage, and perform another transition between state containers, this time using the penultimate sampling point. The signal integrity system 526 can continue this process until all sampling points (e.g., ...) are modified. Figure 7 The sampling points 710-1 in the sampled data are all selectively convolved with the probability density function by their vertical distribution and the added feedback voltage.

[0054] Signal integrity system 528 can aggregate state containers of low and high states from all state containers, which corresponds to a specific vertical cross-section of statistical eye diagram 504. When signaling includes more than two levels, signal integrity system 528 can aggregate state containers for each different state level, which corresponds to a specific vertical cross-section of statistical eye diagram 504. In block 605, the computational system implementing channel analysis tool 500 can determine whether to evaluate an additional offset per unit interval on the channel, for example, by incrementing the offset previously set in block 603. If so, execution returns to block 603, where the computational system implementing channel analysis tool 500 can set a new offset per unit interval on the channel. In some embodiments, offset system 522 in statistical simulation system 520 can select a new offset per unit interval on the channel. Since each offset corresponds to Figure 8A In some embodiments, the statistical simulation system 520 can incrementally increase the offset across unit intervals, such as by a preset value, to achieve the aggregated probability density function of the entire eye diagram—one section at a time. In other embodiments, the statistical simulation system 520 can analyze multiple offsets or sections of the eye diagram in parallel.

[0055] For example, if in block 605, the computational system implementing channel analysis tool 500 decides not to evaluate the additional offset per unit interval on the channel, execution continues to block 606, where the computational system implementing channel analysis tool 500 can use an aggregate probability density function to determine the error probability associated with the feedback voltage added by the decision feedback equalizer. In some embodiments, channel analysis tool 500 may include a burst error system 530 for analyzing the vertical cross-section of the aggregate probability density function to determine the probability that the decision feedback equalizer erred when adding feedback voltage to the channel for that symbol.

[0056] The burst error system 530 may include a symbol overlap system 532 for identifying the locations where high and low states of the aggregate probability density function overlap, and then determining the area of ​​overlap, which may correspond to the probability that the decision feedback equalizer will err when adding a feedback voltage to the channel for that symbol. When the channel has more than two signaling levels, the symbol overlap system 532 may identify when different signal levels overlap and determine the overlap area for each signal level. The burst error system 530 may also include an error probability system 534 for determining the error probability associated with the feedback voltage added by the decision feedback equalizer based on the area of ​​overlap in the high and low states of the aggregate probability density function, or based on multiple overlap areas when analyzing more than two signaling levels. In some embodiments, the ratio of the overlap area to the total density of the aggregate probability density function may correspond to the error probability. In some embodiments, the burst error system 530 may modify the symbol error probability matrix with the determined error probability.

[0057] Figure 10 An example vertical section 1000 of an eye diagram for identifying sign overlap errors due to decision feedback equalization, according to various embodiments of the present invention, is shown. Reference Figure 10 The vertical cross-section of eye diagram 1000 can have a channel voltage 1001 corresponding to the x-axis and a density 1011 corresponding to the y-axis. Density 1011 can correspond to the frequency or probability of the signal 1004 received on the channel at different channel voltages 1001. As described above, the statistical simulation system can determine a probability density function for the vertical cross-section 1000 in the value interval associated with the offset. This will identify the signal voltages at the vertical cross-section 1000 of the value interval and their density or frequency at different points in the vertical cross-section of the value interval. In this example, the received signal 1004 may at least partially overlap with its channel voltage 1001, which may indicate that the decision feedback equalizer has added an erroneous feedback voltage to the channel. The area associated with the overlap, or sign overlap error 1005, can be determined, and one or more probabilities of the decision feedback equalizer adding an erroneous feedback voltage to the channel can be identified using the ratio of sign overlap error 1005 to the total density 1011 of the received signal 1004.

[0058] Return to reference Figure 5 and Figure 6 In block 607, the computational system implementing channel analysis tool 500 can determine whether error probability convergence has occurred. In some embodiments, burst error system 530 can compare the determined error probability with the error probability set in block 602 to determine whether convergence has occurred. When burst error system 530 determines that convergence has not occurred, for example, when the difference between the determined error probability and the error probability set in block 602 is higher than a predetermined threshold level (e.g., the machine accuracy level of the computational system), execution returns to block 602, where channel analysis tool 500 sets the error probability of the DFE tap to the error probability determined by burst error system 530. Blocks 602-606 can be iteratively executed based on previous runs of the blocks, using the symbol error probability matrix and the changing error probabilities in the DFE taps, until in block 607, burst error system 530 determines that convergence has occurred, for example, when the determined error probability is the same as or lower than the predetermined threshold level set in block 602.

[0059] The execution can then proceed to box 608, where the computational system implementing channel analysis tool 500 can determine the signal integrity of the channel based on the aggregated probability density function for different offsets. Signal integrity prediction system 528 can also generate a bit error rate 503 based on statistical eye diagram 504, for example, by determining the ratio of signals falling within a predetermined position in statistical eye diagram 504 towards the center of the eye to signals falling outside said predetermined position. This ratio can describe the ability to predict the number of transmission errors that will occur, taking into account the burst errors caused by error feedback voltage from the decision feedback equalizer.

[0060] The systems and apparatuses described herein may use dedicated processor systems, microcontrollers, programmable logic devices, microprocessors, or any combination thereof to perform some or all of the operations described herein. Some of the operations described herein may be implemented in software, while others may be implemented in hardware. Any operations, processes, and / or methods described herein may be performed by apparatuses, devices, and / or systems substantially similar to those described herein and illustrated with reference to the accompanying drawings.

[0061] A processing device can execute instructions or "code" stored in memory. Memory can also store data. Processing devices can include, but are not limited to, analog processors, digital processors, microprocessors, multi-core processors, processor arrays, network processors, etc. A processing device can be part of an integrated control system or system manager, or it can be provided as a portable electronic device configured to interface with a network system locally or remotely via wireless transmission.

[0062] Processor memory can be integrated with the processing device, such as RAM or FLASH memory housed within an integrated circuit microprocessor or similar device. In other examples, memory can include a separate device, such as an external disk drive, storage array, portable FLASH key card, etc. Memory and processing device can be operatively coupled together or communicate with each other, for example via I / O ports, network connections, etc., and the processing device can read files stored on the memory. The associated memory may be designed as "read-only" (ROM) due to access restrictions, or it may not be. Other examples of memory may include, but are not limited to, WORM, EPROM, EEPROM, FLASH, etc., which can be implemented in solid-state semiconductor devices. Other memories may include moving parts, such as known spinning disk drives. All of these memories can be "machine-readable" and can be read by the processing device.

[0063] Operating instructions or commands may be implemented or embodied in the tangible form of stored computer software (also known as a “computer program” or “code”). The program or code may be stored in digital memory and may be read by a processing device. A “computer-readable storage medium” (or alternatively, a “machine-readable storage medium”) may include all of the aforementioned types of memory, as well as future technologies, provided that the memory is capable of storing digital information, at least temporarily, in the form of a computer program or other data, and that the stored information can be “read” by a suitable processing device. The term “computer-readable” may not be limited to the historical use of “computer” to imply a full range of mainframes, minicomputers, desktops, or even laptops. Rather, “computer-readable” may include storage media that can be read by a processor, processing device, or any computing system. Such media may be any available media that can be accessed locally and / or remotely by a computer or processor, and may include volatile and non-volatile media, as well as removable and non-removable media, or any combination thereof.

[0064] A program stored in a computer-readable storage medium may include a computer program product. For example, a storage medium can be used as a convenient means of storing or transmitting a computer program. For convenience, operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be situations where these functional blocks or diagrams can be equivalently aggregated into a single logical device, program, or operation with unclear boundaries.

[0065] in conclusion

[0066] While this application describes specific examples of implementing embodiments of the invention, those skilled in the art will understand that many variations and substitutions of the above systems and techniques exist within the spirit and scope of the invention as set forth in the appended claims. For example, although specific terms are used above to refer to certain processes, it should be understood that various examples of the invention can be implemented using any desired combination of processes.

[0067] Those skilled in the art will also recognize that the concepts taught herein can be tailored to specific applications in many other ways. In particular, those skilled in the art will recognize that the examples shown are merely one of many alternative implementations that will become apparent upon reading this disclosure.

[0068] Although the specification may refer to “one,” “another,” or “some” examples in multiple places, this does not necessarily mean that each such reference refers to the same one or more examples, or that the feature applies only to a single example.

Claims

1. A method comprising: The step response of a channel in an electronic device is measured by a computing system; The computing system determines the feedback voltage added to the channel by the decision feedback equalizer in response to the detection of inter-symbol interference in the received symbols; The signal integrity of the channel is predicted by the computing system based at least in part on the step response of the channel and the feedback voltage. The computing system uses the predicted signal integrity to determine the probability that the feedback voltage added to the channel by the decision feedback equalizer is incorrect; as well as The signal integrity of the channel is determined by the computing system based at least in part on the step response of the channel, the feedback voltage, and the probability that the feedback voltage added to the channel by the decision feedback equalizer is erroneous.

2. The method according to claim 1, wherein, Determining the signal integrity of the channel further includes: generating the bit error rate of the channel or deriving at least one of an eye diagram representing the signal integrity of the channel.

3. The method according to claim 1, further comprising: The computational system determines the error feedback voltage added to the channel by the decision feedback equalizer, wherein the determination of the signal integrity of the channel is based at least in part on the channel's step response, the feedback voltage, the error feedback voltage, and the probability that the feedback voltage added to the channel by the decision feedback equalizer is erroneous.

4. The method according to claim 1, wherein, Determining the probability that the feedback voltage added to the channel by the decision feedback equalizer is erroneous using the predicted signal integrity further includes: identifying symbols that are erroneously received in the predicted signal integrity, wherein the probability that the feedback voltage added to the channel by the decision feedback equalizer is erroneous corresponds to the ratio of the erroneously received symbols to the total number of received symbols.

5. The method according to claim 1, further comprising: The computing system iteratively re-predicts the signal integrity of the channel based at least in part on the channel’s step response, the feedback voltage, and the probability that the feedback voltage added to the channel by the decision feedback equalizer is incorrect; The computational system iteratively uses the re-predicted signal integrity to determine the different probabilities that the feedback voltage added to the channel by the decision feedback equalizer is erroneous.

6. The method according to claim 5, further comprising: Determine when there is convergence in the probability that the feedback voltage added to the channel by the decision feedback equalizer is erroneous, wherein the determination of the signal integrity of the channel is based at least in part on at least one of the probabilities that the feedback voltage added to the channel by the decision feedback equalizer is erroneous, the step response of the channel, and the feedback voltage.

7. The method according to claim 1, further comprising: The computational system sets the offset of the bit interval on the channel, wherein predicting the signal integrity of the channel further includes aggregating a probability density function of multiple points in the step response of the channel corresponding to the offset.

8. A system comprising: The memory system is configured to store computer-executable instructions; as well as The computing system, in response to the execution of the computer-executable instructions, is configured to: Measure the step response of a channel in an electronic device; Determine the feedback voltage added to the channel by the decision feedback equalizer in response to the detection of inter-symbol interference in the received symbols; The signal integrity of the channel is predicted at least in part based on the step response of the channel and the feedback voltage; The probability that the feedback voltage added to the channel by the decision feedback equalizer is incorrect is determined by using the predicted signal integrity. as well as The signal integrity of the channel is determined at least in part based on the channel’s step response, the feedback voltage, and the probability that the feedback voltage added to the channel by the decision feedback equalizer is erroneous.

9. The system according to claim 8, wherein, The computing system, in response to the execution of the computer-executable instructions, is further configured to determine the signal integrity of the channel by: generating a bit error rate of the channel or deriving an eye diagram representing the signal integrity of the channel.

10. The system according to claim 8, wherein, The computing system, in response to the execution of the computer-executable instructions, is further configured to: Determine the error feedback voltage added to the channel by the decision feedback equalizer; as well as The signal integrity of the channel is determined at least in part based on the channel’s step response, the feedback voltage, the error feedback voltage, and the probability that the feedback voltage added to the channel by the decision feedback equalizer is erroneous.

11. The system according to claim 8, wherein, The computing system, in response to the execution of the computer-executable instructions, is also configured to utilize the predicted signal integrity by identifying symbols that are erroneously received in the predicted signal integrity, wherein the probability that the feedback voltage added to the channel by the decision feedback equalizer is erroneous corresponds to the ratio of the erroneously received symbols to the total number of received symbols.

12. The system according to claim 8, wherein, The computing system, in response to the execution of the computer-executable instructions, is further configured to: The signal integrity of the channel is iteratively re-predicted based at least in part on the channel’s step response, the feedback voltage, and the probability that the feedback voltage added to the channel by the decision feedback equalizer is incorrect; as well as The re-predicted signal integrity is used iteratively to determine the different probabilities that the feedback voltage added to the channel by the decision feedback equalizer is incorrect.

13. The system according to claim 12, wherein, The computing system, in response to the execution of the computer-executable instructions, is further configured to: Determine when the probability that the feedback voltage added to the channel by the decision feedback equalizer is incorrect converges; as well as The signal integrity of the channel is determined at least in part based on at least one of the determined probabilities that the feedback voltage added to the channel by the decision feedback equalizer is erroneous, the step response of the channel, and the feedback voltage.

14. An apparatus comprising at least one computer-readable storage device storing instructions configured to cause one or more processing devices to perform operations, the operations including: Measure the step response of a channel in an electronic device; Determine the feedback voltage added to the channel by the decision feedback equalizer in response to the detection of inter-symbol interference in the received symbols; The signal integrity of the channel is predicted at least in part based on the step response of the channel and the feedback voltage; The probability that the feedback voltage added to the channel by the decision feedback equalizer is incorrect is determined by using the predicted signal integrity. as well as The signal integrity of the channel is determined at least in part based on the channel’s step response, the feedback voltage, and the probability that the feedback voltage added to the channel by the decision feedback equalizer is erroneous.

15. The apparatus according to claim 14, wherein, Determining the signal integrity of the channel further includes: generating the bit error rate of the channel or deriving at least one of an eye diagram representing the signal integrity of the channel.

16. The apparatus according to claim 14, wherein, The instruction is configured to cause the one or more processing devices to perform an operation, the operation further comprising: determining an error feedback voltage added to the channel by the decision feedback equalizer, wherein the determination of the signal integrity of the channel is based at least in part on the step response of the channel, the feedback voltage, the error feedback voltage, and the probability that the feedback voltage added to the channel by the decision feedback equalizer is erroneous.

17. The apparatus according to claim 14, wherein, Determining the probability that the feedback voltage added to the channel by the decision feedback equalizer is erroneous using the predicted signal integrity further includes: identifying symbols that are erroneously received in the predicted signal integrity, wherein the probability that the feedback voltage added to the channel by the decision feedback equalizer is erroneous corresponds to the ratio of the erroneously received symbols to the total number of received symbols.

18. The apparatus according to claim 14, wherein, The instructions are configured to cause the one or more processing devices to perform an operation, the operation further comprising: The signal integrity of the channel is iteratively re-predicted based at least in part on the channel’s step response, the feedback voltage, and the probability that the feedback voltage added to the channel by the decision feedback equalizer is incorrect; The re-predicted signal integrity is used iteratively to determine the different probabilities that the feedback voltage added to the channel by the decision feedback equalizer is incorrect.

19. The apparatus according to claim 18, wherein, The instructions are configured to cause the one or more processing devices to perform an operation, the operation further comprising: determining when there is convergence in the determined probability that the feedback voltage added to the channel by the decision feedback equalizer is erroneous, wherein the determination of the signal integrity of the channel is based at least in part on at least one of the determined probabilities that the feedback voltage added to the channel by the decision feedback equalizer is erroneous, the step response of the channel, and the feedback voltage.

20. The apparatus according to claim 14, wherein, The instructions are configured to cause the one or more processing devices to perform an operation, the operation further comprising: setting an offset of a bit interval on the channel, wherein predicting the signal integrity of the channel further comprises aggregating a probability density function of a plurality of points in the step response of the channel corresponding to the offset.

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