Embedded capacitor in finger connector for crosstalk cancellation

Abstract

Semiconductor devices are described herein. The semiconductor device may include a semiconductor package including a plurality of circuits and a plurality of connectors configured to facilitate signal transmission between the semiconductor package and an apparatus when the semiconductor package is connected to the apparatus via the plurality of connectors. At least a first connector of the plurality of connectors may be embedded with a capacitor. A capacitor embedded in the first connector may be connected to a second connector of the plurality of connectors.

Description

Background Technology

[0001] This disclosure relates to systems and apparatus implemented using semiconductor devices. More specifically, in some embodiments, this disclosure relates to memory devices including embedded capacitors in finger connectors for crosstalk cancellation.

[0002] As memory system data rates increase to relatively high levels, such as exceeding 10 gigabits per second (Gb / s), and with the target of 17.6 Gb / s for double data rate generation 6 (DDR6) memory, signal crosstalk negatively impacts the single-ended channel performance between the CPU and RCD / DB in the memory system. Signal crosstalk is a signal integrity problem caused by unwanted electromagnetic coupling between conductive paths (such as traces on a printed circuit board (PCB)) that are not physically in contact with each other. At relatively high data rates, it is difficult to open the data eye diagram of the memory system using equalization techniques due to signal crosstalk noise. Therefore, it is desirable to reduce signal crosstalk between signals in high data rate memory systems, such as those implementing DDR6 memory channel designs. Summary of the Invention

[0003] In one embodiment, a semiconductor device is generally described. The semiconductor device may include a semiconductor package including multiple circuits and multiple connectors configured to facilitate signal transmission between the semiconductor package and the device when the semiconductor package is connected to a device via the multiple connectors. At least a first connector among the multiple connectors may have a capacitor embedded in it. The capacitor embedded in the first connector may be connected to a second connector among the multiple connectors.

[0004] In one embodiment, a memory module is generally described. The memory module may include a plurality of memory devices and a plurality of connectors configured to facilitate signal transmission between the plurality of memory devices and the device when the plurality of memory devices are connected to the device via the plurality of connectors. At least a first connector of the plurality of connectors may have a capacitor embedded therein. The capacitor embedded in the first connector may be connected to a second connector of the plurality of connectors.

[0005] In one embodiment, a structure is generally described. This structure may include a plurality of connectors, including at least a first connector and a second connector. The first connector includes at least a first layer and a second layer located below the first layer. The first layer of the first connector may include signal traces and a metal plate applied above the signal traces. The second layer of the first connector may include conductive regions that form a capacitor with the metal plate on the first layer of the first connector. The capacitor may be connected to the second connector.

[0006] The above description of the invention is illustrative only and is not intended to be limiting in any way. Other aspects, embodiments, and features will become apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. In the drawings, the same reference numerals denote the same or functionally similar elements. Attached Figure Description

[0007] Figure 1 This is a diagram of an example memory system according to an embodiment of the present disclosure.

[0008] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A block diagram of an example memory module for a memory system.

[0009] Figure 3 This is a diagram of a semiconductor device including an embedded capacitor in a finger connector for crosstalk cancellation in one embodiment.

[0010] Figure 4 This is a diagram of an example implementation of an embedded capacitor in a finger connector for crosstalk cancellation in one embodiment.

[0011] Figure 5A This is a diagram of an example connection of a connector with an embedded capacitor in a finger connector for crosstalk cancellation in one embodiment.

[0012] Figure 5B This is a diagram of another example connection of a connector with an embedded capacitor in a finger connector for crosstalk cancellation in one embodiment.

[0013] Figure 6A This is a diagram of another example connection of a connector with an embedded capacitor in a finger connector for crosstalk cancellation in one embodiment.

[0014] Figure 6B This is a diagram of another example connection of a connector with an embedded capacitor in a finger connector for crosstalk cancellation in one embodiment.

[0015] Figure 6C This is a diagram of another example connection of a connector with an embedded capacitor in a finger connector for crosstalk cancellation in one embodiment.

[0016] Figure 7A This is a diagram of another example connection of a connector with an embedded capacitor in a finger connector for crosstalk cancellation in one embodiment.

[0017] Figure 7BThis is a diagram of another example connection of a connector with an embedded capacitor in a finger connector for crosstalk cancellation in one embodiment.

[0018] Figure 7C This is a diagram of another example connection of a connector with an embedded capacitor in a finger connector for crosstalk cancellation in one embodiment. Specific Implementation

[0019] Power management in DDR random access memory (RAM) modules typically relies on the use of a power management integrated circuit (PMIC) to handle the conversion from a large power input to one or more power outputs, the voltage of which corresponds to the requirements of different components of the DDR memory module, and in some embodiments, also to DDR5 memory modules. In one example, the disclosed embodiments may include unbuffered dual in-line memory modules (UDIMMs). For example, for laptops, the disclosed embodiments may include small outline dual in-line memory modules (SODIMMs), such as DDR5 SODIMMs. In another example, the disclosed embodiments may include register-equipped dual in-line memory modules (RDIMMs). The disclosed embodiments may alternatively include any type of memory module.

[0020] Figure 1 This is a diagram of an example memory system 10 according to an embodiment of the present disclosure. The memory system 10 may include memory modules 201, 202...20 N (Also collectively or individually referred to herein as memory module 20), connector 70, and memory controller 80. In one exemplary embodiment, memory module 20 may include a dual in-line memory module (DIMM). In some embodiments, memory module 20 may be implemented as a double data rate generation 5 (DDR5) SDRAM module. Although described and illustrated herein as components of a particular type, arrangement, and number, in other embodiments, memory module 20 may include any other type, arrangement, or number of components.

[0021] Example memory module 20 may include circuit blocks 301, 302, 303, 304, 305...30 P-4 , 30 P-3 30 P-2 30 P-1 and 30 P Circuit blocks 401, 402, ... 40 M-1 and 40 MThe memory module includes a register clock driver (RCD) 50, a PMIC 60, a connector 70, and any other blocks, circuits, pins, connectors, traces, or other components typically found in a memory module. In some embodiments, circuit blocks 301, 302, 303, 304, 305…30… P-4 , 30 P-3 30 P-2 30 P-1 and 30 P It can be configured as a data buffer, and will also be collectively or individually referred to herein as data buffer 30. In some embodiments, circuit blocks 401, 402, ... 40 M-1 and 40 M It can be configured as a memory device, and will be collectively or separately referred to herein as memory device 40. Although circuit block 30 and circuit block 40 are described herein as data buffer 30 and memory device 40, memory module 20 may also or alternatively use circuit block 30 and circuit block 40 for any other purpose.

[0022] In some embodiments, the data buffer 30 and memory device 40 may include a synchronous dynamic random access memory (SDRAM) device, chip, or module. In some embodiments, the data buffer 30 and memory device 40 may also (or alternatively) include any other type of memory device, such as SRAM, DRAM, MROM, PROM, EPROM, and EEPROM. The data buffer 30, memory device 40, or both may be physically located on one or both sides of the memory module 20 (e.g., the front and back).

[0023] PMIC 60 can be configured to perform power management for memory module 20. For example, PMIC 60 can be configured to scale up or down voltage, perform DC-DC conversion, or perform other similar power management operations. In some embodiments, PMIC 60 may include low-dropout regulators (LDOs), DC-DC converters (e.g., buck or boost converters), pulse frequency modulation (PFM), pulse width modulation (PWM), power MOSFETs, real-time clocks (RTCs), or any other circuitry typically found in a PMIC.

[0024] Connector 70 may include, for example, pins, traces, or other connections configured to connect memory module 20 to other components of the computing system, such as memory controller 80, motherboard, or other components. In some embodiments, connector 70 may include, for example, a 288-pin configuration or any other pin configuration. In some embodiments, memory module 20 may include connector 70. In other embodiments, motherboard, memory controller 80, or any other component of the computing device may include connector 70. In yet another embodiment, one or more connectors in connector 70 may be part of memory module 20, and one or more connectors in connector 70 may be part of motherboard, memory controller 80, or other components of the computing device. Memory module 20 may be connected, for example, via connector 70 to motherboard, memory controller 80, or other components of the computing device to transfer data between components of the computing device and memory module 20. For example, in embodiments implementing UDIMM, connector 70 may include a 64-bit bus, a 72-bit bus, or a bus including any other bit width.

[0025] Figure 1 The memory module 20 shown is connected to the memory controller 80 of the computing device via connector 70. In an exemplary embodiment, the memory controller 80 may be implemented as a component of the computer motherboard of the computing device, for example, located on the northbridge of the motherboard. In another example, the memory controller 80 may be implemented as a component of the microprocessor of the computing device. In yet another example, the memory controller 80 may be implemented as a component of the central processing unit (CPU) of the computing device. In other embodiments, the memory controller 80 may be implemented as part of any other component of the computing device.

[0026] In some embodiments, memory module 20 may be implemented as a DDR5 SDRAM memory module. For example, memory module 20 may include memory module densities of 128 gigabytes (GB), 512 GB, 1 terabyte (TB), or higher per module. Memory module 20 may operate at frequencies ranging from about 1.2 GHz to about 3.2 GHz and data rates ranging from about 3.2 GT / s to about 4.6 GT / s, and in some cases, data rates up to about 8 GT / s or higher. In some embodiments, memory module 20 may alternatively include smaller or larger densities, operate at lower or higher frequencies, and operate at lower or higher data rates.

[0027] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A block diagram of an example memory module of a memory system. Memory module 20 can represent memory modules 201 to 2020.N The memory module 20 is shown communicating with the memory controller 80. The memory controller 80 is shown as part of circuitry 90, such as a motherboard, mainboard, or other component of a computing device that communicates with the memory module 20.

[0028] The memory module 20 may include one or more circuit groups 221, 222, 223, 224, 225...22 Q-4 ,twenty two Q-3 ,twenty two Q-2 ,twenty two Q-1 and 22 Q The data paths 22, which are also collectively or individually referred to herein as memory module 20, are also called data paths 22. In the example shown, memory module 20 may include five data paths 22 (e.g., data paths 221, 222, 223, 224, and 225) located on one side of RCD 50 and five data paths 22 (e.g., data path 22) located on the other side of RCD 50. Q-4 ,twenty two Q-3 ,twenty two Q-2 ,twenty two Q-1 and 22 Q In other embodiments, the memory module 20 may include other arrangements having more or fewer data paths 22 on each side of the RCD 50. Each of the data paths 22 may include corresponding memory channels 421, 422, 423, 424, 425...42 R-4 42 R-3 42 R-2 42 R-1 and 42 R Memory channel 42 is also collectively or individually referred to herein as memory channel 42. Each memory channel 42 may include one or more memory devices in memory device 40. For example, memory channel 421 may include memory devices 401 to 42. s , and memory channel 42 R It may include a memory device 40 T To memory device 40 M .

[0029] The memory controller 80 can be configured to generate various signals, including clock signals (CLK), control signals (ADDR and CMD), and command signals. One or more of the CLK, ADDR, and CMD signals can be provided to the RCD 50 via, for example, one or more buses 23. Signals from the memory controller 80 can also be transmitted from the memory controller 80 to the PMIC 60 via bus 24 (also referred to herein as host interface bus 24). In some embodiments, the host interface bus 24 is bidirectional and configured to transmit commands or other data between the PMIC 60 and the memory controller 80 or other components of the memory module 20. The host interface bus 24 can implement I... 2 C protocol, I 3 C protocol or any other protocol.

[0030] Data bus 72 may be connected between memory controller 80 and data path 22, for example, via data buffer 30, and may include connector 70, such as traces, pins, and other connections, between memory controller 80 and data path 22. Memory controller 80 may generate or receive data signals (e.g., DQa-DQn) and data strobe signals (e.g., DQSa-DQSn), which may be presented to or received from data bus 72. A portion of signals DQa-DQn and signals DQSa-DQSn may be presented to or received from the corresponding data bus 72. In the example shown, each of signals DQa-DQn may have a corresponding signal DQSa-DQSn. In some embodiments, one DQS signal may strobe multiple DQ signals; for example, in some embodiments, one DQS signal strobes four DQ signals.

[0031] RCD 50 can be configured to communicate with memory controller 80, data buffer 30, memory channel 42, and PMIC 60. RCD 50 can be configured to decode instructions, such as control words, received from memory controller 80. For example, RCD 50 can be configured to receive and decode register command words (RCWs). In another example, RCD 50 can be configured to receive and decode buffer control words (BCWs). RCD 50 can be configured to train one or more of the data buffer 30, memory device 40, and command and address lines between RCD 50 and memory controller 80. For example, RCWs can be transferred from memory controller 80 to RCD 50 and used to configure RCD 50.

[0032] In some embodiments, RCD 50 can implement a command / address register, such as a 32-bit 1:2 command / address register. RCD 50 can support a high-speed bus, such as a unidirectional buffered communication (BCOM) bus between RCD 50 and data buffer 30. In some embodiments, RCD 50 can implement automatic impedance calibration, command / address parity checking, control register RCW readback, and a serial bus (e.g., a 1MHz internal integrated circuit (I...). 2 C) bus and 12.5MHz internal integrated circuit (I) 3 C) One or more of the buses. The inputs of the RCD 50 can be pseudo-differential using one or more of the external and internal voltages. The clock output, command / address output, control output, and data buffer control output of the RCD 50 can be grouped and enabled and driven independently with different strengths.

[0033] RCD 50 can be configured to receive CLK signals, ADDR signals, and CMD signals, or other signals (e.g., RCWs and BCWs), from memory controller 80, and is configured to generate corresponding output signals based on the CLK signals, ADDR signals, and CMD signals using various digital logic components. For example, RCD 50 can be configured to generate corresponding signals, such as CLK' signals, ADDR' signals, and CMD' signals, based on the received CLK signals, ADDR signals, and CMD signals. The CLK' signals, ADDR' signals, and CMD' signals can be presented to memory channel 42. For example, the CLK' signal can be transmitted from RCD 50 to memory channel 42 via common bus 25, and the ADDR' signals and CMD' signals can be transmitted from RCD 50 to memory channel 42 via common bus 26. RCD 50 can also be configured to generate one or more data buffer control (DBC) signals, which are transmitted to data buffer 30, for example, via common bus 27 (also referred to herein as data buffer control bus 27).

[0034] Data buffer 30 can be configured to receive commands and data from data buffer control bus 27 and to generate, receive, or send data to and from data bus 72. Each data path 22 also includes a bus 28 between its data buffer 30 and memory channel 42, configured to transfer data between the data buffer 30 and memory channel 42. For example, as Figure 2As shown, data path 221 includes bus 28 between data buffer 301 and memory channel 421. Data buffer 30 is configured to buffer data on bus 72 and bus 28 for write operations (e.g., data transfer from memory controller 80 to the corresponding memory channel 42) and read operations (e.g., data transfer from the corresponding memory channel 42 to memory controller 80).

[0035] In some exemplary embodiments, data buffer 30 exchanges data with memory device 40 via bus 28 in small units (e.g., 4-bit nibbles). In other embodiments, larger or smaller data transfer sizes may be used instead. In some cases, memory devices 40 may be arranged in multiple groups, such as two groups. For example, in a two-group / two-memory-device implementation, such as memory devices 401 and 402, each group may contain a single memory device 40 (e.g., memory device 401 or memory device 402), wherein each memory device 40 is connected to a corresponding data buffer 30 via a high nibble and a low nibble. In a two-group / four-memory-device implementation, each group may contain two memory devices 40. The first group may be connected to a corresponding data buffer 30 via a high nibble, and the second group may be connected to a corresponding data buffer 30 via a low nibble. In a two-group / eight-memory-device implementation, each group may contain four memory devices 40. The first group of four memory devices 40 may be connected to a corresponding data buffer 30 via a high nibble, and the second group of four memory devices may be connected to a corresponding data buffer 30 via a low nibble. Alternatively, other numbers of groups, other numbers of memory devices in each group, and other data unit sizes can be used.

[0036] The memory module 20 may also include an interface 29 configured to enable communication between the RCD 50 and the PMIC 60. For example, interface 29 may be used as part of a register clock driver / power management integrated circuit interface (e.g., an RCD-PMIC interface). Interface 29 is configured to support one or more signals or connections, which may be bidirectional or unidirectional.

[0037] Connector 70 may be an edge connector or a finger connector comprising a plated area formed of a conductive material such as metal. In one embodiment, connector 70 may include a gold-plated area or gold-plated copper pad or trace serving as a contact, and thus may be referred to as a gold finger. In some embodiments, the gold in connector 70 may be an alloy mixed with nickel and cobalt to enhance the gold finger or connector 70. In other embodiments, connector 70 may also be a PCB finger connector comprising additional plated areas formed of conductive metals or various alloys such as silver, tin, and palladium. On the one hand, gold can provide relatively low corrosion resistance and enhanced conductivity, which allows it to form a low-impedance path when used in connector 70, resulting in relatively fast signal transmission.

[0038] When data and signals are exchanged between memory module 20 and controller 80, unwanted electromagnetic coupling generated between the conductive paths of the connectors can cause signal crosstalk. Unwanted electromagnetic coupling can occur because the conductive paths are not in physical contact with each other. Traditional methods for reducing signal crosstalk between signals in high data rate memory systems (such as memory systems implementing DDR6 memory channel designs) include back-drilling in the PCB, adding more ground grid array (BGA) balls, adding more ground vias, having more trace space to isolate interference and affected sources, and embedding capacitors in DIMM PCBs or planar grid array (LGA) areas. However, these traditional methods all have their drawbacks. For example, embedding capacitors in DIMM PCBs or LGA areas occupies package or PCB routing space, thus increasing chip size. Furthermore, if larger capacitance is required, larger capacitors or more capacitors may need to be embedded, which also increases chip size. The addition of BGA balls, ground vias, and more space also increases chip size.

[0039] As will be described in more detail below, capacitors can be embedded in the finger connectors described herein. In one aspect, connector 70 comprises multiple layers, and a plated area including metal contacts may be located on one of the layers, while plated capacitors may be embedded in other layers. Embedding capacitors in connector 70 allows some connectors (e.g., paired and / or adjacent connectors) to be physically connected via the embedded capacitors, and this physical connection can reduce signal crosstalk between conductive paths in connector 70. Because capacitors embedded in connector 70 do not occupy package areas, PCB wiring areas, or LGA areas, and no additional components are required on the PCB, they do not increase chip size. Furthermore, the available space in the connector can accommodate relatively large capacitors. Further, since the finger connector is located in a discontinuous area from the high-speed signal transmission area, embedding capacitors in the finger connector to reduce signal crosstalk can improve signal integrity when signals enter the high-speed signal transmission area through the finger connector. Moreover, because the package area and PCB area where capacitors can be embedded may be limited, embedding capacitors in the finger connector is relatively simpler compared to embedding capacitors in the package area and PCB area. The total capacitance of a DIMM module can be adjusted to meet different application requirements, such as by embedding different numbers of capacitors or capacitors of different sizes in the finger connectors without changing the chip design, whereas changing the capacitance in traditional methods may require changing the chip design.

[0040] Figure 3 This is a diagram of a semiconductor device including an embedded capacitor in a finger connector for crosstalk cancellation in one embodiment. Figure 3 The description can be found here. Figure 1 and Figure 2 The components shown. Figure 3 A three-dimensional (3D) view of package 300 is shown. Package 300 may be a semiconductor package that houses various circuit components, including integrated circuits (ICs), and various active and passive electronic components mounted on a PCB within package 300. Multiple connectors 302 may be connected to package 300. When package 300 is connected to another device via connectors 302, connectors 302 provide conductive paths for the components within package 300 to exchange signals with the connected device. In one embodiment, package 300 may be one of DIMM modules 20, and connectors 302 may be... Figure 1 and Figure 2The connector 70 is shown. Each of the connectors 302 may include multiple layers, with the combined thickness of the multiple layers being 310. For example, the thickness 310 may be approximately 15 micrometers to 50 micrometers. One or more connectors in connector 302 may embed capacitors, and the connectors with embedded capacitors may be physically connected to specific connectors in connector 302 to reduce signal crosstalk. Details of the multiple layers and embedded capacitors in connector 302 will be shown and described in more detail below.

[0041] Figure 4 This is a diagram illustrating an example implementation of an embedded capacitor in a finger connector for crosstalk cancellation in one embodiment. Figure 4 The description can be found here. Figures 1 to 3 The components shown. In Figure 4 In the illustrated embodiment, connector 302 may include four layers 410, 420, 430, and 440. Layer 410, which may be referred to as the top layer or first layer, may include a plate 414 and a void area 416. Plate 414 may be a metal plate, such as a gold plate, applied over signal traces 412. Plate 414 may be applied using various techniques, such as through-hole plating or surface mounting. Plate 414 may cover the area on the first layer 410 that contacts connector 302 to ensure reliable conductivity. Trace 412 may be, for example, a copper trace printed on a substrate or PCB of the first layer 410. Trace 412 may be a differential clock address (DCA) signal trace for exchanging (e.g., sending and receiving) signals, such as DCA signals or other signals, between package area 300 and an external device connected via connector 302. Void area 416 may be a substrate or PCB forming the first layer 410 and may include through-holes for connecting the first layer 410 to the other layers 420, 430, and 440.

[0042] Layer 420, which may be referred to as the second layer, may include a ground region 422, a trace 424, a metal patch 426, and an unused region 428. The ground region 422 may be formed of a conductive material such as copper. The ground region 422 may include two segments, one on each side of the trace 424 (e.g., in the -x direction and the x direction). The ground region 422 may be disconnected from or not overlapped with the trace 424. The trace 424 may be connected to or overlapped with the metal patch 426. The trace 424 may be formed of a conductive material such as copper. The metal patch 426 may be formed of a conductive material such as copper. Because the metal patch 426 is located below the plate 414 (e.g., in the -z direction) and the metal patch 426 is disconnected from or not physically connected to the plate 414, the metal patch 426, or a combination of the trace 424 and the metal patch 426, may form a parallel capacitor with the plate 414 in the first layer 410. The parallel capacitor formed by the metal patch 426 and the plate 414 can be a capacitor embedded in the connector 302. The empty area 428 can be a substrate or PCB forming the second layer 420 and can include through holes for connecting the second layer 420 to the other layers 410, 430, 440.

[0043] Layer 430, which may be referred to as the third layer, may include a ground region 432 and an empty region 434. The ground region 432 may be formed of a conductive material such as copper. The empty region 434 may be a substrate or PCB forming the third layer 420 and may include vias for connecting the third layer 430 to other layers 410, 420, and 440. Layer 440, which may be referred to as the fourth layer, may include a ground region 442 and an empty region 444. The ground region 442 may be formed of a conductive material such as copper. The empty region 444 may be a substrate or PCB forming the third layer 420 and may include vias for connecting the fourth layer 440 to other layers 410, 420, and 430. In one aspect, the second layer in a conventional connector may be... Figure 4 The third layer 430 shown is the same, and the third layer in a conventional connector can be the same as... Figure 4 The fourth layer 440 shown is the same. However, in Figure 4 In the embodiment shown, the vacant area 434 is enlarged and the ground area 432 is reduced in order to reduce the parallel capacitance between the metal patch 426 and ground.

[0044] Figure 5A and Figure 5B This is a diagram illustrating an example connection of a connector with an embedded capacitor in a finger connector for eliminating crosstalk in one embodiment. Figure 5A and Figure 5B The description can be found here. Figures 1 to 4 The components shown. In Figure 5AIn the exemplary embodiment shown, connector 302a among the plurality of connectors may include a first layer 510, a second layer 520, a third layer 530, and a fourth layer 540. The second layer 520 of connector 302 may not have a metal patch 426, therefore connector 302a may not have an embedded capacitor. The first layer 510 of connector 302a and the first layer 410 of connector 302b may include common components, such as a signal trace 412 and a plate 414 applied over the signal trace 412. The second layer 520 of connector 502 may include a ground region and an unused region, similar to... Figure 4 The third layer 430 of connector 302b is shown. Adjacent connectors 302b may have embedded capacitors formed by metal patches 426 and plates 414. To reduce and / or eliminate signal crosstalk between the signal paths of connectors 302a and 302b, signal traces 412 on the first layer 510 of connector 302a may be connected to traces 424 on the second layer 420 of connector 302b. A connection 502, which may be a physical wire, may connect connectors 302a and 302b. The third layer 530 and the fourth layer 540 may include ground areas (similar to ground area 442) and empty areas (similar to empty area 444) formed by a conductive material such as copper. The empty areas in the third layer 530 and the fourth layer 540 may be substrates or PCBs forming the respective layers and may include vias for connecting the respective layers to other layers in connector 302a.

[0045] exist Figure 5B In the exemplary embodiment shown, connector 302c may have an embedded capacitor formed by a metal patch 426 and a plate 414. To reduce and / or eliminate signal crosstalk between the signal paths of connectors 302b and 302c, signal trace 412 on the first layer 410 of connector 302b may be connected to trace 424 on the second layer 420 of connector 302c. A connection 504, which may be a physical wire, may connect connectors 302b and 302c. In one embodiment, Figure 5A and Figure 5B The embodiments shown can be combined such that the first layer 410 of connector 302a can be connected to the trace 424 of the second layer 420 of connector 302b, and the first layer 410 of connector 302b can be connected to the trace 424 of the second layer 420 of connector 302c.

[0046] Figures 6A to 7C This is a diagram of an example connection of a connector with an embedded capacitor in a finger connector for crosstalk cancellation in one embodiment. Figures 6A to 7C The description can be found here. Figures 1 to 5B The components shown. In Figures 6A to 7CIn the illustrated embodiment, multiple connectors 600 can be connected to the package 300. When the package 300 is connected to another device via the connectors 600, the connectors 600 can provide conductive paths for components within the package 300 to exchange signals with the connected device. In one embodiment, connector 302 may be... Figure 1 and Figure 2 The connector 70 is shown. Each connector 600 may include multiple layers, and the thickness of the combined layers is 310 (see [reference]). Figure 3 ).exist Figures 6A to 7C In the illustrated embodiment, a floating structure can be embedded in one or more connectors in connector 600 to connect specific connectors, thereby reducing signal crosstalk. In one aspect, the floating structure in the circuit can be a component or region within a semiconductor device that is not electrically connected to a specific voltage or reference point within the circuit. The floating structures disclosed herein can be used to connect specific connector pairs in connector 600 and are not electrically connected to a voltage or reference point in package 300. Reference Figure 5A and Figure 5B Metal plate 426 is connected to trace 412 of an adjacent connector via trace 424. Since trace 412 is used for signal transmission (e.g., SIG connector) or grounding (e.g., GND connector), trace 412 is connected to a voltage or reference point; therefore, Figure 4 , Figure 5A , Figure 5B The embodiments shown can be non-floating structures.

[0047] Connector 600 may include an arrangement of at least one ground connector GND1 to ground connector GND5 and at least one signal connector SIG1 to ground connector SIG4. Figures 6A to 7C In the exemplary embodiment shown, the ground connector and signal connector in connector 600 are arranged in an alternating manner (e.g., GND, SIG, GND, SIG, etc.). In other embodiments (not shown), the ground connector and signal connector in connector 600 may be arranged in other arrangements and / or sequences. The ground connector in connector 600 provides a ground connection between components in package 300 and external devices connected to package 300 via connector 600. The signal connector in connector 600 can be used to transmit signals and / or data between package 300 and external devices connected to package 300 via connector 600.

[0048] exist Figure 6AIn the exemplary embodiment shown, multiple floating structures 602, 604, and 606 can be connected to the second-layer signal connectors to reduce signal crosstalk between signal connectors 600. Floating structure 602 can connect signal connectors SIG1 and SIG2. Floating structure 604 can connect signal connectors SIG2 and SIG3. Floating structure 606 can connect signal connectors SIG3 and SIG4. Figure 6B In the exemplary embodiment shown, floating structure 602 and floating structure 606 are illustrated. Figure 6A and Figure 6B The embodiments illustrate different numbers of floating structures that can be used to provide different capacitances to reduce varying amounts of signal crosstalk between connectors 600.

[0049] like Figure 6C As shown, each connector 600 may include a first layer 610, a second layer 620, a third layer 630, and a fourth layer 640. The first layer 610 can be connected to... Figure 4 , Figure 5A and Figure 5B The first layer 410 shown is the same as the first layer 510. Each of the second layer 620, the third layer 630, and the fourth layer 640 may include a grounding region formed of a conductive material such as copper (similar to...). Figure 4 The grounding area 442) and the vacant area (similar to) Figure 4 Empty areas 444 in the second layer 620, the third layer 630 and the fourth layer 640 can be substrates or PCBs forming the respective layers and can include through holes for connecting the respective layers to other layers in the same connector.

[0050] When the signal connector in connector 600 is not connected via a floating structure, the second layer 620 of the signal connector can be the same as the second layer of any grounding connector in connector 600, for example, having a grounding area and an empty area. When the signal connector in connector 600 is connected via a floating structure, in addition to the grounding area and empty area, the second layer 620 of the signal connector may also include at least a portion of the floating structure, such as the end and / or connecting portion of the floating structure. For example, in Figure 6C In this configuration, the floating structure can connect two signal connectors (SIG), with one ground connector (GND) located between the two signal connectors. The floating structure can be... Figure 6A , Figure 6B One of the floating structures 602, 604, and 606 shown. Figure 6CThe floating structure shown may include ends 622 and 624 and a connecting portion 626. End 622 may be located on the second layer of one of the two SIG connectors, and end 624 may be located on the other of the two SIG connectors. Connecting portion 626 may connect ends 622 and 624.

[0051] Ends 622 and 624 can be conductive regions formed of a conductive material such as copper. Since ends 622 and 624 are located below (e.g., in the -z direction) and disconnected from their corresponding plates 414, they can form parallel capacitors with their corresponding plates 414 in the first layer 410. The parallel capacitors formed by ends 622 and 624 and their corresponding plates 414 can be capacitors embedded in two signal connectors. Ends 622 and 624 can have various sizes and shapes depending on the desired capacitance of the embedded capacitor. Furthermore, the ends of different floating structures can have different sizes and shapes. For example, end 622 of floating structure 602 can have different dimensions than end 622 of floating structure 604. Connector 626 can be formed of a conductive material such as copper. In one embodiment, connector 626 can be a wire or trace connecting ends 622 and 624. In one embodiment, the second layer 620 of the GND connector between the two SIG connectors may include a relatively large unused area (e.g., a non-shaded / white portion) such that the connection portion 626 does not come into contact with the ground when crossing the second layer of the GND connector.

[0052] exist Figure 7A In the exemplary embodiment shown, multiple floating structures 702, 704, and 706 can be connected to the second-layer signal connectors to reduce signal crosstalk between signal connectors 600. Floating structure 702 can connect signal connectors SIG1 and SIG2. Floating structure 704 can connect signal connectors SIG2 and SIG3. Floating structure 706 can connect signal connectors SIG3 and SIG4. Figure 7B In the exemplary embodiment shown, floating structures 702 and 706 are illustrated. Figure 7A and Figure 7B The embodiments illustrate different numbers of floating structures, which can be used to provide different capacitances to reduce different amounts of signal crosstalk between connectors 600.

[0053] Figure 7C A floating structure including ends 722, 724 and connecting portion 726 is shown. Figure 7C The floating structure shown can be Figure 7A , Figure 7BOne of the floating structures 702, 704, and 706 is shown. End 722 may be located on the second layer of one of the two SIG connectors, and end 724 may be located on the other of the two SIG connectors. Connector 726 may connect ends 722 and 724. In one embodiment, the second layer 620 of the GND connector between the two SIG connectors may include a relatively large unused area (e.g., a non-shaded / white portion) such that connector 726 does not contact ground when crossing the second layer of the GND connector. Ends 722 and 724 may be conductive areas formed of a conductive material such as copper. Since ends 722 and 724 are located below (e.g., in the -z direction) and disconnected from their corresponding plates 414, ends 722 and 724 may form parallel capacitors with their corresponding plates 414 in the first layer 410. The parallel capacitors formed by ends 722 and 724 and their corresponding plates 414 may be capacitors embedded in the two signal connectors. Depending on the required capacitance of the embedded capacitor, the ends 722 and 724 can have various sizes and shapes. Furthermore, the ends of different floating structures can have different sizes and shapes. Figures 6A to 6C Compared to the illustrated embodiment, the ends 722 and 724 can be flat metal plates with a rectangular shape printed on the second layer 620, while the ends 622 and 624 have a circular shape and can be button-type conductive structures deposited on the second layer 620. In some embodiments, the ends 622 and 624 can also be metal plates printed on the second layer 620.

[0054] The semiconductor devices disclosed herein may include connectors, such as finger connectors or gold fingers. The connectors may include conductive structures, such as a metal plate with an intermediate layer (e.g., below a first or top layer), to form embedded capacitors within the connector. Embedded capacitors in different connectors may be physically connected to reduce unwanted coupling between connectors. Embedded capacitors may be located via non-floating structures (such as...) Figures 4 to 5B (as shown) or floating structures (such as) Figures 6A to 7C (As shown) connection. Furthermore, the reduced unwanted coupling can be controlled by varying the number of embedded capacitors and by using non-floating or floating structures of different sizes and shapes. Additionally, the embedded capacitors in the connector do not occupy package or PCB space within the chip (e.g., in package 300).

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “described” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprising” and / or “including” are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0056] All means or steps plus functional elements (if any) in the appended claims are intended to include any structure, material, action, and equivalent that, in combination with other claimed elements, perform the function. The embodiments disclosed herein are presented for illustrative and descriptive purposes and are not intended to be exhaustive or to limit the invention to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described to best explain the principles and practical application of the invention and to enable others skilled in the art to understand the various embodiments of the invention with various modifications suitable for the intended particular use.

Claims

1. A semiconductor device, comprising: A semiconductor package, the semiconductor package comprising multiple circuits; and A plurality of connectors are configured to facilitate signal transmission between the semiconductor package and the device when the semiconductor package is connected to the device via the plurality of connectors, and wherein: At least the first connector of the plurality of connectors has a capacitor embedded in it; and The capacitor embedded in the first connector is connected to the second connector among the plurality of connectors.

2. The semiconductor device according to claim 1, wherein, The multiple connectors are gold finger connectors.

3. The semiconductor device according to claim 1, wherein, The capacitor embedded in the first connector is a capacitor formed by the following parts: A first metal plate on a first layer of the first connector, the first layer of the first connector including signal traces; and The second metal plate on the second layer of the first connector, wherein the second layer of the first connector is located below the first layer of the first connector.

4. The semiconductor device according to claim 3, wherein, The second metal plate in the second layer of the first connector is connected to the metal plate on the first layer of the second connector.

5. The semiconductor device according to claim 3, wherein: The third layer of the first connector includes an empty area and a grounding area; The vacant area is larger than the grounded area; and The third layer of the first connector is located below the second layer of the first connector.

6. The semiconductor device according to claim 3, wherein, The first connector and the second connector are adjacent to each other.

7. The semiconductor device according to claim 1, wherein: The capacitor embedded in the first connector is a capacitor formed by the following parts: A first metal plate on a first layer of the first connector, the first layer of the first connector including signal traces; and The first conductive area on the second layer of the first connector, wherein the second layer of the first connector is located below the first layer of the first connector; The second connector has an embedded capacitor, which consists of the following components: The second metal plate on the first layer of the second connector, wherein the first layer of the second connector includes another signal trace; and The second conductive region on the second layer of the second connector, wherein the second layer of the second connector is located below the first layer of the second connector; and The first conductive region is connected to the second conductive region to form a floating structure, and the floating structure connects the first connector and the second connector.

8. The semiconductor device according to claim 7, wherein, The third connector of the plurality of connectors is located between the first connector and the second connector.

9. A memory module, comprising: Multiple memory devices; A plurality of connectors, the plurality of connectors being configured to facilitate signal transmission between the plurality of memory devices and the device when the plurality of memory devices are connected to the device via the plurality of connectors, wherein: At least the first connector of the plurality of connectors has a capacitor embedded in it; and The capacitor embedded in the first connector is connected to the second connector among the plurality of connectors.

10. The memory module according to claim 9, wherein, The plurality of connectors are finger connectors.

11. The memory module according to claim 9, wherein, The multiple connectors are gold finger connectors.

12. The memory module according to claim 9, wherein, The capacitor embedded in the first connector is a capacitor formed by the following parts: A first metal plate on a first layer of the first connector, the first layer of the first connector including signal traces; and The second metal plate on the second layer of the first connector, wherein the second layer of the first connector is located below the first layer of the first connector.

13. The memory module according to claim 12, wherein, The second metal plate in the second layer of the first connector is connected to the third metal plate in the first layer of the second connector.

14. The memory module according to claim 12, wherein: The third layer of the first connector includes an empty area and a grounding area; The vacant area is larger than the grounded area; and The third layer of the first connector is located below the second layer of the first connector.

15. The memory module according to claim 12, wherein, The first connector and the second connector are adjacent to each other.

16. The memory module according to claim 9, wherein: The capacitor embedded in the first connector is a capacitor formed by the following parts: A first metal plate on a first layer of the first connector, the first layer of the first connector including signal traces; and The first conductive area on the second layer of the first connector, wherein the second layer of the first connector is located below the first layer of the first connector; The second connector has an embedded capacitor, which consists of the following components: The second metal plate on the first layer of the second connector, wherein the first layer of the second connector includes another signal trace; and The second conductive region on the second layer of the second connector, wherein the second layer of the second connector is located below the first layer of the second connector; and The first conductive region is connected to the second conductive region to form a floating structure, and the floating structure connects the first connector and the second connector.

17. The memory module according to claim 16, wherein, The third connector of the plurality of connectors is located between the first connector and the second connector.

18. A structure comprising: Multiple connectors, said multiple connectors including at least a first connector and a second connector, wherein: The first connector includes at least a first layer and a second layer located below the first layer; The first layer of the first connector includes a signal trace and a metal plate applied above the signal trace; The second layer of the first connector includes a conductive region that forms a capacitor with the metal plate on the first layer of the first connector; and The capacitor is connected to the second connector.

19. The structure according to claim 18, wherein: The conductive region in the second layer of the first connector is connected to a metal plate on the first layer of the second connector; The third layer of the first connector includes an empty area and a grounding area; The vacant area is larger than the grounded area; as well as The third layer of the first connector is located below the second layer of the first connector.

20. The structure according to claim 18, wherein: The second connector includes at least another first layer and another second layer located below the other first layer; The first layer of the second connector includes another signal trace and another metal plate applied above the other signal trace; The second layer of the second connector includes another conductive region, which forms another capacitor with the metal plate on the first layer of the second connector; as well as The conductive region in the second layer of the first connector is connected to the conductive region in the second layer of the second connector to form a floating structure, the floating structure connecting the first connector and the second connector.

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