Semiconductor device

Abstract

The semiconductor device includes: a first impurity region, a second impurity region, and a third impurity region formed in a chip; the groove is formed in the chip; a trench insulating film formed on the inner surface of the trench; a conductive embedded body that is embedded in the trench; and an electric field buffer layer formed at the bottom of the trench, the electric field buffer layer including: a first layer formed away from the bottom of the trench toward the second main surface side and having a first impurity concentration; and a second layer formed between the first layer and the bottom of the trench and having a second impurity concentration higher than the first impurity concentration.

Description

[0001] Related applications

[0002] This application corresponds to Japanese Patent Application No. 2023-173681, filed with the Japan Patent Office on October 5, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device. Background Technology

[0004] Patent document 1 discloses an electronic device having an impurity region of a silicon carbide layer introduced by a channel effect implantation method.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: U.S. Patent Application Publication No. 2015 / 0028351 Summary of the Invention

[0008] One embodiment of this disclosure provides a semiconductor device, comprising: a chip having a first main surface and a second main surface opposite thereto; a first impurity region of a first conductivity type formed on a surface portion of the first main surface; a second impurity region of a second conductivity type formed on a surface portion of the first impurity region; a third impurity region of a first conductivity type formed on a surface portion of the second impurity region; a trench extending from the first main surface through the third impurity region and the second impurity region to the first impurity region; a trench insulating film formed on an inner surface of the trench; a conductive embedded body disposed in the trench through the trench insulating film; and an electric field buffer layer of a second conductivity type formed at the bottom of the trench, the electric field buffer layer comprising: a first layer formed extending from the bottom of the trench toward the second main surface and having a first impurity concentration; and a second layer formed between the first layer and the bottom of the trench and having a second impurity concentration higher than the first impurity concentration. Attached Figure Description

[0009] Figure 1 This is a top view of a semiconductor device according to one embodiment of the present disclosure.

[0010] Figure 2 It is along Figure 1 The cross-sectional view along line II-II shown.

[0011] Figure 3 This is a top view showing an example of chip layout.

[0012] Figure 4This is a 3D diagram showing an example of chip layout.

[0013] Figure 5 It is a three-dimensional diagram showing the active region and trench structure.

[0014] Figure 6 It is along Figure 5 The sectional view along line VI-VI is shown.

[0015] Figure 7 It is along Figure 5 The sectional view along line VII-VII shown.

[0016] Figure 8 Is with Figure 6 The same sectional view is a diagram that mainly shows the dimensions of each part.

[0017] Figure 9 Is with Figure 7 The same sectional view is a diagram that mainly shows the dimensions of each part.

[0018] Figure 10 This is a schematic diagram showing the wafer used in the manufacture of the aforementioned semiconductor device.

[0019] Figure 11 This is a flowchart illustrating an example of a method for manufacturing a semiconductor device.

[0020] Figure 12A This is a diagram illustrating a part of the manufacturing process of the aforementioned semiconductor device, showing... Figure 6 The corresponding cross-section.

[0021] Figure 12B This is a diagram illustrating a part of the manufacturing process of the aforementioned semiconductor device, showing... Figure 7 The corresponding cross-section.

[0022] Figure 13A It means Figure 12A Diagram of the subsequent processes.

[0023] Figure 13B It means Figure 12B Diagram of the subsequent processes.

[0024] Figure 14A It means Figure 13A Diagram of the subsequent processes.

[0025] Figure 14B It means Figure 13B Diagram of the subsequent processes.

[0026] Figure 15A It means Figure 14A Diagram of the subsequent processes.

[0027] Figure 15B It means Figure 14B Diagram of the subsequent processes.

[0028] Figure 16A It means Figure 15A Diagram of the subsequent processes.

[0029] Figure 16B It means Figure 15B Diagram of the subsequent processes.

[0030] Figure 17A It means Figure 16A Diagram of the subsequent processes.

[0031] Figure 17B It means Figure 16B Diagram of the subsequent processes.

[0032] Figure 18A It means Figure 17A Diagram of the subsequent processes.

[0033] Figure 18B It means Figure 17B Diagram of the subsequent processes.

[0034] Figure 19A It means Figure 18A Diagram of the subsequent processes.

[0035] Figure 19B It means Figure 18B Diagram of the subsequent processes.

[0036] Figure 20A It means Figure 19A Diagram of the subsequent processes.

[0037] Figure 20B It means Figure 19B Diagram of the subsequent processes.

[0038] Figure 21A It means Figure 20A Diagram of the subsequent processes.

[0039] Figure 21B It means Figure 20B Diagram of the subsequent processes.

[0040] Figure 22A It means Figure 21A Diagram of the subsequent processes.

[0041] Figure 22B It means Figure 21B Diagram of the subsequent processes.

[0042] Figure 23A It means Figure 22A Diagram of the subsequent processes.

[0043] Figure 23B It means Figure 22B Diagram of the subsequent processes.

[0044] Figure 24A It means Figure 23A Diagram of the subsequent processes.

[0045] Figure 24B It means Figure 23B Diagram of the subsequent processes.

[0046] Figure 25A It means Figure 24A Diagram of the subsequent processes.

[0047] Figure 25B It means Figure 24B Diagram of the subsequent processes.

[0048] Figure 26A It means Figure 25A Diagram of the subsequent processes.

[0049] Figure 26B It means Figure 25B Diagram of the subsequent processes.

[0050] Figure 27A It means Figure 26A Diagram of the subsequent processes.

[0051] Figure 27B It means Figure 26B Diagram of the subsequent processes.

[0052] Figure 28A It means Figure 27A Diagram of the subsequent processes.

[0053] Figure 28B It means Figure 27B Diagram of the subsequent processes.

[0054] Figure 29A It means Figure 28A Diagram of the subsequent processes.

[0055] Figure 29B It means Figure 28B Diagram of the subsequent processes.

[0056] Figure 30A It means Figure 29A Diagram of the subsequent processes.

[0057] Figure 30B It means Figure 29B Diagram of the subsequent processes.

[0058] Figure 31 Another embodiment of the semiconductor device is related to Figure 5The corresponding 3D image.

[0059] Figure 32 Another embodiment of the semiconductor device is related to Figure 7 The corresponding sectional view.

[0060] Figure 33 Another embodiment of the semiconductor device is related to Figure 5 The corresponding 3D image.

[0061] Figure 34 Another embodiment of the semiconductor device is related to Figure 5 The corresponding 3D image.

[0062] Figure 35 It is along Figure 34 The cross-sectional view shown along line AA.

[0063] Figure 36 It is along Figure 34 The sectional view shown is along the BB line.

[0064] Figure 37 Another embodiment of the semiconductor device is related to Figure 7 The corresponding sectional view.

[0065] Figure 38 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0066] Figure 39 Another embodiment of the semiconductor device is related to Figure 7 The corresponding sectional view.

[0067] Figure 40 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0068] Figure 41 Another embodiment of the semiconductor device is related to Figure 7 The corresponding sectional view.

[0069] Figure 42 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0070] Figure 43 Another embodiment of the semiconductor device is related to Figure 7 The corresponding sectional view.

[0071] Figure 44 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0072] Figure 45 Another embodiment of the semiconductor device is related to Figure 7 The corresponding sectional view.

[0073] Figure 46 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0074] Figure 47 Another embodiment of the semiconductor device is related to Figure 7 The corresponding sectional view.

[0075] Figure 48 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0076] Figure 49 Another embodiment of the semiconductor device is related to Figure 7 The corresponding sectional view.

[0077] Figure 50 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0078] Figure 51 Another embodiment of the semiconductor device is related to Figure 7 The corresponding sectional view.

[0079] Figure 52 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0080] Figure 53 Another embodiment of the semiconductor device is related to Figure 7 The corresponding sectional view.

[0081] Figure 54 Another embodiment of the semiconductor device is related to Figure 5 The corresponding 3D image.

[0082] Figure 55 Another embodiment of the semiconductor device is related to Figure 5 The corresponding 3D image.

[0083] Figure 56 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0084] Figure 57 Another embodiment of the semiconductor device is related to Figure 5 The corresponding 3D image.

[0085] Figure 58Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0086] Figure 59 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0087] Figure 60 Another embodiment of the semiconductor device is related to Figure 7 The corresponding sectional view.

[0088] Figure 61 Another embodiment of the semiconductor device is related to Figure 5 The corresponding 3D image.

[0089] Figure 62 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0090] Figure 63 Another embodiment of the semiconductor device is related to Figure 7 The corresponding sectional view.

[0091] Figure 64 Another embodiment of the semiconductor device is related to Figure 5 The corresponding 3D image.

[0092] Figure 65 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0093] Figure 66 Another embodiment of the semiconductor device is related to Figure 5 The corresponding 3D image.

[0094] Figure 67 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view.

[0095] Figure 68 Another embodiment of the semiconductor device is related to Figure 5 The corresponding 3D image.

[0096] Figure 69 Another embodiment of the semiconductor device is related to Figure 6 The corresponding sectional view. Detailed Implementation

[0097] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0098] The accompanying drawings are schematic diagrams and not strictly illustrative; scales, ratios, angles, etc., may not be consistent. Corresponding structures in the accompanying drawings are labeled with the same reference symbols, and repeated descriptions are omitted or simplified. For structures where descriptions are omitted or simplified, the descriptions preceding the omission or simplification shall apply.

[0099] When the term "substantially" is used in this specification, it includes not only the numerical value (shape) that is equal to the numerical value (shape) of the comparison object, but also a numerical error (shape error) within a range of ±10% based on the numerical value (shape) of the comparison object. In the following description, terms such as "first," "second," and "third" are used, but these are notations assigned to the names of each structure to clarify the order of description, and are not intended to define the essence of the names of each structure.

[0100] In the following description, "p-type" or "n-type" is used to refer to the conductivity type of the semiconductor (impurity), but "n-type" can also be called the "first conductivity type" and "p-type" the "second conductivity type." "n-type" is a conductivity type derived from pentavalent elements, and "p-type" is a conductivity type derived from trivalent elements. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0101] [Overall structure of semiconductor device 1]

[0102] Figure 1 This is a top view showing a semiconductor device 1 according to an embodiment of the present disclosure. Figure 2 It is along Figure 1 The cross-sectional view along line II-II shown. Figure 3 This is a top view showing a layout example of chip 2. Figure 4 This is a 3D view showing a layout example of chip 2.

[0103] Reference Figures 1 to 4 The semiconductor device 1 includes a chip 2 comprising a SiC single crystal. The chip 2 may also be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, the chip 2 is composed of a hexagonal SiC single crystal and is formed into a cuboid shape. Hexagonal SiC single crystals have various polymorphs, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example of the chip 2 being composed of a 4H-SiC single crystal is shown, but the chip 2 can also be composed of other polymorphs.

[0104] Chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are quadrilaterals when viewed from above in the vertical direction Z (hereinafter referred to as "top view"). The vertical direction Z is also the thickness direction of chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 can also be squares or rectangles when viewed from above.

[0105] The first main surface 3 and the second main surface 4 are preferably formed from the c-plane of a SiC single crystal. In this case, the first main surface 3 is preferably formed from the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed from the carbon surface ((000-1) surface) of the SiC single crystal.

[0106] In the circumference of chip 2, starting from the first side 5A (in) Figure 1 On the first main surface 3 (counterclockwise), the second side 5B is connected to the first side 5A, the third side 5C is connected to the second side 5B, and the fourth side 5D is connected to both the first side 5A and the third side 5C. The first side 5A and the third side 5C extend along the first main surface 3 in a first direction X and are opposite each other in a second direction Y that intersects (specifically, is orthogonal) the first direction X. The second side 5B and the fourth side 5D extend in the second direction Y and are opposite each other in the first direction X.

[0107] In this method, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X can be the a-axis direction of the SiC single crystal, and the second direction Y can be the m-axis direction of the SiC single crystal.

[0108] The XY plane, including the first direction X and the second direction Y, forms a horizontal plane orthogonal to the vertical direction Z. Hereinafter, the axis extending along the vertical direction Z will sometimes be referred to as the "vertical axis". Additionally, hereafter, the first direction X and the second direction Y will sometimes be referred to as the "horizontal direction". The horizontal direction is also the direction extending along the first main plane 3.

[0109] Reference Figure 4 Chip 2 (first main surface 3 and second main surface 4) has a deviation angle θo that is tilted at a predetermined angle relative to the c-plane of the SiC single crystal in a predetermined deviation direction Do. That is, the amount by which the c-axis ((0001) axis) of the SiC single crystal is tilted from the vertical axis toward the deviation direction Do by the deviation angle θo. In addition, the amount by which the c-plane of the SiC single crystal is tilted relative to the horizontal plane by the deviation angle θo.

[0110] The deviation direction Do is preferably the a-axis direction (i.e., the second direction Y) of the SiC single crystal. The deviation angle θo can also be greater than 0° and less than 10°. The deviation angle θo can have any value within any of the following ranges: greater than 0° and less than 1°, greater than 1° and less than 2.5°, greater than 2.5° and less than 5°, greater than 5° and less than 7.5°, and greater than 7.5° and less than 10°.

[0111] The deviation angle θo is preferably 5° or less. Particularly preferred is 2° or more and 4.5° or less. The deviation angle θo is typically set in the range of 4° ± 0.1°. Of course, this specification does not exclude the possibility of a deviation angle θo of 0° (i.e., the first main surface 3 being the front face relative to surface c).

[0112] Chip 2 includes an n-type base layer 6 made of SiC single crystal. The base layer 6 can also be referred to as a "drain region," "base SiC layer," or simply "base region." The base layer 6 extends in a layered manner in the horizontal direction, forming a portion of the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this configuration, the base layer 6 is made of a SiC single crystal substrate (i.e., a SiC substrate). The base layer 6 has the aforementioned offset direction Do and offset angle θo.

[0113] The base layer 6 can also have 1×10 18 cm -3 Above and 1×10 21 cm -3 The following n-type impurity concentrations are taken as peak values. The base layer 6 preferably has a substantially constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted using a single type of pentavalent element. The n-type impurity concentration of the base layer 6 is particularly preferably adjusted using a pentavalent element other than phosphorus. In this method, the n-type impurity concentration of the base layer 6 is adjusted using nitrogen.

[0114] The base layer 6 has a first thickness T1. The first thickness T1 can be 5 μm or more and 300 μm or less. Preferably, the first thickness T1 is 50 μm or more and 250 μm or less.

[0115] Chip 2 includes a SiC single-crystal semiconductor layer 7 stacked on the base layer 6. The semiconductor layer 7, as an example of a first impurity region, may also be referred to as a "drift region," "SiC layer," or "semiconductor region." The semiconductor layer 7 extends horizontally in a layered manner, forming a first main surface 3 and portions of the first to fourth side surfaces 5A to 5D. The semiconductor layer 7 is composed of an epitaxial layer (i.e., a SiC epitaxial layer) crystallized and grown from the base layer 6.

[0116] Semiconductor layer 7 has a lower end and a higher end. The lower end of semiconductor layer 7 is the starting point of crystal growth, and the upper end of semiconductor layer 7 is the ending point of crystal growth. The lower end of semiconductor layer 7 is also the bottom of semiconductor layer 7. Since semiconductor layer 7 is continuously crystallized and grown from base layer 6, the lower end of semiconductor layer 7 coincides with the upper end of base layer 6.

[0117] Semiconductor layer 7 includes an n-type drift region 8. In this configuration, the drift region 8 is formed from a portion (n-type portion) of semiconductor layer 7.

[0118] The boundary between the base layer 6 and the semiconductor layer 7 may not be visually identifiable, but can be evaluated and / or determined indirectly based on other structures and elements. The semiconductor layer 7 has a deviation direction Do and a deviation angle θo that are approximately the same as those of the base layer 6.

[0119] The semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 can be 1 μm or more and 10 μm or less. Preferably, the second thickness T2 is 2 μm or more and 8 μm or less.

[0120] Semiconductor device 1 includes an active region 9 disposed on chip 2. The active region 9 is disposed within chip 2 at intervals from the periphery (first to fourth sides 5A to 5D) of chip 2 when viewed from above. The active region 9 is configured to have a polygonal shape (in this case, a quadrilateral shape) with four sides parallel to the periphery of chip 2 when viewed from above. The planar area of ​​the active region 9 is preferably 50% or more and 90% or less of the planar area of ​​the first main surface 3.

[0121] Semiconductor device 1 includes an outer peripheral region 10 disposed outside an active region 9 in chip 2. Viewed from above, the outer peripheral region 10 is disposed in the region between the periphery of chip 2 and the active region 9. Viewed from above, the outer peripheral region 10 extends in a strip along the active region 9 and is configured as a polygonal ring (in this case, a quadrilateral ring) surrounding the active region 9.

[0122] The semiconductor device 1 includes a plurality of trench structures 11 of the trench electrode type formed in the active region 9 on the first main surface 3. The trench structure 11 may also be referred to as a "gate structure", "trench gate structure", etc. A gate potential, which serves as a control potential, is assigned to the plurality of trench structures 11.

[0123] Multiple trench structures 11 are arranged at intervals from the periphery of the active region 9 inward. In this configuration, the multiple trench structures 11 are arranged at intervals in the first direction X, and are respectively formed as strips extending in the second direction Y. That is, the multiple trench structures 11 are arranged at intervals in the m-axis direction and extend in the a-axis direction.

[0124] Furthermore, in this configuration, multiple trench structures 11 are arranged in a stripe-like pattern extending along the a-axis direction (second direction Y). The extension direction of the multiple trench structures 11 is consistent with the offset direction Do of the semiconductor layer 7. The multiple trench structures 11 are formed at intervals from the lower end (base layer 6) of the semiconductor layer 7 toward the first main surface 3, and are opposed to the base layer 6 across a portion of the semiconductor layer 7.

[0125] The semiconductor device 1 includes a plurality of p-type electric field buffer layers 12 formed at horizontal intervals within the semiconductor layer 7. Specifically, the plurality of electric field buffer layers 12 are formed at the bottom of the trench structure 11.

[0126] The semiconductor device 1 includes a gate pad 13 disposed on a first main surface 3. The gate pad 13 is an electrode to which a gate potential is applied from the outside. The gate pad 13 may also be referred to as a "gate pad electrode", "first pad electrode", etc. The gate pad 13 may also have a stacked structure including a Ti-based metal film and an Al-based metal film sequentially stacked from the side of the first main surface 3.

[0127] In this configuration, the gate pad 13 is disposed on the active region 9. Specifically, the gate pad 13 is disposed in the central region of the side closest to the first main surface 3 (in this configuration, the second side surface 5B) when viewed from above. Alternatively, the gate pad 13 can be disposed in any region along the central portion of the first to fourth side surfaces 5A to 5D. Furthermore, the gate pad 13 can be disposed at any corner of the first main surface 3 when viewed from above. Additionally, the gate pad 13 can be disposed in the central portion of the first main surface 3 when viewed from above. In this configuration, the gate pad 13 is formed into a quadrilateral shape when viewed from above.

[0128] The semiconductor device 1 includes at least one (or multiple) gate wirings 14 extending from a gate pad 13 to a first main surface 3. The gate wirings 14 may also be referred to as "wirings," "wiring electrodes," etc. In this configuration, multiple gate wirings 14 are disposed on an active region 9.

[0129] The plurality of gate wirings 14 may also have a stacked structure comprising Ti-based metal films and Al-based metal films sequentially stacked from the first main surface 3. In this configuration, the plurality of gate wirings 14 includes a first gate wiring 14A and a second gate wiring 14B.

[0130] The first gate wiring 14A extends from the gate pad 13 toward the first side surface 5A and extends linearly along the periphery of the first main surface 3 in a manner that intersects (specifically, orthogonally) with a portion (specifically, an end) of the plurality of trench structures 11. The first gate wiring 14A is electrically connected to an end of the plurality of trench structures 11 at a location not shown.

[0131] The second gate wiring 14B is led out from the gate pad 13 toward the third side surface 5C and extends linearly along the periphery of the first main surface 3 in a manner that intersects (specifically, orthogonally) with a portion (specifically, the other end) of the plurality of trench structures 11. The second gate wiring 14B is electrically connected to the other end of the plurality of trench structures 11 at a location not shown.

[0132] Semiconductor device 1 includes a gate pad 13 and a source pad 15, which is disposed on a first main surface 3 at a distance from the gate wiring 14, and serves as an example of a first main surface electrode. The source pad 15 is an electrode to which a source potential is applied from the outside. The source pad 15 may also be referred to as a "source pad electrode," a "second pad electrode," or the like. The source pad 15 may also have a stacked structure comprising Ti-based metal films and Al-based metal films sequentially stacked from the first main surface 3 side.

[0133] In this configuration, the source pad 15 is disposed on the active region 9 when viewed from above. In this configuration, the source pad 15 is formed as a polygon with a recess along the gate pad 13 when viewed from above. Of course, the source pad 15 can also be formed as a quadrilateral shape when viewed from above.

[0134] Semiconductor device 1 includes a drain pad 16 covering a second main surface 4. The drain pad 16 is an electrode to which a drain potential is applied from the outside. The drain pad 16 may also be referred to as a "drain pad electrode", "third pad electrode", etc. The drain pad 16 forms an ohmic contact with the base layer 6 exposed from the second main surface 4.

[0135] The drain pad 16 can also cover the entire area of ​​the second main surface 4 in a manner connected to the periphery of the chip 2 (first to fourth sides 5A to 5D). The drain pad 16 can also cover the second main surface 4 at intervals from the periphery of the chip 2 inward, so that the periphery of the chip 2 is exposed.

[0136] The breakdown voltage that can be applied between the source pad 15 and the drain pad 16 (between the first main surface 3 and the second main surface 4) can be 500V or higher and 3000V or lower. The breakdown voltage can have a value within any of the following ranges: 500V or higher and 1000V or lower, 1000V or higher and 1500V or lower, 1500V or higher and 2000V or lower, 2000V or higher and 2500V or lower, and 2500V or higher and 3000V or lower.

[0137] The semiconductor device 1 includes at least one (preferably two or more and less than 20) p-type field regions 17 formed in the outer peripheral region 10. The number of field regions 17 is typically four or more and less than eight. The field regions 17 are formed in an electrically floating state to buffer the electric field within the chip 2 at the periphery of the first main surface 3. The number, width, depth, p-type impurity concentration, etc., of the field regions 17 are arbitrary and can take various values ​​depending on the electric field to be buffered. In this configuration, the field regions 17 are arranged at intervals from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).

[0138] Multiple field regions 17 are formed as strips extending along the active region 9 when viewed from above. Each of the multiple field regions 17 has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y. In this manner, the multiple field regions 17 are formed as a ring (specifically a quadrilateral ring) surrounding the active region 9 (i.e., multiple electric field buffer layers 12) when viewed from above.

[0139] [Detailed structure of active region 9 of semiconductor device 1]

[0140] Figure 5 This is a three-dimensional diagram representing the active region 9 and the trench structure 11. Figure 6 It is along Figure 5 The sectional view along line VI-VI is shown. Figure 7 It is along Figure 5 The sectional view along line VII-VII shown. Figure 8 Is with Figure 6 The same sectional view is a diagram that mainly shows the dimensions of each part. Figure 9 Is with Figure 7 The same sectional view is a diagram that mainly shows the dimensions of the various parts. Hereafter, to make the accompanying drawings clear, in... Figure 8 as well as Figure 9 The dimensions (thickness, width, depth, etc.) of various parts of semiconductor device 1 are shown in the diagram. Figures 5-7 Illustrations omitted. Figure 8 and Figure 9 In addition to the dimensions of each part, symbols for the main structure are also marked.

[0141] Reference Figures 5-9 The semiconductor device 1 includes a p-type body region 18 formed on the surface portion of the drift region 8. In this configuration, the body region 18, which is an example of a second impurity region, is formed in a layer extending along the first main surface 3. The body region 18 may also be formed over the entire surface portion of the drift region 8, exposed from the first to fourth side surfaces 5A to 5D. (Refer to...) Figure 5 The main region 18 is formed at intervals from the lower end of the semiconductor layer 7 toward the first main surface 3.

[0142] Main region 18 can also have 1×10 15 cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentration is used as the peak value. The p-type impurity concentration in the main body region 18 is preferably adjusted by at least one trivalent element. The trivalent element in the main body region 18 can be at least one of boron, aluminum, gallium, and indium.

[0143] As described above, the semiconductor device 1 includes a trench structure 11. (Refer to...) Figure 8 as well as Figure 9 Each trench structure 11 has a trench width WT in the arrangement direction and a trench depth DT in the vertical direction Z. The trench width WT is preferably less than the second thickness T2 of the semiconductor layer 7 (refer to...). Figure 4 The groove width WT can be greater than 0.1μm and less than 5μm.

[0144] The groove width WT can have a value belonging to any of the following ranges: 0.1 μm and 0.25 μm, 0.25 μm and 0.5 μm, 0.5 μm and 0.75 μm, 0.75 μm and 1 μm, 1 μm and 1.5 μm, 1.5 μm and 2 μm, 2 μm and 2.5 μm, 2.5 μm and 3 μm, 3 μm and 3.5 μm, 3.5 μm and 4 μm, 4 μm and 4.5 μm, and 4.5 μm and 5 μm.

[0145] The trench depth DT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench depth DT is preferably greater than the trench width WT. That is, the plurality of trench structures 11 preferably each have an aspect ratio DT / WT extending in a longitudinal columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The aspect ratio DT / WT can be, for example, 1 or more and 5 or less, preferably 1 or more and 3 or less.

[0146] The trench depth DT can be 0.1 μm or more and 5 μm or less. The trench depth DT can have a value falling within any of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The trench depth DT is preferably 0.1 μm or more and 1.5 μm or less, more preferably 0.5 μm or more and 1.5 μm or less.

[0147] Multiple trench structures 11 are arranged at intervals of trench spacing PT in the first direction X. The trench spacing PT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench spacing PT is preferably less than the trench depth DT. The trench spacing PT can be 0.1 μm or more and 5 μm or less.

[0148] The trench spacing PT can have any value within the range of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The trench spacing PT is preferably 0.5 μm or more and 3 μm or less, and more preferably 0.5 μm or more and 1.5 μm or less.

[0149] Reference Figures 5-7 Each trench structure 11 includes a trench 19, a trench insulating film 20, and an embedded body 21. The trench 19 can also be called a "component trench" or "gate trench". The trench insulating film 20 can also be called a "component insulating film" or "gate insulating film". The embedded body 21 can also be called an "embedded electrode" or "gate electrode".

[0150] Groove 19 is formed on the first main surface 3, dividing the inner surface of the groove structure 11. Figure 6 and Figure 7 (Showing side surface 22 and bottom surface 23). The bottom surface 23 of the trench 19 preferably has a flat extending portion. A mesa surface 24 formed from a portion of the semiconductor layer 7 is formed between adjacent trenches 19. The mesa surface 24 may also be referred to as an "element mesa surface".

[0151] like Figure 5 As shown, the plurality of groove structures 11 (the plurality of grooves 19) and the plurality of platform surfaces 24 are strips extending along the second direction Y, and are arranged alternately in the first direction X. The plurality of grooves 19 and the plurality of platform surfaces 24 are arranged as a whole in a stripe pattern.

[0152] Reference Figure 6 and Figure 7 Preferably, the flat portion of the bottom surface 23 of the groove 19 extends substantially parallel to the first main surface 3. That is, the bottom wall of the groove 19 preferably has a predetermined offset direction Do relative to the c-surface (see reference). Figure 4The trench 19 is tilted at a predetermined angle with an offset angle θo. That is, preferably, the bottom surface 23 of the trench 19 has a flat portion extending along the offset direction Do. Of course, the bottom surface 23 of the trench 19 can also be bent into an arc shape toward the lower end of the semiconductor layer 7.

[0153] The trench insulating film 20 covers the inner surface of the trench 19. The trench insulating film 20 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this configuration, the trench insulating film 20 has a single-layer structure composed of a silicon oxide film. Particularly preferably, the trench insulating film 20 comprises a silicon oxide film composed of the oxide of the chip 2.

[0154] The embedded body 21 is embedded in the trench 19 and faces the trench through the trench insulating film 20. In this configuration, the embedded body 21 faces the main body region 18 through the trench insulating film 20. The embedded body 21 may also comprise p-type or n-type conductive polycrystalline silicon.

[0155] Reference Figure 6 as well as Figure 7 The embedded body 21 is embedded to the middle portion of the trench 19 in the depth direction. The embedded body 21 has an upper surface 25 located on the side of the second main surface 4 relative to the first main surface 3. Between the upper surface 25 of the embedded body 21 and the first main surface 3, a lower step 26 is formed on the side of the second main surface 4. Through this step 26, a groove 27 is formed in the upper part of the trench 19, which is divided by the upper surface 25 of the embedded body 21 and the side surface 22 of the trench 19.

[0156] The groove 27 is the space enclosed by the two sides 22 of the groove 19 and the upper surface 25 of the embedded body 21. For example... Figure 5 As shown, the groove 27 is formed as a continuous strip in the depth direction (second direction Y) of the trench 19. The trench insulating film 20 is selectively formed in the region sandwiched between the inner surface of the trench 19 and the embedded body 21, and the side surface 22 of the groove 27 (a part of the side surface 22 of the trench 19) is exposed from the trench insulating film 20.

[0157] Through the formation of the groove 27, a portion of the platform surface 24 in the depth direction of the groove 19 protrudes as a protrusion 28 further towards the first main surface 3 (upper side) than the embedded body 21. For example... Figure 5 As shown, the protrusion 28 of the table surface 24 is the portion of the table surface 24 sandwiched between adjacent grooves 27, and is formed as a continuous strip in the depth direction of the groove 19.

[0158] As described above, the semiconductor device 1 includes an electric field buffer layer 12. The electric field buffer layer 12 is formed at the bottom of the trench structure 11. More specifically, the electric field buffer layer 12 is formed at the bottom of the trench 19. The electric field buffer layer 12 is exposed from the bottom surface 23 of the trench 19 and is in contact with the trench insulating film 20. Therefore, the upper end of the electric field buffer layer 12 is exposed at the bottom surface 23 of the trench structure 11 (trench 19).

[0159] The electric field buffer layer 12 is positioned opposite the embedded body 21 across the trench insulating film 20 in the depth direction of the trench 19. At the bottom of the trench 19, the trench insulating film 20 is sandwiched between the embedded body 21 and the electric field buffer layer 12.

[0160] Reference Figure 5 The electric field buffer layer 12 is formed entirely along the depth direction of the trench 19 at the bottom of the trench 19, forming a strip extending along the depth direction of the trench 19. (Refer to...) Figure 6 as well as Figure 7 An electric field buffer layer 12 is formed across one end and the other end of a trench 19 in the width direction. In this manner, the electric field buffer layer 12 has a side surface 29 formed on a plane substantially coplanar with a side surface 22 in the width direction of the trench 19 in the depth direction, and another side surface 29 formed on a plane substantially coplanar with the other side surface 22 in the width direction of the trench 19.

[0161] In other words, each electric field buffer layer 12 has a side surface 29 that is coplanarly connected to the two side surfaces 22 of the trench 19 in the depth direction of the trench structure 11. The side surface 29 of the electric field buffer layer 12 extends along the depth direction of the trench structure 11, forming a boundary surface with the semiconductor layer 7 (drift region 8). Therefore, the electric field buffer layer 12 is physically separated from the main region 18 in the depth direction of the trench structure 11 and forms the entire bottom surface 23 of the trench structure 11.

[0162] In this configuration, the electric field buffer layer 12 has a stacked structure of a first layer 30 and a second layer 31. The first layer 30 is formed from the bottom of the trench 19 (in this configuration, the bottom surface 23) toward the second main surface 4. The second layer 31 is formed between the first layer 30 and the bottom of the trench 19 (in this configuration, the bottom surface 23). The second layer 31 is exposed from the bottom surface 23 of the trench 19 and contacts the trench insulating film 20. The second layer 31 is sandwiched between the first layer 30 and the trench 19.

[0163] Regarding the impurity concentration of the electric field buffer layer 12, the first layer 30 has a first impurity concentration, and the second layer 31 has a second impurity concentration. In this configuration, the second impurity concentration of the second layer 31 is higher than the first impurity concentration of the first layer 30. Alternatively, the first impurity concentration of the first layer 30 can be equal to the impurity concentration of the main body region 18. The second impurity concentration of the second layer 31 can be higher than the impurity concentration of the main body region 18.

[0164] For example, the first impurity concentration in the first layer 30 can also be 1×10. 15 cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentration is taken as the peak value. The second impurity concentration of the second layer 31 can also have 1×10 18 cm -3 Above and 1×10 21 cm -3 The following p-type impurity concentrations are used as peak values. The p-type impurity concentrations of the first layer 30 and the second layer 31 are preferably adjusted by at least one trivalent element. The trivalent element of the first layer 30 and the second layer 31 can be at least one of boron, aluminum, gallium, and indium.

[0165] The stacked structure of the first layer 30 and the second layer 31 is continuous in the depth direction of the trench 19. In this manner, as... Figure 5 As shown, the electric field buffer layer 12 is formed as a strip extending along the depth direction of the trench 19 in a continuous manner, with the first layer 30 and the second layer 31 stacked throughout the trench 19. For example, multiple electric field buffer layers 12 are arranged at intervals in the m-axis direction and extend in the a-axis direction of the SiC single crystal. The multiple electric field buffer layers 12 are formed as stripes extending along the a-axis direction (second direction Y), and the extension direction of the multiple electric field buffer layers 12 is opposite to the deviation direction Do of the semiconductor layer 7 (see reference). Figure 4 (Consistent)

[0166] Multiple electric field buffer layers 12 overlap with multiple trench structures 11 in the depth direction of the trench 19. Specifically, the multiple electric field buffer layers 12 overlap with the multiple trench structures 11 in a one-to-one correspondence in the thickness direction of the chip 2. In this manner, the multiple electric field buffer layers 12 are respectively connected to the bottom surface 23 of the corresponding trench structure 11.

[0167] Reference Figure 8 as well as Figure 9 The electric field buffer layer 12 has a buffer depth DR in the vertical direction Z.

[0168] The buffer depth DR can have a value belonging to any of the following ranges: greater than 0.25 μm and less than 0.5 μm, greater than 0.5 μm and less than 1 μm, greater than 1 μm and less than 1.5 μm, greater than 1.5 μm and less than 2 μm, greater than 2 μm and less than 3 μm, greater than 3 μm and less than 4 μm, and greater than 4 μm and less than 5 μm. The buffer depth DR is preferably greater than 1.5 μm and less than 2.5 μm.

[0169] Multiple electric field buffer layers 12 each have a buffer width WR in their arrangement direction. The buffer width WR can be greater than 0.25 μm and less than 5 μm. The buffer width WR can have a value within any of the following ranges: greater than 0.25 μm and less than 0.5 μm, greater than 0.5 μm and less than 0.75 μm, greater than 0.75 μm and less than 1 μm, greater than 1 μm and less than 1.5 μm, greater than 1.5 μm and less than 2 μm, greater than 2 μm and less than 2.5 μm, greater than 2.5 μm and less than 3 μm, greater than 3 μm and less than 3.5 μm, greater than 3.5 μm and less than 4 μm, greater than 4 μm and less than 4.5 μm, and greater than 4.5 μm and less than 5 μm.

[0170] Reference Figure 5 and Figure 6 The semiconductor device 1 includes a source region 32, which is an example of a third impurity region, on the surface layer of the first main surface 3. The source region 32 is formed in the region between a plurality of trench structures 11. The source region 32 is formed on the surface layer of the main body region 18.

[0171] In this configuration, multiple source regions 32 traverse the mesa 24 in the width direction, forming from one side 22 of the mesa 24 to the other side 22 (one side 22 and the other side 22 of the trench 19). The multiple source regions 32 are spaced apart in each mesa 24 along the depth direction of the trench 19. Consequently, in each mesa 24, multiple channel intervals 33 are spaced apart in the second direction Y (the depth direction of the trench 19). In each channel interval 33, a channel is formed on the side 22 of the trench 19 on both sides of the mesa 24 in the first direction X.

[0172] Source region 32 has a higher n-type impurity concentration (peak value) than semiconductor layer 7 (drift region 8). Source region 32 can also have a concentration of 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 The following n-type impurity concentrations are taken as peak values.

[0173] Reference Figure 8The source region 32 has a source thickness ST1. The source thickness ST1 can also be the thickness of the source region 32 in the vertical direction Z from the first main surface 3. The source thickness ST1 can be, for example, 0.2 μm or more and 1.0 μm or less, preferably 0.4 μm or more and 0.8 μm or less.

[0174] Reference Figure 5 and Figure 7 The semiconductor device 1 includes a first contact region 34 on the surface portion of the first main surface 3. The first contact region 34 is formed in the region between a plurality of trench structures 11. The first contact region 34 is formed adjacent to the source region 32 on the surface portion of the main body region 18.

[0175] In this configuration, multiple first contact regions 34 traverse the mesa 24 in the width direction, extending from one side 22 of the mesa 24 to the other side 22. In each mesa 24, multiple source regions 32 and multiple first contact regions 34 are alternately arranged along the depth direction of the trench 19. Each source region 32 and each first contact region 34 is exposed from both sides 22 of the trench 19 (both sides 22 of the mesa 24).

[0176] Main comparison Figure 6 and Figure 7 The main body region 18 includes a first main body portion 35 formed directly below the source pole region 32. Figure 6 ) and the second main body portion 36 formed directly below the first contact area 34 ( Figure 7 The first main body portion 35 is the portion of the main body region 18 sandwiched between the source region 32 and the drift region 8 in the depth direction of the trench 19. The second main body portion 36 is the portion of the main body region 18 sandwiched between the first contact region 34 and the drift region 8 in the depth direction of the trench 19.

[0177] Reference Figure 8 and Figure 9 The first main body portion 35 has a first main body thickness BT1, and the second main body portion 36 has a second main body thickness BT2. The second main body thickness BT2 is greater than the first main body thickness BT1. (See reference...) Figures 5-7 The main region 18 forms a base boundary surface 37 between itself and the drift region 8. This base boundary surface 37 is located at a certain depth from the bottom surface 23 of the trench 19 along the depth direction of the trench 19. Figure 5 As shown, the main body region 18 has a main body protrusion 38 that selectively protrudes toward the first main surface 3 directly below the first contact region 34. Through this main body protrusion 38, the main body region 18 has a second main body portion 36 that is selectively thicker relative to the base boundary surface 37.

[0178] Reference Figure 6The first boundary surface 39 of the first main body 35 and the source region 32 is located further to the second main surface 4 than the upper surface 25 of the embedded body 21. This first boundary surface 39 is formed at a position lower than the upper surface 25 of the embedded body 21, and a first step 40 is formed between the upper surface 25 of the embedded body 21 and the first boundary surface 39. A portion of the source region 32 (e.g., the lower end) is opposed to the embedded body 21 through a trench insulating film 20. This ensures the formation of a channel between the source and drain.

[0179] Reference Figure 7 The second boundary surface 41 of the second main body 36 and the first contact area 34 is located on the side closer to the first main surface 3 than the upper surface 25 of the embedded body 21. This second boundary surface 41 is formed at a position higher than the upper surface 25 of the embedded body 21, and a second step 42 is formed between the upper surface 25 of the embedded body 21 and the second boundary surface 41. A portion of the second main body 36 (e.g., the upper end) protrudes further towards the first main surface 3 (upper side) than the embedded body 21. The first contact area 34 is not a region that directly contributes to the formation of the source-drain channel, and therefore may differ from the source region 32, not being opposed to the embedded body 21 via the trench insulating film 20.

[0180] Reference Figure 5 and Figure 7 The semiconductor device 1 includes a second contact region 43 on the surface portion of the first main surface 3. The second contact region 43 is connected to the first contact region 34 and the electric field buffer layer 12. The second contact region 43 is formed from the first contact region 34 toward the second main surface 4 along the side 22 of the trench 19 and is connected to the electric field buffer layer 12. In this manner, the second contact region 43 is formed from the first contact region 34 exposed from both sides 22 of the mesa 24 along both sides 22 of the mesa 24.

[0181] The second contact area 43 is formed integrally along the depth direction of the trench 19 from the top to the bottom. The second contact area 43 has a lower end near the bottom of the trench 19 and an upper end near the top of the trench 19.

[0182] The second contact region 43 extends through the main body region 18, spanning the area between the main body region 18 and the electric field buffer layer 12. The second contact region 43 forms a boundary with and connects to the main body region 18. The second contact region 43 also connects to the semiconductor layer 7 (drift region 8) below the main body region 18. That is, in the interval between the main body region 18 and the electric field buffer layer 12, a pn junction is formed by the second contact region 43 and the drift region 8.

[0183] Reference Figure 7The second contact region 43 is exposed from the side 22 of the trench 19 and contacts the trench insulating film 20 on the side 22 of the trench 19. The lower end of the second contact region 43 contacts the second layer 31 of the electric field buffer layer 12. Thus, in the semiconductor layer 7, a p-type integral impurity region 44 is formed by the first contact region 34, the second contact region 43 and the second layer 31.

[0184] Reference Figure 7 In the side surfaces 22 and bottom surfaces 23 of the trench 19, integral impurity regions 44 partially cover the embedded body 21 via the trench insulating film 20. More specifically, the two end corners 45 of the trench 19 in the width direction are covered at the second buffer portion 47 by integral impurity regions 44 that appear approximately Z-shaped when viewed in cross-section. This suppresses the concentration of electric field towards the corners 45 of the trench 19.

[0185] On the other hand, refer to Figure 6 In the first buffer section 46, a portion of the electric field buffer layer 12 (second layer 31) may also be located away from the corner of the trench 19. That is, in the depth direction of the trench 19, the corner 45 of the trench 19 may also have a portion covered by the electric field buffer layer 12 and a portion not covered by the electric field buffer layer 12.

[0186] In this manner, multiple integral impurity regions 44 are formed at intervals along the depth direction of the trench 19. Along the depth direction of the trench 19, the first contact region 34 and the second contact region 43 have the same width, and a strip-shaped integral impurity region 44 of a certain width is formed on the upper surface (first main surface 3) of the platform 24 and the side surface 22 (side surface 22 of the trench 19) of the platform 24.

[0187] Compare Figure 6 as well as Figure 7 In the width direction of the trench 19, the integral impurity region 44 has a width wider than the first layer 30 of the electric field buffer layer 12. This is because the second contact region 43 is connected to the side of the second layer 31, and the portion of the second contact region 43 integrated in the second layer 31 selectively widens.

[0188] Reference Figure 9 The second contact region 43 has a second contact thickness CT2. The second contact thickness CT2 can also be the thickness of the second contact region 43 in the horizontal direction from the side 22 of the trench 19. The second contact thickness CT2 can be, for example, 10 nm or more and 200 nm or less, preferably 20 nm or more and 100 nm or less.

[0189] Reference Figure 9The first contact area 34 has a first contact thickness CT1. The first contact thickness CT1 can also be the thickness of the first contact area 34 in the vertical direction Z from the first main surface 3. In this case, the first contact thickness CT1 is larger than the second contact thickness CT2. The first contact thickness CT1 can be, for example, 0.1 μm or more and 1.0 μm or less, preferably 0.2 μm or more and 0.5 μm or less.

[0190] Reference Figure 8 as well as Figure 9 In this manner, the ratio of the thickness of the first layer 30 and the second layer 31 of the electric field buffer layer 12 is such that the thickness of the first buffer portion 46 formed directly below the source region 32 is... Figure 6 ) and the second buffer portion 47 formed directly below the first contact area 34 ( Figure 7 )different.

[0191] More specifically, this is considered under the premise that the first layer 30 has a first buffer thickness RT1A (RT1B) and the second layer 31 has a second buffer thickness RT2A (RT2B). In this case, Figure 8 The thickness ratio (RT2A / RT1A) of the second buffer thickness RT2A in the first buffer section 46 shown is less than that of the first buffer thickness RT1A. Figure 9 The thickness ratio (RT2B / RT1B) in the second buffer section 47 shown. Of course, the thickness ratio (RT2A / RT1A) can also be the same as the thickness ratio (RT2B / RT1B).

[0192] For example, if the total thickness RT0 (RT1A+RT2A or RT1B+RT2B) defined by the buffer depth DR of the electric field buffer layer 12 is the same in the first buffer section 46 and the second buffer section 47, then the first buffer thickness RT1A in the first buffer section 46 is larger than the first buffer thickness RT1B in the second buffer section 47. Conversely, the second buffer thickness RT2A of the first buffer section 46 is smaller than the second buffer thickness RT2B of the second buffer section 47. However, when the thickness ratio (RT2A / RT1A) and the thickness ratio (RT2B / RT1B) are the same, the first buffer thickness RT1A and the first buffer thickness RT1B can also be equal, and the second buffer thickness RT2A and the second buffer thickness RT2B can be equal.

[0193] In this method, the first buffer thickness RT1A can be 0.2 μm or more and 1.0 μm or less, and the second buffer thickness RT2A can be 0.2 μm or more and 1.0 μm or less. Preferably, the first buffer thickness RT1A is 0.4 μm or more and 0.8 μm or less, and the second buffer thickness RT2A is preferably 0.4 μm or more and 0.8 μm or less.

[0194] Alternatively, the first buffer thickness RT1B can be 0.1 μm or more and 0.6 μm or less, and the second buffer thickness RT2B can be 0.1 μm or more and 0.6 μm or less. Preferably, the first buffer thickness RT1B is 0.2 μm or more and 0.5 μm or less, and the second buffer thickness RT2B is preferably 0.2 μm or more and 0.5 μm or less.

[0195] Reference Figure 6 and Figure 7 In the first buffer section 46, the first boundary surface 48 between the first layer 30 and the second layer 31 is located closer to the first main surface 3 than the second boundary surface 49 between the first layer 30 and the second layer 31 in the second buffer section 47. Conversely, the second boundary surface 49 is located closer to the second main surface 4 than the first boundary surface 48.

[0196] Reference Figures 5-7 The drift region 8 includes a stacked structure of base region 50 and high concentration region 51.

[0197] The base region 50 is formed separately from the main body region 18 on the side of the electric field buffer layer 12 closest to the second main surface 4. The base region 50 is formed in a layered shape extending along the first main surface 3 at a position away from the main body region 18 and the trench 19 towards the second main surface 4. The base region 50 may also be formed over the entire surface portion of the semiconductor layer 7 on the side of the second main surface 4, exposed from the first to fourth side surfaces 5A to 5D. The base region 50 forms the boundary surface between the semiconductor layer 7 and the base layer 6.

[0198] Reference Figure 8 as well as Figure 9 The base region 50 has a base thickness BT. The base thickness BT can be 0.5 μm or more and 20 μm or less. Preferably, the base thickness BT is 1 μm or more and 10 μm or less.

[0199] The n-type impurity concentration in the base region 50 is preferably lower than that in the base layer 6. The base region 50 may also have a concentration of 1 × 10⁻⁶. 15 cm -3 Above and 5×10 16 cm -3 The following n-type impurity concentrations are taken as peak values. The n-type impurity concentration in the base region 50 can also be approximately fixed in the thickness direction. Of course, the n-type impurity concentration in the base region 50 can also have a concentration gradient that gradually increases and / or decreases towards the thickness direction (crystal growth direction) of the chip 2.

[0200] Reference Figures 5-7Regarding the relationship between the electric field buffer layer 12 and the base region 50, the first layer 30 of the electric field buffer layer 12 is formed in the thickness direction of the chip 2 to a depth reaching the base region 50. More specifically, the bottom of the first layer 30 of the electric field buffer layer 12 contacts the base region 50, forming a boundary between them.

[0201] A high-concentration region 51 is formed between the base region 50 and the main region 18 on the side of the trench 19 and the electric field buffer layer 12. In this configuration, the high-concentration region 51 also includes a stacked structure of a first high-concentration region 52 and a second high-concentration region 53.

[0202] The first high-concentration region 52 forms the upper layer of the layered structure of the high-concentration region 51. The first high-concentration region 52 is in contact with the main body region 18 and is formed as a layer extending along the first main surface 3. The first high-concentration region 52 may also be formed over the entire surface portion on the side of the first main surface 3 of the drift region 8, exposed from the first to fourth side surfaces 5A to 5D. In this manner, the first high-concentration region 52 forms the boundary surface between the drift region 8 and the main body region 18.

[0203] The n-type impurity concentration in the first high-concentration region 52 is preferably higher than that in the base region 50. The first high-concentration region 52 may also have a concentration of 1 × 10⁻⁶. 18 cm -3 Above and 1×10 19 cm -3 The following n-type impurity concentrations are taken as peak values. The n-type impurity concentration in the first high-concentration region 52 can also be approximately constant in the thickness direction. Of course, the n-type impurity concentration in the first high-concentration region 52 can also have a concentration gradient that gradually increases and / or decreases towards the thickness direction (crystal growth direction) of the chip 2.

[0204] The first high-concentration region 52 is formed in the thickness direction of the chip 2 from the main region 18 at a depth shallower than the bottom of the trench 19.

[0205] The second high-concentration region 53 forms the lower layer of the stacked structure of the high-concentration region 51. The second high-concentration region 53 is formed on the side of the second main surface 4 relative to the first high-concentration region 52. The second high-concentration region 53 is sandwiched between the first high-concentration region 52 and the base region 50 in the thickness direction of the chip 2. The second high-concentration region 53 may also be formed as a layer extending along the first main surface 3 and exposed from the first to fourth side surfaces 5A to 5D. In this configuration, the second high-concentration region 53 covers the entire thickness direction of the chip 2 from the side of the first main surface 3 to the side of the second main surface 4, and contacts the sides of the first layer 30 and the second layer 31 of the electric field buffer layer 12. In addition, the second high-concentration region 53 covers the bottom of the trench 19 and the boundary 54 of the electric field buffer layer 12 (see reference). Figure 6 ).

[0206] The concentration of n-type impurities in the second high-concentration region 53 is preferably lower than that in the first high-concentration region 52. The first high-concentration region 52 may also have a concentration of 1×10⁻⁶. 16 cm -3 Above and 1×10 18 cm -3 The following n-type impurity concentration is taken as the peak value. The n-type impurity concentration in the second high-concentration region 53 can also be approximately constant in the thickness direction. Of course, the n-type impurity concentration in the second high-concentration region 53 can also have a concentration gradient that gradually increases and / or decreases towards the thickness direction (crystal growth direction) of chip 2.

[0207] Reference Figure 8 and Figure 9 Regarding the thicknesses of the first high-concentration region 52 and the second high-concentration region 53, the first thickness HT1 of the first high-concentration region 52 is greater than the second thickness HT2 of the second high-concentration region 53. For example, the first thickness HT1 of the first high-concentration region 52 can be 0.1 μm or more and 0.5 μm or less, and the second thickness HT2 of the second high-concentration region 53 can be 0.5 μm or more and 2.0 μm or less. The first thickness HT1 is preferably 0.15 μm or more and 0.4 μm or less, and the second thickness HT2 is preferably 0.8 μm or more and 1.5 μm or less.

[0208] In this method, the n-type impurity concentrations of the base region 50, the first high-concentration region 52, and the second high-concentration region 53 are adjusted using nitrogen. The base region 50, the first high-concentration region 52, and the second high-concentration region 53 may also have n-type impurity concentrations adjusted by at least one pentavalent element. For example, the n-type impurity concentrations of the base region 50, the first high-concentration region 52, and the second high-concentration region 53 can also be adjusted using at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0209] Semiconductor device 1 includes an interlayer insulating layer 55 embedded in a groove 27 of semiconductor layer 7. The interlayer insulating layer 55 may also be referred to as an "insulating film", "interlayer film", "intermediate insulating film", etc. In this embodiment, the interlayer insulating layer 55 may also include at least one of silicon oxide film, silicon nitride film, and silicon oxynitride film.

[0210] Reference Figure 6 and Figure 7The interlayer insulating layer 55 is embedded in the groove 27 such that the upper edge 56 of the groove 19 protrudes from the first main surface 3. The upper edge 56 of the groove 19 may also be the part where the top of the groove 19 intersects with the first main surface 3 on the side 22 of the groove 19. That is, the interlayer insulating layer 55 does not cover the periphery of the groove 19 on the first main surface 3, but is housed in the inner region of the groove 19 in the width direction of the groove 19. In this manner, the upper surface 57 of the interlayer insulating layer 55 is located on the bottom side of the groove 19 in the depth direction of the groove 19, which is closer to the first main surface 3.

[0211] Reference Figure 5 The interlayer insulation layer 55 is embedded in the groove 27 throughout the depth direction of the trench 19, forming a strip extending along the depth direction of the trench 19. (Refer to...) Figure 6 and Figure 7 The interlayer insulating layer 55 contacts the source region 32 and the first contact region 34 on the side 22 of the groove 27 (the side 22 of the trench 19).

[0212] Reference Figure 6 as well as Figure 7 The semiconductor device 1 includes a silicide layer 58 formed on each surface of the source region 32 and the first contact region 34. By forming the silicide layer 58, the contact resistance relative to the source region 32 and the first contact region 34 can be reduced.

[0213] In this manner, the silicide layer 58 is selectively formed on the protrusions 28 of each facet 24. More specifically, it is formed along the upper surface (first main surface 3) and side surface 22 (side surface 22 of the groove 27) of the protrusions 28 of the facet 24. Inside the protrusions 28 of the facet 24, which are located inwardly from the upper surface (first main surface 3) and side surface 22 of the facet 24, non-silicide portions 59 (surrounded on three sides) defined by the silicide layer 58 may also be formed.

[0214] The silicide layer 58 can be, for example, nickel silicide, titanium silicide, aluminum silicide, copper silicide, etc. Furthermore, the thickness ST2 of the silicide layer 58 can be, for example, 50 nm or more and 500 nm or less in the vertical direction Z from the upper surface (first main surface 3) of the protrusion 28 of the mesa 24 and the side surface 22. The thickness ST2 of the silicide layer 58 is preferably 80 nm or more and 300 nm or less.

[0215] Reference Figure 6 as well as Figure 7 The semiconductor device 1 includes a first main surface electrode 60. The first main surface electrode 60 is formed on a first main surface 3 such that it covers an interlayer insulating layer 55. The first main surface electrode 60 has a stacked structure including a barrier layer 61 and a body layer 62 stacked sequentially from the side of the first main surface 3.

[0216] The barrier layer 61 is formed as a film along the first main surface 3 and the inner surface of the groove 27 (the side surface 22 of the groove 27 and the upper surface 57 of the interlayer insulating layer 55). The barrier layer 61 is in ohmic contact with the silicide layer 58. The barrier layer 61 also divides a second groove 63 within the groove 27.

[0217] The barrier layer 61 may also include at least one of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer. The thickness of the barrier layer 61 may be 0.05 μm or more and 0.3 μm or less. Preferably, the thickness of the barrier layer 61 is 0.1 μm or more and 0.2 μm or less.

[0218] A main body layer 62 is formed on a barrier layer 61. The main body layer 62 covers the entire area of ​​the main surface of the barrier layer 61. The main body layer 62 is partially embedded in a second recess 63. The main body layer 62 is electrically connected to the source region 32 and the first contact region 34 via the barrier layer 61 and the silicide layer 58. In this configuration, the first main surface electrode 60 is connected to the source region 32 and the first contact region 34 in the side 22 of the recess 27 and in the first main surface 3. Therefore, the first main surface electrode 60 may also include the aforementioned source pad 15 in the semiconductor device 1. The electric field buffer layer 12 is fixed to the source potential via the first contact region 34 and the second contact region 43.

[0219] The main body layer 62 includes at least one of the following: a pure Al layer (meaning an Al layer composed of Al with a purity of 99% or higher), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0220] The thickness of the main layer 62 exceeds the thickness of the barrier layer 61. The thickness of the main layer 62 can be 1 μm or more and 10 μm or less. Preferably, the thickness of the main layer 62 is 3 μm or more and 6 μm or less.

[0221] Semiconductor device 1 includes a resin layer 64 covering a first main surface electrode 60. The resin layer 64 is formed in a film shape along the main surface of the first main surface electrode 60. The resin layer 64 may also include a photosensitive resin. The photosensitive resin can be negative or positive. The resin layer 64 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the resin layer 64 includes polybenzoxazole. Furthermore, a passivation film (not shown) made of, for example, an insulating film such as silicon nitride may be interposed between the resin layer 64 and the first main surface electrode 60.

[0222] [Manufacturing method of semiconductor device 1]

[0223] Figure 10This is a schematic diagram showing a wafer 65 used in the manufacture of semiconductor device 1. Wafer 65 is the substrate of base layer 6, comprising SiC single crystal. Wafer 65 is formed in a flat disk shape. Alternatively, wafer 65 can also be formed in a flat cuboid shape. Wafer 65 has a first wafer main surface 66 on one side, a second wafer main surface 67 on the other side, and a wafer side surface 68 connecting the first wafer main surface 66 and the second wafer main surface 67.

[0224] The first wafer principal surface 66 corresponds to the upper end of the base layer 6, and the second wafer principal surface 67 corresponds to the lower end of the base layer 6. Both the first wafer principal surface 66 and the second wafer principal surface 67 are formed from the c-plane of a SiC single crystal. The first wafer principal surface 66 is formed from the silicon plane of a SiC single crystal, and the second wafer principal surface 67 is formed from the carbon plane of a SiC single crystal. The wafer 65 (the first wafer principal surface 66 and the second wafer principal surface 67) has the aforementioned offset direction Do and offset angle θo.

[0225] The wafer 65 has a mark 69 on its side surface 68 indicating the crystal orientation of the SiC single crystal. The mark 69 may also include either or both of an orientation plane and an orientation notch. The orientation plane is formed by a cut that appears as a straight line when viewed from above. The orientation notch is formed by a cut that is concave (e.g., tapered) towards the center of the first wafer main surface 66 when viewed from above.

[0226] Marker 69 may also include either or both of a first directional plane extending along the m-axis and a second directional plane extending along the a-axis. Marker 69 may also include either or both of a directional notch recessed in the m-axis direction and a directional notch recessed in the a-axis direction. Figure 10 The diagram shows an oriented plane extending along the m-axis (first direction X) when viewed from above.

[0227] For example, on wafer 65, multiple device regions 70 and multiple cut-off lines 71 are defined by alignment marks, etc. Each device region 70 is a region corresponding to semiconductor device 1. The multiple device regions 70 are each set as quadrilateral shapes when viewed from above.

[0228] In this configuration, multiple device regions 70 are arranged in a matrix shape along the first direction X and the second direction Y when viewed from above. The multiple device regions 70 are spaced apart from the periphery of the first wafer main surface 66 inwards when viewed from above. Multiple predetermined cutting lines 71 are arranged in a grid shape extending along the first direction X and the second direction Y to divide the multiple device regions 70.

[0229] Figure 11 This is a flowchart illustrating a manufacturing method of semiconductor device 1. Figure 12A as well as Figures 12B to 30A as well as Figure 30BThis is a cross-sectional view illustrating an example of a manufacturing method for semiconductor device 1. Figure 12A as well as Figures 12B to 30A as well as Figure 30B In the diagram, the one recorded along with "A" is... Figure 6 The corresponding diagram, recorded together with "B", is the one with... Figure 7 The corresponding diagram.

[0230] First, refer to Figure 12A as well as Figure 12B Perform the aforementioned wafer 65 preparation process ( Figure 11 Step S1). Next, the semiconductor layer 7 is formed ( Figure 11 Step S2). The semiconductor layer 7 is formed by epitaxial growth starting from the first wafer main surface 66 (wafer 65).

[0231] Next, refer to Figure 13A as well as Figure 13B The process of forming the second high-concentration region 53 is implemented. Figure 11 (Step S3). In the process of forming the second high-concentration region 53, n-type impurities are introduced into the entire region of the semiconductor layer 7. As a result, the second high-concentration region 53 is formed in the entire surface region of the semiconductor layer 7. At the same time, a base region 50 separated from the second high-concentration region 53 is formed.

[0232] Next, refer to Figure 14A and Figure 14B The formation process of the first high-concentration zone 52 is implemented. Figure 11 (Step S4). In the formation process of the first high-concentration region 52, n-type impurities are introduced into the entire region of the semiconductor layer 7. As a result, the first high-concentration region 52 is formed in the entire surface region of the second high-concentration region 53.

[0233] Next, refer to Figure 15A and Figure 15B The process of forming the main area 18 is implemented. Figure 11 (Step S5 in the process). In the formation process of the main body region 18, p-type impurities are introduced into the entire region of the semiconductor layer 7. As a result, the main body region 18 is formed in the entire surface region of the first high concentration region 52.

[0234] Next, refer to Figure 16A and Figure 16B The process of forming source region 32 is implemented. Figure 11Step S6). In the process of forming the source region 32, n-type impurities are selectively introduced into the semiconductor layer 7 (the surface portion of the main body region 18). As a result, the source region 32 is formed on the surface portion of the main body region 18. At this time, the area where the first contact region 34 is to be formed is selectively covered by a mask (not shown) to prevent the introduction of n-type impurities.

[0235] Next, the process of forming multiple grooves 19 is carried out. First, refer to... Figure 17A and Figure 17B Forming a first mask 72 with a predetermined pattern Figure 11 Step S7). The first mask 72 is preferably an inorganic mask (hard mask). The first mask 72 has a plurality of first openings 73 that expose the areas where the plurality of trenches 19 should be formed.

[0236] Next, refer to Figure 18A as well as Figure 18B Unwanted portions of the semiconductor layer 7 are removed by etching through the first mask 72. The etching method can be either wet etching or dry etching, or both. The preferred etching method is RIE (Reactive Ion Etching). This forms a plurality of trenches 19 at the upper end of the semiconductor layer 7. Figure 11 (Step S8). At the same time, a platform 24 is formed between adjacent trenches 19.

[0237] Next, refer to Figure 19A and Figure 19B While the first mask 72 remains on the semiconductor layer 7, a process for forming multiple electric field buffer layers 12 is performed. Figure 11 (Step S9). In the process of forming the electric field buffer layer 12, p-type impurities are selectively introduced into the semiconductor layer 7 via the first mask 72. As a result, the electric field buffer layer 12 is formed at the bottom of each trench 19.

[0238] More specifically, the process involves a first step of introducing p-type impurities with a relatively high first energy and a relatively low first dose, and a second step of introducing p-type impurities with a second energy lower than the first energy and a second dose higher than the first dose. First, by performing the first step, a first layer 30 is formed at the bottom of the trench 19. Next, by performing the second step, a second layer 31 is formed on the surface portion of the first layer 30. Furthermore, at this time, the second buffer thickness RT2A of the second layer 31 of the first buffer portion 46 (refer to...) Figure 8 The second buffer thickness RT2B of the second layer 31 of the second buffer section 47 (refer to) Figure 9 )same.

[0239] Various ion implantation methods can be applied as a method for forming the electric field buffer layer 12. For example, the electric field buffer layer 12 can also be formed by channel effect ion implantation. The channel effect implantation process is performed based on the deviation angle θo data (information). If it is a channel implantation process, the electric field buffer layer 12 can be selectively and easily formed at a deeper location in the semiconductor layer 7. In the case where the electric field buffer layer 12 is formed by channel effect ion implantation, the electric field buffer layer 12 can also be formed before the main body region 18. Afterwards, the first mask 72 is removed.

[0240] Next, refer to Figure 20A and Figure 20B Remove the first mask 72 ( Figure 11 Step S10).

[0241] Next, refer to Figure 21A and Figure 21B This forms a first contact area 34 and a second contact area 43. In this process, firstly, a second mask 74 with a predetermined pattern is formed. Figure 11 (Step S11). The second mask 74 is preferably a photoresist. The second mask 74 has a plurality of second openings 75 that expose the areas where the first contact area 34 and the second contact area 43 should be formed. More specifically, the second mask 74 has second openings 75 that selectively cover the first body portion 35 and the first buffer portion 46 of each stage portion 24 and selectively expose the second body portion 36 and the second buffer portion 47.

[0242] Next, p-type impurities are introduced into the surface portion of the semiconductor layer 7 via ion implantation through the second mask 74. This introduces p-type impurities into the surface of the mesa 24 exposed from the second opening 75 and the inner surface of the trench 19, forming the first contact region 34 and the second contact region 43. Figure 11 Step S12). In this method, tilted implantation with a predetermined angle relative to the first wafer main surface 66 is performed. Therefore, ions can be implanted into the side surface 22 of the trench 19 in addition to the first wafer main surface 66 and the bottom surface 23 of the trench 19. On the other hand, as described above, the trench structure 11 has an aspect ratio DT / WT (e.g., 1 or more and 5 or less) extending in a longitudinal columnar shape, and the trench depth DT is much greater than the trench width WT. Therefore, in order to uniformly implant ions into the side surface 22 of the trench 19, the implantation angle needs to be increased. As a result, the ion implantation depth from the side surface 22 of the trench 19 becomes shallower, and the second contact thickness CT2 is smaller than the first contact thickness CT1 (see reference). Figure 9 ).

[0243] At this time, p-type impurities are also introduced into the bottom surface 23 of the trench 19, thus selectively thickening the second layer 31 of the second buffer section 47. This results in a second buffer thickness RT2A (refer to...). Figure 8 ) and the second buffer thickness RT2B (refer to Figure 9 The difference is that the thickness ratio of the first buffer portion 46 (RT2A / RT1A) is less than the thickness ratio of the second buffer portion 47 (RT2B / RT1B). Furthermore, the second layer 31 of the second buffer portion 47 can be thickened non-selectively. For example, if the implantation depth of the p-type impurity used in the first contact region 34 and the second contact region 43 is shallower than that of the second layer 31, the second layer 31 of the second buffer portion 47 is thickened non-selectively. Thus, the thickness ratio (RT2A / RT1A) remains the same as the thickness ratio (RT2B / RT1B).

[0244] Next, refer to Figure 22A and Figure 22B After removing the second mask 74 ( Figure 11 Step S13), perform annealing treatment to activate the impurity region ( Figure 11 Step S14).

[0245] Next, refer to Figure 23A and Figure 23B The process of forming insulating film 76 is carried out. Figure 11 (Step S15 in the process). The formation process of the insulating film 76 also serves as the formation process of the trench insulating film 20. The insulating film 76 can also be formed by any one or both of CVD (Chemical Vapor Deposition) and oxidation processes. In this method, the insulating film 76 is formed by CVD. The insulating film 76 is formed in film form on the walls of the plurality of trenches 19 and is formed over the entire area of ​​the first wafer main surface 66.

[0246] Next, the process of forming the embedded body 21 will be carried out. Figure 11 Step S16). In this process, refer to Figure 24A as well as Figure 24B The process involves forming a base electrode film 77 on the insulating film 76. In this method, the base electrode film 77 comprises conductive polycrystalline silicon. The base electrode film 77 backfills multiple trenches 19, covering the first wafer main surface 66 of the semiconductor layer 7. The base electrode film 77 can also be formed by CVD.

[0247] Next, refer to Figure 25A as well as Figure 25BUnwanted portions of the base electrode film 77 are removed by etching. The unwanted portions of the base electrode film 77 are removed until the insulating film 76 is exposed and the upper surface 25 of the base electrode film 77 is located at the midpoint of the depth direction of the trench 19. The etching method can be either wet etching or dry etching, or both. Thus, multiple embedded bodies 21 are embedded within the multiple trenches 19, forming multiple trench structures 11. Furthermore, grooves 27 are formed within each trench 19.

[0248] Next, the process of forming interlayer insulation layer 55 is carried out. Figure 11 Step S17). In this process, refer to Figure 26A as well as Figure 26B The process involves forming a base insulating film 78 on the first wafer main surface 66. In this method, the base insulating film 78 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The base insulating film 78 is integrated with the insulating film 76 by backfilling the grooves 27 of the plurality of trenches 19, covering the first wafer main surface 66 of the semiconductor layer 7. The base insulating film 78 can also be formed by CVD. Thus, the insulating film 76 remaining between the buried body 21 and the inner surface of the trench 19 is formed as a trench insulating film 20.

[0249] Next, refer to Figure 27A and Figure 27B Unwanted portions of the base insulating film 78 are removed using an etching method. Removal of these unwanted portions continues until the base insulating film 78 outside the trench 19 is removed, and subsequently, the insulating film 76 on the first wafer main surface 66 is removed. This exposes the first wafer main surface 66, with the upper surface 57 of the base insulating film 78 located at the midpoint of the trench 19's depth. Furthermore, the sidewalls 22 of the groove 27 are exposed through the removal of the insulating film 76. The etching method can be either wet etching or dry etching, or both. This allows for the embedding of multiple interlayer insulating layers 55 within the multiple trenches 19.

[0250] Next, refer to Figure 28A and Figure 28B The process of forming silicide layer 58 is carried out. Figure 11 Step S18 in the process. Specifically, a metal film (e.g., a nickel film, a titanium film, etc.) for silicide formation is formed on the main surface 66 of the first wafer. This metal film is deposited over the entire area of ​​the main surface 66 of the first wafer, for example, by sputtering. Then, by annealing (e.g., RTA: Rapid Thermal Anneal), the metal film reacts with silicon in the semiconductor layer 7 to form a silicide layer 58 (metal silicide). Then, the metal film is stripped off.

[0251] Next, refer to Figure 29A as well as Figure 29BThe process of forming the first main surface electrode 60, including the gate pad 13 and the source pad 15, is carried out. Figure 11 Step S19). The first main surface electrode 60 is formed by sputtering a first metal film that forms the basis of the barrier layer 61 and a second metal film that forms the basis of the host layer 62 onto the first wafer main surface 66, and then forming a predetermined layout by etching through a mask (not shown) with a predetermined layout.

[0252] Next, refer to Figure 30A and Figure 30B The process of forming resin layer 64 is carried out. Figure 11 (Step S20). The resin layer 64 is formed by selectively forming pad openings after the resin material that will become the base of the resin layer 64 is coated onto the first main surface electrode 60 and cured.

[0253] Next, the process of forming the drain pad 16 is performed. Figure 11 Step S21). The drain pad 16 is formed by depositing a metal film onto the main surface 67 of the second wafer using a sputtering method. Then, the wafer 65 is cut along multiple predetermined dicing lines 71. Figure 11 Step S22). Through the above processes, multiple semiconductor devices 1 are manufactured from one wafer 65.

[0254] [Effects of Semiconductor Device 1]

[0255] According to the semiconductor device 1, the impurity concentration of the first layer 30 of the electric field buffer layer 12 is relatively low compared to the second layer 31. Since the depletion layer can extend relatively far from the first pn junction between the first layer 30 and the semiconductor layer 7 (drift region 8), the device breakdown voltage can be improved. On the other hand, the impurity concentration of the second layer 31 of the electric field buffer layer 12 is relatively high compared to the first layer 30. The width of the depletion layer extending from the second pn junction between the second layer 31 and the semiconductor layer 7 can be narrower than the width of the depletion layer extending from the first pn junction. Therefore, the depletion layer extending from the second pn junction towards the bottom of the trench 19 can be narrowed, thus buffering the electric field strength applied to the trench insulating film 20. That is, both buffering the electric field strength applied to the trench insulating film 20 and improving the device breakdown voltage can be achieved.

[0256] Furthermore, the stacked structure of the first layer 30 and the second layer 31 extends in the depth direction of the trench 19. As a result, the electric field strength applied to the trench insulating film 20 can be buffered over a large range in the depth direction of the trench 19, and the withstand voltage of the device can be improved.

[0257] Furthermore, the first main surface electrode 60, which is connected to the source region 32, is electrically connected to the first layer 30 of the electric field buffer layer 12 via the first contact region 34 and the second contact region 43. Thus, the potential of the first layer 30 of the electric field buffer layer 12 can be fixed to the same potential as that of the source region 32.

[0258] Furthermore, since the multiple source regions 32 and the multiple first contact regions 34 are arranged alternately along the depth direction of the trench 19, the current path (channel) formed in the depth direction of the trench 19 can be formed in a balanced and good manner along the depth direction of the trench 19. In particular, in each mesa 24, the source regions 32 and the first contact regions 34 are arranged adjacent to each other in the depth direction of the trench 19, thus enabling miniaturization of the device.

[0259] Furthermore, the interlayer insulating layer 55 is embedded in the groove 27 of the trench 19, and the upper edge 56 of the trench 19 is exposed. This allows the source region 32 to be exposed over a large area on the first main surface 3. Therefore, in applications requiring miniaturized structures, the contact area between the first main surface electrode 60 and the source region 32 can be sufficiently ensured. Furthermore, there is no need to form contact openings in the interlayer insulating layer 55. Since there is no need to consider positional offset margins when forming contact openings, further miniaturization of the device can be achieved.

[0260] Furthermore, the upper surface 57 of the interlayer insulating layer 55 is located on the bottom side of the trench 19, closer to the first main surface 3 than the first main surface 3, in the depth direction of the trench 19. The first main surface electrode 60 is connected to the source region 32 on the side surface 22 of the groove 27 and on the first main surface 3. As a result, the contact area between the first main surface electrode 60 and the source region 32 can be increased, thereby reducing their contact resistance.

[0261] Furthermore, a high-concentration region 51 with a higher impurity concentration than the base region 50 is formed on the side of the electric field buffer layer 12. Therefore, when the device (in this case, a MISFET) is turned off, a wider depletion layer can extend through the relatively low-concentration base region 50, thus ensuring an increased device breakdown voltage. Moreover, by configuring the relatively high-concentration region 51 on the side of the electric field buffer layer 12, excessive expansion of the depletion layer around the periphery of the electric field buffer layer 12 can be suppressed when the device (in this case, a MISFET) is turned on. By suppressing the expansion of this depletion layer, a current path can be ensured, thus suppressing an increase in on-resistance.

[0262] Furthermore, the relatively high-concentration first high-concentration region 52 in the high-concentration region 51 is formed at a depth shallower than the bottom of the trench 19. The first high-concentration region 52 acts as a current spreading layer (CSL) that spreads the current flowing through the trench to the entire area between adjacent trenches 19, thereby reducing on-resistance. Furthermore, the bottom of the first high-concentration region 52 is shallower than the bottom of the trench 19 and does not contact the bottom of the trench 19 or the boundary 54 of the electric field buffer layer 12. Thus, even if the concentration of the first high-concentration region 52 is increased, the impact on the device breakdown voltage and the electric field of the trench insulating film 20 can be reduced. In addition, by arranging a relatively low-concentration second high-concentration region 53 on the second main surface 4 side of the first high-concentration region 52, the device breakdown voltage can also be improved.

[0263] Furthermore, the first layer 30 of the electric field buffer layer 12 is formed in the thickness direction of the chip 2 to a depth reaching the base region 50. As a result, a first pn junction can be formed between the first layer 30 and the base region 50, thus allowing the depletion layer to extend further and further improving the device's breakdown voltage.

[0264] Furthermore, the bottom of the first layer 30 of the electric field buffer layer 12 contacts the base region 50, forming a boundary between them. Thus, the first layer 30 contacts the base region 50, but prevents the contact area from becoming excessive. As a result, the depletion layer can be extended extensively, while maintaining a moderate extension range, thereby ensuring a sufficient current path.

[0265] [Other embodiments of semiconductor device 1]

[0266] Reference Figures 31 to 69 Other embodiments of semiconductor device 1 will be described below. Hereinafter, the description will primarily focus on... Figures 5-9 The parts of the semiconductor device 1 shown are structurally different from those of the semiconductor device 1 shown. Figures 5-9 The common parts are omitted.

[0267] (1) Figure 31 way

[0268] Figure 31 Other embodiments of semiconductor device 1 are shown, which are related to Figure 5 The corresponding 3D diagram. (Refer to...) Figure 31The electric field buffer layer 12 can also be arranged at intervals in the depth direction of the trench 19. For example, it can be selectively formed on the portion of the mesa 24 corresponding to the second main body portion 36, but not on the portion corresponding to the first main body portion 35. That is, the electric field buffer layer 12 can also be selectively formed in the portion of the mesa 24 that avoids the channel interval 33. Since the electric field buffer layer 12 is not formed in the channel interval 33, a wider current path can be ensured in the channel interval 33.

[0269] (2) Figure 32 way

[0270] Figure 32 Other embodiments of semiconductor device 1 are shown, which are related to Figure 7 The corresponding sectional view. (Refer to...) Figure 32 If it is not necessary to fix the electric field buffer layer 12 to the source potential, the second contact region 43 may not be formed. In this case, the first contact region 34 and the electric field buffer layer 12 are electrically separated by the drift region 8.

[0271] (3) Figure 33 way

[0272] Figure 33 Other embodiments of semiconductor device 1 are shown, which are related to Figure 5 The corresponding 3D diagram. (Refer to...) Figure 33 Alternatively, the upper part of the table surface 24 (the surface part of the main body region 18) can be divided into two regions, with one region (in this case, ) being the upper part of the table surface 24. Figure 33 The front side of the paper is provided with a strip-shaped source region 32 extending along the depth direction of the trench 19. In another region (in this manner, Figure 33 The back side of the paper can also be provided with a first contact region 34 extending along the depth direction of the trench 19. That is, in the semiconductor device 1, the plurality of source regions 32 and the plurality of first contact regions 34 may not be arranged alternately along the depth direction of the trench 19.

[0273] (4) Figures 34-36 way

[0274] Figure 34 Other embodiments of semiconductor device 1 are shown, which are related to Figure 5 The corresponding 3D image. Figure 35 It is along Figure 34 The cross-sectional view shown along line AA. Figure 36 It is along Figure 34 The sectional view shown is along the BB line.

[0275] Reference Figures 34-36The groove 19 can also be formed into a grid pattern by a plurality of striped first grooves 79 extending along the second direction Y and a plurality of striped second grooves 80 extending along the first direction X. Thus, each sill 24 is formed in the window portion of the grid-shaped groove 19. The plurality of sills 24 are arranged in a matrix.

[0276] In each stage 24, the source region 32 is formed on one side 22 and the other side 22 in the first direction X of the stage 24. In this manner, as... Figure 34 as well as Figure 35 As shown, a pair of strip-shaped source regions 32 extend from one side 22 to the other side 22 in the second direction Y along the depth direction of the second trench 80 in each platform 24.

[0277] Furthermore, a first contact region 34 is formed at the center of the facet 24 in the first direction X between a pair of source regions 32. The first contact region 34 is sandwiched between the pair of source regions 32 in the first direction X. The first contact region 34 penetrates the source regions 32 in the thickness direction and is connected to the main body region 18. The first contact region 34 extends from one side 22 to the other side 22 in the second direction Y along the depth direction of the second groove 80 in each facet 24. Thus, in each facet 24, the first contact region 34 and the pair of source regions 32 sandwiching the first contact region 34 from both sides are formed in a stripe shape extending along the depth direction of the second groove 80.

[0278] The electric field buffer layer 12 is formed entirely over the bottom of the lattice-shaped trench 19. Therefore, the electric field buffer layer 12 is formed in a lattice shape when viewed from above.

[0279] The second contact region 43 is selectively formed on the side surface 22 along the first direction X of each stage 24, but not on the side surface 22 along the second direction Y. Thus, in each stage 24, the channel interval 33 is ensured on the side surface 22 along the second direction Y. On the other hand, by forming the second contact region 43 on the side surface 22 along the first direction X, the electric field buffer layer 12 can be fixed to the source potential. (Refer to...) Figure 36 The first contact areas 34 of the plurality of platform surfaces 24 arranged along the second direction Y are electrically connected to each other via the second contact areas 43 spanning the adjacent platform surfaces 24 and the electric field buffer layer 12 (second layer 31).

[0280] Reference Figure 35 and Figure 36In this configuration, the embedded body 21 is embedded in the trench 19 to the first main surface 3. Thus, no groove 27 is formed, and the upper surface 25 of the embedded body 21 and the first main surface 3 are formed substantially flat. An interlayer insulating layer 55 is formed on the first main surface 3 to cover the embedded body 21 and the upper edge 56 of the trench 19. The interlayer insulating layer 55 has a contact opening 81 through which the first main surface electrode 60 is connected to the source region 32 and the first contact region 34.

[0281] (5) Figure 37 way

[0282] Figure 37 Other embodiments of semiconductor device 1 are shown, which are related to Figure 7 The corresponding sectional view. (Refer to...) Figure 37 The second contact region 43 can also be selectively formed on one side 22 of the mesa 24 and the other side 22. This allows a channel to be formed on the side 22 where the second contact region 43 is not formed, thus increasing the channel area of ​​the device. As a result, the on-resistance can be reduced.

[0283] (6) Figure 38 and Figure 39 way

[0284] Figure 38 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. Figure 39 Other embodiments of semiconductor device 1 are shown, which are related to Figure 7 The corresponding sectional view. (Refer to...) Figure 38 and Figure 39 The embedded body 21 is embedded in the trench 19 to the first main surface 3. As a result, the groove 27 is not formed, and the upper surface 25 of the embedded body 21 and the first main surface 3 are formed to be approximately flat.

[0285] An interlayer insulating layer 55 is formed on the first main surface 3 such that it covers the upper edge 56 of the embedded body 21 and the trench 19. The interlayer insulating layer 55 has a contact opening 82 through which the first main surface electrode 60 is connected to the source region 32 and the first contact region 34.

[0286] (7) Figure 40 and Figure 41 way

[0287] Figure 40 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. Figure 41 Other embodiments of semiconductor device 1 are shown, which are related to Figure 7 The corresponding sectional view. (Refer to...) Figure 40 and Figure 41The interlayer insulation layer 55 is embedded in the trench 19 to the first main surface 3.

[0288] Therefore, no groove 27 remains on the interlayer insulating layer 55, and the upper surface 57 of the interlayer insulating layer 55 and the first main surface 3 are formed approximately flat to each other. In this manner, since the upper edge 56 of the trench 19 is not covered by the interlayer insulating layer 55, the source region 32 can also be exposed over a large area on the first main surface 3. Therefore, in terms of requiring a miniaturized structure, the contact area between the first main surface electrode 60 and the source region 32 can be sufficiently ensured. Furthermore, there is no need to form a contact opening in the interlayer insulating layer 55. Since there is no need to consider the positional offset margin when forming the contact opening, the miniaturization of the device can be further advanced.

[0289] (8) Figure 42 and Figure 43 way

[0290] Figure 42 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. Figure 43 Other embodiments of semiconductor device 1 are shown, which are related to Figure 7 The corresponding sectional view. (Refer to...) Figure 42 as well as Figure 43 The drift region 8 can also be formed from a single layer of the base region 50. That is, the high-concentration region 51 can also be omitted in the semiconductor layer 7.

[0291] (9) Figure 44 and Figure 45 way

[0292] Figure 44 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. Figure 45 Other embodiments of semiconductor device 1 are shown, which are related to Figure 7 The corresponding sectional view. (Refer to...) Figure 44 as well as Figure 45 The high-concentration region 51 can also be formed by a monolayer of either the first high-concentration region 52 or the second high-concentration region 53. In this configuration, the high-concentration region 51 is formed by a monolayer of the second high-concentration region 53.

[0293] (10) Figure 46 and Figure 47 way

[0294] Figure 46 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. Figure 47 Other embodiments of semiconductor device 1 are shown, which are related to Figure 7 The corresponding sectional view. (Refer to...) Figure 46 and Figure 47 The bottom of the first high-concentration region 52 (the boundary 83 between the first high-concentration region 52 and the second high-concentration region 53) is located in the first buffer section 46 further to the second main surface 4 than the first boundary 48 between the first layer 30 and the second layer 31. Figure 46 ), and in the second buffer section 47, it is also located further to the second main surface 4 than the second boundary surface 49 of the first layer 30 and the second layer 31 ( Figure 47 ).

[0295] (11) Figure 48 and Figure 49 way

[0296] Figure 48 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. Figure 49 Other embodiments of semiconductor device 1 are shown, which are related to Figure 7 The corresponding sectional view. (Refer to...) Figure 48 as well as Figure 49 The first layer 30 of the electric field buffer layer 12 is formed at a depth in the thickness direction of the chip 2, reaching the base region 50 and then the middle part of the thickness direction of the base region 50. That is, the first layer 30 extends beyond the boundary between the base region 50 and the high concentration region 51 on the second main surface 4 and is partially buried in the base region 50.

[0297] (12) Figure 50 and Figure 51 way

[0298] Figure 50 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. Figure 51 Other embodiments of semiconductor device 1 are shown, which are related to Figure 7 The corresponding sectional view. (Refer to...) Figure 50 and Figure 51 The first layer 30 of the electric field buffer layer 12 can also be separated from the base region 50 toward the first main surface 3 in the thickness direction of the chip 2. That is, in the thickness direction of the chip 2, a portion of the high concentration region 51 (in this case, the second high concentration region 53) can also be located between the bottom of the first layer 30 and the base region 50.

[0299] (13) Figure 52 and Figure 53 way

[0300] Figure 52 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. Figure 53 Other embodiments of semiconductor device 1 are shown, which are related to Figure 7 The corresponding sectional view. (Refer to...) Figure 52 as well as Figure 53 Silicide layers 58 may not be formed on the surfaces of the source region 32 and the first contact region 34.

[0301] (14) Figure 54 way

[0302] Figure 54 Other embodiments of semiconductor device 1 are shown, which are related to Figure 5 The corresponding 3D diagram. (Refer to...) Figure 54 The element structure of semiconductor device 1 differs from that of MISFET and can also be an IGBT (Insulated Gate Bipolar Transistor) structure. In this case, a p-type collector region 84 can be formed instead of the base layer 6. Alternatively, a p-type base region 85 can be formed from the main body region 18, and an n-type emitter region 86 can be formed from the source region 32.

[0303] (15) Figure 55 and Figure 56 way

[0304] Figure 55 Other embodiments of semiconductor device 1 are shown, which are related to Figure 5 The corresponding 3D image. Figure 56 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. (Refer to...) Figure 55 and Figure 56 The source region 32 is spaced apart from one side 22 of the platform surface 24 and is selectively formed on the other side 22 of the platform surface 24. On the other hand, the first contact region 34 is adjacent to the source region 32 in the width direction of the platform surface 24 and is selectively formed on one side 22 of the platform surface 24.

[0305] The source region 32 and the first contact region 34 are arranged in a strip-like pattern along the depth direction of the trench 19 on each stage 24. That is, in this configuration, one source region 32 and one first contact region 34 are formed on each stage 24, and they are formed as a whole in a stripe shape. A channel section 33 for forming a channel is selectively formed on the other side of the width direction of the stage 24. On the other hand, a second contact region 43 is selectively formed on one side of the stage 24.

[0306] (16) Figure 57 and Figure 58 way

[0307] Figure 57 Other embodiments of semiconductor device 1 are shown, which are related to Figure 5The corresponding 3D image. Figure 58 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view.

[0308] Reference Figure 57 and Figure 58 In each stage 24, source regions 32 are formed on one side 22 and the other side 22 in a first direction X of the stage 24. In this configuration, a pair of strip-shaped source regions 32 extend in a stripe-like pattern along the depth direction of the groove 19 in each stage 24.

[0309] Furthermore, a first contact region 34 is formed at the center of the facet 24 in the first direction X between a pair of source regions 32. The first contact region 34 is sandwiched between the pair of source regions 32 in the first direction X. The first contact region 34 penetrates the source regions 32 in the thickness direction and is connected to the main body region 18. The first contact region 34 extends in a strip shape along the depth direction of the groove 19 in each facet 24. Thus, in each facet 24, the first contact region 34 and the pair of source regions 32 sandwiching the first contact region 34 from both sides are formed in a stripe shape extending along the depth direction of the groove 19.

[0310] Reference Figure 58 The embedded body 21 is embedded in the trench 19 to the first main surface 3. Thus, no groove 27 is formed, and the upper surface 25 of the embedded body 21 and the first main surface 3 are formed substantially flat. An interlayer insulating layer 55 is formed on the first main surface 3 to cover the embedded body 21 and the upper edge 56 of the trench 19. The interlayer insulating layer 55 has a contact opening 87 through which the first main surface electrode 60 is connected to the source region 32 and the first contact region 34.

[0311] (17) Figure 59 and Figure 60 way

[0312] Figure 59 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. Figure 60 Other embodiments of semiconductor device 1 are shown, which are related to Figure 7 The corresponding sectional view.

[0313] Reference Figure 59 as well as Figure 60An electric field buffer layer 12 is formed by extending from one end of the trench 19 to the other in the width direction of the trench 19. More specifically, the electric field buffer layer 12 is integrally formed with the main body region 18 and is selectively formed on the opposite side of the trench 19 in the first direction X. In this manner, the electric field buffer layer 12 extends downward from a portion of the main body region 18 of each stage surface 24 in the vertical direction Z below the bottom surface 23 of the trench 19 and extends along the horizontal direction along the first main surface 3, overlapping the bottom surface 23 of the trench 19.

[0314] The electric field buffer layer 12 forms at least a portion of the side surface 22 and bottom surface 23 of one of the opposing side surfaces 22 of a pair of trenches 19, and is in contact with the trench insulating film 20. The electric field buffer layer 12 has a generally L-shaped exposed surface in each trench 19, which is exposed as the bottom surface 23 of the trench 19, which is continuous with the lower part of the side surface 22.

[0315] (18) Figures 61-63 way

[0316] Figure 61 Other embodiments of semiconductor device 1 are shown, which are related to Figure 5 The corresponding 3D image. Figure 62 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. Figure 63 Other embodiments of semiconductor device 1 are shown, which are related to Figure 7 The corresponding sectional view. (Refer to...) Figures 61-63 In this method, a Schottky barrier diode 88 is formed as a component structure.

[0317] More specifically, the semiconductor layer 7 is formed as a single layer of base region 50 (drift region 8). A first main surface electrode 60 is Schottky-bonded to the drift region 8. Thus, a Schottky barrier is formed between the first main surface electrode 60 (Schottky electrode) and the drift region 8, thereby constituting a Schottky barrier diode 88. Figure 61 As shown, in each of the facet surfaces 24, multiple Schottky regions 89 and multiple first contact regions 34, which form Schottky barriers, are alternately arranged in the depth direction of the trench 19.

[0318] Furthermore, in this method, the silicide layer 58 and the interlayer insulating layer 55 are not provided. By omitting the silicide layer 58, Schottky bonding between the drift region 8 and the first main surface electrode 60 can be ensured. The first main surface electrode 60 (barrier layer 61) is directly connected to the embedded body 21.

[0319] (19) Figure 64 and Figure 65 way

[0320] Figure 64 Other embodiments of semiconductor device 1 are shown, which are related to Figure 5 The corresponding 3D image. Figure 65 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. (Refer to...) Figure 64 and Figure 65 In this configuration, a pn diode 90 is formed as a component structure.

[0321] More specifically, the semiconductor layer 7 (drift region 8) is formed as a single-layer cathode region 91. The drain pad 16 (in this configuration, the cathode electrode) is electrically connected to the cathode region 91 via the base layer 6. Additionally, the body region 18 is formed as an anode region 92, exposed from the first main surface 3. The first main surface electrode 60 (in this configuration, the anode electrode) makes ohmic contact with the anode region 92. A pn ​​junction is formed between the anode region 92 and the cathode region 91, thereby constituting a pn diode 90. Figure 64 As shown, in each facet 24, a p-type integral impurity region 44 is formed across the entire surface of the first main facet 3.

[0322] In addition, in this method, no interlayer insulation layer 55 is provided. The first main surface electrode 60 (barrier layer 61) is directly connected to the embedded body 21.

[0323] (20) Figure 66 and Figure 67 way

[0324] Figure 66 Other embodiments of semiconductor device 1 are shown, which are related to Figure 5 The corresponding 3D image. Figure 67 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. Figure 66 as well as Figure 67 yes Figures 61-63 This is a variation of the Schottky barrier diode 88. In this embodiment, the drift region 8 comprises a stacked structure of a base region 50 and a high-concentration region 51. Furthermore, the electric field buffer layer 12 formed at the bottom of the trench 19 is not a stacked structure of the first layer 30 and the second layer 31, but a single-layer structure. The single-layer electric field buffer layer 12 can also be used... Figures 1 to 60 The MISFET and IGBT shown Figure 54 The electric field buffer layer 12 at the bottom of the groove 19.

[0325] (twenty one) Figure 68 and Figure 69 way

[0326] Figure 68 Other embodiments of semiconductor device 1 are shown, which are related to Figure 5The corresponding 3D image. Figure 69 Other embodiments of semiconductor device 1 are shown, which are related to Figure 6 The corresponding sectional view. Figure 68 and Figure 69 yes Figure 64 and Figure 65 A modified example of the pn diode 90. In this embodiment, the cathode region 91 includes a stacked structure of the base region 50 and the high-concentration region 51. Furthermore, the electric field buffer layer 12 formed at the bottom of the trench 19 is not a stacked structure of the first layer 30 and the second layer 31, but a single-layer structure.

[0327] The embodiments of this disclosure have been described, but this disclosure can also be implemented in other ways.

[0328] For example, in the aforementioned embodiments, a base layer 6 and a semiconductor layer 7, each comprising a SiC single crystal, are used. However, at least one or all of the base layer 6 and the semiconductor layer 7 may also comprise a single crystal of a wide-bandgap semiconductor other than SiC.

[0329] A wide bandgap semiconductor is a semiconductor with a bandgap larger than that of silicon. Examples of single crystals that can be considered wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga₂O₃). The base layer 6 and the semiconductor layer 7 can be composed of the same type of single crystal or different types of single crystals. Alternatively, at least one or all of the base layer 6 and the semiconductor layer 7 can be made of silicon (Si).

[0330] Hereinafter, examples of features extracted from this specification and accompanying drawings are shown. Hereinafter, alphanumeric characters, etc., denote corresponding constituent elements in the foregoing embodiments, but do not imply that the scope of each clause is limited to the embodiments. The term "semiconductor device" in the following item can be replaced as needed with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "GBT device," "diode device," etc.

[0331] Appendix A-1. A semiconductor device 1, comprising:

[0332] Chip 2 has a first main surface 3 and a second main surface 4 on its opposite side;

[0333] The first impurity region 7 of the first conductivity type is formed on the surface portion of the first main surface 3;

[0334] The second impurity region 18 of the second conductivity type is formed on the surface of the first impurity region 7.

[0335] The third impurity region 32 of the first conductivity type is formed on the surface portion of the second impurity region 18;

[0336] The trench 19 extends from the first main surface 3 through the third impurity region 32 and the second impurity region 18 to the first impurity region 7.

[0337] A trench insulating film 20 is formed on the inner surface of the trench 19;

[0338] A conductive embedded body 21 is embedded in the trench 19 through the trench insulating film 20; and

[0339] A second conductive electric field buffer layer 12 is formed at the bottom 23 of the trench 19.

[0340] The electric field buffer layer 12 includes: a first layer 30 formed from the bottom 23 of the trench 19 toward the second main surface 4, having a first impurity concentration; and a second layer 31 formed between the first layer 30 and the bottom 23 of the trench 19, having a second impurity concentration higher than the first impurity concentration.

[0341] According to this structure, the impurity concentration of the first layer 30 of the electric field buffer layer 12 is relatively lower than that of the second layer 31. Since the depletion layer can extend relatively far from the first pn junction between the first layer 30 and the first impurity region 7, the device breakdown voltage can be improved. On the other hand, the impurity concentration of the second layer 31 of the electric field buffer layer 12 is relatively higher than that of the first layer 30. The width of the depletion layer extending from the second pn junction between the second layer 31 and the first impurity region 7 can be narrower than the width of the depletion layer extending from the first pn junction. As a result, the depletion layer extending from the second pn junction towards the bottom of the trench 19 can be narrowed, which can buffer the electric field strength applied to the trench insulating film 20. In other words, it is possible to balance the buffering of the electric field strength applied to the trench insulating film 20 and the improvement of the device breakdown voltage.

[0342] Appendix A-2. The semiconductor device 1 according to Appendix A-1, wherein,

[0343] The electric field buffer layer 12 is formed as a strip extending in the depth direction Y of the trench 19, with the first layer 30 and the second layer 31 stacked in a continuous manner.

[0344] According to this structure, the electric field strength applied to the trench insulating film 20 can be buffered over a wide area in the depth direction Y of the trench 19, and the withstand voltage of the device can be improved.

[0345] Appendix A-3. The semiconductor device 1 according to Appendix A-2 includes:

[0346] A first contact region 34 of the second conductivity type is formed adjacent to the third impurity region 32 on the surface portion of the second impurity region 18 and connected to the second impurity region 18; and

[0347] The second contact area 43 is formed from the first contact area 34 toward the second main surface 4 along the side 22 of the groove 19 and is connected to the second layer 31 of the electric field buffer layer 12.

[0348] According to this structure, the potential of the first layer 30 of the electric field buffer layer 12 can be fixed to the same potential as the third impurity region 32 via the first contact region 34 and the second contact region 43.

[0349] Appendix A-4. The semiconductor device 1 according to Appendix A-3, wherein,

[0350] The plurality of third impurity regions 32 and the plurality of first contact regions 34 are arranged alternately along the depth direction Y of the trench 19 in such a way that they are exposed on the side 22 of the trench 19.

[0351] According to this structure, since multiple third impurity regions 32 and multiple first contact regions 34 are arranged alternately, the current path (channel) formed in the depth direction Z of the trench 19 can be formed in a balanced and good manner along the depth direction Y of the trench 19.

[0352] Appendix A-5. The semiconductor device 1 according to Appendix A-3 or Appendix A-4, wherein,

[0353] The plurality of grooves 19 are formed in a stripe pattern.

[0354] A platform surface 24 is formed, which is sandwiched between adjacent grooves 19. Starting from the first main surface 3, the third impurity region 32, the second impurity region 18, and the first impurity region 7 are formed sequentially.

[0355] The first contact area 34 is adjacent to the third impurity area 32 in the depth direction Y of the trench 19, and is formed from one side 22 of the platform surface 24 to the other side 22.

[0356] The second contact area 43 is formed along both one side 22 and the other side 22 of the table surface 24.

[0357] According to this structure, the third impurity region 32 and the first contact region 34 are arranged adjacently in the depth direction Y of the trench 19 on each of the facets 24, thus enabling the miniaturization of the device.

[0358] Appendix A-6. The semiconductor device 1 according to Appendix A-5, wherein,

[0359] The spacing PT of the plurality of grooves 19 is greater than 0.1 μm and less than 5 μm.

[0360] This structure enables the miniaturization of devices.

[0361] Appendix A-7. Semiconductor device 1 according to any one of Appendices A-1 to A-6, wherein,

[0362] A groove 27 is formed in the upper part of the trench 19, which is divided by the upper surface 25 of the embedded body 21 and the side surface 22 of the trench 19.

[0363] include:

[0364] An interlayer insulating layer 55 is embedded in the groove 27 such that the upper edge 56 of the trench 19 is exposed.

[0365] A first main surface electrode 60 is formed on the first main surface 3 in such a way as to cover the interlayer insulating layer 55 and is connected to the third impurity region 32.

[0366] According to this structure, the interlayer insulating layer 55 is embedded in the groove 27 of the trench 19, and the upper edge 56 of the trench 19 is exposed. This allows the third impurity region 32 to be exposed with a relatively wide area in the first main surface 3. Therefore, in terms of requiring a miniaturized structure, the contact area between the first main surface electrode 60 and the third impurity region 32 can be sufficiently ensured. Furthermore, there is no need to form contact openings in the interlayer insulating layer 55. Since there is no need to consider the positional offset margin when forming contact openings, further miniaturization of the device can be achieved.

[0367] Appendix A-8. The semiconductor device 1 according to Appendix A-7, wherein,

[0368] The upper surface 57 of the interlayer insulating layer 55 is located in the depth direction Z of the trench 19 on the side closer to the bottom 23 of the trench 19 than the first main surface 3.

[0369] The first main surface electrode 60 is connected to the third impurity region 32 in the side surface 22 of the groove 27 and the first main surface 3.

[0370] According to this structure, since the contact area between the first main electrode 60 and the third impurity region 32 can be increased, the contact resistance between the two can be reduced.

[0371] Appendix A-9. Semiconductor device 1 according to any one of Appendices A-1 to A-8, wherein,

[0372] The first impurity region 7 includes: a base region 50, which is formed away from the second impurity region 18 on the side of the electric field buffer layer 12 closer to the second main surface 4; and a high concentration region 51, which is formed on the side of the electric field buffer layer 12 between the base region 50 and the second impurity region 18, and has a higher impurity concentration than the base region 50.

[0373] According to this structure, a depletion layer with a wider width than the relatively low-concentration base region 50 can be extended, thus ensuring an increase in device breakdown voltage. Furthermore, by configuring a relatively high-concentration region 51 on the side of the electric field buffer layer 12, excessive expansion of the depletion layer around the periphery of the electric field buffer layer 12 can be suppressed. By suppressing the expansion of this depletion layer, a current path can be ensured, thus suppressing an increase in on-resistance.

[0374] Appendix A-10. The semiconductor device 1 according to Appendix A-9, wherein,

[0375] The high-concentration region 51 includes: a first high-concentration region 52; and a second high-concentration region 53, which is formed on the side closer to the second main surface 4 than the first high-concentration region 52, in a manner that covers the bottom 23 of the trench 19 and the boundary 54 of the electric field buffer layer 12, and has a lower impurity concentration than the first high-concentration region 52.

[0376] According to this structure, the first high-concentration region 52 serves as a current spreading layer (CSL) that extends the current flowing through the channel to the entire area between adjacent trenches 19, thereby reducing on-resistance. Furthermore, by configuring a relatively low-concentration second high-concentration region 53 on the second main surface 4 side of the first high-concentration region 52, an improvement in device breakdown voltage can also be achieved.

[0377] Appendix A-11. The semiconductor device 1 according to Appendix A-10, wherein,

[0378] The first high-concentration region 52 is in contact with the second impurity region 18 and is formed from the second impurity region 18 at a depth shallower than the bottom 23 of the trench 19 in the thickness direction Z of the chip 2.

[0379] According to this structure, the bottom of the first high-concentration region 52 is shallower than the bottom of the trench 19 and does not contact the bottom of the trench 19 and the boundary 54 of the electric field buffer layer 12. Therefore, even if the concentration of the first high-concentration region 52 is increased, the impact on the device withstand voltage and the electric field of the trench insulating film 20 can be reduced.

[0380] Note A-12. Semiconductor device 1 according to any one of Notes A-9 to A-11, wherein,

[0381] The first layer 30 of the electric field buffer layer 12 is formed in the thickness direction Z of the chip 2 to a depth reaching the base region 50.

[0382] According to this structure, the first pn junction can be formed between the first layer 30 and the base region 50, thus enabling the depletion layer to extend further and further improving the device's withstand voltage.

[0383] Appendix A-13. The semiconductor device 1 according to Appendix A-12, wherein,

[0384] The bottom of the first layer 30 of the electric field buffer layer 12 contacts the base region 50, forming a boundary between them.

[0385] According to this structure, the first layer 30 is in contact with the base region 50, but the contact area is prevented from becoming too large. This allows for a greater extension of the depletion layer, while ensuring the extension range is appropriate, thus guaranteeing a sufficient current path.

[0386] Appendix A-14. Semiconductor device 1 according to any one of Appendices A-3 to A-6, wherein,

[0387] The chip 2 is a Si-based semiconductor chip 2, comprising:

[0388] A silicide layer 58 is formed on each surface of the third impurity region 32 and the first contact region 34; and

[0389] The first main electrode 60 is connected to the third impurity region 32 and the first contact region 34 via the silicide layer 58.

[0390] According to this structure, the contact resistance relative to the third impurity region 32 and the first contact region 34 can be reduced.

[0391] Appendix A-15. The semiconductor device 1 according to any one of Appendices A-1 to A-14 comprises:

[0392] The drain region 6 of the first conductivity type is formed on the side of the second main surface 4 relative to the first impurity region 7.

[0393] The main body region 18 is formed by the second impurity region 18;

[0394] Source region 32, which is formed by the third impurity region 32; and

[0395] The trench gate structure 11 is formed by the trench 19, the trench insulating film 20 and the embedded body 21.

[0396] Appendix A-16. The semiconductor device 1 according to any one of Appendices A-1 to A-14 comprises:

[0397] The collector region 84 of the second conductivity type is formed on the side of the second main surface 4 relative to the first impurity region 7.

[0398] The base region 85 is formed by the second impurity region 18;

[0399] Emitter region 86, which is formed by the third impurity region 32; and

[0400] The trench gate structure 11 is formed by the trench 19, the trench insulating film 20 and the embedded body 21.

[0401] Note A-17. Semiconductor device 1 according to any one of Notes A-1 to A-16, wherein,

[0402] The chip 2 is a SiC chip 2.

[0403] Note A-18. The semiconductor device 1 according to Note A-3 or Note A-4, wherein,

[0404] The plurality of grooves 19 are formed in a stripe pattern.

[0405] A platform surface 24 is formed, which is sandwiched between adjacent grooves 19. Starting from the first main surface 3, the third impurity region 32, the second impurity region 18, and the first impurity region 7 are formed sequentially.

[0406] The third impurity region 32 is selectively formed on the other side 22 of the table surface 24 at intervals from one side 22 of the table surface 24.

[0407] Appendix A-19. The semiconductor device 1 according to Appendix A-18, wherein,

[0408] The first contact area 34 is adjacent to the third impurity area 32 in the width direction of the table surface 24 and is selectively formed on one side 22 of the table surface 24.

[0409] Appendix A-20. Semiconductor device 1 according to Appendix A-19, wherein,

[0410] The third impurity region 32 and the first contact region 34 are formed in a stripe shape on the surface 24 extending along the depth direction Y of the groove 19.

[0411] Note A-21. The semiconductor device 1 according to Note A-1 or Note A-2, wherein,

[0412] The plurality of grooves 19 are formed in a stripe pattern.

[0413] A platform surface 24 is formed, which is sandwiched between adjacent grooves 19. Starting from the first main surface 3, the third impurity region 32, the second impurity region 18, and the first impurity region 7 are formed sequentially.

[0414] The third impurity region 32 is formed on one side 22 and the other side 22 of the platform surface 24.

[0415] Appendix A-22. Semiconductor device 1 according to Appendix A-21,

[0416] The first contact region 34, including the second conductivity type, is formed adjacent to the third impurity region 32 in the central portion of the width direction of the table surface 24, which is away from one side 22 and the other side 22 of the table surface 24, and is connected to the second impurity region 18.

[0417] Note A-23. Semiconductor device 1 according to Note A-22, wherein,

[0418] The first contact area 34 and a pair of third impurity areas 32 sandwiching the first contact area 34 from both sides of the table surface 24 are formed in the table surface 24 as stripes extending along the depth direction Y of the groove 19.

[0419] Appendix A-24. Semiconductor device 1 according to any one of Appendices A-3 to A-6, wherein,

[0420] The second impurity region 18 includes: a first portion 35 formed directly below the third impurity region 32, having a first thickness BT1; and a second portion 36 formed directly below the first contact region 34, having a second thickness BT2 greater than the first thickness BT1.

[0421] Appendix A-25. The semiconductor device 1 according to Appendix A-8, wherein,

[0422] The first main surface electrode 60 includes: a barrier layer 61 formed along the inner surface of the groove 27, further dividing the groove 27 into a second groove 63; and a main body layer 62 formed on the barrier layer 61 and partially embedded in the second groove 63.

[0423] Appendix A-26. The semiconductor device 1 according to Appendix A-8, wherein,

[0424] The chip 2 is a Si-based semiconductor chip 2.

[0425] This includes a silicide layer 58, which is formed along the surface of the third impurity region 32 and the inner surface of the groove 27.

[0426] The first main electrode 60 is connected to the third impurity region 32 via the silicide layer 58.

[0427] Note A-27. The semiconductor device 1 according to Note A-26, wherein,

[0428] The first main surface electrode 60 includes: a barrier layer 61 formed along the inner surface of the groove 27 and connected to the silicide layer 58, further dividing the groove 27 into a second groove 63; and a main body layer 62 formed on the barrier layer 61 and partially embedded in the second groove 63.

[0429] Note A-28. The semiconductor device 1 according to Note A-25 or Note A-27, wherein,

[0430] The barrier layer 61 is formed of Ti-based metal, and the main body layer 62 is formed of Al-based metal.

[0431] Appendix A-29. Semiconductor device 1 according to any one of Appendices A-1 to A-28, wherein,

[0432] The electric field buffer layer 12 is formed across one end of the trench 19 and the other end of the trench 19 in the width direction.

[0433] Appendix A-30. Semiconductor device 1 according to any one of Appendices A-1 to A-28, wherein,

[0434] The electric field buffer layer 12 is formed separately from one end of the trench 19 to the other in the width direction of the trench 19.

[0435] Appendix A-31. Semiconductor device 1 according to any one of Appendices A-1 to A-30, wherein,

[0436] The first layer 30 has first buffer thicknesses RT1A and RT1B.

[0437] The second layer 31 has a second buffer thickness RT2A, RT2B that is smaller than the first buffer thickness RT1A, RT1B.

[0438] Appendix B-1. A semiconductor device 1, comprising:

[0439] Chip 2 has a first main surface 3 and a second main surface 4 on its opposite side;

[0440] A plurality of striped gate trenches 19 are formed on the surface portion of the first main surface 3 and are spaced apart in the first direction X.

[0441] A gate insulating film 20 is formed on the inner surface of each of the gate trenches 19;

[0442] Gate electrode 21 is embedded in the gate trench 19 through the gate insulating film 20;

[0443] A plurality of striped mesa faces 24 are sandwiched between adjacent gate trenches 19 and are spaced apart in the first direction X.

[0444] A first impurity region 7 of a first conductivity type is formed across the plurality of mesa sections 24;

[0445] The second impurity region 18 of the second conductivity type is formed in the surface portion of the first impurity region 7 in each of the mesa 24.

[0446] The third impurity region 32 of the first conductivity type is formed on the surface portion of the second impurity region 18;

[0447] The first contact region 34 of the second conductivity type is adjacent to the third impurity region 32 in the depth direction Y of the gate trench 19, and is formed by transversely crossing the mesa 24 in the width direction, and is connected to the second impurity region 18; and

[0448] A second conductivity type electric field buffer layer 12 is formed at the bottom 23 of the gate trench 19.

[0449] The electric field buffer layer 12 has a stacked structure, comprising: a first layer 30 formed from the bottom 23 of the gate trench 19 toward the second main surface 4 and having a first impurity concentration; and a second layer 31 formed between the first layer 30 and the bottom 23 of the gate trench 19 in such a way that it is exposed at the bottom 23 of the gate trench 19 and has a second impurity concentration higher than the first impurity concentration.

[0450] Appendix B-2. According to Appendix B-1, the semiconductor device 1, wherein,

[0451] The electric field buffer layer 12 is formed as a strip extending in the depth direction Y of the gate trench 19 in a continuous manner with the stacked structure in the trench 19.

[0452] Appendix B-3. Semiconductor device 1 according to Appendix B-1 or Appendix B-2,

[0453] It includes a second contact area 43, which extends from the first contact area 34 toward the second main surface 4 along both sides 22 of the platform surface 24 and is connected to the second layer 31 of the electric field buffer layer 12.

[0454] An integral impurity region 44 of the second conductivity type is formed by the first contact region 34, the second contact region 43 and the second layer 31.

[0455] Appendix B-4. The semiconductor device 1 according to Appendix B-3, wherein,

[0456] The two corners 45 of the gate trench 19 in the width direction are covered by the integral impurity region 44.

[0457] Appendix B-5. The semiconductor device 1 according to Appendix B-3 or Appendix B-4, wherein,

[0458] Multiple integral impurity regions 44 are formed at intervals along the depth direction Y of the gate trench 19.

[0459] Appendix B-6. Semiconductor device 1 according to any one of Appendices B-3 to B-5, wherein,

[0460] In the width direction of the gate trench 19, the integral impurity region 44 has a width that is wider than the first layer 30 of the electric field buffer layer 12.

[0461] Appendix B-7. Semiconductor device 1 according to any one of Appendices B-1 to B-6, wherein,

[0462] The spacing PT of the plurality of gate trenches 19 is greater than 0.1 μm and less than 5 μm.

[0463] Appendix B-8. Semiconductor device 1 according to any one of Appendices B-1 to B-7, wherein,

[0464] A groove 27 is formed on the upper part of the gate trench 19, which is divided by the upper surface 25 of the gate electrode 21 and the side surface 22 of the gate trench 19.

[0465] include:

[0466] An interlayer insulating layer 55 is embedded in the groove 27 such that the upper edge 56 of the gate trench 19 is exposed; and

[0467] A first main surface electrode 60 is formed on the first main surface 3 in such a way as to cover the interlayer insulating layer 55 and is connected to the third impurity region 32.

[0468] Appendix B-9. The semiconductor device 1 according to Appendix B-8, wherein,

[0469] The upper surface 57 of the interlayer insulating layer 55 is located in the depth direction Z of the gate trench 19 on the side closer to the bottom 23 of the gate trench 19 than the first main surface 3.

[0470] The first main surface electrode 60 is connected to the third impurity region 32 in the side surface 22 of the groove 27 and the first main surface 3.

[0471] Appendix B-10. Semiconductor device 1 according to any one of Appendices B-1 to B-9, wherein,

[0472] The first impurity region 7 includes: a base region 50, which is formed away from the second impurity region 18 on the side closer to the second main surface 4 than the electric field buffer layer 12; and a high concentration region 51, which is formed on the side of the electric field buffer layer 12 between the base region 50 and the second impurity region 18, and has a higher impurity concentration than the base region 50.

[0473] Appendix B-11. The semiconductor device 1 according to Appendix B-10, wherein,

[0474] The high-concentration region 51 includes: a first high-concentration region 52; and a second high-concentration region 53, which is formed on the side closer to the second main surface 4 than the first high-concentration region 52, in a manner that covers the bottom 23 of the gate trench 19 and the boundary 54 of the electric field buffer layer 12, and has a lower impurity concentration than the first high-concentration region 52.

[0475] Appendix B-12. The semiconductor device 1 according to Appendix B-11, wherein,

[0476] The first high-concentration region 52 is in contact with the second impurity region 18 and is formed from the second impurity region 18 at a depth shallower than the bottom 23 of the gate trench 19 in the thickness direction Z of the chip 2.

[0477] Appendix B-13. Semiconductor device 1 according to any one of Appendices B-10 to B-12, wherein,

[0478] The first layer 30 of the electric field buffer layer 12 is formed in the thickness direction Z of the chip 2 to a depth reaching the base region 50.

[0479] Appendix B-14. The semiconductor device 1 according to Appendix B-13, wherein,

[0480] The bottom of the first layer 30 of the electric field buffer layer 12 contacts the base region 50, forming a boundary between them.

[0481] Appendix B-15. Semiconductor device 1 according to any one of Appendices B-1 to B-14, wherein,

[0482] The chip 2 is a Si-based semiconductor chip 2.

[0483] include:

[0484] A silicide layer 58 is formed on each surface of the third impurity region 32 and the first contact region 34; and

[0485] The first main electrode 60 is connected to the third impurity region 32 and the first contact region 34 via the silicide layer 58.

[0486] Appendix B-16. Semiconductor device 1 according to any one of Appendices B-1 to B-15, wherein,

[0487] The chip 2 is a SiC chip 2.

[0488] Appendix C-1. A semiconductor device 1, comprising:

[0489] Chip 2 has a first main surface 3 and a second main surface 4 on the opposite side thereon, and an active region 9 is formed on the first main surface 3;

[0490] The first impurity region 7 of the first conductivity type is formed on the surface of the active region 9;

[0491] The component structure is formed on the surface layer of the first impurity region 7;

[0492] A trench 19 is formed in the active region 9 and has a bottom in the first impurity region 7;

[0493] A trench insulating film 20 is formed on the inner surface of the trench 19;

[0494] A conductive embedded body 21 is embedded in the trench 19 through the trench insulating film 20; and

[0495] A second conductive electric field buffer layer 12 is formed at the bottom 23 of the trench 19.

[0496] The electric field buffer layer 12 includes: a first layer 30 formed from the bottom 23 of the trench 19 toward the second main surface 4, having a first impurity concentration; and a second layer 31 formed between the first layer 30 and the bottom 23 of the trench 19, having a second impurity concentration higher than the first impurity concentration.

[0497] Appendix C-2. The semiconductor device 1 according to Appendix C-1, wherein,

[0498] The electric field buffer layer 12 is formed as a strip extending in the depth direction Y of the trench 19, with the first layer 30 and the second layer 31 stacked in a continuous manner.

[0499] Appendix C-3. The semiconductor device 1 according to Appendix C-2, wherein it comprises:

[0500] A first contact region 34 of the second conductivity type is formed adjacent to the trench 19 on the surface portion of the first main surface 3; and

[0501] The second contact area 43 is formed from the first contact area 34 toward the second main surface 4 along the side 22 of the groove 19 and is connected to the second layer 31 of the electric field buffer layer 12.

[0502] Appendix C-4. The semiconductor device 1 according to Appendix C-3, wherein,

[0503] The plurality of grooves 19 are formed in a stripe pattern.

[0504] A platform 24 is formed by the plurality of adjacent grooves 19.

[0505] The first contact area 34 extends from one side 22 of the table surface 24 to the other side 22.

[0506] The second contact area 43 is formed along both one side 22 and the other side 22 of the table surface 24.

[0507] Appendix C-5. The semiconductor device 1 according to Appendix C-4, wherein,

[0508] The spacing PT of the plurality of grooves 19 is greater than 0.1 μm and less than 5 μm.

[0509] Appendix C-6. Semiconductor device 1 according to any one of Appendices C-1 to C-5, wherein,

[0510] A groove 27 is formed in the upper part of the trench 19, which is divided by the upper surface 25 of the embedded body 21 and the side surface 22 of the trench 19.

[0511] include:

[0512] An interlayer insulating layer 55 is embedded in the groove 27 with the upper edge 56 of the trench 19 exposed; and

[0513] A first main surface electrode 60 is formed on the first main surface 3 in such a way as to cover the interlayer insulating layer 55 and is connected to the element structure.

[0514] Appendix C-7. The semiconductor device 1 according to Appendix C-6, wherein,

[0515] The upper surface 57 of the interlayer insulating layer 55 is located in the depth direction Z of the trench 19 on the side closer to the bottom 23 of the trench 19 than the first main surface 3.

[0516] The first main surface electrode 60 is connected to the component structure on the side 22 of the groove 27 and the first main surface 3.

[0517] Appendix C-8. Semiconductor device 1 according to any one of Appendices C-3 to C-5, wherein,

[0518] The chip 2 is a Si-based semiconductor chip 2.

[0519] include:

[0520] A silicide layer 58 is formed on each surface of the first contact region 34; and

[0521] The first main electrode 60 is connected to the first contact region 34 via the silicide layer 58.

[0522] Appendix D-1. A semiconductor device 1, comprising:

[0523] Chip 2 has a first main surface 3 and a second main surface 4 on the opposite side thereon, and an active region 9 is formed on the first main surface 3;

[0524] The first impurity region 7 of the first conductivity type is formed on the surface of the active region 9;

[0525] The component structure is formed on the surface layer of the first impurity region 7;

[0526] A trench 19 is formed in the active region 9 and has a bottom in the first impurity region 7;

[0527] A trench insulating film 20 is formed on the inner surface of the trench 19;

[0528] A conductive embedded body 21 is embedded in the trench 19 through the trench insulating film 20; and

[0529] A second conductive electric field buffer layer 12 is formed at the bottom 23 of the trench 19.

[0530] The first impurity region 7 includes: a base region 50, which is formed away from the second main surface 4 compared to the electric field buffer layer 12; and a high concentration region 51, which is formed on the side of the electric field buffer layer 12 between the base region 50 and the first main surface 3, and has a higher impurity concentration than the base region 50.

[0531] Appendix D-2. The semiconductor device 1 according to Appendix D-1, wherein,

[0532] The high-concentration region 51 includes: a first high-concentration region 52; and a second high-concentration region 53, which is formed on the side of the second main surface 4 closer to the first high-concentration region 52, in a manner that covers the bottom 23 of the trench 19 and the boundary 54 of the electric field buffer layer 12, and has a lower impurity concentration than the first high-concentration region 52.

[0533] Appendix D-3. The semiconductor device 1 according to Appendix D-1 or Appendix D-2, wherein,

[0534] The electric field buffer layer 12 is formed in the thickness direction Z of the chip 2 to a depth reaching the base region 50.

[0535] Appendix D-4. The semiconductor device 1 according to Appendix D-3, wherein,

[0536] The bottom of the electric field buffer layer 12 contacts the base region 50, forming a boundary between the two regions.

[0537] Symbol Explanation

[0538] 1—Semiconductor device, 2—Chip, 3—First main surface, 4—Second main surface, 5A—First side surface, 5B—Second side surface, 5C—Third side surface, 5D—Fourth side surface, 6—Base layer, 7—Semiconductor layer, 8—Drift region, 9—Active region, 10—Outer peripheral region, 11—Trench structure, 12—Electric field buffer layer, 13—Gate pad, 14—Gate wiring, 14A—First gate wiring, 14B—Second gate wiring, 15—Source pad, 16—Drain pad, 17—Field region, 18—Main region, 19—Trench, 20—Trench insulating film, 2 1—Embedded body, 22—Side side, 23—Bottom surface, 24—Platform surface, 25—Upper surface, 26—Step, 27—Groove, 28—Protrusion, 29—Side side, 30—First layer, 31—Second layer, 32—Source region, 33—Channel section, 34—First contact region, 35—First main body, 36—Second main body, 37—Base boundary surface, 38—Main body protrusion, 39—First boundary surface, 40—First step, 41—Second boundary surface, 42—Second step, 43—Second contact region, 44—Integral impurity region, 45—Corner, 46— 47—Second buffer section, 48—First boundary surface, 49—Second boundary surface, 50—Base region, 51—High concentration region, 52—First high concentration region, 53—Second high concentration region, 54—Boundary section, 55—Interlayer insulating layer, 56—Upper edge, 57—Upper surface, 58—Silicide layer, 59—Non-silicide section, 60—First main electrode, 61—Barrier layer, 62—Main layer, 63—Second groove, 64—Resin layer, 65—Wafer, 66—First wafer main surface, 67—Second wafer main surface, 68—Wafer side surface, 69— Markers: 70—Device region, 71—Pre-cut line, 72—First mask, 73—First opening, 74—Second mask, 75—Second opening, 76—Insulating film, 77—Base electrode film, 78—Base insulating film, 79—First trench, 80—Second trench, 81—Contact opening, 82—Contact opening, 83—Boundary surface, 84—Collector region, 85—Base region, 86—Emitter region, 87—Contact opening, 88—Schottky barrier diode, 89—Schottky region, 90—PN diode, 91—Cathode region, 92—Anode region.

Claims

1. A semiconductor device, characterized in that, include: A chip having a first main surface and a second main surface on its opposite side; A first impurity region of a first conductivity type is formed on the surface portion of the first main surface; A second impurity region of a second conductivity type is formed on the surface portion of the first impurity region; The third impurity region of the first conductivity type is formed on the surface of the second impurity region; A trench that extends from the first main surface through the third impurity region and the second impurity region to the first impurity region; A trench insulating film formed on the inner surface of the trench; A conductive embedded body is embedded in the trench through the trench insulating film; as well as A second type of conductive electric field buffer layer is formed at the bottom of the trench. The electric field buffer layer includes: a first layer formed from the bottom of the trench toward the second main surface side, and having a first impurity concentration; And a second layer, which is formed between the first layer and the bottom of the trench, and has a second impurity concentration that is higher than the first impurity concentration.

2. The semiconductor device according to claim 1, characterized in that, The electric field buffer layer is formed as a strip extending in the depth direction of the trench, with the first layer and the second layer stacked in a continuous manner.

3. The semiconductor device according to claim 2, characterized in that, include: The first contact region of the second conductivity type is formed adjacent to the third impurity region on the surface portion of the second impurity region and is connected to the second impurity region. as well as The second contact area is formed along the side of the groove from the first contact area toward the second main surface and is connected to the second layer of the electric field buffer layer.

4. The semiconductor device according to claim 3, characterized in that, The plurality of third impurity regions and the plurality of first contact regions are arranged alternately along the depth direction of the trench in a manner that exposes the sides of the trench.

5. The semiconductor device according to claim 3 or 4, characterized in that, The multiple grooves are formed into a stripe pattern. A platform surface is formed, which is sandwiched between adjacent grooves. Starting from the first main surface side, the third impurity region, the second impurity region, and the first impurity region are formed sequentially. The first contact area is adjacent to the third impurity area in the depth direction of the trench, and extends from one side of the platform to the other side. The second contact area is formed along both one side and the other side of the table surface.

6. The semiconductor device according to claim 5, characterized in that, The spacing between the plurality of grooves is greater than 0.1 μm and less than 5 μm.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, A groove is formed in the upper part of the trench by the upper surface of the embedded body and the side of the trench. include: An interlayer insulating layer is embedded in the groove with its upper edge exposed; and A first main surface electrode is formed on the first main surface in such a way as to cover the interlayer insulating layer and is connected to the third impurity region.

8. The semiconductor device according to claim 7, characterized in that, The upper surface of the interlayer insulation layer is located in the depth direction of the trench on the bottom side of the trench, which is closer to the first main surface. The first main surface electrode is connected to the third impurity region on the side of the groove and in the first main surface.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The first impurity region includes: a base region formed away from the second impurity region on the side of the electric field buffer layer closer to the second main surface than the electric field buffer layer; and a high concentration region formed on the side of the electric field buffer layer between the base region and the second impurity region, having a higher impurity concentration than the base region.

10. The semiconductor device according to claim 9, characterized in that, The high-concentration region includes: a first high-concentration region; and a second high-concentration region, which is formed at a position closer to the second main surface than the first high-concentration region, such that it covers the bottom of the trench and the boundary of the electric field buffer layer, and has a lower impurity concentration than the first high-concentration region.

11. The semiconductor device according to claim 10, characterized in that, The first high-concentration region is in contact with the second impurity region and is formed in the thickness direction of the chip, starting from the second impurity region at a depth shallower than the bottom of the trench.

12. The semiconductor device according to any one of claims 9 to 11, characterized in that, The first layer of the electric field buffer layer is formed in the thickness direction of the chip at a depth reaching the base region.

13. The semiconductor device according to claim 12, characterized in that, The bottom of the first layer of the electric field buffer layer contacts the base region, forming a boundary between them.

14. The semiconductor device according to any one of claims 3 to 6, characterized in that, The chip is a Si-based semiconductor chip. include: A silicide layer is formed on each surface of the third impurity region and the first contact region; and The first main electrode is connected to the third impurity region and the first contact region via the silicide layer.

15. The semiconductor device according to any one of claims 1 to 14, characterized in that, include: The drain region of the first conductivity type is formed on the second main surface side relative to the first impurity region; The main region is formed by the second impurity region; The source region is formed by the third impurity region; as well as A trench gate structure, which is formed by the trench, the trench insulating film and the embedded body.

16. The semiconductor device according to any one of claims 1 to 14, characterized in that, include: The collector region of the second conductivity type is formed on the second main surface side relative to the first impurity region; The base region is formed by the second impurity region; The emitter region, which is formed by the third impurity region; and A trench gate structure, which is formed by the trench, the trench insulating film and the embedded body.

17. The semiconductor device according to any one of claims 1 to 16, characterized in that, The chip is a SiC chip.

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