Semiconductor device

Abstract

The invention provides a semiconductor device which can be easily miniaturized. Provided is a semiconductor device in which parasitic capacitance is reduced. The semiconductor device includes a first insulating layer, a second insulating layer, a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first conductive layer is on the second insulating layer and includes a first opening to the second insulating layer. The first insulating layer is on the first conductive layer and includes a second opening overlapping the first opening. The second conductive layer is located on the first insulating layer. The semiconductor layer has a portion in contact with the second conductive layer, a portion along a side surface of the first insulating layer within the second opening, a portion in contact with the side surface of the first conductive layer within the first opening, and a portion in contact with a top surface of the second insulating layer at a bottom of the first opening. The third insulating layer covers the semiconductor layer in the first opening and the second opening. The third conductive layer covers the third insulating layer in the first opening and the second opening.

Description

Technical Field

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, a storage device, a display device, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving these devices, and methods for manufacturing these devices. A semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Background Technology

[0003] In recent years, semiconductor devices have been developed, with CPUs, memory, and other LSIs primarily used in semiconductor devices. A CPU is an assembly of semiconductor integrated circuits (including at least transistors and memory) formed by processing semiconductor wafers to create chips, and semiconductor elements having electrodes formed as connection terminals.

[0004] CPUs, memory, or other LSI semiconductor circuits (IC chips) are mounted on circuit boards, such as printed circuit boards, and used as components of various electronic devices.

[0005] Furthermore, the technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted considerable attention. These transistors are widely used in electronic devices such as integrated circuits and image display devices (simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, and oxide semiconductors are also attracting attention as other materials.

[0006] Furthermore, it is known that the leakage current of transistors using oxide semiconductors is extremely small in the non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current. Additionally, for example, Patent Document 2 discloses a storage device that achieves long-term retention of stored content.

[0007] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high-density integrated circuits has increased. Furthermore, there is a need to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 discloses a technique in which multiple memory cells are stacked in an overlapping manner by layering a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of the integrated circuit. Furthermore, Patent Document 4 discloses a vertical transistor in which the gate electrode covers the sidewall of the oxide semiconductor through a gate insulator.

[0008] [Preliminary Technology Documents] [Patent Literature] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187; [Patent Document 2] Japanese Patent Application Publication No. 2011-151383; [Patent Document 3] International Patent Application Publication No. 2021 / 053473; [Patent Document 4] Japanese Patent Application Publication No. 2013-211537. Summary of the Invention

[0009] The technical problem that the invention aims to solve One objective of this invention is to provide a semiconductor device that is easily miniaturized. Furthermore, one objective of this invention is to provide a semiconductor device capable of achieving high integration. Furthermore, one objective of this invention is to provide a semiconductor device with reduced parasitic capacitance. Furthermore, one objective of this invention is to provide a semiconductor device with reduced wiring load. Furthermore, one objective of this invention is to provide a semiconductor device with high reliability. Furthermore, one objective of this invention is to provide a semiconductor device with good electrical characteristics. Furthermore, one objective of this invention is to provide a semiconductor device with high operating speed.

[0010] One objective of this invention is to provide a semiconductor device, memory device, display device, or electronic device with a novel structure. Another objective of this invention is to at least mitigate at least one of the problems of the prior art.

[0011] Note that the description of these objectives does not preclude the existence of other objectives. Also note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Furthermore, objectives other than those described above can be extracted from the description in the specification, drawings, claims, etc.

[0012] means of solving technical problems One aspect of the present invention is a semiconductor device including a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first conductive layer has a portion situated on the second insulating layer and includes a first opening extending into the second insulating layer. The first insulating layer has a portion situated on the first conductive layer and includes a second opening overlapping the first opening. The second conductive layer has a portion situated on the first insulating layer. The semiconductor layer has a portion contacting the second conductive layer, a portion within the second opening along a side surface of the first insulating layer, a portion within the first opening contacting a side surface of the first conductive layer, and a portion at the bottom of the first opening contacting a top surface of the second insulating layer. The third insulating layer covers the semiconductor layer within the first and second openings, and the third conductive layer covers the third insulating layer within the first and second openings.

[0013] The aforementioned semiconductor device preferably further includes a fourth conductive layer. Preferably, the second insulating layer is located on the fourth conductive layer, and the first conductive layer contacts the top surface of the fourth conductive layer at the outer side of the end of the second insulating layer. Preferably, the first conductive layer comprises a metal oxide, and the fourth conductive layer comprises a metal or alloy. Furthermore, the second insulating layer preferably includes a first insulating film in contact with the fourth conductive layer and a second insulating film thereon in contact with the semiconductor layer. Preferably, the first insulating film comprises one or more of silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, and hafnium oxide, and the second insulating film comprises silicon oxide or silicon oxynitride.

[0014] The aforementioned semiconductor device preferably further includes a fifth conductive layer and a fourth insulating layer. The fourth insulating layer preferably has a portion located on the third insulating layer and includes a third opening that overlaps with the first opening and extends into the third insulating layer. The fifth conductive layer has a portion located on the fourth insulating layer. The third conductive layer has a portion embedded in the third opening and its top surface contacts the fifth conductive layer.

[0015] The aforementioned semiconductor device preferably further includes a fifth insulating layer. The fifth insulating layer is preferably disposed within the second opening along the side of the first insulating layer and located between the first insulating layer and the semiconductor layer. In this case, the first insulating layer preferably comprises silicon oxide or silicon oxynitride. The fifth insulating layer preferably comprises one or more of silicon nitride, aluminum oxide, silicon oxide, and hafnium oxide.

[0016] In the aforementioned semiconductor device, the semiconductor layer preferably has a cylindrical shape within the first and second openings. The third insulating layer preferably has a portion at the bottom of the first opening that contacts the top surface of the second insulating layer. In this case, the semiconductor layer preferably contacts the side surface of the second conductive layer but not the top surface of the second conductive layer.

[0017] Invention Effects According to one aspect of the present invention, a semiconductor device that is easily miniaturized can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device capable of achieving high integration can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with reduced parasitic capacitance can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with reduced wiring load can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high operating speed can be provided.

[0018] According to one aspect of the present invention, a semiconductor device, memory device, display device, or electronic device with a novel structure can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be mitigated.

[0019] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the invention does not necessarily require all of the aforementioned effects. Furthermore, effects other than those described above can be extracted from the description in the specification, drawings, claims, etc.

[0020] Brief description of the attached figures Figure 1A and Figure 1B This is an example of the structure of a semiconductor device.

[0021] Figure 2A and Figure 2B This is an example of the structure of a semiconductor device.

[0022] Figure 3A and Figure 3B This is an example of the structure of a semiconductor device.

[0023] Figures 4A to 4D This is an example of the structure of a semiconductor device.

[0024] Figure 5A and Figure 5B This is an example of the structure of a semiconductor device.

[0025] Figure 6A and Figure 6B This is an example of the structure of a semiconductor device.

[0026] Figures 7A to 7E This is a diagram illustrating the manufacturing process of a semiconductor device.

[0027] Figures 8A to 8C This is a diagram illustrating the manufacturing process of a semiconductor device.

[0028] Figures 9A to 9C This is a diagram illustrating the manufacturing process of a semiconductor device.

[0029] Figure 10A and Figure 10B This is a diagram illustrating the manufacturing process of a semiconductor device.

[0030] Figure 11A and Figure 11B This is a diagram illustrating the manufacturing process of a semiconductor device.

[0031] Figure 12A and Figure 12B This is a diagram illustrating the manufacturing process of a semiconductor device.

[0032] Figure 13A and Figure 13B This is a diagram illustrating the manufacturing process of a semiconductor device.

[0033] Figures 14A to 14C This is an example of the structure of a storage device.

[0034] Figures 15A to 15C This is an example of the structure of a storage device.

[0035] Figure 16A and Figure 16B This is an example of the structure of a storage device.

[0036] Figure 17A and Figure 17B This is an example of the structure of a storage device.

[0037] Figure 18A and Figure 18B This is an example of the structure of a storage device.

[0038] Figure 19 This is an example of the structure of a storage device.

[0039] Figures 20A to 20D This is a diagram illustrating a method for depositing metal oxides.

[0040] Figures 21A to 21D This is a diagram illustrating a method for depositing metal oxides.

[0041] Figure 22 This is an example of the structure of a storage device.

[0042] Figure 23A and Figure 23B This is an example of the structure of a storage device.

[0043] Figures 24A to 24D This is an example of the structure of a storage device.

[0044] Figure 25 This is an example of the structure of a storage device.

[0045] Figure 26A and Figure 26BThis is an example of the structure of a display device.

[0046] Figure 27 This is an example of the structure of a display device.

[0047] Figure 28 This is an example of the structure of a display device.

[0048] Figure 29 This is an example of the structure of a display device.

[0049] Figures 30A to 30C This is an example of the structure of a display device.

[0050] Figure 31A and Figure 31B This is an example of the structure of a display device.

[0051] Figures 32A to 32D This is an example of the structure of an electronic device.

[0052] Figures 33A to 33F This is an example of the structure of an electronic device.

[0053] Figures 34A to 34G This is an example of the structure of an electronic device.

[0054] Figure 35A and Figure 35B This is a structural example of an electronic component.

[0055] Figures 36A to 36C This is an example of the architecture of a mainframe computer.

[0056] Figure 37A This is an example of the structure of space equipment. Figure 37B This is an example of a storage system structure.

[0057] Methods of implementing the invention The embodiments will now be described with reference to the accompanying drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments shown below.

[0058] Note that in the structure of the invention described below, the same symbols are used in different figures to represent the same parts or parts having the same function, and repeated descriptions are omitted. Furthermore, when representing parts having the same function, the same shading lines are sometimes used without additional symbols.

[0059] Note that in the various figures described in this specification, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, the invention is not limited to the dimensions shown in the figures.

[0060] Note that the ordinal numbers such as "first" and "second" used in this specification are appended to avoid confusion of the constituent elements, and are not intended to limit the quantity.

[0061] A transistor is a type of semiconductor device that can amplify current or voltage, control switching operations (turning the device on or off), etc. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0062] Furthermore, in cases where transistors with different polarities are used or the direction of current changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be used interchangeably.

[0063] Furthermore, in this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include, in addition to electrodes or wiring, switching elements such as transistors, resistors, coils, and other elements with various functions.

[0064] Note that in this specification, "electrical connection" does not include the case where two nodes are connected through insulators such as the dielectric of a capacitor element, the gate insulating film of a transistor, and the interlayer insulating film.

[0065] Note that in this specification, "generally consistent top surface shape" means that at least a portion of the outline of each layer in the stack overlaps. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, strictly speaking, there are cases where the outlines do not overlap and the upper layer is located inside or outside the lower layer; in such cases, it can sometimes be said that the "top surface shape is generally consistent."

[0066] Note that in this specification, the top surface shape of a constituent element refers to the outline shape of the constituent element when viewed from a plane. Furthermore, "viewed from a plane" means the view taken from the normal direction of the surface on which the constituent element is formed or the surface of the support (e.g., a substrate) on which the constituent element is formed.

[0067] Note that the use of directions such as "up" and "down" in the following description will generally follow the direction indicated in the accompanying drawings. However, for the sake of simplicity, the direction indicated by "up" or "down" in the specification may sometimes differ from that in the accompanying drawings. For example, when describing the stacking sequence (or formation sequence) of laminates, etc., even if the surface on which the laminate is located (the surface to be formed, the supporting surface, the adhesive surface, the flat surface, etc.) is located on the upper side of the laminate in the accompanying drawings, the surface to be formed may sometimes be described as "down" and the laminate side as "up".

[0068] Note that in this specification, the channel length direction of a transistor refers to one of the directions parallel to the straight line connecting the source and drain regions with the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the on state. Furthermore, the channel width direction refers to a direction orthogonal to the channel length direction. Note that, depending on the transistor's structure or shape, sometimes the channel length direction and channel width direction are not limited to one direction.

[0069] Furthermore, in this specification and other materials, the terms "film" and "layer" may be interchanged. For example, sometimes "insulating layer" and "insulating film" may be interchanged.

[0070] (Implementation Method 1) This embodiment illustrates a structural example of a semiconductor device according to one aspect of the present invention and an example of its manufacturing method. The following describes a transistor as an example of a semiconductor device.

[0071] In one embodiment of the present invention, the source and drain electrodes of the transistor are located at different heights, so current flows through the semiconductor layer in the height direction. That is, the channel length direction has a height (vertical) component, therefore one embodiment of the present invention can also be called VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, vertical channel type transistor, etc.

[0072] More specifically, a first insulating layer serving as a first spacer is provided such that it covers the lower electrode of one of the source and drain electrodes of the transistor, and an upper electrode of the other of the source and drain electrodes is provided on the first insulating layer. A semiconductor layer, which contacts the lower electrode and forms a channel along the side of the first insulating layer, is provided inside an opening provided in the first insulating layer. Furthermore, a gate insulating layer is provided along the semiconductor layer inside the opening of the first insulating layer, and a gate electrode is provided such that it overlaps with the semiconductor layer through the gate insulating layer.

[0073] A portion of the lower electrode has a portion located on the second insulating layer and includes an opening reaching the second insulating layer. The opening in the first insulating layer overlaps with the opening of the lower electrode. A semiconductor layer contacts the side of the lower electrode inside the opening of the lower electrode. Additionally, the semiconductor layer contacts the second insulating layer at the bottom of the opening of the lower electrode. Thus, when an opening is provided in the lower electrode at the bottom of the opening in the first insulating layer, the overlapping area of ​​the gate electrode and the lower electrode can be reduced, thereby reducing the parasitic capacitance between them. This enables the realization of a transistor capable of high-speed operation.

[0074] Furthermore, an opening can also be provided in the semiconductor layer at the bottom of the opening of the lower electrode. In other words, the semiconductor layer can also have a cylindrical shape with sidewalls along the opening of the first insulating layer and the opening of the lower electrode. By adopting the above structure, the parasitic capacitance between the gate electrode and the semiconductor layer can be reduced, thereby enabling transistors that can be driven at higher speeds.

[0075] Furthermore, it is preferable to provide an insulating layer serving as a second spacer between the gate wiring connected to the gate electrode and the upper electrode. Preferably, the gate electrode is positioned within the second spacer, with its top surface in contact with the gate wiring. This reduces the parasitic capacitance between the gate wiring and the upper electrode, thus enabling transistors that can be driven at higher speeds.

[0076] Oxide semiconductors are preferably used for the semiconductor layer. For example, silicon, a typical semiconductor material, requires doping with impurities to act as donors or acceptors in order to form the source and drain regions. However, in a vertical transistor according to one aspect of the present invention, the channel formation region is located vertically relative to the substrate surface due to the difference in height between the source and drain, making it sometimes difficult to precisely dope the semiconductor layer with impurities. On the other hand, oxide semiconductors can form low-resistance regions and connect well to the source and drain electrodes even without such impurity doping, thus enabling the manufacture of transistors with three-dimensional structures, such as those according to one aspect of the present invention, with high yield.

[0077] One embodiment of the transistor of this invention allows for extremely short channel lengths, reducing the occupied area, enabling high current flow, lowering parasitic capacitance, and achieving high-speed operation. This transistor can be applied to a wide variety of semiconductor devices, such as memory devices, computing devices, display devices, and imaging devices.

[0078] The following are more specific examples, with reference to the accompanying drawings.

[0079] [Structure Example 1] Figure 1A , Figure 1BThese are all 3D diagrams of transistor 10. In each diagram, arrows indicate the X, Y, and Z directions. Figure 1B It was cut off Figure 1A A partial 3D view. Note that in Figure 1A , Figure 1B In the diagram, insulating layers 41 and 42, which serve as interlayer insulating layers, are shown only in outline with dashed lines.

[0080] Figure 2A , Figure 2B A cross-sectional view of transistor 10 is shown. Figure 2A The cross-section is shown along a plane perpendicular to the X direction. Figure 2B The cross-section is shown along a surface perpendicular to the Y direction.

[0081] Transistor 10 is disposed on insulating layer 11 on a substrate (not shown). Insulating layer 11 serves as a base insulating layer. Transistor 10 includes a semiconductor layer 21, an insulating layer 22 serving as a gate insulating layer, a conductive layer 23 serving as a gate electrode, a conductive layer 24 serving as one of a source electrode and a drain electrode, and a conductive layer 25 serving as the other of the source electrode and drain electrode. Figure 2A , Figure 2B The following example is shown: conductive layer 23 includes conductive layer 23a and conductive layer 23b, conductive layer 24 includes conductive layer 24a and conductive layer 24b, and conductive layer 25 includes conductive layer 25a and conductive layer 25b.

[0082] Conductive layer 23 is connected to conductive layer 31, which serves as gate wiring. Furthermore, conductive layers 24 and 25 are also used for wiring. Here, an example is shown where conductive layers 31 and 24 extend in the X direction and conductive layer 25 extends in the Y direction. Note that the extension direction of each conductive layer is not limited to this; it may also extend in a direction that is neither the X nor the Y direction.

[0083] An insulating layer 45 is provided on the insulating layer 11. The insulating layer 45 serves as a protective insulating layer and prevents impurities such as hydrogen from diffusing from one side of the insulating layer 11 to the semiconductor layer 21. For example, a film that is less susceptible to hydrogen diffusion (having hydrogen-blocking properties) compared to a silicon oxide film, such as a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film, can be used. Alternatively, the insulating layer 45 may be omitted if not required.

[0084] A conductive layer 24a is disposed on an insulating layer 45, an island-shaped insulating layer 40 is disposed on the conductive layer 24a, and a conductive layer 24b is disposed to cover the conductive layer 24a and the insulating layer 40. Additionally, an insulating layer 41 is disposed on the conductive layer 24b and the insulating layer 45, and a conductive layer 25 is disposed on the insulating layer 41. The insulating layer 41 includes an opening 20a. The conductive layer 24b includes an opening 20b reaching the insulating layer 40 at a position overlapping the opening 20a. Furthermore, an example is shown here where the conductive layer 25 also includes an opening at a position overlapping the opening 20a.

[0085] The semiconductor layer 21 has a portion that contacts the top surface of the conductive layer 25, a portion that contacts the side surface of the conductive layer 25, a portion that contacts the side surface (inner wall, sidewall) of the insulating layer 41 within the opening 20a, a portion that contacts the side surface of the conductive layer 24b within the opening 20b, and a portion that contacts the top surface of the insulating layer 40 at the bottom of the opening 20b. Furthermore, the semiconductor layer 21 can also be described as having portions disposed along the sidewalls of the openings 20a and 20b.

[0086] The source and drain electrodes of transistor 10 are located at different heights, so the current flowing through the semiconductor flows in the height direction. That is, the channel length direction can have a height (vertical) component, so the transistor of one embodiment of the present invention can also be called a VFET, a vertical transistor, a vertical channel transistor, etc. In transistor 10, two or more of the source electrode, semiconductor, and drain electrode can be stacked, so the occupied area can be significantly reduced compared to so-called planar transistors (also called lateral transistors, LFETs, etc.) where the semiconductor is arranged on a plane.

[0087] Furthermore, the channel length of the transistor 10 can be precisely controlled according to the thickness of the insulating layer 41 used as a spacer, thus significantly reducing channel length non-uniformity compared to planar transistors. Moreover, by thinning the insulating layer 41, transistors with extremely short channel lengths can be manufactured. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less but greater than 5 nm, 7 nm or more, or 10 nm or more can be manufactured. Thus, transistors with extremely small channel lengths that cannot be achieved with mass production exposure equipment can be realized. Furthermore, transistors with channel lengths less than 10 nm can be achieved without the very expensive exposure equipment used in state-of-the-art LSI technology.

[0088] Semiconductor layer 21 can be made of various semiconductor materials, with oxide semiconductors containing metal oxides being particularly preferred. By using oxide semiconductors formed under appropriate conditions, transistors with both high on-state current and extremely low off-state current can be realized at low cost. Below, unless otherwise emphasized, preferred structural examples of using oxide semiconductors as semiconductor layer 21 will be described.

[0089] Here, both conductive layer 24 and conductive layer 25 have a stacked structure. Both conductive layer 24b and conductive layer 25b have a structure that contacts semiconductor layer 21. Therefore, when an oxide semiconductor is used for semiconductor layer 21, there is a concern that the surfaces of conductive layers 24b and 25b may be oxidized due to heat during or after the deposition process of the semiconductor film that forms semiconductor layer 21, resulting in the formation of an insulating oxide film between conductive layers 24b and 25b and semiconductor layer 21, thus increasing the contact resistance. Therefore, it is preferable to use oxide conductors containing conductive oxides for conductive layers 24b and 25b. This can suppress the increase in contact resistance caused by oxidation of the surfaces of conductive layers 24b and 25b. Conductive layers 24b and 25b may be referred to as oxide layers, metal oxide layers, or oxide conductor layers, etc.

[0090] Conductive layer 24 can be used as one of the source wiring and drain wiring. Furthermore, conductive layer 25 can be used as the other of the source wiring and drain wiring. Therefore, low resistance is preferred. As conductive layers 24a and 25a, materials with higher conductivity than oxide conductors, such as metals, alloys, or their nitrides, are preferably used. Thus, it is preferable that conductive layer 24 has a stacked structure of a low-resistance conductive layer 24a and a conductive layer 24b comprising a metal oxide, and conductive layer 25 has a stacked structure of a low-resistance conductive layer 25a and a conductive layer 25b comprising a metal oxide.

[0091] An insulating layer 40 is disposed in the region overlapping openings 20a and 20b. The top surface of the insulating layer 40 corresponds to the bottom surface of opening 20b. When the insulating layer 40 is disposed between conductive layers 23 and 24a, the parasitic capacitance between them can be reduced. This enables high-speed operation of the transistor 10. For example, when the transistor 10 is used in a storage device, high-speed write and read operations can be achieved. Furthermore, when the transistor 10 is used in a display device, the following effects are achieved: high-speed frame rate and improved resolution.

[0092] An example of a two-layer structure, comprising an insulating layer 40a and an insulating layer 40b, is shown here. The insulating layer 40b has a portion that contacts the semiconductor layer 21. The insulating layer 40b is preferably an oxide insulating film that releases oxygen upon heating. For example, silicon oxide, silicon oxynitride, or similar oxide insulating films are preferred. This allows oxygen to be supplied from the insulating layer 40b to the semiconductor layer 21 via heat applied during the process, reducing oxygen vacancies in the semiconductor layer 21 and enabling the realization of a highly reliable transistor 10. On the other hand, when the insulating layer 40b releases oxygen upon heating, it contacts the conductive layer 24a, causing a portion of the conductive layer 24a to oxidize, potentially leading to a decrease in conductivity. Therefore, it is preferable to provide an insulating layer 40a, which is less prone to oxygen diffusion than the insulating layer 40b, between the insulating layer 40b and the conductive layer 24a, so that the insulating layer 40b does not contact the conductive layer 24a. As the insulating layer 40a, for example, insulating materials that are less prone to oxygen diffusion than silicon oxide can be used, such as silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium aluminate, hafnium silicate, etc.

[0093] Note that in this specification, etc., oxynitrides refer to materials with an oxygen content greater than a nitrogen content. Nitrogen oxides refer to materials with a nitrogen content greater than a oxygen content.

[0094] The insulating layer 22 is provided in such a way that it covers the insulating layer 41, the conductive layer 25, the semiconductor layer 21, the conductive layer 24b, and the insulating layer 40. The portion of the insulating layer 22 located inside the openings 20a and 20b is provided along the surface of the semiconductor layer 21 (the side of the conductive layer 23).

[0095] An insulating layer 42 is provided on the insulating layer 22, and the insulating layer 42 is used as an interlayer insulating layer. The insulating layer 42 is provided with an opening 20c that overlaps with the opening 20a.

[0096] The conductive layer 23 is provided to fill openings 20a and 20c. Furthermore, the conductive layer 23 is provided within openings 20a and 20c to cover the insulating layer 22. Here, the conductive layer 23 is planarized such that the height of its top surface is approximately the same as the top surface of the insulating layer 42. Additionally, a conductive layer 31 is provided on the insulating layer 42, and the conductive layer 31 contacts the top surface of the conductive layer 23. The conductive layer 31 is used as a gate wiring.

[0097] By providing an insulating layer 42, which serves as an interlayer insulating layer, between the conductive layer 31 used for gate wiring and the conductive layer 25 and the semiconductor layer 21 on the conductive layer 25, the parasitic capacitance between them can be reduced. This allows for the realization of a transistor 10 capable of higher-speed operation. Furthermore, by providing the insulating layer 42, the parasitic capacitance between the conductive layer 24 and the conductive layer 31 can be significantly reduced. Therefore, the conductive layer 24 and the conductive layer 31 can be made to extend in the same direction, thus increasing the freedom of circuit design.

[0098] This example shows a stacked structure of conductive layer 23 having conductive layer 23a and conductive layer 23b. Since conductive layer 23 is in contact with insulating layers 22, 42, etc., when insulating films such as silicon oxide that allow oxygen diffusion are used as them, conductive layer 23 may be oxidized due to heat during the process, resulting in reduced conductivity. Therefore, conductive layer 23a, which is in contact with insulating layers 22 and 42, preferably uses a conductive material that is less prone to oxidation than conductive layer 23b. For example, tantalum nitride, titanium nitride, or other metal nitride films are preferably used as conductive layer 23a. On the other hand, conductive layer 23b can use a conductive material containing a metal or alloy with low resistance. This improves the reliability of transistor 10.

[0099] Insulating layer 41 is used as an interlayer insulating layer (spacer) to insulate conductive layer 24 from conductive layer 25. Here, a case is shown where a laminated film of insulating layers 41a, 41b and 41c is used as insulating layer 41.

[0100] The semiconductor layer 21 is disposed in contact with the inner wall of the opening 20a of the insulating layer 41b. The insulating layer 41b is preferably made of an oxide insulating film. In particular, an oxide insulating film that releases oxygen upon heating is preferred. Furthermore, the insulating layer 41b is preferably sandwiched between insulating layers 41a and 41c, which are oxygen-barrier materials. This confines the oxygen in the insulating layer 41b within the region surrounded by the insulating layers 41a, 41c, and the semiconductor layer 21. It also prevents the oxygen in the insulating layer 41b from escaping and decreasing during processing. Therefore, oxygen can be supplied to the semiconductor layer 21 more efficiently.

[0101] The portion of semiconductor layer 21 that contacts insulating layer 41b is a region where oxygen vacancies are reduced, which can be considered an i-type region. On the other hand, the portion that does not contact insulating layer 41b is preferably an n-type region containing multiple charge carriers. That is, the portion of semiconductor layer 21 that contacts insulating layer 41b can be referred to as a channel formation region, and the region outside it can be referred to as a low-resistance region (also called a source region or drain region).

[0102] Since the insulating layer 41b is in contact with the semiconductor layer 21, it is preferably a film that contains as little hydrogen as possible. Oxygen vacancies in the semiconductor layer 21 bond with hydrogen to generate charge carriers, which can sometimes affect, for example, the threshold voltage of the transistor 10. Therefore, an insulating film other than an oxide insulating film, which is not easily diffused by hydrogen, can also be used as the insulating layer 41b. For example, a single layer of an insulating film that blocks hydrogen and oxygen can also be used as the insulating layer 41.

[0103] Since the semiconductor layer 21 and the insulating layer 22 are formed along the inner wall of the opening 20a of the insulating layer 41b, the thickness of this portion may be reduced depending on the deposition method. For example, in deposition methods such as sputtering or plasma CVD, the thickness of the film deposited on a surface inclined to or perpendicular to the substrate surface tends to be thinner than the thickness of the film deposited on a surface parallel to the substrate surface. On the other hand, when using deposition methods such as atomic layer deposition (ALD) or thermal CVD, a film with uniform thickness can be deposited regardless of the angle of the surface to be formed. For example, when the angle of the sidewall of the opening 20a of the insulating layer 41b is 75 degrees or more, 80 degrees or more, or 85 degrees or more, it is preferable to use the ALD method to form the semiconductor layer 21 and the insulating layer 22.

[0104] [Components] <Substrate> Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium-stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon on Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can also be used. Furthermore, examples include insulating substrates with conductive or semiconductor layers, semiconductor substrates with conductive or insulating layers, and conductive substrates with semiconductor or insulating layers. Alternatively, substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements (including transistors), light-emitting elements, and memory elements.

[0105] <Semiconductor layer> Semiconductor layer 21 preferably comprises metal oxide (oxide semiconductor).

[0106] Examples of metal oxides that can be used in semiconductor layer 21 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In or Zn. Furthermore, the metal oxide preferably contains two or three elements selected from In, element M, and Zn. Note that element M is a metallic or half-metallic element with a high bond energy with oxygen, such as a metallic or half-metallic element with a higher bond energy with oxygen than indium. Specific examples of element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Note that metal oxides containing In, M, and Zn are sometimes referred to below as In-M-Zn oxides. Note that in this specification, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification may sometimes include half-metallic elements.

[0107] When using In-M-Zn oxides as metal oxides, the atomic ratio of In in the In-M-Zn oxide is preferably greater than or equal to the atomic ratio of M. Examples of such atomic ratios of the metal elements in In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions close to these. Note that "close to" includes a range of ±30% of the desired atomic ratio. By increasing the proportion of indium atoms in metal oxides, the on-state current or field-effect mobility of transistors can be improved.

[0108] In In-M-Zn oxides, the atomic ratio of In can also be less than that of M. For example, examples of the atomic ratios of the metal elements in such In-M-Zn oxides include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, or compositions close to these ratios. By increasing the atomic ratio of M in the metal oxide, the formation of oxygen vacancies can be suppressed.

[0109] The semiconductor layer 21 can be made of, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, etc. Additionally, Ga-Zn oxide can also be used. Using a Zn-free material such as indium oxide improves the affinity with the LSI manufacturing process, making it preferred. On the other hand, using a Zn-containing material easily improves crystallinity, making it preferred as well.

[0110] Note that metal oxides can also replace indium or contain one or more metals with high period numbers in the periodic table besides indium. The greater the overlap of the orbitals of the metal element, the greater the carrier conduction in the metal oxide. Therefore, including metals with high period numbers can sometimes improve the field-effect mobility of transistors. Examples of metals with high period numbers include those belonging to period 5 and period 6. Specific examples of such metals include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0111] Furthermore, metal oxides can also contain one or more non-metallic elements. The inclusion of non-metallic elements in metal oxides can sometimes improve the field-effect mobility of transistors. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0112] Metal oxides can be formed appropriately using sputtering or atomic layer deposition (ALD). In particular, metal oxides are preferably deposited using ALD, which offers excellent coverage. Note that when metal oxides are formed using sputtering, the composition of the deposited metal oxide sometimes differs from that of the target material. In particular, the zinc content in the deposited metal oxide sometimes decreases to about 50% of the zinc content in the target material.

[0113] In this specification, the content of a certain metal element in a metal oxide refers to the proportion of the number of atoms of that element relative to the total number of atoms of the metal element contained in the metal oxide. For example, in a metal oxide containing metal elements X, Y, and Z, the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A. X A Y A ZWhen the content of metallic element X is such that it can be expressed as A, the percentage of X in the composition of metal can be expressed as A. X / (A X +A Y +A Z Furthermore, when the ratio of the number of atoms of metal elements X, Y, and Z in a metal oxide is expressed as B... X B Y B Z When the content of metallic element X is such that B is used, the percentage of X can be expressed as B. X / (B) X +B Y +B Z ).

[0114] For example, when using metal oxides containing In, transistors with high on-state current can be achieved by increasing the In content.

[0115] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability under forward bias can be realized. That is, a transistor with small fluctuations in the threshold voltage during PBTS (Positive Bias Temperature Stress) testing can be achieved. Furthermore, when using a Ga-containing metal oxide, the Ga content is preferably lower than the In content. Thus, a transistor with both high mobility and high reliability can be realized.

[0116] On the other hand, by increasing the Ga content, transistors with high reliability for light can be achieved. In other words, transistors with small threshold voltage variations during NBTIS (Negative Bias Temperature Illumination Stress) testing can be realized. Specifically, the band gap of metal oxides with a higher Ga atom count than those with a higher In atom count can be larger, thus reducing the threshold voltage variation during NBTIS testing of the transistor.

[0117] Furthermore, by increasing the zinc content to create a highly crystalline metal oxide, the diffusion of impurities in the metal oxide can be suppressed. This suppresses variations in the electrical characteristics of the transistor, thereby improving reliability.

[0118] Semiconductor layer 21 may also have a stacked structure comprising two or more metal oxide layers. The compositions of the two or more metal oxide layers included in semiconductor layer 21 may also be the same or substantially the same. By employing a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thus reducing manufacturing costs. Note that a stacked structure of two or more oxide semiconductor layers with different compositions can also be used. Furthermore, by utilizing the ALD method, metal oxide layers with continuously varying compositions in the thickness direction can be formed. Therefore, compared to using a film with a predetermined composition, not only can the range of design choices be expanded, but the formation of interface states, etc., between two layers with different compositions can also be prevented, thus improving electrical characteristics and reliability.

[0119] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (high conductivity) than the first layer in the second layer, i.e., the layer closest to the gate electrode. This allows for the formation of a normally-off transistor with a large on-state current. Therefore, both low power consumption and high performance can be achieved. Alternatively, a material with higher mobility than the second layer can be used in the first layer, i.e., the layer in contact with the source and drain electrodes. This reduces the contact resistance between the semiconductor layer 21 and the source or drain electrode, thereby reducing parasitic resistance and enabling the formation of a transistor with a large on-state current.

[0120] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material in the second layer with a higher mobility than the first and third layers. This allows for the realization of transistors with high on-state current and high reliability.

[0121] For example, the aforementioned mobility or conductivity can be replaced by the indium content. In addition, the following factors also affect mobility and conductivity: the presence or content of elements other than indium that contribute to improved conductivity. Examples of high-mobility materials include those with an In:Ga:Zn ratio of 4:3:2 or similar, In:Zn ratio of 1:1 or similar, In:Zn ratio of 2:1 or similar, In:Zn ratio of 4:1 or similar, and In:Sn:Zn ratio of 40:X:10 (where X is 0.1 or higher and less than 5, typically X=1) or similar. On the other hand, materials with lower mobility or conductivity than the aforementioned materials include those with an atomic ratio of 1:3:2 or closer, In:Ga:Zn = 1:3:4 or closer, In:Ga:Zn = 2:2:1 or closer, In:Ga:Zn = 1:1:1 or closer, and In:Ga:Zn = 1:1:2 or closer.

[0122] A crystalline metal oxide layer is preferably used as the semiconductor layer 21. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, or a nano-crystal (nc) structure can be used. By using a crystalline metal oxide layer as the semiconductor layer 21, the defect state density in the semiconductor layer 21 can be reduced, thereby enabling a highly reliable semiconductor device.

[0123] The higher the crystallinity of the metal oxide layer used for semiconductor layer 21, the lower the defect state density in semiconductor layer 21 can be. On the other hand, by using a metal oxide layer with low crystallinity, transistors capable of carrying large currents can be realized.

[0124] Compared to transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have a very high field-effect mobility. Furthermore, the leakage current between the source and drain of an OS transistor in the off-state (hereinafter also called off-state current) is extremely low, allowing the charge stored in the capacitor connected in series with the transistor to be retained for extended periods. Additionally, the power consumption of semiconductor devices can be reduced by using OS transistors.

[0125] A semiconductor device according to one aspect of the present invention can be applied, for example, to processors, memory devices, or various ICs. A transistor according to one aspect of the present invention has the characteristics of enabling large current flow and extremely low off-state current, thus enabling both high-speed circuit operation and low power consumption.

[0126] One aspect of the semiconductor device of the present invention can also be applied to a display device. When increasing the luminous brightness of the light-emitting device included in the pixel circuit of a display device, it is necessary to increase the current flowing through the light-emitting device. For this purpose, it is necessary to increase the source-drain voltage of the driving transistor included in the pixel circuit. Because the source-drain breakdown voltage of an OS transistor is higher than that of a silicon transistor (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, the current flowing through the light-emitting device can be increased, thereby improving the luminous brightness of the light-emitting device.

[0127] When operating in the saturation region, OS transistors, compared to Si transistors, allow for smaller changes in source-drain current in response to variations in the gate-source voltage. Therefore, by using OS transistors as driving transistors within pixel circuits, the amount of current flowing through the light-emitting device can be precisely controlled. This, in turn, increases the grayscale of the pixel circuit. Furthermore, a stable current can flow even when variations or inhomogeneities occur in the electrical characteristics of the light-emitting device (e.g., resistance).

[0128] As described above, by using OS transistors as driving transistors included in pixel circuits, it is possible to achieve "suppression of black blur", "increase in light emission brightness", "multi-grayscale conversion", and "suppression of the effects of uneven manufacturing of light-emitting devices".

[0129] OS transistors exhibit minimal changes in electrical characteristics due to radiation exposure, meaning they possess high radiation tolerance and can therefore be appropriately used in environments where radiation exposure is possible. OS transistors can also be described as having high reliability against radiation. For example, OS transistors can be appropriately used as pixel circuits in X-ray flat panel detectors. Furthermore, OS transistors can be appropriately used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0130] Note that the semiconductor material that can be used in semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors composed of a single element or compound semiconductors can be used. Examples of semiconductors composed of a single element include silicon (including monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) or germanium. Examples of compound semiconductors include gallium arsenide and silicon-germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, or oxide semiconductors. Note that these semiconductor materials may also contain impurities as dopants.

[0131] Alternatively, semiconductor layer 21 may also have a layered material that functions as a semiconductor. Layered materials are a general term for a group of materials with a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked together by bonds weaker than covalent and ionic bonds, such as van der Waals bonds. Layered materials have high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material that functions as a semiconductor and has high two-dimensional conductivity in the channel formation region, transistors with large on-state currents can be provided.

[0132] Examples of the aforementioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements (elements belonging to Group 16). Furthermore, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers in transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0133] There are no particular restrictions on the crystallinity of the semiconductor material used for semiconductor layer 21; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystallinity other than single crystals (polycrystalline semiconductors, microcrystalline semiconductors, or semiconductors in which a portion has crystalline regions) can be used. When using a crystalline semiconductor, the degradation of transistor characteristics can be suppressed, so it is preferred.

[0134] <Gate insulating layer> The insulating layer 22 is used as the gate insulating layer of the transistor. When an oxide semiconductor is used for the semiconductor layer 21, an oxide insulating film is preferably used as the film in the insulating layer 22 that is at least in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used as the insulating layer 22. In addition, nitride insulating films such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride can also be used as the insulating layer 22. Furthermore, the insulating layer 22 can also have a stacked structure, for example, it can also have a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0135] Furthermore, the insulating layer 22 is preferably used by laminating an insulating material composed of a high-k material, and preferably uses a laminate structure of a material with a high relative permittivity (high-k) and a material with a dielectric strength greater than that high-k material. For example, as the insulating layer 22, an insulating film (also known as ZAZ) sequentially laminated with zirconium oxide, alumina, and zirconium oxide can be used. Alternatively, an insulating film (also known as ZAZA) sequentially laminated with zirconium oxide, alumina, zirconium oxide, and alumina can be used. Furthermore, an insulating film sequentially laminated with hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina can be used. By using an insulator with high dielectric strength, such as alumina, the dielectric strength can be increased, thereby suppressing electrostatic discharge damage to the capacitor.

[0136] Furthermore, ferroelectric materials can also be used as the insulating layer 22. Examples of ferroelectric materials include hafnium oxide, zirconium oxide, and HfZrO. X Metal oxides (where X is a real number greater than 0).

[0137] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film with hydrogen trapping or fixing function as the film in contact with the semiconductor layer 21, and an insulating film with hydrogen blocking function as the film on the side of the conductive layer 23 used as the gate electrode. This suppresses hydrogen diffusion from the conductive layer 23 side to the semiconductor layer 21, thereby enabling a highly reliable transistor.

[0138] Hafnium oxide films, hafnium silicate films, and aluminum oxide films are preferred as insulating films for capturing or fixing hydrogen. Furthermore, silicon nitride films, silicon oxynitride films, aluminum oxide films, magnesium oxide films, hafnium oxide films, and gallium oxide films are preferred as insulating films that block hydrogen.

[0139] Alternatively, an insulating film that releases oxygen upon heating can be used as a film in contact with the semiconductor layer 21, and an insulating film that blocks hydrogen can be used as a film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen upon heating can be used as a film in contact with the semiconductor layer 21, and an insulating film that traps or fixes hydrogen can be used as a film located on the conductive layer 23 side.

[0140] When the insulating layer 22 has a three-layer structure, it is preferable that the insulating film in contact with the semiconductor layer 21 is made of a material containing a material with a lower relative permittivity than the other films, the insulating film located on one side of the conductive layer 23 is made of a material that blocks hydrogen and oxygen, and the insulating film located between them is made of a material that traps or fixes hydrogen. Silicon oxide or silicon oxynitride can be used as the material with a low relative permittivity. By employing this structure, oxygen can be supplied to the semiconductor layer 21 from the film in contact with it. Furthermore, the film located on one side of the conductive layer 23 prevents oxygen from diffusing to that side, thereby suppressing the oxidation of the conductive layer 23.

[0141] As an insulating film that blocks oxygen, aluminum oxide film, silicon nitride film, hafnium oxide film, hafnium silicate film, etc. are preferred. As an insulating film that blocks both oxygen and hydrogen, aluminum oxide film, silicon nitride film, hafnium oxide film, etc. are preferred.

[0142] When the insulating layer 22 has a four-layer structure, it is preferable that the film in contact with the semiconductor layer 21 is an insulating film that blocks oxygen, the film closest to the semiconductor layer 21 is an insulating film containing a material with a lower relative permittivity than other films, the film closest to the semiconductor layer 21 is an insulating film that traps or fixes hydrogen, and the film closest to the conductive layer 23 is an insulating film that blocks both hydrogen and oxygen. That is, a structure can be adopted that adds a film in contact with the semiconductor layer 21 in addition to the above three-layer structure. By using an insulating film that blocks oxygen as the film in contact with the semiconductor layer 21, oxygen can be suppressed from escaping from the semiconductor layer 21. In this case, an alumina film is preferably used as the film in contact with the semiconductor layer 21. Alumina not only blocks oxygen but also traps or fixes hydrogen, thus preventing hydrogen diffusion into the semiconductor layer 21.

[0143] When the insulating layer 22 has a stacked structure, each insulating film is preferably a thin film. For example, by setting the thickness of the insulating layer 22 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also known as the S-value) of the transistor can be reduced. In addition, the thickness of each insulating film is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less.

[0144] As a specific example, it is preferable to adopt a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked sequentially from one side of the semiconductor layer 21, and their thicknesses are set to 1nm, 2nm, 2nm, and 1nm from one side of the semiconductor layer 21.

[0145] Note that in this specification, etc., barrier properties refer to the property that the corresponding substance does not easily diffuse (or, in other words, the property that the corresponding substance is not easily permeable, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). Furthermore, hydrogen, referred to as the corresponding substance, includes, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH-. - At least one of the following: substances bonded to hydrogen. Furthermore, unless otherwise specified, impurities referred to as corresponding substances refer to impurities in the channel-forming region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), copper atoms, etc. Additionally, oxygen referred to as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc.

[0146] Here, by surrounding a transistor using a metal oxide film with an insulating film that suppresses the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. The insulating film that suppresses the permeation of impurities and oxygen can be, for example, a single layer or a stack of insulating films selected from one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the material used for the insulating film that suppresses the permeation of impurities and oxygen can be metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride.

[0147] Specifically, materials for insulating films that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Furthermore, materials for insulating films that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include, for example, oxides containing aluminum and hafnium (hafnium aluminate). Additionally, materials for insulating films that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include, for example, nitrides such as aluminum nitride, titanium aluminum nitride, silicon oxynitride, and silicon nitride.

[0148] Materials used as insulating films with the function of trapping or fixing hydrogen include metal oxides such as hafnium oxides, magnesium oxides, aluminum oxides, and oxides containing both aluminum and hafnium (hafnium aluminate). Furthermore, these metal oxides may also contain zirconium; for example, oxides containing both hafnium and zirconium can be cited. In metal oxides with amorphous structures, the ability to trap or fix hydrogen is high because some oxygen atoms have dangling bonds. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure can be achieved by including silicon in these oxides. For example, oxides containing both hafnium and silicon (hafnium silicate) are preferred. Note that sometimes metal oxides have one or both of crystalline regions and grain boundaries in a portion of their structure.

[0149] <Conductive Layer> Conductive layers 24 and 25 are in contact with the semiconductor layer 21. Here, when an oxide semiconductor is used as the semiconductor layer 21, there is a concern that if a metal that is easily oxidized, such as aluminum, is used for the portion of conductive layer 24 or conductive layer 25 that contacts the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may form between the conductive layer 24 or conductive layer 25 and the semiconductor layer 21, hindering conduction between them. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, or an oxide conductive material for at least the portion of conductive layer 24 and conductive layer 25 that contacts the semiconductor layer 21.

[0150] For example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferably used as conductive layers 24 and 25. These materials are conductive materials that are not easily oxidized or maintain conductivity even when oxidized, and are therefore preferred.

[0151] In addition, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide can be used. In particular, conductive oxides containing indium have high conductivity and are therefore preferred. Furthermore, oxide materials such as In-Ga-Zn oxide, which can be applied to the aforementioned semiconductor layer 21, can also be used in the conductive layer by increasing the carrier concentration.

[0152] For example, both conductive layer 24 and conductive layer 25 can be constructed using a single-layer structure of the conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked sequentially, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on top of tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on top of the conductive oxide film, or a two-layer structure in which the conductive oxide film is stacked on top of a ruthenium film or a ruthenium oxide film.

[0153] The conductive layer 23 serves as the gate electrode and can be made of various conductive materials. For example, the conductive layer 23 preferably uses a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing that metal element. Alternatively, nitrides or oxides of the aforementioned metals or alloys can be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferred. Furthermore, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicides can also be used.

[0154] Alternatively, the conductive layer 23 may also use the nitrides and oxides that are applicable to the conductive layers 24 and 25 as described above.

[0155] Conductive layers 23, 24, and 25 are also used for wiring, and therefore preferably are made of low-resistance conductive materials. For example, the lower layer of conductive layers 24 and 25 may also be made of a low-resistance conductive material that is suitable for conductive layer 23.

[0156] <Insulating layer> The insulating layer 41b can be used as an interlayer insulating film. For example, deposition methods such as sputtering or plasma CVD are preferred. In particular, when using sputtering, hydrogen gas is not required as the deposition gas, thereby achieving a film with extremely low hydrogen content. This suppresses the supply of hydrogen to the semiconductor layer 21, thus stabilizing the electrical characteristics of the transistor 10.

[0157] Since the insulating layer 41b contacts the channel formation region of the semiconductor layer 21, an oxide insulating film is preferably used. In particular, an oxide insulating film that releases oxygen upon heating is preferred. As the insulating layer 41b, the oxide insulating film described above, which can be used as a gate insulating layer, can be used.

[0158] Furthermore, since insulating layer 41b is used as an interlayer insulating layer, a deposition method that can be used to deposit it at a higher deposition rate than other insulating layers is preferred. For example, as insulating layer 41, a silicon oxide film can also be used, which is formed by using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC2H5)4) and employing plasma CVD. This can improve productivity.

[0159] The insulating layers 41a and 41c are preferably made of films that are not easily diffused by hydrogen. By sandwiching the insulating layer 41b between the upper and lower parts of the insulating layer 41b by the insulating layers 41a and 41c, which are not easily diffused by hydrogen, hydrogen can be prevented from mixing into the insulating layer 41b that is in contact with the semiconductor layer 21 from the outside.

[0160] As insulating layers 41a and 41c, one or more of silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used, for example. In particular, silicon nitride and silicon oxynitride have the characteristics of releasing very few impurities (such as water and hydrogen) and not easily allowing oxygen and hydrogen to permeate, so they can be suitably used as insulating layers 41a and 41c.

[0161] Insulating layer 11 and insulating layer 42 are used as interlayer insulating layers, respectively. As insulating layer 11 and insulating layer 42, insulating materials suitable for insulating layer 41b or insulating materials suitable for insulating layers 41a and 41c can be used appropriately.

[0162] The above is an explanation of the constituent elements.

[0163] [Structure Example 2] The following describes structural examples where some constituent elements differ from those in structural example 1 above. Note that the same symbols are used for parts that are repeated above, and sometimes the explanation is omitted.

[0164] Figure 3A , Figure 3B A cross-sectional schematic diagram of transistor 10A is shown. The main difference between transistor 10A and transistor 10 shown in structural example 1 above is that transistor 10A includes an insulating layer 15.

[0165] in addition, Figure 4A An enlarged view of the insulating layer 15 and its vicinity is shown.

[0166] The insulating layer 15 has a portion located inside the opening 20a. The insulating layer 15 is disposed in contact with the side surfaces of the conductive layer 25b, the conductive layer 25a, the insulating layer 41a, the insulating layer 41b, and the insulating layer 41c. Inside the opening 20a, the semiconductor layer 21 is disposed in contact with the insulating layer 15.

[0167] The insulating layer 15 preferably has hydrogen-barrier properties. This prevents hydrogen contained in the insulating layer 41b from diffusing directly or indirectly through the conductive layer to the semiconductor layer 21. This allows for the realization of a semiconductor device with good electrical characteristics and high reliability. For example, one or more of silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. Silicon nitride is particularly preferred.

[0168] Furthermore, the insulator 15 preferably also has oxygen-blocking properties. This prevents oxidation of the sides of the conductive layer 25 (especially the conductive layer 25a). For example, oxidation of the sides of the conductive layer 25 can be prevented during processes such as deposition of the film that forms the semiconductor layer 21, plasma processing for supplying oxygen to the semiconductor layer 21, microwave processing, and other heat treatments.

[0169] Figure 4B An example is shown where the insulating layer 15 has a two-layer structure. The insulating layer 15 includes an insulating layer 15a that contacts the insulating layer 41 and the like, and an insulating layer 15b that contacts the semiconductor layer 21.

[0170] The insulating layer 15a can be described with reference to the above description of the hydrogen-blocking membrane and the oxygen-blocking membrane.

[0171] As the insulating layer 15b, it is preferable to use an insulating film that has a gettering (adsorption, absorption, capture, or fixation) function for hydrogen. For example, by performing a heat treatment after forming the semiconductor layer 21 in contact with the insulating layer 15b, the hydrogen contained in the semiconductor layer 21 is captured and fixed by the insulating layer 15b, thereby reducing the hydrogen concentration in the semiconductor layer 21.

[0172] Furthermore, oxides containing one or both of aluminum and hafnium can be cited as examples of insulators with hydrogen gettering capabilities. Moreover, these oxides are more preferably amorphous. Oxides with amorphous structures sometimes possess the property that oxygen atoms have dangling bonds, which trap or fix hydrogen. Furthermore, while these metal oxides are preferably amorphous, some may also have crystalline regions.

[0173] As the insulating layer 15b, aluminum oxide, hafnium oxide, or hafnium silicate can be used. Alternatively, for example, a laminated film of aluminum oxide and silicon nitride can also be used as the insulating layer 15b.

[0174] Figure 4C An example is shown where the insulating layer 15 has a three-layer structure. Figure 4C In the middle, the insulating layer 15 includes insulating layer 15a, insulating layer 15b and insulating layer 15c. The insulating layer 15c is in contact with the semiconductor layer 21.

[0175] As the insulating layer 15c in contact with the semiconductor layer 21, an oxide insulating film is preferably used. For example, inorganic insulating films such as silicon oxide, silicon oxynitride, and aluminum oxide can be used. Furthermore, the insulating layer 15c is preferably an oxide insulating film containing excess oxygen to the extent that oxygen is released upon heating. When an insulating layer 15c containing excess oxygen and having a reduced hydrogen concentration is provided in contact with the semiconductor layer 21, oxygen vacancies in the semiconductor layer 21 are reduced and the hydrogen concentration is lowered, thereby enabling the transistor 10 to achieve high reliability.

[0176] In addition, the insulating layer 15b has a hydrogen gettering function, so the hydrogen concentration of the insulating layer 15c can be reduced by heat treatment after the insulating layer 15c is formed in contact with the insulating layer 15b.

[0177] The portion of semiconductor layer 21 that contacts insulating layer 15c is a region where oxygen vacancies are reduced, which can be considered an i-type region. On the other hand, the portion that does not contact insulating layer 15c is preferably an n-type region containing multiple charge carriers. That is, the portion of semiconductor layer 21 that contacts insulating layer 15c can be referred to as a channel formation region, and its outer region can also be referred to as a low-resistance region (also called a source region or drain region).

[0178] also, Figure 4D An example is shown where the insulating layer 41 has a single-layer structure and the insulating layer 15 is not provided.

[0179] As Figure 4D The insulating layer 41 shown is preferably an insulating film that blocks hydrogen and oxygen. This suppresses oxygen diffusion from the semiconductor layer 21 to the insulating layer 41, preventing the formation of oxygen vacancies in the semiconductor layer 21, and inhibiting oxygen diffusion from the insulating layer 41 to the semiconductor layer 21, thereby enabling a highly reliable transistor. The insulating layer 41 can be one or more of silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate. Silicon nitride or silicon oxynitride is particularly preferred.

[0180] Alternatively, it can also be done in Figure 4D An insulating layer 15 is also provided in the structure shown.

[0181] [Structure Example 3] Figure 5A The main difference between the transistor shown and the structure example 1 described above is the shape of the semiconductor layer 21.

[0182] A capacitor with insulating layer 22 as the dielectric is sometimes formed between a portion of the semiconductor layer 21 located at the bottom of the opening 20b and the conductive layer 23 used as the gate electrode. Therefore, it is preferable to provide a region at the bottom of the opening 20b where the conductive layer 23 and the semiconductor layer 21 do not overlap.

[0183] The semiconductor layer 21 is disposed in contact with the side surface of the conductive layer 25, the side surface of the insulating layer 41 within the opening 20a, and the side surface of the conductive layer 24b within the opening 20b, and has a cylindrical shape along each opening. Furthermore, the lower end of the semiconductor layer 21 is disposed in contact with the top surface of the insulating layer 40. Therefore, oxygen can be supplied from the insulating layer 40b to the semiconductor layer 21 by heat or other means during the process.

[0184] The insulating layer 22 is disposed such that it contacts the top surface of the insulating layer 40b at the bottom of the opening 20b. For example... Figure 5A As shown, it is preferable not to provide a semiconductor layer 21 between the bottom surface of the conductive layer 23 and the top surface of the insulating layer 40. Furthermore, when the insulating layer 22 is in contact with the insulating layer 40b, if the insulating layer 22 has the function of diffusing oxygen, oxygen can be supplied from the insulating layer 40b through the insulating layer 22 to the semiconductor layer 21 by heat or the like during the process.

[0185] By adopting this structure, parasitic capacitance can be further reduced, enabling transistors to operate at higher speeds.

[0186] Figure 5B yes Figure 5A Examples of variations. In Figure 5A The insulating layer 41 has a three-layer structure; however, a single-layer structure is shown here. The insulating layer 41 can be made of an insulating material that does not readily allow oxygen and hydrogen to diffuse, as described above. In this structure, oxygen can be supplied directly from the insulating layer 40 to the semiconductor layer 21, or via the insulating layer 22, while preventing hydrogen from diffusing from the insulating layer 41 to the semiconductor layer 21 and oxygen from the semiconductor layer 21 to the insulating layer 41. Therefore, a transistor with excellent electrical characteristics and reliability can be achieved.

[0187] [Structure Example 4] Below, a more specific structural example of a transistor according to one aspect of the present invention will be described. Figure 6A The diagram below shows a top view of the transistor and its surroundings. Figure 6B Show along Figure 6A A schematic diagram of the cross-section when cut by the cut-off line AB. Note that in Figure 6A Some components (such as insulating layer 41) are omitted.

[0188] Figure 6A , Figure 6B The connecting electrode 35a connected to the conductive layer 24 and the connecting electrode 35b connected to the conductive layer 25 are shown. Furthermore, an insulating layer 43 serving as an interlayer insulating layer is provided on the insulating layer 42 and the conductive layer 31. Regarding the insulating layer 43, please refer to the description of the insulating layer 42.

[0189] Furthermore, an example of a three-layer structure having conductive layer 24a1, conductive layer 24a2, and conductive layer 24b is shown. As conductive layer 24a1, a low-resistance conductive film, the same as that used in conductive layer 24, can be used. As conductive layer 24a2, a conductive material less prone to oxidation than conductive layer 24a1 can be used, similar to that used in conductive layer 23a. This suppresses oxidation of conductive layer 24a2.

[0190] Furthermore, an insulating layer 46 is provided in a manner that covers the insulating layer 45. The insulating layer 46 can be a hydrogen-gettering insulating film, similar to that used in the insulating layer 15b described above. By providing the insulating layer 46 beneath the transistor, the amount of hydrogen that may diffuse into the transistor can be reduced.

[0191] Furthermore, an insulating layer 47 is provided between insulating layer 42 and insulating layer 22, and between insulating layer 42 and conductive layer 23. The insulating layer 47 is preferably made of a film that does not readily allow oxygen and hydrogen to diffuse, similar to insulating layers 41a and 41c. This prevents hydrogen from diffusing from insulating layer 42 through insulating layer 22 or conductive layer 23 to semiconductor layer 21, and prevents oxygen from diffusing from semiconductor layer 21 through insulating layer 22 to insulating layer 42.

[0192] The connecting electrode 35a is disposed in insulating layers 43, 42, 47, 22, 41c, 41b, 41a, and conductive layer 24b, and is embedded in the opening reaching conductive layer 24a1, thus contacting conductive layer 24a1. In this way, when the connecting electrode 35a contacts the low-resistance conductive layer 24a1 without contacting conductive layer 24b, the contact resistance between them can be reduced.

[0193] The connecting electrode 35b is disposed in the insulating layers 43, 42, 47, 22, semiconductor layer 21, and conductive layer 25b, and is embedded in the opening leading to the conductive layer 25a, thus contacting the conductive layer 25a. This reduces the contact resistance in the same way as the connecting electrode 35a.

[0194] An insulating layer 48 is provided between the connecting electrodes 35a and 35b and the sidewall of the opening. The insulating layer 48 can be made of a material that does not easily allow hydrogen and oxygen to diffuse, just like the insulating layer 47. As a result, oxidation of the connecting electrodes 35a and 35b caused by oxygen in the interlayer insulating layers can be suppressed, as well as the diffusion of hydrogen from the connecting electrodes 35a and 35b to one side of the interlayer insulating layers.

[0195] Furthermore, the connecting electrodes 35a and 35b include a conductive layer 32 disposed along the side and bottom surfaces of the opening, and a conductive layer 33 filling the opening on the conductive layer 32. The conductive layer 33 can use the same low-resistance conductive material as the conductive layer 23b, etc. Moreover, the conductive layer 32 can use the same conductive material as the conductive layer 23a, etc., that is less prone to oxidation than the conductive layer 33. Therefore, oxidation of the conductive layer 33 can be suppressed.

[0196] The insulating layer 15 is disposed in contact with the sides of the conductive layer 25 and the insulating layer 41. Here, as... Figure 6B As shown, at the end of the conductive layer 24b on the side of the opening 20b, the thickness of the portion in contact with the insulating layer 15 decreases. Therefore, in addition to the bottom surface of the insulating layer 15, a portion of the side surface of the insulating layer 15 also contacts the conductive layer 24b.

[0197] Furthermore, in the semiconductor layer 21, the thickness of the region covering the conductive layer 25 at the end of the opening is greater than the thickness of the portion covering the top surface of the conductive layer 25. In other words, the semiconductor layer 21 can also be described as having a protruding shape. For example, the semiconductor layer 21 sometimes has the above-described shape when deposited using a physical vapor deposition (PVD) method such as sputtering.

[0198] When the semiconductor layer 21 has a protruding shape, the conductive layer 23 has a portion that tapers. Specifically, the portion of the conductive layer 23 that tapers within the opening included in the conductive layer 25 has a taper. The conductive layer 23 needs to be formed in a way that fills the aforementioned complex-shaped opening, so it is preferable to use a chemical vapor deposition (CVD) method with good step coverage, especially a thermal CVD method, to deposit the conductive layers 23a and 23b.

[0199] The above is an explanation of the structural examples.

[0200] [Example of manufacturing method] The following describes an example of a method for manufacturing a transistor according to one aspect of the present invention. Here, the transistor shown in the above-described structural example 4 will be used as an example for explanation.

[0201] Note that the thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, chemical vapor deposition, vacuum evaporation, pulsed laser deposition (PLD), ALD, and other methods.

[0202] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, and doctor blade coating.

[0203] Examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing conductive metal films. Furthermore, pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0204] CVD methods can be categorized into plasma-enhanced chemical vapor deposition (PECVD), thermal CVD (TCVD), and photochemical CVD. Furthermore, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0205] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because plasma is not used in thermal CVD, plasma damage to the workpiece is reduced. Additionally, since no plasma damage occurs during deposition in thermal CVD, films with fewer defects can be obtained.

[0206] As ALD methods, there are thermal ALD methods that use only thermal energy to react the precursors and reactants, and PEALD methods that use reactants excited by plasma.

[0207] Unlike sputtering, CVD and ALD are deposition methods with good step coverage and are less affected by the shape of the substrate. In particular, ALD offers excellent step coverage and thickness uniformity, making it suitable for covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other deposition methods, such as CVD, which has a faster deposition rate.

[0208] When using CVD (CVD), films of arbitrary composition can be deposited depending on the source gas flow rate ratio. For example, when using CVD, films with continuously varying compositions can be deposited by changing the source gas flow rate ratio during deposition. Since the time required for transfer or pressure adjustment is eliminated when deposition is performed simultaneously with changing the source gas flow rate ratio, the deposition time can be shortened compared to deposition using multiple deposition chambers. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0209] When using the ALD method, films of arbitrary composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, by controlling the number of cycles for each precursor while introducing multiple different precursors, films of arbitrary composition can be deposited. Furthermore, similar to the CVD method, films with continuously varying compositions can be deposited.

[0210] When processing thin films constituting semiconductor devices, photolithography and other methods can be used. In addition to the methods mentioned above, nanoimprint lithography, sandblasting, and lift-off methods can also be used to process thin films. Furthermore, island-shaped thin films can be directly formed using deposition methods that employ metal masks or similar masking techniques.

[0211] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, processing the film through etching, and then removing the resist mask. The other method involves depositing a photosensitive thin film, followed by exposure and development to process the film into the desired shape.

[0212] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these rays. Alternatively, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can be employed. Additionally, extreme ultraviolet (EUV) light or X-rays can be used as the light for exposure. Furthermore, electron beams can be used instead of the light used for exposure. When using EUV light, X-rays, or electron beams, extremely fine processing can be achieved, making them preferred. Moreover, when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0213] For thin film etching, dry etching, wet etching, sandblasting, and other methods can be used.

[0214] Figures 7A to 13B These are cross-sectional schematic diagrams corresponding to each process in the manufacturing method examples described below.

[0215] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0216] As a substrate, a substrate with heat resistance sufficient to withstand subsequent heat treatment can be used. When using an insulating substrate, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, organic resin substrates, etc., can be used. In addition, single-crystal semiconductor substrates or polycrystalline semiconductor substrates made of materials such as silicon or silicon carbide, compound semiconductor substrates such as silicon-germanium and gallium nitride, SOI substrates, etc., can also be used.

[0217] As the insulating layer 11, inorganic insulating films such as silicon oxide films and silicon oxynitride films can be used. The deposition of the insulating layer 11 can be performed using sputtering, CVD, MBE, PLD, ALD, etc. If the surface on which the insulating layer 11 is formed is not flat, it is preferable to perform planarization treatment after depositing the insulating layer 11 to make the top surface of the insulating layer 11 flat.

[0218] Next, insulating layers 45 and 46 are formed on insulating layer 11. Insulating layers 45 and 46 can be formed using deposition methods such as sputtering, ALD, and CVD.

[0219] Next, conductive films 24a1f and 24a2f are stacked on the insulating layer 46. Figure 7A The conductive films 24a1f and 24a2f can be formed by deposition methods such as sputtering, ALD, and CVD.

[0220] Next, insulating films 40af and 40bf are stacked on the conductive film 24a1f. Figure 7B The insulating films 40af and 40bf can be formed by deposition methods such as sputtering, ALD, and CVD.

[0221] Next, a resist mask is formed on the insulating film 40bf, and unwanted portions of the insulating films 40bf and 40af are removed by etching to form an insulating layer 40 with stacked insulating layers 40b and 40a. Figure 7C Dry etching is preferred as the etching method. Alternatively, dry cleaning using plasma or wet cleaning using a chemical solution (containing acid or alkali) or water (containing carbonated water) can be performed after dry etching.

[0222] After depositing the insulating film 40bf or processing it into the insulating layer 40b, oxygen can be supplied to the insulating film 40bf or the insulating layer 40b. Thus, oxygen can be supplied from the insulating layer 40 to the semiconductor layer 21 by heat or the like applied after the semiconductor film 21f is formed.

[0223] Examples of oxygen supply methods include heating in an oxygen-containing atmosphere or plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere using a sputtering method. The deposited oxide film can be removed immediately or may remain. Furthermore, the oxygen-containing atmosphere includes not only oxygen gas (O2) but also atmospheres containing oxygen-containing compounds such as ozone (O3) and nitrous oxide (N2O).

[0224] Next, conductive film 24bf is formed by covering conductive film 24a1f, insulating layer 40a, and insulating layer 40b. Figure 7D The conductive film 24bf can be formed using deposition methods such as sputtering and ALD. When formed using PVD methods such as sputtering, the thickness of the portion covering the sides of the insulating layer 40a and the insulating layer 40b is sometimes smaller than that of the other portions.

[0225] Next, a resist mask is formed on the conductive film 24bf, and unwanted portions of the conductive films 24bf, 24a1f, and 24a2f are removed by etching to form a conductive layer 24 (with conductive layers 24a2, 24a1, and 24b stacked on top of each other). Figure 7E As etching, one or both of wet etching and dry etching methods can be used. In particular, dry etching is preferred. Alternatively, dry cleaning using plasma or wet cleaning using a chemical solution (containing acid or alkali) or water (containing carbonated water) can be performed after dry etching.

[0226] Next, insulating layers 41a, 41b, and 41c are formed on the conductive layer 24 and the insulating layer 46. Figure 8A Insulating layers 41a, 41b, and 41c can be applied using sputtering, CVD, MBE, PLD, ALD, or other appropriate methods, respectively.

[0227] Here, insulating layers 41a and 41c are preferably made of insulating films whose composition or constituent elements are different from those of insulating layer 41b.

[0228] In addition, since the thickness of insulating layers 41a, 41b and 41c affects the channel length of the transistor, it is important to avoid uneven thickness of insulating layers 41a, 41b and 41c.

[0229] The insulating layer 41b is preferably an oxide film containing oxygen to the extent that oxygen is released upon heating and has a low hydrogen content. The insulating layer 41b can be deposited using deposition methods such as PECVD, sputtering, and ALD, with sputtering being particularly preferred. In particular, by depositing the insulating layer 41b using an oxygen-containing gas instead of a hydrogen-containing gas as the deposition gas, an insulating layer 41b with extremely low hydrogen content and excess oxygen can be deposited. By depositing the insulating layer 41b in this way, oxygen can be supplied from the insulating layer 41b to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0230] After depositing insulating layer 41b and before depositing insulating layer 41c, oxygen supply to insulating layer 41b can also be performed. The oxygen supply process can be referred to the description above.

[0231] Next, conductive films 25af and 25bf are stacked on the insulating layer 41c. Figure 8B The conductive films 25af and 25bf can be formed by deposition methods such as sputtering, ALD, and CVD.

[0232] Next, a resist mask is formed on the conductive film 25bf, and an opening 20a is formed in the conductive film 25bf, the conductive film 25af, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a to reach the conductive layer 24b. Figure 8C ).

[0233] By using dry etching for etching the conductive film 25bf, conductive film 25af, insulating layer 41c, insulating layer 41b, and insulating layer 41a, fine openings 20a can be formed. Note that this is not a limitation; wet etching and dry etching can also be combined, and processing can also be performed by wet etching. Additionally, dry cleaning using plasma or wet cleaning using a chemical solution (containing acid or alkali) or water (containing carbonated water) can be performed after dry etching.

[0234] like Figure 8C As shown, when forming the opening 20a, sometimes a portion of the upper part of the conductive layer 24b is etched, and the thickness of the portion overlapping the opening 20a is reduced.

[0235] When forming opening 20a, conductive film 25bf can also be used as a hard mask. In this case, an opening is first formed in conductive film 25bf using a photoresist mask. Then, using conductive film 25bf as a mask, insulating layers 41c, 41b, and 41a are etched sequentially, thereby forming opening 20a. Alternatively, the photoresist mask can be removed after etching conductive film 25bf, during etching of insulating layers 41c, 41b, and 41a, or after forming opening 20a.

[0236] In addition, such as Figure 8C As shown, when forming opening 20a, the end of conductive film 25bf sometimes has a tapered shape. Note that it is not limited to conductive film 25bf; conductive film 25af, insulating layer 41c, insulating layer 41b, etc., may also sometimes have tapered shapes. Furthermore, sometimes due to the effect of etching in a direction parallel to the substrate (also called side etching), the upper film becomes a shape that protrudes more than the lower film (protrusion shape). For example, sometimes it is processed in such a way that the side of insulating layer 41b located at opening 20a is located outside the side of insulating layer 41c.

[0237] Note that in this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is disposed at an angle relative to the substrate surface.

[0238] When the sidewall of the opening 20a has a shape approximately perpendicular to the top surface of the conductive layer 24, the area of ​​the opening 20a can be reduced, which is therefore preferred. By employing this structure, transistors with a small footprint can be manufactured. Alternatively, the sidewall of the opening 20a can also be tapered. Having a tapered shape improves the coverage of the film formed inside the opening 20a.

[0239] The maximum width of the opening 20a (the maximum diameter of the opening 20a when it is circular when viewed from a plane) is preferably as fine as possible. For example, the maximum width of the opening 20a is preferably less than 2 μm, less than 1 μm, less than 500 nm, less than 300 nm, less than 150 nm, less than 100 nm, less than 60 nm, less than 50 nm, less than 40 nm, less than 30 nm, or less than 20 nm and more than 5 nm. In particular, in order to perform extremely fine processing on the opening 20a, photolithography using short-wavelength light such as EUV light or electron beams is preferred.

[0240] Next, a heat treatment can be performed. The heat treatment can be performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen and oxygen gas, the oxygen gas ratio can be set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the released oxygen, it can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By performing the above-described heat treatment, impurities such as water and hydrogen contained in the insulating layer 41 can be reduced before the oxide semiconductor film, which is deposited as the semiconductor layer, is formed.

[0241] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, it is preferable that the water content of the gas used in the heat treatment is 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the insulating layer 41 can be prevented as much as possible.

[0242] Next, an insulating film 15f is formed on the conductive film 25bf and inside the opening 20a. Figure 9A The insulating film 15f can be formed by deposition methods such as sputtering, ALD, and CVD. ALD is particularly preferred.

[0243] Next, the insulating film 15f is etched using anisotropic dry etching without a resist mask to form an annular (cylindrical) insulating layer 15 that contacts the sides of the conductive film 25bf, conductive film 25af, insulating layer 41c, insulating layer 41b, and insulating layer 41a. After etching the insulating film 15f, the exposed portion of the conductive layer 24b is continuously etched, thereby forming an opening 20b in the conductive layer 24b that reaches the insulating layer 40b. Figure 9B ).

[0244] During etching of the insulating layer 15, sometimes portions of the insulating film 15f along the sidewalls of the opening 20a are also exposed to the etching and become thinner. Therefore, it is preferable to form the insulating film 15f thick beforehand so that it has the desired thickness after etching. Thinning is particularly easy to occur when the opening 20a has a tapered shape, and forming the insulating film 15f thick as described above is effective.

[0245] Furthermore, during the etching of the conductive layer 24b, etching is performed with the top surface of the conductive film 25bf exposed. Therefore, there is a concern that the conductive film 25bf might even disappear if the same conductive film is used for both the conductive layer 24b and the conductive film 25bf. Therefore, it is preferable to form the conductive film 25bf to be sufficiently thicker than the conductive layer 24b beforehand. Alternatively, a protective layer can be formed on the conductive film 25bf and removed after the opening 20b is formed. The protective layer can be a film that does not disappear during the formation of the opening 20a and the opening 20b, or it can be an insulating film, a conductive film, or a semiconductor film. Moreover, when removing the protective layer, one or both of dry etching and wet etching can be used.

[0246] Next, a semiconductor film 21f is formed by covering the conductive film 25bf, opening 20a, and opening 20b. Figure 9C ).

[0247] As the semiconductor film, a metal oxide (oxide semiconductor) film with semiconductor properties can be used. When depositing this metal oxide film, sputtering, CVD, MBE, PLD, ALD, and other methods can be appropriately employed. Here, the metal oxide film is preferably formed in contact with the sidewall of the high aspect ratio opening 20a and the bottom and sidewall of the opening 20b. Therefore, a deposition method with good coverage is preferred when depositing this metal oxide film, and ALD is more preferably employed.

[0248] The metal oxide film preferably has crystallinity. In one aspect of the invention, the metal oxide film particularly preferably comprises a metal oxide having a CAAC structure.

[0249] During or after the deposition of a metal oxide film, it is preferable to perform a treatment to improve the crystallinity of the metal oxide film. Examples of such treatments include heat treatment, plasma treatment, microwave treatment (typically 2.45 GHz), microwave plasma treatment, and light (e.g., ultraviolet light) irradiation. Note that multiple treatments can be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment can be performed simultaneously. Alternatively, microwave plasma treatment can be performed after heat treatment.

[0250] Furthermore, it is more preferable to perform multiple treatments to improve the crystallinity of the metal oxide film during deposition. For example, when forming a metal oxide film by the ALD method, it is preferable to perform microwave plasma treatment after each atomic layer is formed. Alternatively, it is preferable to perform treatments to improve crystallinity after each metal oxide film with a predetermined thickness is formed, as this can improve productivity. Specifically, it is preferable to form a first metal oxide film of 1 nm or more and 10 nm or less and perform a first microwave plasma treatment, and then form a second metal oxide film of 1 nm or more and 10 nm or less and perform a second microwave plasma treatment.

[0251] Note that there are no particular limitations on the deposition methods for the first and second metal oxide films; either ALD (Alternating Deposition) or sputtering can be used. In particular, depositing the first metal oxide film using ALD prevents elements constituting the layer forming the surface from mixing into both the first and second metal oxide films (also known as mixing). This is especially suitable when the element in the layer forming the surface blocks the crystallization of the metal oxide (e.g., when it contains silicon, carbon, etc.). Furthermore, the first and second metal oxide films can have different compositions. While a stacked structure of the first and second metal oxide films is shown here, the method is not limited to this. The same treatment can be applied when the metal oxide films have a single-layer structure or a stacked structure of three or more layers.

[0252] Furthermore, treatments to improve the crystallinity of metal oxide films can be performed after the deposition of the metal oxide film. Specifically, this treatment can be performed directly on the deposited metal oxide film or in the presence of other films, such as an insulating film, deposited on the metal oxide film. For example, microwave plasma treatment can be performed after the deposition of the metal oxide film, or an insulating film (e.g., silicon nitride film, silicon oxide film, aluminum oxide film, etc.) can be deposited after the deposition of the metal oxide film, and then the metal oxide film can be subjected to heat treatment or microwave plasma treatment in the presence of the insulating film.

[0253] Note that the above-described treatment to improve the crystallinity of metal oxide films can also be used to remove impurities from the metal oxide films. For example, carbon, hydrogen, nitrogen, etc., can be appropriately removed from the metal oxide films. Alternatively, by performing the treatment to improve the crystallinity of the metal oxide films under an oxygen gas atmosphere, oxygen vacancies in the metal oxide films can be reduced.

[0254] When performing a process to improve the crystallinity of a metal oxide film, it is preferable to set the heat treatment temperature (or substrate temperature) to room temperature (e.g., 25°C) or higher, 100°C or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.

[0255] By increasing the crystallinity of metal oxide films, transistors with high reliability can be achieved.

[0256] Metal oxide films can be formed, for example, by sputtering using a metal oxide target.

[0257] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film, wherein impurities such as hydrogen and water are minimized. In particular, a crystalline metal oxide film is preferred as the metal oxide film.

[0258] When depositing metal oxide films, oxygen gas and inert gases (e.g., helium, argon, xenon, etc.) can also be mixed. Note that the higher the proportion of oxygen gas in the overall deposition gas composition during metal oxide film deposition (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, enabling the realization of transistors with high reliability. Conversely, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film, enabling the realization of transistors with improved on-state current.

[0259] When depositing metal oxide films, the higher the substrate temperature, the more dense and crystalline the metal oxide film can be formed. On the other hand, the lower the substrate temperature, the more crystalline and conductive the metal oxide film can be formed.

[0260] Metal oxide films can be deposited at a substrate temperature above room temperature and below 250°C, preferably above room temperature and below 200°C, and more preferably above room temperature and below 140°C. For example, a substrate temperature above room temperature and below 140°C is preferred, thereby improving productivity. When metal oxide films are deposited at a substrate temperature of room temperature or without intentional heating, crystallinity can be reduced.

[0261] When using ALD methods, thermal ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced ALD) methods are preferred. Thermal ALD is preferred because it offers extremely high step coverage. Furthermore, PEALD not only offers high step coverage but also allows for low-temperature deposition, making it a preferred method as well.

[0262] For example, when using a metal oxide for semiconductor layer 21, a precursor containing the metal element constituting the metal oxide and an oxidant can be deposited using the ALD method.

[0263] For example, when depositing In-Ga-Zn oxide, three precursors can be used: one containing indium, one containing gallium, and one containing zinc. Alternatively, two precursors can be used: one containing indium and one containing both gallium and zinc.

[0264] As indium-containing precursors, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, etc. can be used.

[0265] In addition, as gallium-containing precursors, trimethylgallium, triethylgallium, tris(dimethylamide)gallium(III), gallium(III)acetylacetone, tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid)gallium, dimethylgallium chloride, diethylgallium chloride, gallium(III) chloride, etc. can be used.

[0266] In addition, zinc-containing precursors such as dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptadecanoic acid) zinc, and zinc chloride can be used.

[0267] As an oxidant, ozone, oxygen, water, etc. can be used, for example.

[0268] Methods for controlling the composition of the resulting membrane include adjusting the source gas flow rate ratio, the time the source gas flows through, and the order in which the source gas flows through. By adjusting these parameters, membranes with continuously varying compositions can be deposited. Furthermore, two or more membranes with different compositions can be deposited consecutively.

[0269] After depositing the metal oxide film, a heat treatment is preferably performed. The heat treatment can be performed within a temperature range that does not cause polycrystalline formation of the metal oxide film, preferably between 250°C and 650°C, and more preferably between 400°C and 600°C. Note that the heat treatment is performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm, 1%, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen and oxygen gas, the oxygen gas ratio can be set to approximately 20%. Alternatively, the heat treatment can also be performed under reduced pressure. Alternatively, after performing the heat treatment in a nitrogen or inert gas atmosphere, a heat treatment can be performed in an atmosphere containing 10 ppm, 1%, or 10% or more of an oxidizing gas to replenish the released oxygen.

[0270] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, the water content of the gas used in the heat treatment can be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the metal oxide film can be prevented as much as possible.

[0271] Figure 9C An example is shown in which the thickness of the portion of the semiconductor film 21f covering the conductive film 25bf is made larger than that of the other portions. Here, an example is shown of the cross-sectional shape when the semiconductor film 21f is formed as a stack of three layers: a metal oxide film deposited by ALD, a metal oxide film deposited by sputtering, and a metal oxide film deposited by ALD.

[0272] Next, a photoresist mask is formed on the semiconductor film 21f, and unwanted portions of the semiconductor film 21f, conductive film 25bf, and conductive film 25af are etched, thereby forming the semiconductor layer 21, conductive layer 25b, and conductive layer 25a. Figure 10A As etching, one or both of wet etching and dry etching methods can be used. In particular, dry etching is preferred. Dry etching is especially preferred. Alternatively, dry cleaning using plasma or wet cleaning using a chemical solution (containing acid or alkali) or water (containing carbonated water) can be performed after dry etching.

[0273] Next, an insulating layer 22 is formed in such a manner that it covers an insulating layer 41c, a conductive layer 25a, a conductive layer 25b, and a semiconductor layer 21. Figure 10B The insulating layer 22 can be formed using deposition methods such as sputtering, ALD, and CVD.

[0274] An insulating layer 22 is disposed on the surface of the semiconductor layer 21 within the openings 20a and 20b with the most uniform thickness possible. Therefore, it is particularly preferable to form the insulating layer 22 by means of the ALD method, which is a deposition method with excellent coverage. In addition, when the sidewalls of the openings 20a and 20b have a tapered shape, the insulating layer 22 can be deposited by deposition methods such as sputtering or CVD.

[0275] Next, a dummy layer 17 is formed, which fills the openings 20a and 20b and has a shape that protrudes upwards compared to the top surface of the insulating layer 22. Figure 11A ).

[0276] As the dummy layer 17, organic resins or inorganic insulating materials can be used. For example, when using coating-type insulating films such as SOC (Spin On Carbon) films and SOG (Spin On Glass) films, the top surface can be flattened without the need for planarization treatment, which is preferred. For example, a structure formed by stacking SOG films on SOC films is preferred. Furthermore, the dummy layer 17 can be formed by deposition methods such as sputtering or CVD. As for the material used for the dummy layer 17, it is preferable to meet the following conditions: it can be formed thickly; it can be formed or processed vertically; it is easy to remove (no residue is generated, and the damage to the formed surface is minimal); etc.

[0277] The dummy layer 17 can be formed by forming a resist mask after forming the insulating film and etching away the unwanted parts. Alternatively, if a photosensitive organic resin is used as the dummy layer 17, the dummy layer 17 can also be formed by removing the unwanted parts through exposure and development processes after depositing the insulating film.

[0278] Next, insulating layers 47 and 42 are stacked to form insulating layers. Sputtering, CVD, MBE, PLD, and ALD methods can be used to deposit insulating layers 47 and 42, respectively. For example, ALD, a deposition method with high step coverage, can be used to form insulating layer 47, and sputtering, a deposition method that easily increases the deposition rate, can be used to form insulating layer 42.

[0279] Next, through planarization, the upper part of insulating layer 42 and insulating layer 47 is etched until the top surface of dummy layer 17 is exposed. Figure 11B Planarization can be performed using methods such as CMP (Chemical Mechanical Polishing) or dry etching. Additionally, a portion of the dummy layer 17 can also be removed through planarization. For example, when the dummy layer 17 is a structure in which an SOG film is stacked on top of an SOC film, the planarization process can be completed when the SOG film is removed through planarization and the top surface of the SOC film is exposed.

[0280] Next, by removing the dummy layer 17, an opening 20c is formed in the insulating layer 47. Figure 12A The dummy layer 17 can be removed by wet etching or dry etching. Alternatively, after dry etching, dry cleaning using plasma or wet cleaning using a chemical solution (containing acid or alkali) or water (containing carbonated water) can be performed.

[0281] Next, conductive films forming conductive layer 23a and conductive layer 23b are sequentially formed on insulating layer 42 and within openings 20c, 20a, and 20b. The conductive films forming conductive layer 23a and conductive layer 23b can be formed using CVD, ALD, sputtering, etc. CVD is particularly preferred. The conductive film forming conductive layer 23b is formed thick enough to fill each opening.

[0282] Next, a planarization process is performed, etching is carried out on the top of each conductive film until the top surface of the insulating layer 47 is exposed. Figure 12B Thus, conductive layers 23a and 23b can be formed embedded in openings 20a, 20b and 20c.

[0283] Transistors are manufactured at this stage.

[0284] Next, a conductive film is formed on the insulating layer 42 and the conductive layer 23, and the unwanted parts are removed by etching, thereby forming the conductive layer 31. Figure 13A When depositing the conductive film that forms the conductive layer 31, sputtering, CVD, or ALD methods can be used.

[0285] Next, insulating layer 43 is formed by covering insulating layer 42 and conductive layer 31. Insulating layer 43 can be formed using the same method as insulating layer 42.

[0286] Next, a resist mask is formed on the insulating layer 43 and the insulating layer 43 is etched to form openings reaching the conductive layer 24a1 and the conductive layer 25a. Dry etching is preferably used when forming the openings. Alternatively, dry cleaning using plasma or wet cleaning using a chemical solution (containing acid or alkali) or water (containing carbonated water) can be performed after dry etching.

[0287] The two openings can be formed using the same resist mask and process, or they can be formed sequentially using different resist masks.

[0288] Next, an insulating film is deposited along the insulating layer 43, reaching the sidewall of the opening of the conductive layer 24a1, and reaching the sidewall of the opening of the conductive layer 25a, and then anisotropic dry etching is performed to form an annular (cylindrical) insulating layer 48 in contact with the sidewall of each opening.

[0289] The insulating film that forms the insulating layer 48 can be formed using deposition methods such as sputtering, ALD, and CVD. ALD is particularly preferred.

[0290] Next, after forming a conductive film as conductive layer 32 along the sidewalls of each opening, a conductive film as conductive layer 33 is formed to fill each opening. Then, the upper parts of the two conductive films are etched until the top surface of the insulating layer 43 is exposed to form connecting electrode 35a and connecting electrode 35b. Figure 13B ).

[0291] Then, wiring that contacts the connecting electrode 35a and wiring that contacts the connecting electrode 35b may also be formed on the insulating layer 43. For details regarding this wiring, please refer to the description of the conductive layer 31.

[0292] Through the above-described process, a semiconductor device including the transistor shown in structural example 4 can be manufactured.

[0293] The above is an explanation of examples of manufacturing methods.

[0294] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0295] (Implementation Method 2) The following describes the structure of a storage device using a transistor and capacitor according to one aspect of the present invention.

[0296] Figure 14AThis is a circuit diagram of memory cell 30. Memory cell 30 consists of a transistor Tr1 and a capacitor C, and can also be referred to as 1Tr1C. The gate of transistor Tr1 is connected to wiring WL, one of its source and drain terminals is connected to wiring BL, and the other is connected to one electrode of capacitor C. The other electrode of capacitor C is connected to wiring PL.

[0297] Storage cell 30 stores data by maintaining the data potential input from wiring BL through transistor Tr1 in capacitor C. Furthermore, data can be retained by de-conducting transistor Tr1. Conversely, data can be read by outputting a potential corresponding to the retained data to wiring BL when transistor Tr1 is turned on. Wiring WL is supplied with signals controlling the on / off state of transistor Tr1. Wiring PL is supplied with a predetermined potential (e.g., a fixed potential).

[0298] Figure 14B and Figure 14C This is a cross-sectional view of storage unit 30. Figure 14B This is a cross-sectional view along the extension direction of conductive layer 25 and conductive layer 34. Figure 14B This is a cross-sectional view along the extension direction of the conductive layer 31. The storage cell 30 has a structure in which a transistor 10 is stacked on top of a capacitor 50. The transistor 10 and the capacitor 50 correspond to the transistor Tr1 and the capacitor C mentioned above, respectively.

[0299] The structure of transistor 10 can be referred to in Embodiment 1, and therefore the description is omitted. Here, an example of using transistor 10 is shown, but it is not limited to transistor 10 and can be replaced with various transistors described in Embodiment 1.

[0300] The capacitor 50 includes a conductive layer 51, a conductive layer 52, and an insulating layer 53 sandwiched between them. The capacitor 50 constitutes a so-called MIM (Metal-Insulator-Metal) capacitor.

[0301] A capacitor 50 is disposed on an insulating layer 11. A conductive layer 34 and an insulating layer 55 are disposed on the insulating layer 11. The insulating layer 55 has an opening 20d extending to the conductive layer 34. A conductive layer 51 is disposed inside the opening 20d, in contact with the side surface of the insulating layer 55 and the top surface of the conductive layer 34. Furthermore, an insulating layer 53 is disposed covering the insulating layer 55 and the conductive layer 51. An insulating layer 56 is disposed on the insulating layer 53. A conductive layer 52 is disposed embedded in the insulating layer 56 and the opening 20d.

[0302] The top surfaces of the conductive layer 52 and the insulating layer 56 are planarized, and their top surfaces are approximately the same height. A conductive layer 24a is disposed on the conductive layer 52 and the insulating layer 56. The conductive layer 31 is disposed in contact with the top surface of the conductive layer 24a.

[0303] exist Figure 14B and Figure 14C In this configuration, conductive layer 32 corresponds to wiring BL, conductive layer 23 corresponds to wiring WL, and conductive layer 34 corresponds to the aforementioned wiring PL.

[0304] Low-resistance conductive materials can be used as conductive layers 34, 51, and 52. For example, materials suitable for conductive layer 23b can be used.

[0305] Insulating layer 53 is used as the dielectric layer of capacitor 50. The thinner the insulating layer 53 and the higher its relative permittivity, the larger the capacitance of capacitor 50. For example, a material that can be used for the aforementioned insulating layer 22 is preferably used.

[0306] Figure 15A This is a circuit diagram of memory cell 30a. Memory cell 30a includes transistor Tr2 replacing capacitor C in memory cell 30. In transistor Tr2, the gate is connected to the other of the source and drain of transistor Tr1, one of the source and drain is connected to wiring SL and the other is connected to wiring RL.

[0307] Storage cell 30a maintains the data potential input from wiring BL through transistor Tr1 at a node connected to the gate of transistor Tr2, thereby storing data. Furthermore, data can be retained by de-conducting transistor Tr1. Additionally, in transistor Tr2, the conduction states of wiring SL and wiring RL change depending on the potential maintained at the gate. For example, data can be read based on the magnitude of the potential or current output to the other when a signal is supplied to one of wiring SL and wiring RL. Therefore, storage cell 30a can be used as a memory capable of non-destructive readout.

[0308] Alternatively, it can also be done in Figure 15A A capacitor C is provided in the storage cell 30a shown. More specifically, a structure can also be adopted in which one electrode of the capacitor C is connected to a node that is connected to the source and drain of transistor Tr1 and the gate of transistor Tr2. In this case, the other electrode of the capacitor C can be connected to the wiring PL described above. The capacitor C can have the same structure as the capacitor 50 described above, or various MIM capacitors such as parallel plate type, cylindrical type, and column type can be used.

[0309] Figure 15B , Figure 15CThis is a cross-sectional view of memory cell 30a. Memory cell 30a has a structure in which transistor 10 is stacked on top of transistor 70. The structure of transistor 10 is the same as that of memory cell 30 described above.

[0310] Transistor 70 includes conductive layer 74a, conductive layer 74b, insulating layer 40c, insulating layer 40d, semiconductor layer 71, insulating layer 72, conductive layer 73, conductive layer 75a, and conductive layer 75b. Transistor 70 is a vertical transistor superimposed on the region of the opening 20e provided in conductive layer 75b, conductive layer 75a, insulating layer 55a, insulating layer 55b, and insulating layer 55c. For details on transistor 70, please refer to the description of transistor 10.

[0311] A conductive layer 74a is disposed on the insulating layer 11. Insulating layers 40c and 40d are disposed on the conductive layer 74a. A conductive layer 74b is disposed to cover the conductive layers 74a, 40c, and 40d. Insulating layers 55a, 55b, and 55c are stacked on the conductive layer 74b. The conductive layers 75a and 75b are disposed on the insulating layer 55c. A semiconductor layer 71 and an insulating layer 72 are disposed along the inner wall of the opening 20e in the conductive layers 75a, 75b, 55c, and 55a. The semiconductor layer 71 is disposed in contact with the top and side surfaces of the conductive layer 75b, the side surfaces of the conductive layers 75a, 55a, 55b, 55c, and 40d, and the top surface of the insulating layer 40d. A conductive layer 73 is disposed to fill the insulating layer 56 and the opening 20e.

[0312] exist Figure 15B , Figure 15C In the diagram, conductive layer 73 corresponds to the gate of transistor Tr2, conductive layers 75a and 75b correspond to one of wiring SL and wiring RL, and conductive layers 74a and 74b correspond to the other of wiring SL and wiring RL.

[0313] Figure 16A and Figure 16B An example of a storage device in which two storage cells 30 are connected to the same wiring is shown. Figure 16A This is a top view of the storage device. Figure 16B It is along Figure 16A A schematic diagram of the cross-section of the cut-off line A3-A4 in the diagram.

[0314] The conductive layer 31 used for wiring WL is disposed in each of the two memory cells 30. The conductive layer 25a used for wiring BL is disposed in a manner shared by the two memory cells 30.

[0315] Furthermore, the conductive layer 25a, used as wiring BL, is embedded in the interlayer insulating layers and is electrically connected to the conductive layers 61 and 62, which serve as plugs (also called connection electrodes). The conductive layer 61 can also be electrically connected to a readout amplifier (not shown) disposed below the insulating layer 11. In addition, the conductive layer 61 can also be electrically connected to the conductive layer 32 of the memory cell stacked above the insulating layer 65.

[0316] The insulating layer 65 is used as a barrier layer and has the function of preventing impurities such as water and hydrogen from diffusing into the storage device from the outside.

[0317] Furthermore, a memory cell array can be constructed by arranging the memory cells 30 in a three-dimensional matrix. As an example of a memory cell array, Figure 17A and Figure 17B An example of a storage device is shown, in which 4 × 2 × 4 storage units 30 are arranged in the X, Y and Z directions. Figure 17A This is a floor plan of the storage device. Figure 17B It is along Figure 17A The cross-sectional view of the cut-off lines A3-A4 in the figure.

[0318] A group consisting of four storage units 30 can be referred to as a memory unit 60. Figure 17A , Figure 17B Eight memory cells are shown (memory cells 60[1,1] to memory cells 60[2,4]). In memory cell 60[a,b] (a and b are each positive integers), a represents the address in the Y direction and b represents the address in the Z direction.

[0319] The memory cells 60 are centered around conductive layer 61 or conductive layer 62, with each pair of memory cells 30 arranged symmetrically. The conductive layers 32 of the memory cells 60 stacked in the Z direction are electrically connected to each other through conductive layers 62. In this way, by stacking multiple memory cells 60, the storage capacity per unit area can be increased, providing a storage device that can achieve miniaturization or high integration.

[0320] Figure 18A and Figure 18B This shows an example of a case where the connection is positioned at the end of a memory cell. Figure 18A This is a floor plan of the storage device. Figure 18B This is a cross-sectional view. Here, as an example of a memory cell array, an example of a memory device is shown that has 3 × 3 × m (m is an integer greater than 2) memory cells 30 configured. In the layers that include the memory cells 30, the first layer is referred to as layer 80[1], and the m-th layer (the top layer) is referred to as layer 80[m].

[0321] The conductive layer 63 is disposed on the outside of the memory cell. The conductive layer 63 may also be connected to wiring in the layer above the layer 80 that includes the conductive layer 63. For example, the conductive layer 63 disposed in layer 80[1] is electrically connected to wiring disposed in layer 80[2]. Furthermore, not limited thereto, the conductive layer 63 may also be electrically connected to wiring in the layer 80 below the layer 80 that includes the conductive layer 63.

[0322] Figure 19 An example of a cross-sectional structure of a storage device is shown, wherein a layer including a storage cell 30 is stacked on a layer having a drive circuit including a readout amplifier.

[0323] Figure 19 An example is shown with a capacitor 50 stacked above a transistor 90 and a transistor 10 thereon. Transistor 90 is one of the transistors in a sense amplifier.

[0324] By arranging the read amplifier in a manner that overlaps with the memory cell 30, the bit line can be shortened. This reduces the load on the bit line, thereby improving the read sensitivity of the read amplifier. Therefore, high-speed driving of the memory device is possible.

[0325] Transistor 90 is disposed on substrate 91 and includes a conductive layer 94 serving as a gate, an insulating layer 93 serving as a gate insulating layer, a semiconductor region 92 formed by a portion of substrate 91, and low-resistance regions 95a and 95b serving as source or drain regions. Transistor 90 may also be p-channel or n-channel.

[0326] Here, in Figure 19 In the transistor 90 shown, the semiconductor region 92 (a portion of the substrate 91) forming the channel has a convex shape. Furthermore, a conductive layer 94 is provided such that it covers the sides and top surface of the semiconductor region 92 with an insulating layer 93 in between. Because of the convexity of the semiconductor substrate, this transistor 90 is also called a FIN-type transistor.

[0327] Preferably, there is a structure in which interlayer insulating layers and wiring layers are alternately stacked between the layer where transistors 90 are disposed and the layer where memory cells 30 are disposed (also known as multilayer wiring layers). Figure 19 An example is shown where the low-resistance region 95b of transistor 90 is electrically connected to the conductive layer 32, which serves as the bit line of memory cell 30, via wiring and plugs.

[0328] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0329] (Implementation Method 3) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer for a transistor is described.

[0330] [Oxide semiconductor layer] In one aspect of the present invention, the oxide semiconductor layer preferably comprises a crystalline metal oxide. Examples of structures with crystalline metal oxides include CAAC (c-axis aligned crystal), polycrystalline, and nanocrystalline (nc) structures. By using a crystalline metal oxide in the oxide semiconductor layer, the defect state density in the oxide semiconductor layer can be reduced. Therefore, the reliability of transistors using the oxide semiconductor layer of one aspect of the present invention can be improved, and the reliability of semiconductor devices in which transistors are mounted can be improved.

[0331] In one aspect of the invention, the oxide semiconductor layer preferably comprises a metal oxide having a CAAC structure. A CAAC structure is a crystal structure in which multiple microcrystals (typically multiple microcrystals with a hexagonal crystal structure) are c-axis oriented and connected without orientation on the ab plane. When a cross-section of an oxide semiconductor layer with a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image (also known as a multibeam interferometry image), it can be confirmed that the metal atoms are arranged in layers within the crystalline regions. Therefore, it can also be said that the oxide semiconductor layer with a CAAC structure has layered crystalline regions. When the metal atoms are arranged in layers within the crystalline regions, clusters of bright spots reflecting the layered arrangement of the metal atoms (specifically, bright spots arranged in layers) are observed in the cross-section of the oxide semiconductor layer observed using a TEM image.

[0332] The CAAC structure is formed, for example, with the c-axis perpendicular or substantially perpendicular to the surface being formed. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or substantially parallel to the surface being formed. In the region having the CAAC structure, the angle formed by the c-axis and the surface being formed is preferably within 90° ± 20° (70° or more and 110° or less), more preferably within 90° ± 15° (75° or more and 105° or less), even more preferably within 90° ± 10° (80° or more and 100° or less), and even more preferably within 90° ± 5° (85° or more and 95° or less).

[0333] The crystallinity of oxide semiconductor layers can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Furthermore, multiple methods can be combined for analysis.

[0334] When an oxide semiconductor layer with a CAAC structure is subjected to electron diffraction, spots (bright spots) representing the c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned with the direction of the normal vector parallel to the normal vector of the formed surface of the oxide semiconductor layer or the normal vector of the surface of the oxide semiconductor layer.

[0335] Furthermore, the FFT pattern obtained by processing the TEM image with Fast Fourier Transform (FFT) reflects the same reciprocal space information as the electron diffraction pattern.

[0336] By obtaining a cross-sectional TEM image of an oxide semiconductor layer with a CAAC structure and performing FFT processing on each region in the cross-sectional TEM image to create an FFT pattern, the crystal axis orientation of each region can be calculated based on the created FFT pattern. Specifically, in the spots observed in the created FFT pattern, the direction of the line segment connecting two spots with high brightness and approximately equal distances from the center is taken as the crystal axis orientation. Regions whose angle relative to the surface of formation is calculated from the FFT image is preferably 70° or more and 110° or less (within 90° ± 20°), more preferably 75° or more and 105° or less (within 90° ± 15°), more preferably 80° or more and 100° or less (within 90° ± 10°), and even more preferably 85° or more and 95° or less (within 90° ± 5°) can be considered as CAAC structures.

[0337] When an oxide semiconductor layer with a CAAC structure is observed using TEM images from a direction perpendicular to the formed surface, triangular or hexagonal atomic arrangements with crystalline properties are observed on the ab surface. Furthermore, in Voronoi diagrams created by image analysis of TEM images of the oxide semiconductor layer with a CAAC structure observed from a direction perpendicular to the formed surface, pentagonal, hexagonal, and heptagonal Voronoi regions are predominantly observed, with hexagonal Voronoi regions being particularly prominent. For example, in the Voronoi regions observed in Voronoi diagrams, hexagonal Voronoi regions account for more than 30% but less than 100%.

[0338] The following explains how to create a Voronoi diagram. First, when performing image analysis on a TEM image, after FFT processing, filtering is applied to retain only a certain range of information, followed by an inverse Fast Fourier Transform (IFFT) to create an FFT-filtered image. Lattice points are extracted from the created FFT-filtered image, and perpendicular bisectors of line segments connecting nearby lattice points are constructed. The point where the three perpendicular bisectors intersect is the Voronoi point, and the polygonal region enclosed by the line segments connecting the Voronoi points is the Voronoi region. This allows the creation of the Voronoi diagram.

[0339] Note that, as an example of the observation range of a TEM when creating a Voronoi diagram, a rectangular region with a vertical side length of 50 nm and a horizontal side length of 50 nm can be observed. Note that the observation range is not limited to this.

[0340] Furthermore, when analyzing the orientation distribution of the hexagonal lattice using lattice points extracted through image analysis of planar TEM images, the following state was observed at the boundary between two structures with different orientations of the hexagonal lattice: the difference in orientation between the hexagonal lattice is small, the boundary is blurred, and the two structures are connected in an intertwined manner. In other words, no clear boundary was observed in the CAAC structure.

[0341] Note that the orientation of a hexagonal lattice can be calculated from the orientation of the hexagon formed by the six lattice points closest to each lattice point.

[0342] Furthermore, there are no particular restrictions on the crystallinity of the semiconductor material contained in the oxide semiconductor layer. For example, the oxide semiconductor layer may sometimes contain one or more of the following: amorphous semiconductor (semiconductor with an amorphous structure), single-crystal semiconductor (semiconductor with a single-crystal structure), and semiconductor with crystallinity other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor with partially crystalline regions). When the oxide semiconductor layer is crystallinity, it can sometimes suppress the degradation of transistor characteristics.

[0343] According to one aspect of the invention, the metal oxide preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Here, the metal oxide may contain indium as a main component, and may also contain element M. Furthermore, the metal oxide preferably contains two or three selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide may contain indium and zinc as main components, and may also contain element M. Note that element M is a metallic or half-metallic element with a high bond energy with oxygen, for example, a metallic or half-metallic element with a higher bond energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the invention preferably contains one or more elements selected from indium, gallium, and zinc. Note that in this specification and the like, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification and the like sometimes include half-metallic elements.

[0344] In cross-sections of oxide semiconductor layers observed using TEM images, it was confirmed that metal atoms were arranged in layers parallel or substantially parallel to the surface in which they were formed. For example, in metal oxides containing indium, indium was confirmed to be arranged in layers. Furthermore, for example, in metal oxides containing indium and zinc, indium and zinc were confirmed to be arranged in layers.

[0345] As one embodiment of the metal oxide according to the present invention, indium oxide, gallium oxide, zinc oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (also denoted as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. Alternatively, examples include indium tin oxide (also known as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide), which contain silicon.

[0346] When the ratio of the number of indium atoms to the total number of atoms of all metal elements in a metal oxide is increased, transistors can achieve large on-state current and high frequency characteristics.

[0347] Note that metal oxides can also contain one or more metals with high period numbers in the periodic table to replace indium. Alternatively, metal oxides can also contain one or more metals with high period numbers in the periodic table in addition to indium. The greater the overlap of the orbitals of a metal element, the greater the carrier conduction in the metal oxide. Therefore, by including metals with high period numbers in the periodic table, the field-effect mobility of transistors can sometimes be improved. Examples of metals with high period numbers in the periodic table include metals belonging to period 5 and period 6. Specifically, examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0348] Furthermore, metal oxides may also contain one or more non-metallic elements. The inclusion of non-metallic elements in metal oxides can sometimes improve the field-effect mobility of transistors. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0349] Furthermore, by increasing the ratio of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the metal oxide can be made highly crystallizable, thereby suppressing the diffusion of impurities in the metal oxide. This suppresses variations in the electrical characteristics of the transistor and improves reliability.

[0350] Furthermore, by increasing the ratio of the number of atoms of element M to the total number of atoms of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, thereby enabling transistors with low off-state current. In addition, variations in the electrical characteristics of the transistor are suppressed, thus improving reliability.

[0351] In one aspect of the present invention, the oxide semiconductor layer can be fabricated by forming a metal oxide using two deposition methods.

[0352] In the fabrication of an oxide semiconductor layer according to one aspect of the present invention, a crystalline metal oxide is deposited using a first deposition method. The deposited metal oxide preferably has a CAAC structure. For example, metal oxide films deposited using sputtering methods tend to be crystalline.

[0353] When sputtering is used as the first deposition method, a mixed layer sometimes forms at the interface between the metal oxide and the layer to be formed due to particles released from the target material (also called sputtered particles) or energy supplied to the substrate side by the sputtered particles. The mixed layer may hinder the crystallization of the metal oxide.

[0354] For example, when silicon oxide is used as the surface to be formed, if a metal oxide is formed on the silicon oxide using a sputtering method, silicon may become mixed into the metal oxide. Due to the incorporation of silicon, the crystallization of the metal oxide may be hindered.

[0355] Therefore, in one embodiment of the present invention, a metal oxide is formed using a second deposition method before forming the metal oxide using a first deposition method. That is, after forming a first layer of metal oxide using the second deposition method, a second layer of metal oxide is formed on the first layer using the first deposition method. In this case, as the second deposition method, a deposition method that causes less damage to the surface to be formed compared to the first deposition method is preferably used. This suppresses the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on which it is formed, thereby further improving crystallinity. Compared to sputtering, ALD and CVD methods, for example, can suppress damage to the surface to be formed, and are therefore suitable for use as the second deposition method.

[0356] Furthermore, as the first layer, a metal oxide with a microcrystalline or amorphous structure having a lower crystallinity than the CAAC structure is sometimes formed. The crystallinity of the first layer is sometimes improved by forming a highly crystalline second layer on the low-crystallinity first layer, or by performing heat treatment after forming the second layer. Thus, the crystallinity of the entire oxide semiconductor layer, including the area near the interface with the formed surface, can sometimes be improved.

[0357] Examples of primary deposition methods include sputtering and PLD.

[0358] Examples of second deposition methods include ALD, plasma-enhanced CVD (PECVD), thermal CVD, photo-CVD, metal-organic CVD (MOCVD), and molecular beam epitaxy (MBE). Furthermore, wet deposition methods can also be used as second deposition methods. Examples of wet deposition methods include spray coating.

[0359] As an example, the oxide semiconductor layer of one aspect of the present invention can be manufactured by forming a metal oxide as a second layer using a sputtering method after forming a metal oxide as a first layer using the ALD method. Furthermore, the metal oxide formed using the sputtering method preferably has a CAAC structure.

[0360] Furthermore, a third layer can also be formed on the second layer. Since the second layer has high crystallinity, the third layer can be grown using the crystals of the second layer as nuclei or seeds. Therefore, even without using a deposition method that readily produces crystals as the deposition method for the third layer, the third layer can be crystallized. Here, for example, by using a deposition method with higher coverage than the second layer as the deposition method for the third layer, the entire oxide semiconductor layer can possess both high crystallinity and high coverage.

[0361] Furthermore, by setting a first layer to reduce the influence of the formed surface, the crystallinity of the second layer is improved, resulting in extremely excellent crystallinity. Therefore, it is expected that an extremely crystallinity layer will also be formed in the third layer, which crystallizes with the second layer as the nucleus or seed.

[0362] Furthermore, the third layer is the topmost layer of the oxide semiconductor layer. When the oxide semiconductor layer is used as the semiconductor layer of a transistor, the third layer is, for example, the layer in contact with the gate insulating film. By increasing the crystallinity of the layer in contact with the gate insulating film, the carrier mobility of the transistor in the on state can be improved.

[0363] As an example, the oxide semiconductor layer of one aspect of the present invention can be manufactured by forming a metal oxide as a first layer and a third layer using the same second deposition method, and forming a metal oxide as a second layer using the first deposition method. Specifically, the second deposition method can be the ALD method, and the first deposition method can be the sputtering method.

[0364] [Manufacturing method of oxide semiconductor layer] Reference Figures 20A to 21D An example illustrating a method for manufacturing the oxide semiconductor layer 230.

[0365] The oxide semiconductor layer 230 can be manufactured, for example, by forming oxide semiconductor 230a on layer 229, which is the formed surface, using an ALD method; forming oxide semiconductor 230b on oxide semiconductor 230a using a sputtering method; and forming oxide semiconductor 230c on oxide semiconductor 230b using an ALD method. Furthermore, after forming the oxide semiconductor layer 230, heat treatment is preferably performed. Heat treatment can improve the crystallinity of the oxide semiconductor layer 230. Here, heat treatment is not limited to heating. For example, it can also be heat applied during the manufacturing process. Layer 229 is an insulating film, such as a silicon oxide film, silicon oxynitride film, silicon nitride film, silicon oxynitride film, aluminum oxide film, hafnium oxide film, or other insulating films.

[0366] The oxide semiconductor layer 230 can be used in the semiconductor layer 21 included in each transistor described in Embodiment 1. In addition, layer 229 corresponds to one or more of the insulating layer 40b, conductive layer 24b, insulating layer 41a, insulating layer 41b, insulating layer 41c, conductive layer 25a, and conductive layer 25b described in Embodiment 1.

[0367] Layer 229 may also be non-crystalline. Alternatively, if layer 229 is crystalline, it may have a crystal structure with low lattice matching with the metal oxide contained in oxide semiconductor layer 230.

[0368] First, an oxide semiconductor 230a is formed on layer 229. Figure 20A Next, oxide semiconductor 230b is formed on oxide semiconductor 230a. Figure 20B ).

[0369] The oxide semiconductor 230b is preferably formed using a sputtering method. Furthermore, the oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure.

[0370] Compared to the deposition method of oxide semiconductor 230b, it is preferable to use a deposition method that causes less damage to the surface to be formed to form oxide semiconductor 230a. Here, oxide semiconductor 230a is formed using the ALD method.

[0371] When depositing metal oxide films using sputtering, regions sometimes form as mixed layers where components from the metal oxide film are alloyed with components from the layer on which they are formed. In such cases, it is difficult to improve the crystallinity of the alloyed regions even with subsequent heat treatment. Furthermore, oxide semiconductor layers including mixed layers can negatively impact the initial characteristics or reliability of transistors. Therefore, it is preferable to suppress the formation of mixed layers.

[0372] By employing the above structure, the thickness of the mixing layer can be reduced to a point where it is not observable. For example, the thickness of the mixing layer can be 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Furthermore, Figure 20A and Figure 20B An example is shown where no hybrid layer is formed between layer 229 and oxide semiconductor 230a.

[0373] In addition, the thickness of the hybrid layer can sometimes be calculated by performing line analysis of the composition of the region and its surroundings using energy dispersive X-ray spectroscopy (EDX) or by performing SIMS.

[0374] For example, using the direction perpendicular to the surface to which the oxide semiconductor 230a is formed as the depth direction, EDX line analysis is performed on the aforementioned region and its surrounding area. Next, in the distribution of quantitative values ​​of each element relative to the depth direction obtained through this analysis, the depth at which the quantitative value of a metal (In when the oxide semiconductor 230a contains In) that is a major component of the oxide semiconductor 230a but not a major component of the layer formed on the surface (here, layer 229) reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the oxide semiconductor 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is a major component of the layer formed on the surface but not a major component of the oxide semiconductor 230a reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the layer formed on the surface. Through these steps, the thickness of the mixed layer can be calculated.

[0375] In one aspect of the oxide semiconductor layer of the present invention, when the thickness of the mixed layer is observed by EDX analysis, for example, its thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0376] Furthermore, for example, when a silicon oxide layer is used as layer 229 and SIMS analysis is performed on the oxide semiconductor layer 230 formed on layer 229, the interface can be measured at a depth where the silicon concentration reaches 50% of the maximum concentration in layer 229, and the silicon concentration can be reduced to 1.0 × 10⁻⁶. 21 atoms / cm 3 Preferred size: 5.0×10 20 atoms / cm 3 More preferably 1.0×10 20 atoms / cm 3 The distance between depths. This distance is preferably less than 3 nm, more preferably less than 2 nm.

[0377] Furthermore, by reducing the thickness of the hybrid layer, a CAAC structure can be formed near the surface to be formed. Here, "near the surface to be formed" refers, for example, to a region in the substantially vertical direction from the surface to be formed of the oxide semiconductor layer 230 that is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and more preferably more than 1 nm and less than 2 nm.

[0378] Furthermore, when forming oxide semiconductor 230a using the ALD method, sometimes oxide semiconductor layers with microcrystalline or amorphous structures having lower crystallinity than the CAAC structure are formed. That is, in Figure 20A In the manufacturing stages shown, oxide semiconductor 230a sometimes includes regions whose crystallinity is lower than that of oxide semiconductor 230b.

[0379] Microwave plasma treatment is preferably performed after the oxide semiconductor 230a is formed.

[0380] In this specification and the like, microwaves refer to electromagnetic waves with frequencies of 300 MHz or higher and 300 GHz or lower. Microwave plasma treatment, for example, refers to a process using a device that includes a power source for generating high-density plasma using microwaves. Microwave plasma treatment may also be referred to as microwave-excited high-density plasma treatment.

[0381] Microwave plasma treatment is preferably performed in an oxygen-containing atmosphere, thereby reducing the impurity concentration in the oxide semiconductor layer 230. Note that hydrogen and carbon are particularly noteworthy impurities. Note that the above describes a structure in which the metal oxide is microwave-plasma-treated in an oxygen-containing atmosphere, but this is not a limitation. For example, an insulating film disposed near the metal oxide, more specifically, a silicon oxide film, can also be microwave-plasma-treated in an oxygen-containing atmosphere. Furthermore, the crystallinity of the oxide semiconductor layer is sometimes improved due to the heat generated during microwave plasma treatment.

[0382] Microwave plasma treatment is preferably performed under reduced pressure, preferably between 10 Pa and 1000 Pa, more preferably between 300 Pa and 700 Pa. Microwave plasma treatment is preferably performed with a heated substrate, preferably at a temperature between room temperature (e.g., 25°C) and 500°C, more preferably between 100°C and 500°C, more preferably between 200°C and 500°C, further preferably between 300°C and 500°C, and even more preferably between 400°C and 500°C. For example, it can be between 400°C and 450°C.

[0383] Alternatively, heating treatment can be performed continuously after microwave plasma treatment without exposure to external air. The heating temperature is preferably 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 400°C or higher and 450°C or lower.

[0384] For example, microwave plasma treatment can be performed using oxygen and argon gases. By performing microwave plasma treatment in an oxygen-containing atmosphere, high-frequency plasma treatment can be used to plasmaify the oxygen gas, causing the generated oxygen free radicals to act on the oxide semiconductor layer. Through the action of plasma, microwaves, oxygen free radicals, etc., hydrogen can be introduced into defects in the oxygen vacancies (sometimes referred to below as V0) within the oxide semiconductor layer. O H) is separated into oxygen vacancies and hydrogen, and hydrogen can be removed from the oxide semiconductor layer. In this way, V in the oxide semiconductor layer can be reduced. OH. Furthermore, oxygen or carbon bonded to hydrogen can sometimes be removed. Thus, by performing microwave plasma treatment, impurities such as carbon or hydrogen can be reduced. In addition, by supplying the aforementioned oxygen free radicals to the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0385] Furthermore, during microwave plasma treatment, the crystallinity of the oxide semiconductor 230a can be expected to be improved through the following mechanism. First, active species such as oxygen free radicals excited by microwaves reach the surface of the oxide semiconductor, and a substitution reaction occurs between these active species and oxygen in the oxide semiconductor. At this time, nuclei or species are formed. In addition, lateral growth of the nuclei or species is induced. Furthermore, the aforementioned lateral growth is promoted when the active species excited by microwaves contain oxygen (typically oxygen ions) that can be easily adsorbed on the sides of the nuclei or species, which is therefore preferred. By performing microwave plasma treatment, the formation of nuclei or species and the lateral growth of nuclei or species occur, thereby improving the crystallinity of the oxide semiconductor.

[0386] On the other hand, when some of the oxygen in the oxide semiconductor present before microwave plasma treatment reacts with the hydrogen in the oxide semiconductor, i.e., when the reaction "2H + O → H2O↑" occurs, the hydrogen can be removed as H2O (also known as dehydration or dehydrogenation). Since H2O is one of the main reasons hindering the improvement of crystallinity, it is preferable to remove H2O from the oxide semiconductor. Removing hydrogen from the oxide semiconductor as H2O reduces the hydrogen concentration in the oxide semiconductor, thereby promoting improved crystallinity. Furthermore, by increasing the temperature in the microwave plasma treatment, the hydrogen concentration in the oxide semiconductor can be further reduced.

[0387] Note that plasma treatment containing oxygen gas can also be used instead of microwave plasma treatment to improve crystallinity.

[0388] When the crystallinity of oxide semiconductor 230a is improved, the crystallinity of oxide semiconductor 230b formed on oxide semiconductor 230a can be further improved. Therefore, the crystallinity of the entire oxide semiconductor layer can be improved.

[0389] The oxygen supplied to the oxide semiconductor layer can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen free radicals (oxygen atoms, oxygen molecules, or oxygen ions containing unpaired electrons). Furthermore, the oxygen implanted into the oxide semiconductor layer can be one or more of the above-mentioned forms, with oxygen free radicals being particularly preferred.

[0390] After forming oxide semiconductor 230a using the ALD method, In-M-Zn oxide is formed on oxide semiconductor 230a as oxide semiconductor 230b using the sputtering method.

[0391] Here, when the oxide semiconductor 230b is formed using a sputtering method, a mixed layer 231 is formed on or near the surface of the oxide semiconductor 230a. Furthermore, due to sputtered particles during the formation of the oxide semiconductor 230b, or energy supplied to the substrate side by sputtered particles, small crystalline regions sometimes form in the mixed layer 231. In subsequent heat treatment processes, at least a portion of the oxide semiconductor 230a may crystallize using the mixed layer 231 or the small crystalline regions formed in the mixed layer 231 as nuclei.

[0392] In-M-Zn oxides can be used as targets for sputtering. For example, when forming metal oxides using sputtering, oxygen or a mixture of oxygen and rare gases can be used as the sputtering gas. Furthermore, by increasing the proportion of oxygen in the sputtering gas, excess oxygen in the deposited oxide film can be increased. Additionally, highly crystalline metal oxides can be formed.

[0393] When forming metal oxides using sputtering, oxygen-excess metal oxides can sometimes be formed by deposition under conditions where the proportion of oxygen contained in the sputtering gas is higher than 30% and lower than 100%, preferably higher than 70% and lower than 100%. Transistors using oxygen-excess oxide semiconductors in the channel formation region can achieve high reliability. Note that one aspect of the invention is not limited to this. Oxygen-deficient metal oxides can be formed by deposition under conditions where the proportion of oxygen contained in the sputtering gas is higher than 1% and lower than 30%, preferably higher than 5% and lower than 20%. Transistors using oxygen-deficient metal oxides in the channel formation region can have higher field-effect mobility.

[0394] When depositing oxide semiconductor 230b using sputtering, it is preferable to heat the substrate. When forming metal oxide, by increasing the substrate temperature (stage temperature) during metal oxide formation, it is sometimes possible to form a highly crystalline metal oxide. When depositing oxide semiconductor 230b using sputtering, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, more preferably 200°C or higher and 300°C or lower.

[0395] Through the above processes, such as Figure 20B As shown, oxide semiconductor 230a and oxide semiconductor 230b on oxide semiconductor 230a can be formed on layer 229.

[0396] Next, oxide semiconductor 230c is formed on oxide semiconductor 230b. Figure 20C Here, oxide semiconductor 230c is formed using the ALD method. For the formation of oxide semiconductor 230c using the ALD method, please refer to the formation method of oxide semiconductor 230a.

[0397] When an oxide semiconductor 230c is formed on an oxide semiconductor 230b having a CAAC structure using the ALD method, the oxide semiconductor 230c is sometimes epitaxially grown with the oxide semiconductor 230b as the core. Therefore, when forming the oxide semiconductor 230c, the oxide semiconductor 230c sometimes includes a region having a CAAC structure. Furthermore, this region having a CAAC structure is preferably formed throughout the oxide semiconductor 230c.

[0398] Next, a heat treatment process can be carried out.

[0399] The heat treatment temperature can be, for example, 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, more preferably 350°C or higher and 550°C or lower. Typically, it can be 400°C ± 25°C (375°C or higher and 425°C or lower). Furthermore, the processing time can be 10 hours or less, 1 minute or more and 5 hours or less, or 1 minute or more and 2 hours or less. Furthermore, when using an RTA device, the processing time can, for example, be 1 second or more and 5 minutes or less. Through this heat treatment, it is expected that the atomic-level crystalline voids in the CAAC structure of the oxide semiconductor 230b will be repaired by the oxide semiconductor 230c (in other words, the individual crystalline molecules formed using the ALD method).

[0400] There are no particular restrictions on the heating device used for heat treatment; devices that utilize heat conduction or thermal radiation from a heating element such as a resistance heating element can also be used to heat the workpiece. For example, electric furnaces or RTA (Rapid Thermal Anneal) devices such as LRTA (Lamp Rapid Thermal Anneal) and GRTA (Gas Rapid Thermal Anneal) devices can be used. An LRTA device heats the workpiece using radiation (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device uses high-temperature gas for heat treatment.

[0401] Through this heat treatment process, the crystallinity of the region having a CAAC structure in the oxide semiconductor 230c is sometimes improved. Furthermore, when this region is formed only below the oxide semiconductor 230c after deposition using the ALD method, it sometimes extends upwards due to this heat treatment process. Figure 20D In other words, by performing this heat treatment, regions with CAAC structures are sometimes formed throughout the oxide semiconductor 230c.

[0402] Furthermore, preferably, through this heat treatment process, at least a portion of the oxide semiconductor 230a undergoes CAAC (catheterization). Figure 20D It is expected that CAAC formation can easily occur using the mixed layer 231 formed in the oxide semiconductor 230a during the deposition of oxide semiconductor 230b as a core or seed. The CAAC formation region in the oxide semiconductor 230a is preferably large, and preferably extends to the vicinity of layer 229.

[0403] Furthermore, since CAAC formation occurs from the top to the bottom of the oxide semiconductor 230a, it is not limited by the material or crystallinity of layer 229, and CAAC formation can reach the vicinity of layer 229. For example, even if layer 229 has an amorphous structure, a highly crystalline oxide semiconductor 230a can be formed. Therefore, the method for manufacturing an oxide semiconductor layer according to one aspect of the present invention is particularly suitable for cases where the layer to be formed has an amorphous structure.

[0404] Alternatively, microwave plasma treatment can be performed after the oxide semiconductor 230c is formed. By performing one or both of the above-mentioned heat treatment and microwave plasma treatment, the crystallinity of the entire oxide semiconductor layer can be improved.

[0405] As described above, impurities in the oxide semiconductor layer can be reduced. By performing crystal growth with a reduced impurity concentration in the oxide semiconductor layer, crystallinity can be further improved.

[0406] In addition, one or both of the above-mentioned heat treatment and microwave plasma treatment can be performed directly on the oxide semiconductor layer, or after forming an insulating film on the oxide semiconductor layer.

[0407] Thus, in one aspect of the metal oxide deposition method of the present invention, the crystallinity of the upper and lower oxide semiconductors (here, oxide semiconductors 230a and 230c) can be improved by using a highly crystalline oxide semiconductor 230b (i.e., CAAC) as a nucleus or seed. This improves the overall crystallinity of the oxide semiconductor. In other words, by using oxide semiconductor 230b as a nucleus or seed to grow the upper and lower oxide semiconductors in a solid phase, a highly crystalline oxide semiconductor can be formed. The oxide semiconductor formed using the above deposition method, in this case, the CAAC film, can be referred to as axially grown CAAC (AG CAAC).

[0408] In the oxide semiconductor layer 230, regions having the CAAC structure are preferably widely present throughout the entire layer. Figure 21AThis diagram shows the crystallized state of oxide semiconductors 230a, 230b, and 230c. The crystals of the CAAC-structured regions in oxide semiconductor 230a are connected to the CAAC-structured regions in oxide semiconductor 230b. Similarly, the crystals of the CAAC-structured regions in oxide semiconductor 230c are connected to the CAAC-structured regions in oxide semiconductor 230b. Therefore, sometimes the boundaries between oxide semiconductors 230a and 230b, and between oxide semiconductors 230b and 230c, are not observed. Sometimes, oxide semiconductor layer 230 can be described as a single layer or layer without a clearly observed interface. For example, the boundaries between the two stacked films can be observed using cross-sectional TEM or cross-sectional STEM (scanning transmission electron microscopy).

[0409] In the regions with CAAC structures in each of oxide semiconductors 230a, 230b, and 230c, bright spots arranged in directions parallel or substantially parallel to the formed surface are confirmed, for example, in cross-sectional observation using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure in each of oxide semiconductors 230a, 230b, and 230c is preferably substantially parallel to the normal direction of the formed surface of the oxide semiconductor layer 230.

[0410] In addition, sometimes a portion of oxide semiconductor 230a or oxide semiconductor 230c is not crystallized. Figure 21B The example shown illustrates the following situation: in oxide semiconductor 230a, the area near the interface with layer 229 is not crystallized. Figure 21C The following situation is shown: in oxide semiconductor 230c, the vicinity of the surface does not crystallize. Figure 21D The following situation is shown: the area near the interface between oxide semiconductor 230a and layer 229 and the area near the surface of oxide semiconductor 230c are not crystallized.

[0411] By improving the crystallinity of the oxide semiconductor layer, the increase in semiconductor layer resistance in transistors using oxide semiconductor layers is suppressed, or the initial characteristics of the transistor (especially the on-state current) are improved, thereby making it possible to realize transistors suitable for high-speed driving. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0412] As described above, using metal oxides with a high In content in transistors can improve the field-effect mobility of the transistors. On the other hand, oxide semiconductors with a high In content tend to polycrystalline. When using metal oxides with polycrystalline structures in transistors, it negatively impacts the initial characteristics or reliability of the transistors. Therefore, by using oxide semiconductors with a high In content in one or both of oxide semiconductors 230a and 230c, forming a crystal that reflects the orientation of the crystals contained in oxide semiconductor 230b, polycrystalline formation can be suppressed.

[0413] Furthermore, the lattice mismatch between the crystals contained in oxide semiconductor 230b and those contained in oxide semiconductor 230a or oxide semiconductor 230c is preferably small. Therefore, oxide semiconductor 230a or oxide semiconductor 230c can form crystals that reflect the orientation of the crystals contained in oxide semiconductor 230b. At this time, for example, when cross-sectional observation of the oxide semiconductor layer 230 is performed using a high-resolution TEM, bright spots arranged in a layered pattern in the oxide semiconductor 230a or oxide semiconductor 230c are confirmed.

[0414] As long as the lattice mismatch between the crystal contained in oxide semiconductor 230b and the crystal contained in oxide semiconductor 230a or oxide semiconductor 230c is small, there are no particular restrictions on the crystal structure of oxide semiconductor 230a or oxide semiconductor 230c. The crystal structure of oxide semiconductor 230a or oxide semiconductor 230c can be any of the following: cubic, tetragonal, orthorhombic, hexagonal, monoclinic, or trigonal.

[0415] Furthermore, when one or both of the microwave plasma treatment and heat treatment are performed in the process of forming the oxide semiconductor layer 230, it is sometimes unnecessary to form the oxide semiconductor 230b. For example, as described above, by performing one or both of the microwave plasma treatment and heat treatment after forming the oxide semiconductor 230a, the crystallinity of the oxide semiconductor 230a can be improved, thereby improving the crystallinity of the oxide semiconductor 230c using the oxide semiconductor 230a as a core or seed. Furthermore, by performing one or both of the microwave plasma treatment and heat treatment after forming the oxide semiconductor 230c, the crystallinity of the oxide semiconductor layer 230 can be improved. Therefore, a CAAC structure can be formed in the oxide semiconductor layer 230.

[0416] Furthermore, for example, when the metal oxide layer is provided as layer 229, the crystallinity of the oxide semiconductor 230a can be improved by using the metal oxide layer as a nucleus or seed. Moreover, the crystallinity of the oxide semiconductor layer 230 can be improved by performing microwave plasma treatment and heat treatment, either or both, after forming the oxide semiconductor 230a and after forming the oxide semiconductor 230c. Therefore, a CAAC structure can be formed in the oxide semiconductor layer 230.

[0417] As described above, even in a structure without oxide semiconductor 230b, the oxide semiconductor above can be solid-phase grown using layer 229 or oxide semiconductor 230a as a nucleus or seed, thereby forming a highly crystalline oxide semiconductor. The oxide semiconductor formed by the above deposition method can also be called AG CAAC. That is, AG CAAC can be formed even without using the first deposition method. In other words, AG CAAC can also be formed using the second deposition method described above (e.g., ALD and CVD methods) and one or both of microwave plasma treatment and heat treatment.

[0418] [Composition of the oxide semiconductor layer] The composition of oxide semiconductor 230a is preferably different from that of oxide semiconductor 230b. Furthermore, the composition of oxide semiconductor 230c is preferably different from that of oxide semiconductor 230b. Alternatively, oxide semiconductor 230a may use the same composition as oxide semiconductor 230c. Or, the composition of oxide semiconductor 230a may also be different from that of oxide semiconductor 230c.

[0419] As described above, the composition of the oxide semiconductor 230b is preferably suitable for forming a CAAC structure. The oxide semiconductor 230b can be formed, for example, by sputtering. The oxide semiconductor 230b preferably contains zinc, for example. By including zinc, a highly crystalline metal oxide can be obtained. Furthermore, the oxide semiconductor 230b preferably contains element M in addition to zinc. By including element M in the oxide semiconductor 230b, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of transistors using the oxide semiconductor layer can be improved. Specifically, as the oxide semiconductor 230b, metal oxides with the following compositions can be used: In:M:Zn = 1:1:1 [atomic ratio] or a near-atomic ratio; In:M:Zn = 1:1:1.2 [atomic ratio] or a near-atomic ratio; In:M:Zn = 1:1:0.5 [atomic ratio] or a near-atomic ratio; In:M:Zn = 1:1:2 [atomic ratio] or a near-atomic ratio; In:M:Zn = 4:2:3 [atomic ratio] or a near-atomic ratio; In:M:Zn = 1:3:2 [atomic ratio] or a near-atomic ratio; or In:M:Zn = 1:3:4 [atomic ratio] or a near-atomic ratio. Furthermore, the near-atomic ratio includes a range of ±30% of the desired atomic ratio. As element M, one or more of gallium, aluminum, and tin are preferably used.

[0420] The oxide semiconductor 230b may also not contain element M. For example, In-Zn oxide may be used. Specifically, it may be an In:Zn composition of 1:1 (atomic ratio) or near, In:Zn composition of 2:1 (atomic ratio) or near, or In:Zn composition of 4:1 (atomic ratio) or near. Alternatively, indium oxide may be used. Furthermore, it may contain trace amounts of element M. For example, it may be an In:Ga:Zn composition of 4:0.1:1 (atomic ratio) or near, or In:Ga:Zn composition of 2:0.1:1 (atomic ratio) or near. Alternatively, it may be an In:Sn:Zn composition of 4:0.1:1 (atomic ratio) or near, or In:Sn:Zn composition of 2:0.1:1 (atomic ratio) or near.

[0421] Oxide semiconductors 230a and 230c can use metal oxides with a high In content. Oxide semiconductors 230a and 230c can be formed, for example, using the ALD method. Furthermore, metal oxides with a higher In content than element M are particularly preferred. By using metal oxides with a high In content, when the oxide semiconductor layer is used in a transistor, the on-state current can be increased and the frequency characteristics improved.

[0422] Furthermore, oxide semiconductors 230a and 230c may not contain element M. For example, In-Zn oxide may also be used. Specifically, it may be an In:Zn ratio of 1:1 or similar, an In:Zn ratio of 2:1 or similar, or an In:Zn ratio of 4:1 or similar. Alternatively, indium oxide may also be used. Furthermore, oxide semiconductors 230a and 230c may also contain trace amounts of element M. Specifically, it may be an In:Ga:Zn ratio of 4:0.1:1 or similar, an In:Ga:Zn ratio of 2:0.1:1 or similar, an In:Sn:Zn ratio of 4:0.1:1 or similar, or an In:Sn:Zn ratio of 2:0.1:1 or similar.

[0423] Furthermore, oxide semiconductors 230a and 230c can use metal oxides with a higher In ratio compared to oxide semiconductor 230b.

[0424] For example, metal oxides with a higher Ga ratio than oxide semiconductor 230b can be used as oxide semiconductors 230a and 230c. For instance, oxide semiconductors 230a and 230c preferably use metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, an In:Ga:Zn ratio of 1:3:2 or similar, or an In:Ga:Zn ratio of 1:3:4 or similar. By increasing the Ga ratio, the band gap of oxide semiconductors 230a and 230c can sometimes be made larger than that of oxide semiconductor 230b. Thus, oxide semiconductor 230b is sandwiched between oxide semiconductors 230a and 230c with larger band gaps, and oxide semiconductor 230b is primarily used as a current path (channel). By sandwiching oxide semiconductor 230b between oxide semiconductors 230a and 230c, the trap levels at and near the interface of oxide semiconductor 230b can be reduced. This enables buried-channel transistors with the channel located far from the insulating layer interface, thereby improving field-effect mobility. Furthermore, the influence of the interface energy level formed on the back channel side is reduced, suppressing transistor optical degradation (e.g., optical negative bias degradation), thus improving transistor reliability.

[0425] Furthermore, one of the oxide semiconductors 230a and 230c may use a metal oxide with a higher proportion of In compared to oxide semiconductor 230b, and the other may use a metal oxide with a higher proportion of Ga compared to oxide semiconductor 230b.

[0426] Furthermore, multiple layers having the above-described composition may be stacked in oxide semiconductors 230a, 230b, and 230c. For example, oxide semiconductor 230c may also have a structure in which a metal oxide with a high proportion of In is stacked on top of a metal oxide with a high proportion of Ga.

[0427] Furthermore, in one embodiment of the oxide semiconductor layer of the present invention, even if the oxide semiconductors 230a and 230c are composed of a structure that is not easily formed when forming a monolayer, the entire oxide semiconductor layer including oxide semiconductors 230a and 230c can have a CAAC structure by crystal growth with oxide semiconductor 230b as the core. Alternatively, regions including at least a portion of each of oxide semiconductors 230a and 230c extending to the region of oxide semiconductor 230b can have a CAAC structure.

[0428] In particular, when the oxide semiconductors 230a and 230c employ a high In ratio, a crystallinity suitable for transistors can be obtained. In one embodiment of the oxide semiconductor layer of the present invention, reliability can be improved by employing a highly crystallinity CAAC structure while increasing the In ratio to improve the transistor's turn-on characteristics.

[0429] Furthermore, oxide semiconductors 230a and 230c can also use metal oxides with the same composition as oxide semiconductor 230b. By using the same composition, it is sometimes easy to achieve CAAC after heat treatment.

[0430] Furthermore, compared to an oxide semiconductor layer with a CAAC structure formed using one deposition method, an oxide semiconductor layer with a CAAC structure formed using the two deposition methods described above sometimes has a higher relative permittivity, film density, and film hardness.

[0431] By using the oxide semiconductor layer with CAAC structure formed by the above two deposition methods to form the channel region of the transistor, transistors with excellent characteristics can be realized (e.g., transistors with large on-state current, transistors with high field-effect mobility, transistors with small S-value, transistors with high frequency characteristics (also known as f-characteristics), transistors with high reliability, etc.).

[0432] The composition of the metal oxide used in the oxide semiconductor layer 230 can be analyzed using methods such as EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, multiple methods can be combined. Note that the actual content of elements with low concentrations may differ from the analytically obtained content due to the limitations of analytical precision. For example, when the content of element M is low, the analytically obtained content of element M may sometimes be lower than the actual content.

[0433] [Oxide semiconductor layer of a transistor] The oxide semiconductor layer of one aspect of the present invention can be used as the semiconductor layer of a transistor.

[0434] One embodiment of the present invention provides an oxide semiconductor layer having a CAAC structure. In the oxide semiconductor layer having a CAAC structure, metal atoms in the crystalline portion are arranged in layers in a direction parallel or substantially parallel to the surface being formed.

[0435] In one embodiment of the semiconductor device of the present invention, in the oxide semiconductor layer 230, metal atoms are arranged in layers in a direction parallel to or substantially parallel to the surface to be formed. Alternatively, the ab plane of the CAAC structure may be provided in a direction parallel to or substantially parallel to the surface to be formed. Here, even when the surface to be formed is substantially perpendicular to the substrate surface, the metal atoms in the oxide semiconductor layer 230 are arranged in layers in a direction substantially parallel to the surface to be formed. By employing this structure, the ab plane of the CAAC structure can be provided in the channel of the transistor along the direction of current flow. This increases the on-state current of the transistor.

[0436] When the oxide semiconductor layer 230 is used as the semiconductor layer of a transistor, the thickness of the oxide semiconductor layer 230 is, for example, 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, further preferably 10 nm or more and 100 nm or less, even more preferably 10 nm or more and 70 nm or less, even more preferably 15 nm or more and 70 nm or less, even more preferably 15 nm or more and 50 nm or less, and even more preferably 20 nm or more and 50 nm or less. Furthermore, in transistors used in more miniaturized semiconductor devices, the thickness of the oxide semiconductor layer 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less. Furthermore, the average thickness of the oxide semiconductor layer 230 in the channel formation region of the transistor is particularly preferably 2 nm or more and 15 nm or less.

[0437] The oxide semiconductor 230b is preferably 200 nm or less. Furthermore, when the oxide semiconductor 230b is layered, the thickness is preferably 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and even more preferably 2 nm or more and 100 nm or less.

[0438] Alternatively, if the oxide semiconductor 230b can act as a crystal nucleus, it may exist not as a layer but as an aggregate of island-like regions. In this case, for example, the island-like regions included in the oxide semiconductor 230b are dispersed.

[0439] The thickness of oxide semiconductors 230a and 230c is preferably 0.5 nm or more and 50 nm or less, more preferably 0.5 nm or more and 30 nm or less, even more preferably 0.5 nm or more and 20 nm or less, even more preferably 1 nm or more and 50 nm or less, still more preferably 1 nm or more and 30 nm or less, even more preferably 1 nm or more and 20 nm or less, and even more preferably 2 nm or more and 20 nm or less. Furthermore, the thickness of oxide semiconductor 230a is more preferably 0.5 nm or more and 3 nm or less.

[0440] Impurities in oxide semiconductors Here, we will explain the effects of various impurities in oxide semiconductors.

[0441] In the channel formation region of a transistor using oxide semiconductors as the semiconductor layer, it is preferable that the concentration of oxygen vacancies is low or the concentration of impurities such as hydrogen, nitrogen, and metal elements is low compared to the source and drain regions. When oxygen vacancies (V0) are present in the channel formation region of the oxide semiconductor... OWhen impurities are present, the electrical properties are prone to change, and reliability may decrease. Furthermore, hydrogen near oxygen vacancies forms V... O H may generate electrons that become charge carriers. Therefore, when oxygen vacancies are included in the channel formation region of an oxide semiconductor, the transistor tends to have always-on characteristics. Thus, in the channel formation region, V O H is also preferably reduced. Thus, the channel formation region of the transistor is a high-resistivity region with low carrier concentration. Therefore, the channel formation region of the transistor can be described as i-type (intrinsic) or substantially i-type.

[0442] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that impurities in an oxide semiconductor refer, for example, to elements other than the main components constituting the oxide semiconductor. For example, elements with a concentration below 0.1 atomic% can be considered impurities.

[0443] When an oxide semiconductor contains silicon or carbon, one of Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 Below. Furthermore, the silicon concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred.18 atoms / cm 3 the following.

[0444] Furthermore, when nitrogen is included in an oxide semiconductor, electrons are generated as charge carriers, increasing the charge carrier concentration and making it easier to n-type. As a result, transistors using nitrogen-containing oxide semiconductors tend to have always-on characteristics. Alternatively, when nitrogen is included in an oxide semiconductor, trapped states sometimes form. Consequently, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0445] Furthermore, hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms to generate electrons as charge carriers. Therefore, transistors using hydrogen-containing oxide semiconductors tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor, as measured using SIMS, is set to be less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 5×10 19 atoms / cm 3 More preferably less than 1×10 19 atoms / cm 3 Further optimization is to select those smaller than 5×10 18 atoms / cm 3 Furthermore, a value less than 1×10 is preferred. 18 atoms / cm 3 Furthermore, it is preferred to select those smaller than 1×10 17 atoms / cm 3 .

[0446] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect states are sometimes formed, generating charge carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to have always-on characteristics. Consequently, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0447] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0448] [c-axis orientation] One embodiment of the present invention has an oxide semiconductor layer with a CAAC structure. For example, crystal orientation can be used to evaluate the crystallinity of the oxide semiconductor layer of one embodiment of the present invention.

[0449] Crystal orientation can be determined using an FFT pattern obtained by processing a TEM image using a Fast Fourier Transform (FFT). Specifically, the crystal axis orientation can be obtained using the FFT pattern. The FFT pattern obtained through FFT processing reflects the same reciprocal lattice space information as the electron diffraction pattern.

[0450] By performing FFT processing on each region within a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region over a certain area, a map showing the crystal orientation can be formed. Specifically, two high-intensity spots are observed in the FFT pattern of a region with layered crystals. The crystal axis orientation of this region can be obtained from the angle of the line segment connecting these two spots.

[0451] The degree of c-axis orientation can be calculated by determining the proportion of the c-axis orientation region in a diagram showing crystal orientation. Here, the c-axis orientation region refers to a region whose orientation coincides with the c-axis, preferably within 20 degrees, more preferably within 15 degrees, even more preferably within 10 degrees, and still more preferably within 5 degrees. Here, the angle of the c-axis is the angle relative to the surface being formed.

[0452] In one embodiment of the present invention, the oxide semiconductor layer can be observed, for example, by cross-section or planar TEM, and the c-axis orientation can be calculated using the above-described diagram showing crystal orientation. Furthermore, the region for performing the FFT (also called the FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region for performing the FFT is not limited to a circle.

[0453] Furthermore, when using cross-sectional TEM images for analysis, for example, the observation range of the cross-sectional TEM image can be set to a region with a longitudinal direction perpendicular to the formed surface and a transverse width of 100 nm. Note that the observation range is not limited to this.

[0454] In one embodiment of the oxide semiconductor layer of the present invention, the c-axis orientation degree is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, even more preferably 80% or more, still more preferably 90% or more, and still more preferably 95% or more. Here, it is preferable to calculate the c-axis orientation degree, for example, as the proportion of the region whose difference from the c-axis is within 20°.

[0455] Furthermore, the c-axis orientation degrees of the regions deposited as oxide semiconductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c are Rc1, Rc2, and Rc3, respectively. Rc2 is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, even more preferably 80% or more, still more preferably 90% or more, and still more preferably 95% or more. Rc3 is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, even more preferably 80% or more, still more preferably 90% or more, and still more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Furthermore, Rc2 / Rc1 is preferably greater than 1. Here, it is preferable to calculate the c-axis orientation degree as, for example, the proportion of regions whose difference from the c-axis is within 20°.

[0456] In addition, sometimes no clear boundaries of oxide semiconductors 230a, 230b and 230c are observed after the oxide semiconductor layer 230 is fabricated.

[0457] In one embodiment of the present invention, the oxide semiconductor layer 230 can be sequentially divided into three regions on layer 229: a first region, a second region, and a third region. Each region is a layered region.

[0458] The first, second, and third regions all have a CAAC structure. Furthermore, the c-axis orientation degree of the third region is preferably higher than that of the first region. Similarly, the c-axis orientation degree of the second region is preferably higher than that of the first region. Moreover, the c-axis orientation degree of the third region is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, even more preferably 80% or more, still more preferably 90% or more, and even more preferably 95% or more. Furthermore, the c-axis orientation degree of the second region is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, even more preferably 80% or more, still more preferably 90% or more, and even more preferably 95% or more. Here, it is preferable to calculate the c-axis orientation degree, for example, as the proportion of regions whose difference from the c-axis is within 20°.

[0459] The first region is located on the top surface of the delamination layer 229 at a distance of 0 nm to 3 nm, and the third region is located on the top surface of the delamination oxide semiconductor layer 230 at a distance of 0 nm to 3 nm.

[0460] Alternatively, the thickness of the layers in each region may be approximately equal.

[0461] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0462] (Implementation Method 4) In this embodiment, refer to Figures 22 to 25 This invention describes a storage device according to one aspect of the present invention. In this embodiment, an example of a storage device structure is described, in which a layer including storage cells is stacked on top of a drive circuit including a readout amplifier.

[0463] <Example of storage device structure> Figure 22 This is a block diagram illustrating a structural example of a storage device 480 according to one aspect of the present invention. Figure 22 The storage device 480 shown includes a layer 420 and a stacked layer 470.

[0464] Layer 420 is a layer that includes Si transistors. In layer 470, element layers 430[1] to 430[m] (m is an integer greater than or equal to 2) are stacked. Element layers 430[1] to 430[m] are layers that include OS transistors. Layer 470, which has layers including OS transistors, can be stacked on layer 420.

[0465] The OS transistors and capacitors included in the element layers 430[1] to 430[m] constitute the memory cells. Figure 22An example is shown in which multiple storage cells 432, arranged in a matrix of m rows and n columns (n ​​being an integer greater than 2), are included in element layers 430[1] to 430[m].

[0466] exist Figure 22 In this embodiment, the storage unit 432 in the first row and first column is represented as storage unit 432[1, 1], and the storage unit 432 in the m-th row and n-th column is represented as storage unit 432[m, n]. Furthermore, in this embodiment, etc., sometimes an arbitrary row is represented by the term "i-th row". Also, sometimes an arbitrary column is represented by the term "j-th column". Therefore, i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n. Furthermore, in this embodiment, etc., the storage unit 432 in the i-th row and j-th column is represented as storage unit 432[i, j]. Note that in this embodiment, etc., when represented as "i+α" (α is a positive or negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when represented as "j+α", "j+α" is not less than 1 and not greater than n.

[0467] Furthermore, as an example, Figure 22 The diagram shows m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment, the first (row 1) wiring WL is denoted as wiring WL[1], and the m (row 1) wiring WL is denoted as wiring WL[m]. Similarly, the first (row 1) wiring PL is denoted as wiring PL[1], and the m (row 1) wiring PL is denoted as wiring PL[m]. Similarly, the first (column 1) wiring BL is denoted as wiring BL[1], and the n (column 1) wiring BL is denoted as wiring BL[n]. Note that the number of component layers 430[1] to 430[m] and the number of wirings WL (and wiring PL) may be different.

[0468] Multiple storage cells 432 located in row i are electrically connected to the wiring WL (wiring WL[i]) and wiring PL (wiring PL[i]) in row i. Multiple storage cells 432 located in column j are electrically connected to the wiring BL (wiring BL[j]) in column j.

[0469] Wiring BL is used as the bit line for writing and reading data. Wiring WL is used as the word line for controlling the on or off (conducting or de-conducting) state of the access transistors used as switches. Wiring PL is used as the constant potential line connected to the capacitor. Additionally, wiring for transmitting the back gate potential can be provided separately.

[0470] The memory cells 432 included in the element layers 430[1] to 430[m] are connected to the sense amplifier 446 via wiring BL. The wiring BL can be configured in a direction parallel to or perpendicular to the surface of the substrate on which the layer 420 is disposed. By forming the wiring BL extending from the memory cells 432 included in the element layers 430[1] to 430[m] by wiring configured in a direction parallel to the substrate surface and wiring configured in a direction perpendicular to the substrate surface, the wiring length between the element layer 430 and the sense amplifier 446 can be shortened. Since the signal transmission distance between the memory cells and the sense amplifier can be shortened and the resistance and parasitic capacitance of the bit lines can be significantly reduced, power consumption and signal delay can be reduced. As a result, the power consumption and signal delay of the memory device 480 can be reduced. Furthermore, it can operate even if the capacitance of the capacitors included in the memory cells 432 is reduced. As a result, the memory device 480 can be miniaturized.

[0471] Layer 420 includes PSW471 (power switch), PSW472, and peripheral circuitry 422. Peripheral circuitry 422 includes drive circuitry 440, control circuitry 473, and voltage generation circuitry 474. Note that all circuits included in layer 420 are circuits that include Si transistors.

[0472] In the storage device 480, circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, while signal RDA is a signal output to the outside. Signal CLK is the clock signal.

[0473] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is for writing data, and signal RDA is for reading data. Signals PON1 and PON2 are power gating control signals. Furthermore, signals PON1 and PON2 can also be generated in control circuit 473.

[0474] The control circuit 473 is a logic circuit that controls the overall operation of the storage device 480. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device 480 (e.g., write operation, read operation). Alternatively, the control circuit 473 generates control signals for the drive circuit 440 to execute the aforementioned operating mode.

[0475] The voltage generation circuit 474 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 474. For example, when the signal WAKE is supplied with a high-level signal, the signal CLK is input to the voltage generation circuit 474, and the voltage generation circuit 474 generates a negative voltage.

[0476] The driver circuit 440 is used to write and read data from the storage cell 432. In addition to the row decoder 442, column decoder 444, row driver 443, column driver 445, input circuit 447, and output circuit 448, the driver circuit 440 also includes the aforementioned sense amplifier 446.

[0477] Row decoder 442 and column decoder 444 are used to decode the signal ADDR. Row decoder 442 is used to specify the circuit to be accessed in a row, and column decoder 444 is used to specify the circuit to be accessed in a column. Row driver 443 is used to select the wiring WL specified by row decoder 442. Column driver 445 has the following functions: writing data to memory cell 432; reading data from memory cell 432; and storing the read data.

[0478] Input circuit 447 has the function of holding signal WDA. The data held in input circuit 447 is output to column driver 445. The output data of input circuit 447 is the data written to memory cell 432 (Din). The data read from memory cell 432 by column driver 445 (Dout) is output to output circuit 448. Output circuit 448 has the function of holding Dout. In addition, output circuit 448 has the function of outputting Dout to the outside of memory device 480. The data output from output circuit 448 is signal RDA.

[0479] PSW471 controls the supply of VDD to the peripheral circuit 422. PSW472 controls the supply of VHM to the row driver 443. Here, the high supply voltage of the storage device 480 is VDD, and the low supply voltage is GND (ground potential). Furthermore, VHM is a high supply voltage used to make the word line high, which is higher than VDD. Signal PON1 controls the on / off state of PSW471, and signal PON2 controls the on / off state of PSW472. Figure 22 In the peripheral circuit 422, the number of power domains supplied with VDD is 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0480] Component layers 430[1] to 430[m] can be stacked on layer 420. Figure 23A This is a perspective view of a storage device 480 in which five (m=5) element layers 430[1] to 430[5] are stacked on layer 420.

[0481] exist Figure 23A In this context, the component layer 430 located in the first layer is referred to as component layer 430[1], the component layer 430 located in the second layer is referred to as component layer 430[2], and the component layer 430 located in the fifth layer is referred to as component layer 430[5]. Furthermore, Figure 23A The diagram shows wirings WL and PL extending in the X direction, and wirings BL and BLB extending in the Y and Z directions (perpendicular to the substrate surface where the drive circuitry is located). Wiring BLB is an inverted bit line. Note that for clarity, a portion of the wirings WL and PL included in each of component layers 430 is omitted from the description.

[0482] Figure 23B This is an explanation Figure 23A The schematic diagram shows an example of a structure of a sense amplifier 446 connected to wiring BL and wiring BLB and a memory cell 432 included in the component layers 430[1] to 430[5] connected to wiring BL and wiring BLB. In addition, a structure in which multiple memory cells (memory cells 432) are electrically connected to a wiring BL and wiring BLB is also called a "memory string".

[0483] Figure 23B An example of the circuit structure of a memory cell 432 connected to the wiring BLB is shown. The memory cell 432 includes a transistor 437 and a capacitor 438. Regarding the transistor 437, the capacitor 438 and the wirings (BL and WL, etc.), for example, wiring BL[1] and wiring WL[1] are sometimes referred to as wiring BL and wiring WL, etc. As the memory cell 432, for example, the memory cell 30 shown in the above embodiment can be used. That is, transistor 10 can be used as transistor 437, and capacitor 50 can be used as capacitor 438. In addition, transistor 90 can be used as the transistor included in the sense amplifier 446 (see Figure 18).

[0484] In memory cell 432, one of the source and drain of transistor 437 is connected to wiring BL. The other of the source and drain of transistor 437 is connected to one electrode of capacitor 438. The other electrode of capacitor 438 is connected to wiring PL. The gate of transistor 437 is connected to wiring WL.

[0485] The wiring PL is a wire that supplies a constant potential to maintain the potential of capacitor 438. The number of wires can be reduced by connecting multiple wiring PLs together as a single wire.

[0486] In one embodiment of the present invention, while stacking OS transistors, wiring used as bit lines is arranged in a direction perpendicular to the surface of the substrate on which layer 420 is disposed. Furthermore, transistors 437 and capacitors 438 included in the memory cell 432 are arranged in a direction perpendicular to the surface of the substrate on which layer 420 is disposed. By arranging each element and each wiring in a direction perpendicular to the substrate surface, the wiring length between element layers can be shortened, and the element density per unit area can be increased. Thus, a memory device with excellent storage capacity and reduced power consumption can be realized.

[0487] [Structure example of memory cell 432 and sense amplifier 446] Figure 24A and Figure 24B This refers to the circuit diagram corresponding to the aforementioned storage unit 432 and the corresponding circuit block diagram. For example... Figure 24A and Figure 24B As shown, storage unit 432 is sometimes represented as a block in accompanying drawings, etc. Furthermore, in... Figure 24A and Figure 24B The same representation can be used when the wiring BL shown is replaced with wiring BLB.

[0488] also, Figure 24C and Figure 24D This is a circuit diagram corresponding to the aforementioned readout amplifier 446 and a corresponding circuit block diagram. The readout amplifier 446 shows a switching circuit 482, a pre-charge circuit 483, a pre-charge circuit 484, and an amplification circuit 485. In addition to wiring BL and BLB, wiring SA_OUT and SA_OUTB, which output the readout signal, are also shown.

[0489] like Figure 24C As shown, the switching circuit 482 includes, for example, n-channel transistors 482_1 and 482_2. Transistors 482_1 and 482_2 switch the conduction state of wiring pairs SA_OUT and SA_OUTB, as well as wiring pairs BL and BLB, according to the signal CSEL.

[0490] like Figure 24C As shown, the pre-charge circuit 483 is composed of n-channel transistors 483_1 to 483_3. The pre-charge circuit 483 is used to pre-charge wiring BL and wiring BLB to an intermediate potential VPRE equivalent to potential VDD / 2 according to the signal EQ.

[0491] like Figure 24CAs shown, the pre-charge circuit 484 is composed of p-channel transistors 484_1 to 484_3. The pre-charge circuit 484 is used to pre-charge wiring BL and wiring BLB to an intermediate potential VPRE equivalent to potential VDD / 2 according to the signal EQB.

[0492] like Figure 24C As shown, the amplifier circuit 485 consists of p-channel transistors 485_1 and 485_2 and n-channel transistors 485_3 and 485_4 connected to the wiring SAP or wiring SAN. The wiring SAP or wiring SAN is a wiring that supplies VDD or VSS. Transistors 485_1 to 485_4 are transistors that form the inverter loop.

[0493] also, Figure 24D It corresponds to Figure 24C The circuit block diagram of the readout amplifier 446 is described in the example. Figure 24D As shown, the readout amplifier 446 is sometimes represented as a block in the accompanying drawings, etc.

[0494] Figure 25 yes Figure 22 The circuit diagram of storage device 480. Figure 25 Use Figures 24A to 24D The circuit blocks described in the text.

[0495] like Figure 25 As shown, layer 470, having element layer 430[m], includes storage cells 432. As an example, Figure 25 The storage unit 432 shown is connected to a pair of wirings BL[1] and BLB[1] or BL[2] and BLB[2]. The storage unit 432 connected to the wiring BL is a storage unit for writing or reading data.

[0496] Wiring BL[1] and wiring BLB[1] are connected to the readout amplifier 446[1], and wiring BL[2] and wiring BLB[2] are connected to the readout amplifier 446[2]. The readout amplifier 446[1] and readout amplifier 446[2] can be configured according to... Figure 24C The data is read from the various signals described in the text.

[0497] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0498] (Implementation Method 5) In this embodiment, an example of the structure of a display device using a transistor according to one aspect of the present invention will be described.

[0499] The transistor of one aspect of the present invention can be formed into an extremely miniaturized form, so a display device using the transistor of one aspect of the present invention can be an extremely high-definition display device. For example, the display device of one aspect of the present invention can be used in the display section of information terminal devices (wearable devices) such as watch-type and bracelet-type devices, and in the display section of VR devices such as head-mounted displays and AR devices such as glasses-type devices (HMDs).

[0500] [Display Module] Figure 26A A perspective view of display module 280 is shown. Display module 280 includes display device 200A and FPC 290. Note that the display device included in display module 280 is not limited to display device 200A, but may also be display device 200B or display device 200C, which will be described later.

[0501] The display module 280 includes a substrate 291 and a substrate 292. The display module 280 includes a display section 281. The display section 281 is an area for displaying images.

[0502] Figure 26B A perspective view of one side of the substrate 291 is shown. A circuit section 282, a pixel circuit section 283 on the circuit section 282, and a pixel section 284 on the pixel circuit section 283 are stacked on the substrate 291. Furthermore, a terminal section 285 for connecting to the FPC 290 is provided on a portion of the substrate 291 that does not overlap with the pixel section 284. The terminal section 285 is electrically connected to the circuit section 282 via a wiring section 286 composed of multiple wirings.

[0503] The pixel unit 284 includes a plurality of pixels 284a arranged periodically. Figure 26B The right side shows an enlarged view of pixel 284a. Pixel 284a includes a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0504] The pixel circuit section 283 includes a plurality of pixel circuits 283a arranged periodically. One pixel circuit 283a controls the emission of light from the three light-emitting elements included in one pixel 284a. A pixel circuit 283a may also include three circuits controlling the emission of light from one light-emitting element. For example, the pixel circuit 283a may have a structure with at least one selection transistor, one current control transistor (driving transistor), and a capacitor for each light-emitting element. In this case, the gate of the selection transistor is input with a gate signal, and the source is input with a source signal. Thus, an active matrix display panel can be realized.

[0505] The circuit section 282 includes circuitry for driving each pixel circuit 283a of the pixel circuit section 283. For example, it preferably includes one or both of a gate line driving circuit and a source line driving circuit. Furthermore, it may include at least one of an arithmetic circuit, a storage circuit, and a power supply circuit. Additionally, transistors disposed in the circuit section 282 may also constitute part of the pixel circuit 283a. That is, the pixel circuit 283a may be constituted by transistors included in the pixel circuit section 283 and transistors included in the circuit section 282.

[0506] The FPC290 is used for wiring to supply video signals or power potentials to the circuit section 282 from the outside. Additionally, ICs can be mounted on the FPC290.

[0507] The display module 280 can have a structure in which one or both of the pixel circuit section 283 and circuit section 282 are stacked on the lower side of the pixel section 284, so that the display section 281 can have an extremely high aperture ratio (effective display area ratio). For example, the aperture ratio of the display section 281 can be 40% or more and less than 100%, preferably 50% or more and less than 95%, more preferably 60% or more and less than 95%. In addition, the pixels 284a can be arranged in an extremely high density, thereby enabling the display section 281 to have extremely high resolution. For example, in the display section 281, it is preferable to arrange the pixels 284a with a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more and less than 20000 ppi or less or less than 30000 ppi.

[0508] This display module 280 is extremely clear, making it suitable for use in VR devices such as head-mounted displays or AR devices such as glasses. For example, because the display module 280 has a display section 281 with extremely high clarity, even when the display section of the display module 280 is viewed through a lens and magnified, no pixels are visible, thus achieving a highly immersive display. Furthermore, the display module 280 is not limited to this; it can also be suitable for electronic devices with smaller display sections. For example, it is suitable for display sections in wearable electronic devices such as watch-type devices.

[0509] [Display Device 200A] Figure 27 The display device 200A shown includes a substrate 331, a light-emitting element 110R, a light-emitting element 110G, a light-emitting element 110B, a capacitor 240, and a transistor 320.

[0510] Substrate 331 is equivalent to Figure 26A Substrate 291 in the middle.

[0511] Transistor 320 is a vertical-channel transistor that uses oxide semiconductor in the semiconductor layer forming the channel. Transistor 320 includes semiconductor layer 321, insulating layer 323, conductive layer 324, conductive layer 325, and conductive layer 326, etc.

[0512] Transistor 320 can use the various transistors shown in Embodiment 1.

[0513] An insulating layer 332 is disposed on the substrate 331. The insulating layer 332 serves as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from escaping from the semiconductor layer 321 towards the insulating layer 332. As the insulating layer 332, for example, a film that is less susceptible to hydrogen or oxygen diffusion than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0514] A conductive layer 327 is disposed on an insulating layer 332, an insulating layer 329 is disposed on the conductive layer 327, and a conductive layer 325 is disposed on both the insulating layer 329 and the conductive layer 327. Furthermore, an insulating layer 334 is disposed on the conductive layer 325, and a conductive layer 326 is disposed on the insulating layer 334. An opening extending to the insulating layer 329 is provided in both the insulating layer 334 and the conductive layer 325, and a semiconductor layer 321 and an insulating layer 323 are disposed within this opening. An insulating layer 263 is disposed on the insulating layer 323, and a conductive layer 327 is disposed within an opening in the insulating layer 263. Furthermore, a conductive layer 328 is disposed on the insulating layer 263 that contacts the top surface of the conductive layer 327. Additionally, an insulating layer 264 is disposed to cover the conductive layer 328.

[0515] Insulating layer 264 is used as an interlayer insulating layer. A barrier layer may also be provided between insulating layer 264 and insulating layer 254 to prevent impurities such as water or hydrogen in insulating layer 264 from diffusing into transistor 320. As a barrier layer, the same insulating film as insulating layer 332 can be used.

[0516] A plug 274, electrically connected to one of the conductive layers 326, is embedded in insulating layers 264 and 263. Preferably, the plug 274 includes a conductive layer 274a covering a portion of the side of the opening in the insulating layer 264 and the top surface of the conductive layer 326, and a conductive layer 274b in contact with the top surface of the conductive layer 274a. In this case, a conductive material that does not readily diffuse with hydrogen and oxygen is preferably used as the conductive layer 274a.

[0517] In addition, a capacitor 240 is disposed on the insulating layer 264. The capacitor 240 includes a conductive layer 241, a conductive layer 245, and an insulating layer 243 located therebetween. The conductive layer 241 serves as one electrode of the capacitor 240, the conductive layer 245 serves as the other electrode of the capacitor 240, and the insulating layer 243 serves as the dielectric of the capacitor 240.

[0518] A conductive layer 241 is disposed on an insulating layer 264 and embedded within an insulating layer 254. The conductive layer 241 is electrically connected to the conductive layer 326 of the transistor 320 via a connector 274. An insulating layer 243 is disposed covering the conductive layer 241. A conductive layer 245 is disposed in the region where it overlaps with the conductive layer 241, separated by the insulating layer 243.

[0519] The capacitor 240 is provided with an insulating layer 255a, an insulating layer 255b is provided on the insulating layer 255a, and an insulating layer 255c is provided on the insulating layer 255b.

[0520] Inorganic insulating films can be appropriately used for insulating layers 255a, 255b, and 255c. For example, it is preferable to use silicon oxide films as insulating layers 255a and 255c, and silicon nitride films as insulating layer 255b. Thus, insulating layer 255b can be used as an etching protective film. Although an example is shown in this embodiment where a portion of insulating layer 255c is etched to form a recess, it is also possible not to provide a recess in insulating layer 255c.

[0521] Light-emitting elements 110R, 110G and 110B are provided on the insulating layer 255c.

[0522] Light-emitting element 110R includes a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. Light-emitting element 110G includes a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. Light-emitting element 110B includes a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are jointly disposed in light-emitting elements 110R, 110G, and 110B.

[0523] The organic layer 112R included in the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G included in the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B included in the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. Organic layers 112R, 112G, and 112B may each be referred to as EL layers, and at least include a layer containing a light-emitting organic compound (light-emitting layer).

[0524] The display device 200A forms light-emitting devices for each light-emitting color separately, so the chromaticity variation between low-brightness and high-brightness light emission is small. Furthermore, the organic layers 112R, 112G, and 112B are separated from each other, so crosstalk between adjacent sub-pixels can be suppressed even when using a high-definition display panel. Therefore, a high-definition display device with high display quality can be achieved.

[0525] An insulating layer 125, a resin layer 126, and a layer 128 are provided in the area between adjacent light-emitting elements.

[0526] The pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductive layer 326 of the transistor 320 via a plug 256 embedded in insulating layers 255a, 255b, and 255c, a conductive layer 241 embedded in insulating layer 254, and a plug 274. The height of the top surface of insulating layer 255c is the same as or approximately the same as the height of the top surface of plug 256. Various conductive materials can be used as the plug.

[0527] In addition, a protective layer 121 is provided on the light-emitting elements 110R, 110G and 110B. A substrate 170 is attached to the protective layer 121 by an adhesive layer 171.

[0528] No insulating layer covering the top end of the pixel electrode 111 is provided between two adjacent pixel electrodes 111. Therefore, the spacing between adjacent light-emitting elements can be very small. Thus, a high-definition or high-resolution display device can be realized.

[0529] [Display device 200B] The following describes display devices whose structures differ from the examples above. Note that parts identical to the examples above are described above, and sometimes the description is omitted.

[0530] Figure 28 The display device 200B shown illustrates an example of a planar transistor 320A, which is a semiconductor layer formed on a plane, and a vertical channel transistor 320B. Transistor 320B has the same structure as transistor 320 in the aforementioned display device 200A.

[0531] Transistor 320A includes a semiconductor layer 351, an insulating layer 353, a conductive layer 354, a pair of conductive layers 355, an insulating layer 356, and a conductive layer 357.

[0532] An insulating layer 352 is disposed on the substrate 331. The insulating layer 352 serves as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from escaping from the semiconductor layer 351 towards the insulating layer 352. As the insulating layer 352, for example, a film that is less susceptible to hydrogen or oxygen diffusion than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0533] A conductive layer 357 is disposed on the insulating layer 352, and an insulating layer 356 is disposed to cover the conductive layer 357. The conductive layer 357 is used as the first gate electrode of the transistor 320A, and a portion of the insulating layer 356 is used as a first gate insulating layer. At least the portion of the insulating layer 356 in contact with the semiconductor layer 351 is preferably made of an oxide insulating film such as silicon oxide. The top surface of the insulating layer 356 is preferably planarized.

[0534] A semiconductor layer 351 is disposed on an insulating layer 356. The semiconductor layer 351 preferably comprises a metal oxide (also known as an oxide semiconductor) film exhibiting semiconductor properties. A pair of conductive layers 355 are in contact with the semiconductor layer 351 and serve as source and drain electrodes.

[0535] Insulating layers 358 and 350 are provided on the top and side surfaces of a pair of conductive layers 355 and the side surfaces of semiconductor layer 351. Insulating layer 358 serves as a barrier layer, preventing impurities such as water or hydrogen from diffusing into semiconductor layer 351 and preventing oxygen from escaping from semiconductor layer 351. The same insulating film as the aforementioned insulating layer 352 can be used as insulating layer 358.

[0536] An opening is provided in insulating layer 358 and insulating layer 350 to reach semiconductor layer 351. An insulating layer 353 and a conductive layer 354, which are in contact with the top surface of semiconductor layer 351, are embedded inside the opening. The conductive layer 354 is used as a second gate electrode, and the insulating layer 353 is used as a second gate insulating layer.

[0537] An insulating layer 359 is provided to cover the top surfaces of conductive layer 354, insulating layer 353, and insulating layer 350, ensuring that their top surfaces are at the same or approximately the same height. The insulating layer 359 serves as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the transistor 320. The insulating layer 359 can use the same insulating film as the insulating layer 352 described above.

[0538] Transistor 320 employs a structure in which a semiconductor layer forming a channel is sandwiched between two gates. Alternatively, the transistor can be driven by connecting the two gates and supplying the same signal to both gates. Or, the threshold voltage of the transistor can be controlled by supplying a potential to one of the two gates to control the threshold voltage and a potential to the other to drive it.

[0539] [Display Device 200C] Figure 29 The display device 200C shown has a stacked structure of transistor 310 with a channel formed on a semiconductor substrate and transistor 320 with a vertical channel.

[0540] Transistor 310 is a transistor having a channel formation region in substrate 301. Substrate 301 can be, for example, a semiconductor substrate such as a single-crystal silicon substrate. Transistor 310 includes a portion of substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. Conductive layer 311 serves as the gate electrode. Insulating layer 313 is located between substrate 301 and conductive layer 311 and serves as the gate insulating layer. Low-resistance region 312 is a region in substrate 301 doped with impurities and serves as one of the source and drain electrodes. Insulating layer 314 covers the sides of conductive layer 311.

[0541] In addition, a component separation layer 315 is provided between two adjacent transistors 310 in a manner embedded in the substrate 301.

[0542] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0543] (Implementation Method 6) In this embodiment, an example of the structure of a display device that can be used in a display device manufactured using a transistor according to one aspect of the present invention will be described. The display device shown below can be used in the pixel section 284, etc., of Embodiment 4 described above.

[0544] In one aspect of the present invention, the EL layer is fabricated into a fine pattern using photolithography without using a shadow mask such as a fine metal mask (FMM). Therefore, a display device with high resolution and high aperture ratio, which is currently difficult to achieve, can be realized. Furthermore, since the EL layer can be fabricated separately, a display device with very vivid and high contrast can be realized. Alternatively, for example, both a metal mask and photolithography can be used to fabricate the EL layer into a fine pattern.

[0545] Furthermore, part or all of the EL layer can be physically separated. This suppresses leakage current between light-emitting elements via a layer shared by adjacent light-emitting elements (also known as a common layer). Therefore, crosstalk caused by unintentional light emission can be suppressed, enabling display devices with very high contrast. In particular, display devices with high current efficiency at low brightness can be achieved.

[0546] One aspect of the present invention can also realize a display device that combines a white light-emitting element and a color filter. In this case, light-emitting elements with the same structure can be used as individual light-emitting elements in pixels (sub-pixels) that emit light of different colors, so all layers can be common layers. Furthermore, some or all of each EL layer can be cut using photolithography. As a result, leakage current through the common layer can be suppressed, and a display device with high contrast can be realized. In particular, in a device having a series structure of multiple light-emitting layers stacked with a highly conductive intermediate layer, leakage current through the intermediate layer can be effectively prevented, so a display device with high brightness, high definition, and high contrast can be realized.

[0547] When processing the EL layer using photolithography, degradation can sometimes occur due to partial exposure of the light-emitting layer. Therefore, it is preferable to provide an insulating layer that at least covers the sides of the island-shaped light-emitting layer. This insulating layer may also cover a portion of the top surface of the island-shaped EL layer. The insulating layer is preferably made of a material that blocks water and oxygen. For example, an inorganic insulating film that does not readily allow water or oxygen to diffuse can be used. This suppresses degradation of the EL layer and enables a highly reliable display device.

[0548] Furthermore, there is a region (recess) of the EL layer between two adjacent light-emitting elements where no light-emitting elements are disposed. When a common electrode or a common electrode and a common layer are formed to cover this recess, the common electrode sometimes breaks off due to a step at the end of the EL layer (also known as a break), resulting in the common electrode on the EL layer being insulated. Therefore, it is preferable to use a structure that fills the localized steps between two adjacent light-emitting elements with a resin layer serving as a planarization film (also known as LFP: Local Filling Planarization). This resin layer serves as a planarization film. This suppresses the breakage of the common layer or common electrode, enabling a highly reliable display device.

[0549] Hereinafter, a more specific structural example of a display device according to one aspect of the present invention will be described with reference to the accompanying drawings.

[0550] [Structure Example 1] Figure 30A This diagram shows a top view of a display device 100 according to one embodiment of the present invention. The display device 100 includes a plurality of red light-emitting elements 110R, a plurality of green light-emitting elements 110G, and a plurality of blue light-emitting elements 110B on a substrate 101. Figure 30A To facilitate the differentiation of each light-emitting element, the symbols R, G, and B are attached to the light-emitting area of ​​each element.

[0551] The light-emitting elements 110R, 110G and 110B are all arranged in a matrix. Figure 30AA so-called stripe arrangement in which light-emitting elements of the same color are arranged in one direction is shown. Note that the arrangement method of the light-emitting elements is not limited to this, and other arrangement methods such as S stripe arrangement, Delta arrangement, Bayer arrangement, zigzag arrangement, etc. can also be used, and Pentile arrangement, Diamond arrangement, etc. can also be used.

[0552] As the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, for example, OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode) is preferably used. As the light-emitting substance contained in the EL element, for example, substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), and substances that exhibit thermally activated delayed fluorescence (Thermally activated delayed fluorescence: TADF materials) can be cited. As the light-emitting substance contained in the EL element, in addition to organic compounds, inorganic compounds (such as quantum dot materials) can also be used.

[0553] In addition, Figure 30A A connection electrode 111C electrically connected to the common electrode 113 is shown. The connection electrode 111C is supplied with the potential (for example, anode potential or cathode potential) supplied to the common electrode 113. The connection electrode 111C is provided outside the display area where the light-emitting elements 110R, etc. are arranged.

[0554] The connection electrode 111C can be provided along the outer periphery of the display area. For example, it can be provided along one side of the outer periphery of the display area, or it can straddle two or more sides of the outer periphery of the display area. That is, when the top surface shape of the display area is rectangular, the top surface shape of the connection electrode 111C can be strip-shaped (rectangular), L-shaped, "冂"-shaped (bracket-shaped), or quadrilateral, etc.

[0555] Figure 30B 、 Figure 30C are respectively cross-sectional schematic views corresponding to Figure 30A the dotted lines A1 - A2 and A3 - A4 in Figure 30B A cross-sectional schematic view of the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B is shown, Figure 30C A cross-sectional schematic view of the connection portion 140 where the connection electrode 111C is connected to the common electrode 113 is shown.

[0556] Light-emitting element 110R includes a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. Light-emitting element 110G includes a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. Light-emitting element 110B includes a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are shared in light-emitting elements 110R, 110G, and 110B.

[0557] The organic layer 112R included in the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G included in the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B included in the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. Organic layers 112R, 112G, and 112B may each be referred to as EL layers and include at least a layer containing a light-emitting organic compound (light-emitting layer).

[0558] Hereinafter, when describing the common elements among light-emitting elements 110R, 110G, and 110B, they will sometimes be referred to as light-emitting element 110. Similarly, when describing the common elements among components such as organic layers 112R, 112G, and 112B, which are distinguished by letters, symbols with omitted letters will sometimes be used.

[0559] The organic layer 112 and the common layer 114 may each independently include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the following structure may be adopted: the organic layer 112 has a stacked structure in which a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer are stacked from the pixel electrode 111 side, and the common layer 114 includes an electron injection layer.

[0560] Pixel electrodes 111R, 111G, and 111B are all disposed in each light-emitting element. Furthermore, a common electrode 113 and a common layer 114 are provided as a single layer shared by all light-emitting elements. A conductive film that is transparent to visible light is used as one of the pixel electrodes and the common electrode 113, and a reflective conductive film is used as the other. By making each pixel electrode transparent and the common electrode 113 reflective, a bottom-emitting display device can be realized; conversely, by making each pixel electrode reflective and the common electrode 113 transparent, a top-emitting display device can be realized. Furthermore, by making both the pixel electrode and the common electrode 113 transparent, a double-sided emitting display device can also be realized.

[0561] A protective layer 121 is provided on the common electrode 113 to cover the light-emitting elements 110R, 110G, and 110B. The protective layer 121 has the function of preventing water and other impurities from diffusing from above to each light-emitting element.

[0562] The end of the pixel electrode 111 preferably has a tapered shape. When the end of the pixel electrode 111 has a tapered shape, the organic layer 112 disposed along the end of the pixel electrode 111 can also have a tapered shape. By making the end of the pixel electrode 111 tapered, the coverage of the organic layer 112 disposed across the end of the pixel electrode 111 can be improved. Furthermore, by making the side of the pixel electrode 111 tapered, foreign matter (e.g., dust or particles) from the manufacturing process can be easily removed by washing or other processes, which is therefore preferred.

[0563] For example, it is preferable to have a region where the angle (also called the cone angle) formed by the inclined side and the substrate surface is less than 90°.

[0564] The organic layer 112 is processed into an island shape using photolithography. Therefore, the organic layer 112 has a shape at its ends where the angle between the top surface and the side surface is close to 90 degrees. On the other hand, the thickness of organic films formed using FMM (high-precision metal mask) tends to decrease closer to the ends. For example, the top surface in the range of 1 μm to 10 μm from the ends is formed into a slope, making it difficult to distinguish between the top surface and the side surface.

[0565] An insulating layer 125, a resin layer 126, and a layer 128 are disposed between two adjacent light-emitting elements.

[0566] Between two adjacent light-emitting elements, the sides of each organic layer 112 are separated by a resin layer 126. The resin layer 126 is disposed between two adjacent light-emitting elements and fills the ends of each organic layer 112 and the area between the two organic layers 112. The top surface of the resin layer 126 has a smooth convex shape, and a common layer 114 and a common electrode 113 are disposed to cover the top surface of the resin layer 126.

[0567] The resin layer 126 serves as a planarization film to fill the step between two adjacent light-emitting elements. By providing the resin layer 126, the phenomenon of the common electrode 113 being interrupted (also known as disconnection) due to the step at the end of the organic layer 112 can be prevented, thus insulating the common electrode on the organic layer 112. The resin layer 126 can also be referred to as an LFP (Local Filling Planarization) layer.

[0568] As resin layer 126, an insulating layer containing organic materials can be suitable. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of the above resins can be used as resin layer 126. Furthermore, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used as resin layer 126.

[0569] Furthermore, a photosensitive resin can be used as the resin layer 126. A photoresist can also be used as the photosensitive resin. The photosensitive resin can be either a positive or negative material.

[0570] The resin layer 126 may also contain a material that absorbs visible light. For example, the resin layer 126 itself may be composed of a material that absorbs visible light, and the resin layer 126 may also contain a pigment that absorbs visible light. As the resin layer 126, for example, a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light; or a resin that contains carbon black as a pigment and is used as a black matrix; etc.

[0571] The insulating layer 125 contacts the side surface of the organic layer 112. Furthermore, the insulating layer 125 covers the upper end of the organic layer 112. Additionally, a portion of the insulating layer 125 contacts the top surface of the substrate 101.

[0572] An insulating layer 125 is located between the resin layer 126 and the organic layer 112, and serves as a protective film to prevent the resin layer 126 from contacting the organic layer 112. When the organic layer 112 comes into contact with the resin layer 126, the organic layer 112 may be dissolved due to organic solvents or the like used in forming the resin layer 126. Therefore, by providing an insulating layer 125 between the organic layer 112 and the resin layer 126, the sides of the organic layer 112 can be protected.

[0573] The insulating layer 125 can be an insulating layer containing inorganic materials. For example, inorganic insulating films such as oxide insulating films, nitride insulating films, oxynitride insulating films, and oxynitride insulating films can be used as the insulating layer 125. The insulating layer 125 can be a single-layer structure or a multilayer structure. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, indium gallium zinc oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, and tantalum oxide films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. In particular, by using an aluminum oxide film, hafnium oxide film, or silicon oxide film, or an inorganic insulating film formed by the ALD method, an insulating layer 125 with fewer pinholes and excellent protection of the EL layer can be formed.

[0574] Note that in this specification, etc., oxynitrides refer to materials in which the oxygen content is greater than the nitrogen content in their composition, while oxynitrides refer to materials in which the nitrogen content is greater than the oxygen content in their composition. For example, when described as silicon oxynitride, it refers to materials in which the oxygen content is greater than the nitrogen content in their composition, while when described as silicon oxynitride, it refers to materials in which the nitrogen content is greater than the oxygen content in their composition.

[0575] The insulating layer 125 can be formed using sputtering, CVD, PLD, ALD, or other methods. The insulating layer 125 is preferably formed using the ALD method, which provides good coverage.

[0576] Alternatively, a reflective film (e.g., a metal film selected from one or more of silver, palladium, copper, titanium, and aluminum) can be provided between the insulating layer 125 and the resin layer 126 to reflect the light emitted by the light-emitting layer. This can further improve the light extraction efficiency.

[0577] Layer 128 is a residual portion of a protective layer (also called a mask layer or sacrificial layer) used to protect the organic layer 112 during etching. Layer 128 can use a material that can be used for the insulating layer 125 described above. In particular, it is preferred that the same material be used for both layer 128 and the insulating layer 125, so that processing equipment can be used together.

[0578] In particular, since the aluminum oxide film, hafnium oxide film and other oxide metal films or silicon oxide film formed by the ALD method are films with fewer pinholes, they have excellent protection function for the EL layer and are therefore suitable for use in insulating layer 125 and layer 128.

[0579] The protective layer 121 may, for example, have a single-layer structure or a multilayer structure comprising at least an inorganic insulating film. Examples of inorganic insulating films include oxide films or nitride films such as silicon oxide films, silicon oxynitride films, silicon oxynitride films, silicon nitride films, aluminum oxide films, aluminum oxynitride films, and hafnium oxide films. Alternatively, semiconductor materials or conductive materials such as indium gallium oxide, indium zinc oxide, indium tin oxide, and indium gallium zinc oxide may also be used as the protective layer 121.

[0580] The protective layer 121 can also be a laminate of an inorganic insulating film and an organic insulating film. For example, it is preferable to sandwich an organic insulating film between a pair of inorganic insulating films. Furthermore, the organic insulating film is preferably used as a planarization film. Therefore, the top surface of the organic insulating film can be flattened, thus improving the coverage of the inorganic insulating film thereon, thereby improving the barrier properties. In addition, the flattened top surface of the protective layer 121 is preferred because it reduces the influence of the uneven shape of the underlying structure when structures (e.g., color filters, electrodes of touch sensors, or lens arrays, etc.) are placed above the protective layer 121.

[0581] Figure 30C A connection portion 140 is shown, which electrically connects the connecting electrode 111C to the common electrode 113. In the connection portion 140, an opening is provided in the insulating layer 125 and the resin layer 126 on the connecting electrode 111C. The connecting electrode 111C is electrically connected to the common electrode 113 through this opening.

[0582] Notice, Figure 30C The diagram shows a connection portion 140 where the connecting electrode 111C and the common electrode 113 are electrically connected. However, the common electrode 113 can also be disposed on the connecting electrode 111C with a common layer 114 in between. In particular, when a carrier injection layer is used as the common layer 114, the resistivity of the material used for the common layer 114 is sufficiently low and its thickness is also very thin, so in many cases, it is not a problem for the common layer 114 to be located in the connection portion 140. Therefore, the common electrode 113 and the common layer 114 can be formed using the same masking mask, thus reducing manufacturing costs.

[0583] [Structure Example 2] The following describes a display device whose structure differs from that of Structural Example 1 described above. Note that parts that are the same as those in Structural Example 1 are sometimes omitted from the description with reference to Structural Example 1.

[0584] Figure 31A This is a cross-sectional schematic diagram of display device 100a. The main differences between display device 100a and display device 100 are: the structure of the light-emitting element; and the fact that the former includes a coloring layer.

[0585] Display device 100a includes a light-emitting element 110W that emits white light. The light-emitting element 110W includes a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113. The organic layer 112W emits white light. For example, the organic layer 112W may contain two or more light-emitting materials whose emitted colors are complementary. For example, the organic layer 112W may contain a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. Furthermore, it may also contain a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.

[0586] Between two adjacent light-emitting elements 110W, each organic layer 112W is separated. This suppresses leakage current flowing through the organic layer 112W between adjacent light-emitting elements 110W, and thus suppresses crosstalk caused by this leakage current. Therefore, a display device with high contrast and color reproduction can be achieved.

[0587] An insulating layer 122 serving as a planarization film is provided on the protective layer 121, and a coloring layer 116R, a coloring layer 116G, and a coloring layer 116B are provided on the insulating layer 122.

[0588] As the insulating layer 122, an organic resin film or an inorganic insulating film with a planarized top surface can be used. Since the insulating layer 122 is the surface on which the coloring layers 116R, 116G, and 116B are formed, a planar top surface of the insulating layer 122 can ensure uniform thickness of the coloring layers 116R, etc., thereby improving color purity. Note that when the thickness of the coloring layers 116R, etc., is uneven, the light absorption varies depending on the region within the coloring layer 116R, which may lead to a decrease in color purity.

[0589] [Structure Example 3] Figure 31B This is a cross-sectional schematic diagram of the display device 100b.

[0590] Light-emitting element 110R includes a pixel electrode 111, a conductive layer 115R, an organic layer 112W, and a common electrode 113. Light-emitting element 110G includes a pixel electrode 111, a conductive layer 115G, an organic layer 112W, and a common electrode 113. Light-emitting element 110B includes a pixel electrode 111, a conductive layer 115B, an organic layer 112W, and a common electrode 113. Conductive layers 115R, 115G, and 115B are all transparent and used as optical adjustment layers.

[0591] By using a film that reflects visible light as the pixel electrode 111 and a film that is both reflective and transmissive to visible light as the common electrode 113, a microcavity resonator (microcavity) structure can be realized. At this point, by adjusting the thicknesses of the conductive layers 115R, 115G, and 115B in a manner that achieves the most suitable optical path length, even using an organic layer 112 that emits white light, enhanced light can be obtained by extracting light of different wavelengths from the light-emitting elements 110R, 110G, and 110B respectively.

[0592] Furthermore, by setting color layers 116R, 116G, and 116B on the optical paths of light-emitting elements 110R, 110G, and 110B respectively, light with high color purity can be extracted.

[0593] In addition, an insulating layer 123 is provided covering the ends of the pixel electrode 111 and the conductive layer 115. The ends of the insulating layer 123 preferably have a tapered shape. By providing the insulating layer 123, the coverage of the organic layer 112W, the common electrode 113, and the protective layer 121 formed thereon can be improved.

[0594] The organic layer 112W and the common electrode 113 are respectively disposed as continuous films in each light-emitting element. By adopting this structure, the manufacturing process of the display device can be greatly simplified, so it is preferred.

[0595] Here, the end of the pixel electrode 111 preferably has an almost vertical shape. This allows for a steeply sloping portion to be formed on the surface of the insulating layer 123, while a thin portion can be formed on a part of the organic layer 112W covering that portion, or a part of the organic layer 112W can be separated. This allows for the suppression of leakage current generated between adjacent light-emitting elements through the organic layer 112W without processing the organic layer 112W using photolithography or similar methods.

[0596] The above illustrates an example of the structure of a display device.

[0597] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0598] (Implementation Method 7) In this embodiment, Figures 32 to 34 are used to illustrate an electronic device according to one aspect of the present invention.

[0599] The electronic device of this embodiment includes a display panel (display device) using a transistor according to one aspect of the present invention in its display section. The display device according to one aspect of the present invention easily achieves high definition and high resolution, and furthermore, can achieve high display quality. Therefore, it can be used in the display section of various electronic devices.

[0600] As electronic devices, in addition to large-screen electronic devices such as television sets, desktop or laptop personal computers, monitors for computers, digital signage, and large game machines such as pinball machines, other examples include digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices.

[0601] In particular, because the display panel of one aspect of the present invention can improve clarity, it can be suitably used in electronic devices that include a relatively small display section. Examples of such electronic devices include watch-type and bracelet-type information terminal devices (wearable devices), wearable devices that can be worn on the head, VR devices such as head-mounted displays, AR devices such as glasses, and MR devices.

[0602] The display panel of one embodiment of the present invention preferably has an extremely high resolution, such as HD (1280×720 pixels), FHD (1920×1080 pixels), WQHD (2560×1440 pixels), WQXGA (2560×1600 pixels), 4K (3840×2160 pixels), 8K (7680×4320 pixels), etc. In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (clarity) of the display panel of one embodiment of the present invention is preferably 100 ppi or higher, preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display panel with one or both of the above-described high resolution and high clarity, the sense of realism and depth can be further improved. Furthermore, there are no particular limitations on the screen ratio (aspect ratio) of the display panel according to one aspect of the present invention. For example, the display panel can accommodate various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0603] The electronic device in this embodiment may also include a sensor (which has the function of sensing, detecting or measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor or infrared radiation).

[0604] The electronic device of this embodiment can have various functions. For example, it can have the following functions: displaying various information (static images, dynamic images, text images, etc.) on the display unit; touch panel function; displaying calendar, date, or time, etc.; executing various software (programs); wireless communication function; reading programs or data stored in the storage medium; etc.

[0605] use Figures 32A to 32D This section describes an example of a wearable device that can be worn on the head. These wearable devices have the capability to display either AR (Augmented Reality) content or VR (Virtual Reality) content, or both. Furthermore, these wearable devices may also have the capability to display SR (Simultaneous Reality) or MR (Mortal Reality) content in addition to AR and VR. When an electronic device has the capability to display content of at least one of AR, VR, SR, and MR, the user's sense of immersion can be enhanced.

[0606] Figure 32A The electronic device 700A shown and Figure 32B The electronic devices 700B shown include a pair of display panels 751, a pair of frames 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical components 753, a frame 757, and a pair of nose pads 758.

[0607] The display panel 751 can be an embodiment of the display panel of the present invention. Therefore, an electronic device capable of displaying with extremely high clarity can be realized.

[0608] Both electronic devices 700A and 700B can project images displayed on the display panel 751 onto the display area 756 in the optical component 753. Because the optical component 753 is transparent, the user can see the image displayed on the display area by superimposing it with the image seen through the optical component 753. Therefore, both electronic devices 700A and 700B are capable of AR display.

[0609] In electronic devices 700A and 700B, a camera capable of capturing images of the front can also be provided as an imaging unit. Furthermore, by providing accelerometer sensors such as gyroscopes in electronic devices 700A and 700B, the orientation of the user's head can be detected, and an image corresponding to that orientation can be displayed on the display area 756.

[0610] The communications section includes a wireless communication device through which image signals can be supplied. Furthermore, in addition to or in addition to the wireless communication device, a connector capable of connecting cables supplying image signals and power potential may also be included.

[0611] In addition, electronic devices 700A and 700B are equipped with batteries that can be charged wirelessly or via wired means, or both.

[0612] The frame 721 may also be equipped with a touch sensor module. The touch sensor module has the function of detecting whether the outer surface of the frame 721 is touched. Through the touch sensor module, various processes can be performed based on user tap or swipe operations. For example, a tap operation can temporarily pause or restart a moving image, while a swipe operation can fast forward or rewind. Furthermore, by providing a touch sensor module in each of the two frames 721, the operating range can be expanded.

[0613] Various touch sensors can be used as touch sensor modules. For example, capacitive, resistive, infrared, electromagnetic induction, surface acoustic wave, and optical sensors can be employed. In particular, capacitive or optical sensors are preferred for use in touch sensor modules.

[0614] When using optical touch sensors, photoelectric conversion devices (also known as photoelectric conversion elements) can be used as light-receiving devices (also known as light-receiving elements). One or both of inorganic semiconductors and organic semiconductors can be used in the active layer of the photoelectric conversion device.

[0615] Figure 32C The electronic device 800A shown is Figure 32D The electronic devices 800B shown include a pair of display units 820, a frame 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0616] The display unit 820 can utilize a display panel according to one aspect of the present invention. Therefore, an electronic device capable of displaying extremely high clarity can be realized. This allows the user to experience a highly immersive experience.

[0617] The display unit 820 is located inside the housing 821 in a position visible through the lens 832. Furthermore, by displaying different images on each of the pair of display units 820, three-dimensional display utilizing parallax can be achieved.

[0618] Both electronic devices 800A and 800B can be referred to as VR electronic devices. Users who have installed electronic devices 800A or 800B can see the image displayed on the display unit 820 through the lens 832.

[0619] Electronic devices 800A and 800B preferably have a mechanism in which the left and right positions of the lens 832 and the display unit 820 can be adjusted so that the lens 832 and the display unit 820 are in the most suitable position according to the position of the user's eyes. Furthermore, it is preferable to have a mechanism in which the focus is adjusted by changing the distance between the lens 832 and the display unit 820.

[0620] The user can use the mounting unit 823 to mount the electronic device 800A or electronic device 800B onto the head. Additionally, in Figure 32C Examples of mounting parts 823 with a shape similar to the temples of eyeglasses (also called temple threads, etc.) are shown, but the design is not limited to this. As long as the user can attach it, the mounting part 823 can have, for example, a helmet-shaped or strap-shaped shape.

[0621] The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras can be set to support various viewing angles such as telephoto and wide-angle.

[0622] Note that the example shown here includes an imaging unit 825, which can be a ranging sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object. In other words, the imaging unit 825 is one type of detection unit. For example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used as the detection unit. By using images acquired by a camera and images acquired by a distance image sensor, more information can be obtained, enabling more precise attitude control.

[0623] The electronic device 800A may also include a vibration mechanism for use as bone conduction headphones. For example, a structure in which the vibration mechanism is included in one or more of the display unit 820, the frame 821, and the mounting unit 823 can be adopted. Thus, there is no need to separately install audio equipment such as headphones, earphones, or speakers; one can enjoy images and sound simply by installing the electronic device 800A.

[0624] Electronic devices 800A and 800B may also include input terminals. Cables supplying image signals from image output devices, etc., and power for charging batteries installed in the electronic devices can be connected to the input terminals.

[0625] An electronic device according to one aspect of the present invention may also have the function of wirelessly communicating with the headset 750. The headset 750 includes a communication unit (not shown) and has wireless communication functionality. The headset 750 can receive information (e.g., voice data) from the electronic device through the wireless communication function. For example, Figure 32A The illustrated electronic device 700A has the function of transmitting information to the headset 750 via wireless communication. Furthermore, for example... Figure 32C The electronic device 800A shown has the function of sending information to the headset 750 via wireless communication.

[0626] In addition, electronic devices may also include an earphone unit. Figure 32B The illustrated electronic device 700B includes an earphone unit 727. For example, a structure in which the earphone unit 727 and the control unit are connected by a wire can be adopted. A portion of the wiring connecting the earphone unit 727 and the control unit can also be configured inside the housing 721 or the mounting portion 723.

[0627] same, Figure 32D The illustrated electronic device 800B includes an earphone unit 827. For example, a structure can be adopted in which the earphone unit 827 and the control unit 824 are connected by a wire. A portion of the wiring connecting the earphone unit 827 and the control unit 824 can also be disposed inside the housing 821 or the mounting portion 823. Furthermore, the earphone unit 827 and the mounting portion 823 can also include magnets. Thus, the earphone unit 827 can be magnetically secured to the mounting portion 823, making storage easy, which is preferable.

[0628] Additionally, the electronic device may include an audio output terminal capable of connecting to headphones or headsets. Furthermore, the electronic device may include one or both of an audio input terminal and an audio input mechanism. For example, a microphone or other sound-receiving device can be used as the audio input mechanism. By including an audio input mechanism, the electronic device can function as a so-called headset.

[0629] Thus, as an embodiment of the present invention, both eyeglass type (electronic device 700A and electronic device 700B, etc.) and goggle type (electronic device 800A and electronic device 800B, etc.) are preferred electronic devices.

[0630] Figure 33A The electronic device 6500 shown is a portable information terminal device that can be used as a smartphone.

[0631] Electronic device 6500 includes a frame 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509, etc. The display unit 6502 has a touch panel function. Furthermore, the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be used in the display unit 6502, the control device 6509, etc. Using a semiconductor device according to one aspect of the present invention in the control device 6509 can reduce power consumption, and is therefore preferred.

[0632] The display unit 6502 may use a display panel according to one aspect of the present invention.

[0633] Figure 33B This is a cross-sectional schematic diagram of one end of the microphone 6506, including the frame 6501.

[0634] A light-transmitting protective component 6510 is provided on one side of the display surface of the frame 6501. The space surrounded by the frame 6501 and the protective component 6510 contains a display panel 6511, an optical component 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc.

[0635] The display panel 6511, optical component 6512, and touch sensor panel 6513 are fixed to the protective component 6510 using an adhesive layer (not shown).

[0636] In the area outside the display unit 6502, a portion of the display panel 6511 is folded, and this folded portion is connected to an FPC 6515. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals disposed on a printed circuit board 6517.

[0637] The display panel 6511 can use a flexible display that employs a semiconductor device according to one aspect of the present invention. This allows for the realization of an extremely lightweight electronic device. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while minimizing the thickness of the electronic device. Additionally, by folding a portion of the display panel 6511 to provide a connection to the FPC 6515 on the back of the pixel portion, a narrow-bezel electronic device can be achieved.

[0638] Figure 33C An example of a television device is shown. In the television device 7100, a display unit 7000 is assembled in a frame 7101. Here is shown the structure in which the frame 7101 is supported by a bracket 7103.

[0639] It can be operated using the operating switches provided in the housing 7101 and the separately provided remote control 7111. Figure 33C The operation of the television device 7100 shown is illustrated. Alternatively, a touch sensor may be provided in the display unit 7000, allowing operation of the television device 7100 by touching the display unit 7000 with a finger or the like. Furthermore, a display unit for displaying information output from the remote control 7111 may be provided in the remote control 7111. Channel and volume adjustments can be made using the operation keys or touch panel provided in the remote control 7111, and the images displayed on the display unit 7000 can also be manipulated.

[0640] Furthermore, the television device 7100 includes a receiver and a modem. It can receive general television broadcasts using the receiver. Moreover, by connecting to a wired or wireless communication network via the modem, it can perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0641] Figure 33D An example of a notebook computer is shown. The notebook computer 7200 includes a chassis 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, etc. A display unit 7000 is assembled in the chassis 7211. The control device 7216 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be used in the display unit 7000, the control device 7216, etc. By using a semiconductor device according to one aspect of the present invention in the control device 7216, power consumption can be reduced, and therefore it is preferred.

[0642] Figure 33E and Figure 33F Here is an example of digital signage.

[0643] Figure 33E The digital sign 7300 shown includes a frame 7301, a display unit 7000, and a speaker 7303. It may also include LEDs, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0644] Figure 33F A digital sign 7400 is shown mounted on a cylindrical column 7401. The digital sign 7400 includes a display section 7000 disposed along the curved surface of the column 7401.

[0645] The larger the display unit (7000), the more information it can provide at once. A larger display unit (7000) is also more likely to attract attention, which can improve the effectiveness of advertising.

[0646] By using a touch panel in the display unit 7000, not only can static or dynamic images be displayed on the display unit 7000, but users can also operate it intuitively, making it preferable. Furthermore, when used to provide information such as route information or traffic information, intuitive operation enhances ease of use.

[0647] like Figure 33E and Figure 33F As shown, digital signage 7300 or digital signage 7400 preferably connects wirelessly with information terminal devices 7311 or 7411, such as smartphones carried by the user. For example, advertising information displayed on display unit 7000 can be displayed on the screen of information terminal device 7311 or information terminal device 7411. Furthermore, the display on display unit 7000 can be switched by operating information terminal device 7311 or information terminal device 7411.

[0648] Furthermore, the game can be executed on the digital signage 7300 or 7400 using the screen of information terminal device 7311 or 7411 as the operating unit (controller). This allows multiple users, not specifically designated, to participate in the game simultaneously and enjoy the experience.

[0649] exist Figures 33C to 33F In this embodiment, the display panel of one aspect of the present invention can be used in the display unit 7000.

[0650] Figures 34A to 34G The electronic device shown includes a frame 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, a sensor 9007 (which has the function of sensing, detecting or measuring the following factors: force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor or infrared radiation), a microphone 9008, etc.

[0651] Figures 34A to 34GThe electronic device shown has various functions. For example, it may have the following functions: displaying various information (still images, moving images, text images, etc.) on a display unit; a touch panel function; displaying a calendar, date, or time; controlling processing using various software (programs); wireless communication function; reading and processing programs or data stored in a storage medium; etc. Note that the functions of the electronic device are not limited to the above functions, but can have various functions. The electronic device may also include multiple display units. In addition, a camera or the like may be installed in the electronic device to give it the following functions: capturing still or moving images and storing the captured images in a storage medium (external storage medium or storage medium built into the camera); displaying the captured images on a display unit; etc.

[0652] The following is a detailed explanation. Figures 34A to 34G The electronic device shown.

[0653] Figure 34A This is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used, for example, as a smartphone. Note that a speaker 9003, a connection terminal 9006, a sensor 9007, etc., may also be included in the portable information terminal 9101. Furthermore, as a portable information terminal 9101, text or image information can be displayed on multiple surfaces. Figure 34A The image shows an example displaying three icons 9050. Alternatively, information 9051, shown as a dashed rectangle, can be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of received emails, SNS messages, or phone calls; the subject of the email or SNS message; the sender's name; the date; the time; remaining battery level; and radio wave strength. Alternatively, icons 9050 can be displayed in the same location where information 9051 is displayed.

[0654] Figure 34B This is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has the function of displaying information on three or more surfaces of the display unit 9001. Here, examples are shown where information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, when the portable information terminal 9102 is placed in a jacket pocket, the user can check the information 9053 displayed in a position seen from above the portable information terminal 9102. For example, the user can check this display without taking the portable information terminal 9102 out of their pocket, thereby determining whether to answer a phone call.

[0655] Figure 34CThis is a perspective view of a tablet terminal 9103. The tablet terminal 9103 can, for example, execute various application software such as mobile phone, email, article reading and editing, music playback, network communication, and computer games. The tablet terminal 9103 includes a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the frame 9000; operation keys 9005 serving as operating buttons on the left side of the frame 9000; and a connection terminal 9006 on the bottom surface.

[0656] Figure 34D This is a perspective view showing a watch-type portable information terminal 9200. The portable information terminal 9200 can be used, for example, as a smartwatch (registered trademark). Furthermore, the display surface of the display unit 9001 is curved, allowing display along its curved surface. Additionally, the portable information terminal 9200 can perform hands-free calls, for example, by communicating with a headset capable of wireless communication. Furthermore, by utilizing the connection terminal 9006, the portable information terminal 9200 can transmit data or charge with other information terminals. Furthermore, charging can also be performed wirelessly.

[0657] Figures 34E to 34G This is a perspective view showing the foldable portable information terminal 9201. Furthermore, Figure 34E This is a 3D view of the portable information terminal 9201 in its unfolded state. Figure 34G It is a 3D image of the folded state. Figure 34F From Figure 34E status and Figure 34G The portable information terminal 9201 is a three-dimensional representation of the state transitioning between different states. In its folded state, it is highly portable, while in its unfolded state, it offers excellent browsing capabilities due to its large, seamlessly integrated display area. The display unit 9001 included in the portable information terminal 9201 is supported by three frames 9000 connected by hinges 9055. The display unit 9001 can be bent, for example, within a radius of curvature of 0.1 mm or more and 150 mm or less.

[0658] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0659] (Implementation Method 8) In this embodiment, an application example of a semiconductor device according to one aspect of the present invention is described. For example, the semiconductor device according to one aspect of the present invention can be used in electronic components, electronic devices, mainframe computers, space equipment, and data centers (also known as Data Centers: DCs). Electronic components, electronic devices, mainframe computers, space equipment, and data centers using the semiconductor device according to one aspect of the present invention are highly effective in achieving high performance such as low power consumption.

[0660] Electronic components of a semiconductor device using one aspect of the present invention can be applied to the electronic device shown in Embodiment 5.

[0661] [Electronic Components] Figure 35A A perspective view of a substrate (circuit board 704) on which electronic components 700 are mounted is shown. Figure 35A The electronic component 700 shown includes a semiconductor device 710 within the mold 711. Figure 35A In this text, a portion of the electronic component 700 is omitted to represent its internal structure. The electronic component 700 includes a connecting pad 712 on the outside of the mold 711. The connecting pad 712 is electrically connected to an electrode pad 713, which is electrically connected to a semiconductor device 710 via a lead 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. By combining multiple of the aforementioned electronic components and electrically connecting them respectively on the printed circuit board 702, a circuit board 704 is completed.

[0662] Furthermore, the semiconductor device 710 includes a driver circuit layer 715 and a memory layer 716. The memory layer 716 has a structure with multiple memory cell arrays stacked on top of each other. The stacked structure of the driver circuit layer 715 and the memory layer 716 can be a monolithic stacked structure. In a monolithic stacked structure, the layers can be connected without through-hole electrode technologies such as TSVs (Through Silicon Vias) or bonding technologies such as Cu-Cu direct bonding. When the driver circuit layer 715 and the memory layer 716 have a monolithic stacked structure, for example, a so-called on-chip memory structure in which memory is directly formed on the processor can be realized. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0663] Furthermore, by employing an on-chip memory structure, the size of interconnect wiring can be reduced compared to techniques using through electrodes such as TSVs, thus allowing for an increase in the number of pins. Increasing the number of pins enables parallel operation, thereby improving the memory's bandwidth.

[0664] Furthermore, it is preferable to use OS transistors to form multiple memory cell arrays in memory layer 716, stacking these multiple memory cell arrays monolithically. When multiple memory cell arrays adopt a monolithic stacked structure, one or both of the memory bandwidth and memory access latency can be improved. Note that bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between accessing and starting data exchange. Additionally, when using Si transistors in memory layer 716, it is more difficult to achieve a monolithic stacked structure compared to using OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0665] Furthermore, the semiconductor device 710 may be referred to as a bare die. Note that in this specification, etc., a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) during the semiconductor chip manufacturing process, and then cutting it into small rectangular pieces. Examples of semiconductor materials that can be used for bare dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon wafer.

[0666] then, Figure 35B A perspective view of electronic component 730 is shown. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, a through-plate 731 is provided on a package substrate 732 (printed circuit board), and semiconductor devices 735 and multiple semiconductor devices 710 are provided on the through-plate 731.

[0667] Electronic component 730 illustrates an example of using semiconductor device 710 as a high-bandwidth memory (HBM). Furthermore, semiconductor device 735 can be used in integrated circuits such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), or FPGAs (Field Programmable Gate Arrays).

[0668] The packaging substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The through-hole plate 731 may be, for example, a silicon through-hole plate or a resin through-hole plate.

[0669] The through-hole board 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal spacings. The multiple wirings are composed of a single layer or multiple layers. Furthermore, the through-hole board 731 functions to electrically connect integrated circuits disposed on the through-hole board 731 to electrodes disposed on the package substrate 732. Therefore, the through-hole board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". Additionally, sometimes a through electrode is provided in the through-hole board 731, and this through electrode is used to electrically connect the integrated circuit to the package substrate 732. Furthermore, in the case of using a silicon through-hole board, a TSV can also be used as the through electrode.

[0670] In HBM, numerous wirings are required to achieve wide memory bandwidth. Therefore, the mounting board for HBM must be capable of forming fine wirings at high density. Consequently, silicon mounting boards are preferred as mounting boards for HBM.

[0671] Furthermore, in SiP and MCM applications using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged horizontally on the interposer.

[0672] On the other hand, when multiple integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSVs, space is required for the width of these terminal pitches. Therefore, when the size of the electronic component 730 is to be reduced, the width of these terminal pitches becomes a problem, and it is sometimes difficult to set the required width for multiple wirings to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. Alternatively, a composite structure combining a memory cell array utilizing TSV stacks with a monolithic stacked structure can also be used.

[0673] Alternatively, a heat sink (heat plate) may be provided overlapping with the electronic component 730. When a heat sink is provided, it is preferable that the integrated circuits provided on the insert 731 have the same height. For example, in the electronic component 730 shown in this embodiment, it is preferable that the semiconductor device 710 and the semiconductor device 735 have the same height.

[0674] In order to mount the electronic component 730 on other substrates, an electrode 733 may also be provided on the bottom of the package substrate 732. Figure 35BAn example of forming electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrode 733 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0675] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0676] [Mainframe Computer] Figure 36A A perspe...

Claims

1. A semiconductor device, comprising: transistor; First insulating layer; as well as Second insulating layer, The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first conductive layer has a portion located on the second insulating layer and includes a first opening extending into the second insulating layer. The first insulating layer has a portion located on the first conductive layer and includes a second opening that overlaps with the first opening. The second conductive layer has a portion located on the first insulating layer. The semiconductor layer has a portion that contacts the second conductive layer, a portion along the side of the first insulating layer within the second opening, a portion that contacts the side of the first conductive layer within the first opening, and a portion that contacts the top surface of the second insulating layer at the bottom of the first opening. The third insulating layer covers the semiconductor layer within the first opening and the second opening. Furthermore, the third conductive layer covers the third insulating layer within the first opening and the second opening.

2. The semiconductor device according to claim 1, further comprising: Fourth conductive layer The second insulating layer is located on the fourth conductive layer. Furthermore, the first conductive layer is in contact with the top surface of the fourth conductive layer on the outer side of the end of the second insulating layer.

3. The semiconductor device according to claim 2, The first conductive layer comprises a metal oxide. Furthermore, the fourth conductive layer comprises a metal or alloy.

4. The semiconductor device according to claim 2 or 3, The second insulating layer includes a first insulating film in contact with the fourth conductive layer and a second insulating film thereon in contact with the semiconductor layer. The first insulating film comprises one or more of silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, and hafnium oxide. Furthermore, the second insulating film comprises silicon oxide or silicon oxynitride.

5. The semiconductor device according to claim 1, further comprising: Fifth conductive layer; as well as Fourth insulating layer, The fourth insulating layer has a portion located on the third insulating layer and includes a third opening that overlaps with the first opening and extends into the third insulating layer. The fifth conductive layer has a portion located on the fourth insulating layer. Furthermore, the third conductive layer has a portion embedded in the third opening and its top surface is in contact with the fifth conductive layer.

6. The semiconductor device according to claim 1, further comprising: The fifth insulating layer, The fifth insulating layer is disposed within the second opening along the side of the first insulating layer and located between the first insulating layer and the semiconductor layer.

7. The semiconductor device according to claim 6, The first insulating layer comprises silicon oxide or silicon oxynitride. Furthermore, the fifth insulating layer comprises one or more of silicon nitride, aluminum oxide, silicon oxide, and hafnium oxide.

8. The semiconductor device according to claim 1, The semiconductor layer has a cylindrical shape within the first opening and the second opening. Furthermore, the third insulating layer has a portion at the bottom of the first opening that contacts the top surface of the second insulating layer.

9. The semiconductor device according to claim 8, The semiconductor layer is in contact with the side surface of the second conductive layer but not with the top surface of the second conductive layer.

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