Method for forming electrode and semiconductor device

Abstract

A method of forming an electrode and a transistor device is disclosed. The transistor device includes a gate trace (41) and a drain trace (43) spaced apart from each other. The gate and drain traces comprise respective first and second device electrode layers (421, 423), in which the first device electrode layer (411) protrudes in a direction away from the drain trace (43) by a first distance (p11) different from zero, and in which the second device electrode layer (422) protrudes in a direction away from the drain trace (43) by a second distance (p12) different from zero. In the first device electrode layer (421), the first device electrode layer (413) protrudes below the second device electrode layer (423) in the direction of the gate line (41) and protrudes below the second device electrode layer (421) in the direction of the drain line (43) by less than the first distance (p11), and in the drain line (43), the first device electrode layer (413) protrudes below the second device electrode layer (423) in the direction of the gate line (41) by a second distance (p31) different from zero.

Description

Technical Field

[0001] This disclosure generally relates to methods for forming conductive electrodes over a semiconductor body. Background Technology

[0002] Depending on the specific type of semiconductor device implemented in the semiconductor body, various types of electrodes can be formed above the semiconductor body. The electrodes are connected to the active device region of the semiconductor device and can provide external connections to the active device region. For example, electrodes formed above the semiconductor body of a vertical transistor device include source electrodes connected to the source region of the transistor device, gate traces and gate pads connected to the gate electrode of the transistor device, and drain traces. Summary of the Invention

[0003] One example relates to a transistor device. The transistor device includes gate traces and drain traces spaced apart from each other. Each of the gate traces and drain traces includes a corresponding first device electrode layer and a second device electrode layer. In the gate trace, the first device electrode layer protrudes a first distance, different from zero, below the second device electrode layer in a direction opposite to the drain trace, and protrudes a distance less than the first distance below the second device electrode layer in the direction of the drain trace. In the drain trace, the first device electrode layer protrudes a second distance, different from zero, below the second device electrode layer in the direction of the gate trace.

[0004] Another example relates to a method including a patterned conductive layer. The patterned conductive layer includes: forming an etch mask with an opening on top of the conductive layer, wherein the opening includes sloping sidewalls; and etching a portion of the conductive layer exposed at the bottom of the opening and a portion of the etch mask, such that the opening widens during the etching process, and forming an opening with a sloping edge surface in a first conductive layer.

[0005] Another example relates to a method including forming a conductive via. The method includes: forming a via trench; forming a first tungsten layer in a first deposition process such that the first tungsten layer lining the sidewalls and bottom of the via trench; and forming a second tungsten layer on top of the first tungsten layer in a second deposition process such that the second tungsten layer seals the via trench. Each of the first and second deposition processes uses WF6 as a precursor gas, and at least one of the first and second deposition processes additionally uses nitrogen. The nitrogen flow rate in the first deposition process is lower than that in the second deposition process. Attached Figure Description

[0006] The examples are explained below with reference to the accompanying drawings. The drawings are intended to illustrate certain principles, showing only aspects necessary for understanding these principles. The drawings are not drawn to scale. In the drawings, the same reference numerals denote similar features.

[0007] Figure 1A-1F An example of a method for forming an electrode comprising a portion of a first conductive layer and a portion of a second conductive layer is shown;

[0008] Figure 2 More details are shown in accordance with Figure 1A-1F Electrodes formed in the method;

[0009] Figures 3A-3B Each shows a top view of a transistor device based on an example;

[0010] Figure 4 A vertical cross-sectional view of a portion of the source electrode, gate trace, and drain trace of a transistor device is shown.

[0011] Figure 5 A portion of the source electrode and the gate trace are shown in more detail.

[0012] Figure 6 A portion of the gate trace and drain trace are shown in more detail;

[0013] Figure 7 An example of a transistor cell, each including a gate electrode, is shown;

[0014] Figure 8 An example of a gate electrode is shown in more detail;

[0015] Figure 9 An example of the edge region of a transistor device is shown;

[0016] Figure 10 It shows Figure 9 The edge region shown is in relation to Figure 9 The cross-sectional plane shown is one example of a different cross-sectional plane;

[0017] Figure 11A and 11B Each showed in accordance with Figure 1A-1B Voids that may occur in the second conductive layer formed in the method;

[0018] Figures 12A-12E An example of a method for patterning a first conductive layer to avoid the formation of voids in a second conductive layer is shown; and

[0019] Figures 13A-13C An example of a method for forming conductive vias is shown. Detailed Implementation

[0020] In the following detailed description, reference is made to the accompanying drawings. The drawings form part of the specification and, for illustrative purposes, illustrate examples of how the invention can be used and practiced. It should be understood that, unless otherwise specifically stated, features of the various embodiments described herein can be combined with each other.

[0021] Figure 1A-1F An example of a method for forming an electrode 41 over a semiconductor body 100 is shown. Figures 1A to 1F Each shows a vertical cross-sectional view of a portion of the semiconductor body 100 during the process of forming electrode 41. Figure 1A-1F The vertical cross-sectional view shown is a cross-sectional view in a vertical cross-sectional plane of the semiconductor body 100. For example, the vertical cross-sectional plane is a cross-sectional plane orthogonal to the first surface 101 of the semiconductor body 100.

[0022] For example, according to Figure 1A-1F Electrode 41, formed during the process, is an electrode of the semiconductor device. Therefore, electrode 41 can also be referred to as a device electrode. The semiconductor device may have an active device region integrated within the semiconductor body 100. For example, the semiconductor device is a transistor device. A more detailed example of a transistor device is explained below.

[0023] According to one example, the semiconductor body 100 includes a single-crystal semiconductor material. The single-crystal semiconductor material can be a conventional single-crystal semiconductor material, such as, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc.

[0024] exist Figure 1A-1F Only those features of the semiconductor body 100 related to the formation of the device electrode 41 are shown. That is, device regions that may have been formed in the semiconductor body 100 before the formation of the electrode 41 are not shown.

[0025] It should be noted that the manufacturing process described below can occur at the wafer level. That is, the manufacturing process can be applied simultaneously to multiple semiconductor bodies that are part of a wafer, and the wafer is eventually separated into individual semiconductor bodies (chips, dies).

[0026] Figure 1A-1F An electrode 41 is shown. However, this is for illustrative purposes only. Several electrodes can be formed over the semiconductor body 100 using the same process.

[0027] refer to Figure 1AThe method includes forming a first conductive layer 410 on top of an insulating layer 5 formed over a semiconductor body 100. More specifically, the insulating layer 5 is formed on top of a first surface 101 of the semiconductor body 100. The insulating layer 5 may include oxides, nitrides, etc. The first conductive layer 410 is formed on top of surface 501 of the insulating layer 5.

[0028] According to one example, the first conductive layer 410 comprises a metal such as tungsten (W) or titanium (Ti). According to one example, the first conductive layer 410 is a homogeneous layer of the same material (such as tungsten or titanium). According to another example, the first conductive layer 410 comprises two or more layers. According to one example, one of the layers is a tungsten layer, and the thickness of each of the one or more other layers is less than 10% or less than 5% of the thickness of the tungsten layer.

[0029] According to one example, the first conductive layer 410 includes a first layer comprising titanium (Ti), a second layer comprising titanium nitride (TiN), and a third layer comprising tungsten (W).

[0030] According to one example, a first layer comprising Ti is formed on top of an insulating layer 5, a second layer comprising TiN is formed on top of the first layer, and a third layer comprising W is formed on top of the second layer. According to one example, each of the first, second, and third layers is formed in a deposition process such that the first layer is deposited on the insulating layer 5, the second layer is deposited on the first layer, and the third layer is deposited on the second layer. According to another example, to form the first and second layers, a Ti layer is deposited on the insulating layer 5, and the Ti layer is annealed in a nitrogen-containing (N) environment such that a portion of the Ti layer is converted into a TiN layer. The remaining Ti layer after the annealing process forms the first layer, and the TiN layer formed from a portion of the Ti layer and nitrogen forms the second layer. The third layer may be deposited after the annealing process. In addition to the Ti-containing first layer and the TiN-containing second layer, the stack of layers obtained from the Ti layer and the annealing process may include an intermediate layer between the Ti layer and the TiN layer. The intermediate layer comprises Ti and TiN, wherein the TiN concentration increases toward the second layer.

[0031] According to one example, the thickness of each of the first and second layers is less than 10% or even less than 5% of the thickness of the third layer. According to one example, the thickness of an optional intermediate layer between the first and second layers is less than 10%, less than 5%, or less than 3% of the thickness of the third layer. An example of a first conductive layer 410 comprising three layers is further explained below.

[0032] The thickness d410 of the first conductive layer 410 is, for example, between 0.8 micrometers and 1.5 micrometers, and more particularly, between 0.8 micrometers and 1.2 micrometers. The thickness d410 of the first conductive layer 410 is the dimension of the first conductive layer 410 in a direction orthogonal to the first surface 501 of the insulating layer 5.

[0033] refer to Figure 1B The method further includes patterning the first conductive layer 410 to form a first device electrode layer 411. Patterning the first conductive layer 410 may include forming a first etch mask 310 over the first conductive layer 410 and etching the first conductive layer 410 while the etch mask 310 is in place. The etch mask 310 protects certain areas of the conductive layer 410 from etching and thus substantially defines the size and location of the first device electrode layer 411. According to one example, the etching process used to pattern the first conductive layer 410 is an anisotropic etching process, such as a plasma matching process. Figure 1B The semiconductor body 100 is shown after the etching process and while the first etch mask 310 is still in place.

[0034] refer to Figure 1C The method further includes removing the first etch mask 310 and forming a second conductive layer 420. Forming the second conductive layer 420 includes forming the second conductive layer on top of the portion of the insulating layer 5 not covered by the first electrode layer 411 and on top of the first electrode layer 411.

[0035] For example, the second conductive layer 420 comprises a metal such as aluminum (Al) or copper (Cu), or a metal alloy such as AlCu or AlSiCu. AlSiCu is an alloy comprising aluminum, copper, and silicon. According to one example, the second conductive layer 420 is a homogeneous layer comprising only one material. According to another example, the second conductive layer comprises two or more layers comprising different conductive materials.

[0036] According to one example, the second conductive layer 420 is thicker than the first conductive layer 410. That is, the thickness d420 of the second conductive layer 420 is greater than the thickness d410 of the first conductive layer 410. According to one example, the thickness d420 of the second conductive layer 420 is between 3 micrometers and 10 micrometers. According to one example, the second conductive layer 420 is thicker than 5 micrometers (d420 > 5 μm) and thinner than 8 micrometers (d420 < 8 μm). According to one example, the thickness d420 of the second conductive layer 420 is between 5.5 micrometers and 7.5 micrometers, or between 5.5 micrometers and 6.5 micrometers.

[0037] According to one example, the thickness d410 of the first conductive layer 410 is less than 30% of the thickness d420 of the second conductive layer 420.

[0038] The method for forming device electrode 41 further includes patterning a second conductive layer 420 to form a second device electrode layer 412 at least partially on top of the first device electrode layer 411. Patterning the second conductive layer 420 may include forming a second etch mask 320 over the second conductive layer 420 and etching the second conductive layer 420 when the second etch mask 320 is in place.

[0039] Figure 1D A second conductive layer 420 is shown after the formation of the etching mask 320. The etching mask 320 protects certain areas of the second conductive layer 420 from etching and thus substantially defines the size and location of the second device electrode layer 421. According to one example, the etching process used to pattern the second conductive layer 420 is an isotropic etching process, such as a wet etching process. In this type of process, portions of the second conductive layer 420 located below the edge regions of the etching mask 320 are also etched.

[0040] According to one example, the etching process for patterning the second conductive layer 420 selectively etches the second conductive layer 420 relative to the first electrode layer 411, such that the first electrode layer 411 remains in place. Figure 1E The semiconductor body 100 is shown after an etching process for patterning the second conductive layer 420.

[0041] The device electrode 41 includes a first device electrode layer 411 obtained by patterning a first conductive layer 410 and a second device electrode layer 421 obtained by patterning a second conductive layer 420. This is in Figure 1F As shown in the figure, Figure 1F The semiconductor body 100 is shown after the etch mask 320 used for patterning the second conductive layer 420 has been removed.

[0042] In the method explained earlier in this paper, the size of the first device electrode layer 411 can be adjusted quite precisely based on the size of the first etch mask 310. However, in the process of forming the second device electrode layer 421, certain limitations and process variations exist, making it impossible to adjust the size of the second device electrode layer 421 as precisely as the size of the first device electrode layer 411. (Refer to...) Figure 2 To explain, Figure 2 A detailed view of the device electrode 41 is shown after the formation of the second device electrode layer 421 and while the second etch mask 320 is still in place.

[0043] Referring to the above, forming the second device electrode layer 421 may include an isotropic etching process, wherein the portion of the second conductive layer 420 located below the second etching mask 320 is removed. This type of etching process results in a sloping edge surface of the second device electrode layer 421. The edge surface terminates the device electrode layer 421 in the lateral direction. For illustrative purposes only, Figure 2 The edge surface of the second device electrode layer 421 shown is straight. However, other shapes of the edge surface, such as curved edge surfaces, may also occur due to the etching process.

[0044] refer to Figure 2 The second device electrode layer 421 has a bottom surface 521 and a top surface 621. The bottom surface 521 is the surface facing the first device electrode layer 411, and the top surface 621 is the surface facing the second etching mask 320. Due to the isotropic etching process, the width w521 of the bottom surface 521 is greater than the width w621 of the top surface 621. Hereinafter, the width w621 of the top surface 621 is also referred to as the top width, and the width of the bottom surface 521 is also referred to as the bottom width.

[0045] Basically, the etching process stops when the second conductive layer 420 has been removed down to the first device electrode layer 411 and the insulating layer 5 to form the second device electrode layer 421. The amount of the second conductive layer 420 removed below the second etching mask 320 before it is etched down to the first device electrode layer 411 and the insulating layer 5 depends on the thickness d420 of the second conductive layer 420. Figure 2 In this context, u represents the distance between the edge of the second etch mask 320 and the top surface 621 after the etching process is completed. This distance u is referred to as the undercut in the following text.

[0046] There is a predefined relationship between the thickness d420 of the second conductive layer 420 and the undercut u, which depends on, for example, the material type of the second conductive layer 420 and the etchant used in the etching process. According to one example, the undercut u is essentially given by the thickness of the second conductive layer 420, u≈d420. In this example, when the etching process stops once the second conductive layer d420 has been etched down to the first device electrode layer 411 and the insulating layer 5, the undercut u (on both sides of the second etching mask 320) is essentially equal to the thickness d420.

[0047] Once the second conductive layer 420 has been etched down to the first device electrode layer 411 and the insulating layer 5, and the etching process stops, the bottom width w521 is substantially equal to the width w320 of the second etching mask 320. It should be noted that the widths explained above are the dimensions of the corresponding conductive device layers 411, 421 and the etching mask 320 in the first lateral direction x1.

[0048] One possible variation in the process of forming the second device electrode layer 421 is the duration of the etching process. For example, if the etching process continues after the second conductive layer 420 has been etched down to the first device electrode layer 411 and the insulating layer 5, the bottom width 521 may become smaller than the width w320 of the second etching mask 320. That is, the second conductive layer 420 is etched in the lateral direction after the second conductive layer 420 has been completely removed in the portion not covered by the second etching mask 320.

[0049] Furthermore, to prevent the second etching mask 320 from being stripped during the etching process, the width w320 of the second etching mask should not be less than three times the undercut u, i.e., w320 > 3u. Considering the aforementioned process variations, the second etching mask 320 can be selected such that its width w320 is not less than 3.5 times the thickness d420 of the second conductive layer, i.e., w320 > 3.5·d420. Therefore, the thicker the second conductive layer 420, the wider the second etching mask 320, and the larger the minimum value of the bottom width w521 that can be obtained. In addition, due to process variations, the bottom width w521 can vary within a specific range (e.g., between 0.8 times and 1 times the width w320 of the second etching mask 320).

[0050] Referring to the preceding text, for example, a semiconductor device having an active device region integrated within a semiconductor body 100 is a transistor device. According to one example, the device electrode 41 explained earlier herein is the gate trace of a transistor device. The transistor device is a power transistor device, which, for example, is a transistor device that can be used as an electronic switch. For example, the voltage blocking capability of a power transistor device is in the range of several hundred volts.

[0051] exist Figure 3A and Figure 3B The image shows a top view of two different transistor devices, each including a first device electrode 41 as a gate trace. Figure 3A and 3B Each of these shows a top view of the corresponding overall transistor device.

[0052] refer to Figure 3A and 3B The transistor device also includes a source electrode 42 and a drain trace 43. A gate trace 41 surrounds the source electrode 42 in a lateral direction of the semiconductor body 100. The lateral direction is a direction substantially parallel to the first surface 101 of the semiconductor body 100. The drain trace 43 is disposed above a region of the semiconductor body 100 terminated by sidewalls 103-106 of the semiconductor body 100. Furthermore, the drain trace 43 surrounds the gate trace 41 and the source electrode 42 in a lateral direction.

[0053] refer to Figure 3A and Figure 3B The transistor device may further include a gate pad 44 connected to the gate trace 44. The gate pad 44 forms a gate node G or is connected to the gate node G of the transistor device. The gate pad 44 may be adjacent to the gate trace 42, such as... Figure 3A and 3B As shown. Alternatively, gate pad 44 is spaced apart from gate trace 42, and a resistor (gate resistor) is connected between gate pad 44 and gate trace 42. Source electrode 42 forms the source node S of the transistor device. This is explained further below.

[0054] The source electrode 42, gate pad 44, and drain line 43 are device electrodes that can be formed using the same process as the gate line 41. In the example where the gate pad 44 is adjacent to the gate line 41, the gate pad 44 and the gate line 41 form a continuous device electrode.

[0055] exist Figure 3A In the example shown, the gate pad 44 is positioned substantially midway between the two opposing sidewalls 103, 106 of the semiconductor body 100. According to... Figure 3B In the example, the gate pad 44 is positioned near the corner formed by two adjacent sidewalls 105, 106 of the semiconductor body 100. This is achieved by separating a wafer comprising multiple semiconductor bodies into individual semiconductor bodies (such as...). Figure 3A and 3B The semiconductor body 100 shown in the figure has sidewalls 103-106.

[0056] Figure 4 A vertical cross-sectional view of a portion of the source electrode 42, gate trace 41, and drain trace 43 according to an example is shown. For example, Figure 4 The vertical cross-sectional view shown corresponds to the attached diagram. Figures 3A-3B The diagram shows a vertical section in plane AA. However, in Figure 4 The semiconductor body 100 is shown only schematically. The active device region of the transistor device is not shown.

[0057] refer to Figure 4 Each of the source electrode 42 and the drain trace 43 includes a corresponding first device electrode layer 412, 413 obtained by patterning the first conductive layer 410, and a second device electrode layer 422, 423 obtained by patterning the second conductive layer 420.

[0058] The first device electrode layers, particularly the first device electrode layers 411 and 412 of the gate trace 41 and source electrode 42, can each act as barrier layers to prevent or at least reduce the diffusion of impurity atoms into the insulating layer 5 and the semiconductor body 100. According to one example, the impurity atoms are atoms from a molding compound (shown in dashed lines), which can be formed on top of the semiconductor device after the wafer 1 has been separated into individual devices. Such impurity atoms can negatively impact the function of the semiconductor device. The diffusion of impurity atoms into the semiconductor body 100, particularly in regions near the source electrode 42, is a problem, while it may be less critical in regions further away from the source electrode 42 (such as the region between the gate trace 41 and the drain trace 43).

[0059] Therefore, it is desirable to reduce the size of the gap between the first device electrode layers 411, 412 of the gate trace 41 and the source electrode 42. This can be achieved by the method explained previously, wherein the first and second conductive layers 410, 420 are patterned by separate processes. For example, patterning the first conductive layer 410 using an anisotropic etching process allows a smaller gap to be created between the first device electrode layers 411, 412 than between the second device electrode layers 421, 422 formed by patterning the second conductive layer 420 using an isotropic etching process.

[0060] To ensure the transistor device can withstand the voltage between the gate trace 41 and the source electrode 42, it is desirable to precisely adjust the distance between the source electrode 42 and the gate trace 41. According to one example, this distance is defined by first device electrode layers 411, 412. That is, in the direction of the source electrode 42, the first device electrode layer 411 of the gate electrode 41 protrudes from the second device electrode layer 421. Equivalently, in the direction of the gate trace 41, the first device electrode layer 412 of the source electrode 42 protrudes from the second device electrode layer 422.

[0061] The gap between the first and second device electrode layers 411, 412 of the gate trace 41 and the source electrode 42 depends on the voltage that may occur between the gate trace 41 and the source electrode 42 when the transistor device is operating. Basically, the higher the voltage that may occur, the greater the distance. According to one example, this distance is selected between 1.5 micrometers and 5 micrometers, and more particularly, for example, between 1.6 micrometers and 3 micrometers.

[0062] To reduce the overall size of the transistor device, it may be desirable to minimize the width of the gate trace 41 as much as possible. The width of the gate trace 41 is essentially determined by the width w411 of the first device electrode layer 411. Referring to the above, the width w411 of the first device electrode layer 411 can be adjusted quite precisely in the first etching process. Given the process variations explained above, the bottom width w521 and top width w621 of the second device electrode layer 421 of the gate trace 41 cannot be adjusted as precisely as the width w411 of the first device electrode layer 411.

[0063] Considering that the bottom width w521 of the second device electrode layer 421 explained above is limited to a small value; a small width w411 of the first device electrode layer 411 is desired; the distance between the gate trace 41 and the source electrode 42 should be defined by the first device electrode layers 411 and 412; and in particular, a specific cross-sectional area of ​​the second device electrode layer 421 of the gate trace 41 is desired in order to obtain a low resistance of the gate trace 41, according to Figure 4 The gate trace 41 is implemented as an asymmetric gate trace 41. This will refer to... Figure 5 Detailed explanation.

[0064] Figure 5 It shows that according to Figure 4 An enlarged view of the adjacent portions of the gate trace 41 and the source electrode 42. As explained above, the first device electrode layer 411 of the gate trace 41 protrudes below the second device electrode layer 421 in the direction of the source electrode 42. This protrusion of the first device electrode layer 411 below the second device electrode layer 421... Figure 5 The first protrusion is marked p11 and referred to below as the first protrusion. The implementation of the asymmetric gate trace 41 includes the first device electrode layer 411 of the gate trace 41 below the second device electrode layer 421 in the opposite direction (i.e., below the drain trace 43). Figure 5 In the direction (not shown), the second protrusion p21 is smaller than the first protrusion p11. <p11。

[0065] Referring to the above, the second device electrode layer 421 of the gate trace 41 is formed such that even considering process variations, the first device electrode layer 421 does not extend beyond the first device electrode layer 411 in the direction of the source electrode 42, such that the first device electrode layer 411 protrudes from the second device electrode layer 421, and the distance between the gate trace 41 and the source electrode 42 is defined by the distance between the first device electrode layers 411 and 421.

[0066] The second protrusion p21 of the gate trace 41 is smaller than the first protrusion p11. In the direction of the drain trace 43, the second device electrode layer 421 can completely cover the first device electrode layer 411, or even extend beyond the first device electrode layer 411 (e.g., ...). Figure 5 (As shown by the dashed line in the image). According to one example, the first protrusion p11 is at least 100 nm, at least 500 nm, or at least 1 micrometer. According to one example, the first protrusion p11 is at least 2 times, at least 3 times, at least 5 times, or at least 10 times the size of the second protrusion p21.

[0067] Figure 6 An enlarged view of a portion of the gate trace 41 and the drain trace 43, according to an example, is shown. Figure 6 In the example shown, the drain trace 43 is implemented such that the first device electrode layer 413 of the drain trace 43 protrudes from the second device electrode layer 423 of the drain trace 43 in the direction of the gate trace 41. The protrusion of the first device electrode layer 413 of the drain trace 43 in the direction of the gate trace 41... Figure 6 The term p31 is used to denote this feature, and it is referred to as the first protrusion in the following text. According to one example, the first protrusion p31 is at least 100 nm, at least 500 nm, or at least 1 micrometer.

[0068] In a transistor device, a relatively high voltage may occur between the gate trace 41 and the drain trace 43, necessitating the appropriate selection of the distance between the gate trace 41 and the drain trace 43 to prevent voltage breakdown. For example... Figure 6 As shown, process variations in the fabrication of the second device electrode layer 421 of the gate trace 41 can cause changes in the distance between the gate trace 41 and the drain trace 43, depending on whether the second device electrode layer 421 of the gate trace 41 extends beyond the first device electrode layer 411 in the direction of the drain trace 43. When the second device electrode layer 421 does not extend beyond the first device electrode layer 411, the distance is given by the distance between the first device electrode layers 411 and 413 of the gate trace 41 and the drain trace 43. When the second device electrode layer 421 of the gate trace 41 extends beyond the first device electrode layer 411 in the direction of the drain trace 43, the distance is shorter.

[0069] However, it has been found that the breakdown voltage between the gate trace 41 and the drain trace 43 depends not only on the distance between the gate trace 41 and the drain trace 43, but also on the lateral position of the edge of the drain trace 43 facing the gate trace 41. Therefore, shifting the edge of the drain trace 43 in the direction of the gate trace (e.g., by extending a second device electrode layer 423 beyond the first device electrode layer 413) can have a greater negative impact on the breakdown voltage than shifting the edge of the gate trace 41 in the direction of the drain trace 43 (e.g., by extending a second device electrode layer 421 beyond the first device electrode layer).

[0070] As an example, drain trace 43 is asymmetrical. That is, the second protrusion p32 of the first device electrode layer 413, located below the second device electrode layer 423 in the direction away from the gate trace 41, is smaller than the first protrusion p31. Everything explained above regarding the relationship between the first protrusion p11 and the second protrusion p21 of the gate trace 41 also applies to the first protrusion p31 and the second protrusion p32 of the drain trace 43.

[0071] Figure 3A and 3B Each transistor device shown in the diagram may include an internal region and an edge region in its semiconductor body 100. The internal region is essentially the area of ​​the semiconductor body 100 disposed below the source electrode 42. The edge region surrounds the internal region and is disposed between the internal region and the sidewalls 103-106. Multiple transistor cells are integrated within the internal region of the semiconductor body 100.

[0072] Figure 7 An example of a transistor cell 10 that can be arranged in the internal region is shown. Figure 7 A vertical cross-sectional view of a portion of the semiconductor body 100, the insulating layer 5, and the source electrode 42 is shown. Figure 7 The vertical cross-sectional view shown is, for example... Figure 3A and 3B The vertical cross-section diagram in the cross-sectional plane BB shown.

[0073] refer to Figure 7 Each transistor unit 10 includes a source region 11 of a first doped type, a body region 12 of a second doped type complementary to the first doped type, and a gate electrode 21. The gate electrode 21 is adjacent to the body region 12, is dielectrically insulated from the body region 12 by a gate dielectric 22, and is disposed in a gate trench 120 extending from a first surface 101 of the semiconductor body 100 into the semiconductor body 100.

[0074] refer to Figure 7The source regions and body regions 11, 12 of two adjacent transistor cells 10 can be arranged in a mesa region between adjacent gate trenches 120. In this example, the body region 12 of the two adjacent transistor cells 10 can be formed by a continuous doped region of a second doping type. Furthermore, the two (other) adjacent transistor cells can share a gate electrode 21. That is, the gate electrode 21 of the two adjacent transistor cells can be formed by a continuous electrode arranged in a gate trench 120.

[0075] Gate electrode 21 comprises a conductive material. Examples of conductive materials include doped polycrystalline silicon or metals such as tungsten (W), titanium (Ti), copper (Cu), and aluminum (Al). For example, gate dielectric 22 comprises an oxide. According to one example, the oxide is silicon oxide (SiO2).

[0076] The source electrode 42 either forms a source node S or is connected to the source node S of the transistor device. The source electrode 42 is only... Figure 7 The diagram is schematically shown, so that the first and second device electrode layers 411 and 412 are not shown.

[0077] The source electrode 42 is electrically connected to the source and body regions 11 and 12 of the transistor unit 10. The connection between the source electrode 42 and the source and body regions 11 and 12 is only present in the source region. Figure 7 The diagram is schematically shown. This connection can be achieved using a conductive via that extends from the source electrode 42 through the insulating layer 5 down to the source and body regions 11, 12. Examples of such vias are further explained below.

[0078] An insulating layer 5 is formed on the top of the first surface 101 and the top of the gate electrode 21, and separates the source electrode 42 from the semiconductor body 100 and the gate electrode 21.

[0079] refer to Figure 7 The transistor device also includes a drift region 14 of a first doped type. The drift region 14 is adjacent to the body region 12 of the transistor cell 10, such that a PN junction is formed between the body region 12 and the drift region 14. Furthermore, in the vertical direction, the drift region 14 is arranged between a drain region 13 of the first doped type and the body region 12. The drain region 13 may be adjacent to a second surface 102 opposite to the first surface 101.

[0080] Optionally, a buffer region 16 of the first doping type, with a doping concentration higher than that of the drift region 14 and lower than that of the drain region 13, is arranged between the drift region 14 and the drain region 13.

[0081] refer to Figure 7As described above, the gate trenches having gate electrodes 21 can be spaced apart from each other in the first lateral direction x. According to one example, the gate electrode 21 is implemented as a strip electrode (elongated electrode). In this example, the longitudinal direction of the gate electrode 21 corresponds to a second lateral direction orthogonal to the first lateral direction x.

[0082] Figure 8 An example of a long, thin gate electrode 21 is shown in the figure. Figure 8 The semiconductor body 100 is shown in Figure 7 A portion of the first horizontal cross-sectional plane CC is shown, which cuts through the gate trench 120 having the gate electrode 21 and the gate dielectric 22. The horizontal cross-sectional plane CC is substantially parallel to the first surface 101. Figure 8 In the example shown, the gate electrode 21 extends longitudinally in the second lateral direction y.

[0083] According to one example, the transistor device is implemented as a superjunction transistor device. In this example, the transistor device includes a plurality of compensation regions 15 (shown in dashed lines) spaced apart from each other in the lateral direction of the semiconductor body 100. Each compensation region 15 is adjacent to a corresponding portion of the drift region 14.

[0084] For illustrative purposes only, Figure 7 In the example shown, the compensation regions 15 are spaced apart from each other in the first lateral direction x. According to another example (not shown), the compensation regions 15 are spaced apart from each other in the second lateral direction y.

[0085] The transistor device can operate in an on-state or an off-state. In the on-state, a conductive channel exists in the body region 12 along the gate dielectric 22 between the source region 11 and the drift region 14. For this purpose, the drift region 14 is adjacent to the gate dielectric 22 and the body region 12 of at least one of the transistor cells 10.

[0086] Furthermore, each optional compensation region 15 is adjacent to at least a portion of the drift region 14 and connected to the source electrode 42. Figure 7 In the example shown, each compensation region 15 is adjacent to the body region 12 of at least one transistor cell and is connected to the source electrode 42 via the respective body region 12.

[0087] The transistor device can be operated in a conventional manner by applying a driving voltage (gate-source voltage) between the gate electrode 21 and the source electrode 42. When the driving voltage causes a conductive channel to be formed in the body region 12 along the gate dielectric 22 between the source region 11 and the drift region 14, the transistor device is in the on state (conduction state). When the conductive channel is interrupted, the transistor device is in the off state (blocking state).

[0088] The transistor device can be implemented as an N-type transistor device or a P-type transistor device. For example, when the drive voltage is higher than a predefined positive threshold voltage, the N-type transistor device is in the on state, and when the drive voltage is lower than the threshold voltage, the N-type transistor device is in the off state.

[0089] In an N-type transistor device, the doped region of the first doping type is an N-type region, and the doped region of the second doping type is a P-type region. In a P-type transistor device, the doped region of the first doping type is a P-type region, and the doped region of the second doping type is an N-type region.

[0090] The source region 11, the main region 12, the drift and compensation regions 14 and 15, the buffer region 16, and the drain region 13 can also be referred to as the (active) device regions of a transistor device.

[0091] Figure 9 A more detailed view of an example transistor device is shown in cross-sectional plane AA. Besides gate trace 41, source electrode 42, and drain trace 43, Figure 9 Also shown are transistor cells in the internal region 130 of the semiconductor body 100 below the source electrode 42, and edge termination structures in the edge region 140 below the gate line 41 and the drain line 43.

[0092] Figure 9 The transistor device shown is a superjunction transistor device, which, in addition to the drift region 14, also includes a compensation region 15. According to... Figure 9 As shown in one example, the drift region and the compensation region are arranged not only in the inner region 130, but also in the edge region 140. The drift region arranged in the edge region 140 may be referred to as the edge drift region 14′, and the compensation region arranged in the edge region 140 may be referred to as the edge compensation region 15′.

[0093] Referring to the above, the source and body regions 11 and 12 of the transistor cell are connected to the source electrode 41. According to... Figure 9 In one example, the source and body regions 11, 12 are connected to the source electrode 41 via a conductive via 45 extending from the source electrode 41 through the insulating layer 5 into the source and body regions 11, 12 within the semiconductor body 100. Optionally, each transistor cell 10 includes a body contact region 17 of a second doping type, providing an ohmic contact between the body region 12 and the corresponding conductive via 45. The body contact region 17 has a higher doping concentration than the body region 12.

[0094] In the edge region, the transistor device may include an edge termination structure. Optionally, the edge termination structure includes an edge trench 6 (shown in dashed lines) extending from the first surface 101 into an edge region 140 of the semiconductor body 100 and filled with an electrically insulating layer 51. The optional edge trench 6 having the insulating layer 51 may surround the inner region 130 in the lateral direction.

[0095] refer to Figure 9 The edge termination structure may include a field electrode 31 disposed above the edge trench 6 and electrically connected to the gate trace 41 via a conductive via 46. The field electrode 31 may include, for example, doped polysilicon.

[0096] refer to Figure 9 The transistor device also includes a first-doped field stop region 71 extending along sidewalls 103-106 from drain region 13 or buffer region 16 to the first surface 101. Drain trace 43 is electrically connected to field stop region 51. According to one example, drain trace 43 is connected to field stop region 51 via conductive via 48. According to one example, drain trace 46 is connected to field stop region 73 only in the regions at the four corners of semiconductor body 100.

[0097] Referring to the above, each transistor unit 10 includes a gate electrode 21. The transistor unit in... Figure 3A and 3B Not visible in the image. For illustrative purposes, the positions of some gate electrodes in gate electrode 21 relative to source electrode 42, gate trace 41, and gate pad 44 are shown in the image. Figure 3A and 3B The middle part is indicated by a thick line. Figure 3A and 3B In the example shown, the gate electrodes 21 are elongated electrodes spaced apart from each other in the first lateral direction x. For example, the longitudinal direction of the gate electrodes 21 corresponds to a second lateral direction y orthogonal to the first lateral direction x.

[0098] The gate electrode 21 of each transistor cell is electrically connected to the gate trace 41 at least at one longitudinal end of the respective gate electrode 21. The connection between the gate electrode 21 and the gate trace 41 is not... Figure 3A and 3B As shown in [the image]. Figure 10 An example is shown for connecting the gate electrode 21 to the gate trace 42.

[0099] Figure 10 It shows Figures 3A-3B The diagram shows a vertical cross-sectional view of a transistor device in a cross-sectional plane DD, which is substantially parallel to the longitudinal direction of the gate electrode 21 and cuts through one of the gate electrodes 21. Figure 10A portion of the internal region 130 and edge region 140 of the semiconductor body 100, a portion of the gate trace 41, and a portion of the source electrode 42 are shown. The drain trace 43 and the field stop region 71 are not shown. Figure 10 As shown in the image.

[0100] exist Figure 10 In the example shown, the gate electrode 21 is connected to the gate trace 42 via the field electrode 31. For this purpose, contact fingers 32 extend from the field electrode 31 to the gate electrode 21 in the insulating layer 5 and are connected to the gate electrode 21 at its longitudinal end.

[0101] The field electrode 31 and the contact finger can be formed using the same process, allowing the field electrode 31 and the contact finger 32 to be formed from a continuous electrode layer. The electrode layer is a conductive layer, such as, for example, a doped polysilicon layer.

[0102] exist Figure 1A-1F The method shown for forming the second conductive layer 420 may include a deposition process. During the formation of the second conductive layer 420, growth interference may occur. This growth interference may result in the formation of voids in the second conductive layer 420. Figure 11A and Figure 11B A second conductive layer 420 including voids V is shown according to different examples. Figure 11A In the example shown, the gap V opens toward the surface of the second conductive layer 420. Figure 11B In the example shown, the void V is closed and completely surrounded by a portion of the second conductive layer 420. Any type of void V that may appear in the second conductive layer 420 is undesirable because when the second conductive layer 420 is patterned to form the second device electrode layers 421, 422, 423, it may cause uncontrolled etching of the second conductive layer 420 in the region of the void V.

[0103] Especially in the second conductive layer 420 grown in the first device electrode layer (such as... Figure 11A and 11B Voids may occur on the top of the device electrode layers 411, 412 shown and in those regions where the distance between adjacent first device electrode layers 411, 421 is short (e.g., less than 3 micrometers).

[0104] It has been found that the growth disturbance that generates voids V occurs particularly at the sharp edges of the first device electrode layers 411 and 421.

[0105] Figures 12A-12E The diagram illustrates the formation of electrode layers for two adjacent devices (such as...). Figure 11A and 11B The edges of the electrode layers 411 and 421 of the device shown are such that the second conductive layer 420 (formed on top of the first conductive layer) Figures 12A-12E An example of a method that reduces growth disturbances (not shown in the figure) to make voids less likely to occur.

[0106] Figure 12A A vertical cross-sectional view is shown of an insulating layer 5, a first conductive layer 410 formed on top of the insulating layer 5, and a portion of a first etch mask 310. For example, the first etch mask 310 is a photoresist. For example, the thickness of the first etch mask 320 is between 3 micrometers and 5 micrometers.

[0107] For illustrative purposes only, according to Figures 12A-12E The first conductive layer 410 comprises three layers: a first layer 4101, a second layer 4102, and a third layer 4103. For example, the first layer 4101 is a titanium (Ti) layer, the second layer 4102 is a titanium nitride (TiN) layer, and the third layer is a tungsten (W) layer. For example, the thickness of each of the first layer 4101 and the second layer 4102 is less than 5% of the thickness of the third layer 4103. According to one example, the thickness of the third layer 4103 is, for example, between 0.8 micrometers and 1.2 micrometers.

[0108] Figure 12A The first etch mask 310 is shown after the opening 311 is formed in the first etch mask 310. According to one example, the opening 311 of the first etch mask 310 has sloping sidewalls 312, such that the trench 311 narrows toward the bottom of the trench formed by the first conductive layer 410. According to one example, the angle of the sidewalls 312 relative to the surface of the first conductive layer is between 70° and 80°.

[0109] Figure 12D The first conductive layer 410 is shown after the third layer 4103 has been etched down to the second layer 4102. Figure 12B and Figure 12C The first conductive layer 410 is shown at different stages of the etching process. (As shown from...) Figure 12B-12D As can be seen, the etchant used in the etching process not only etches the first conductive layer 410, but also etches away a portion of the etching mask 310. Firstly, as... Figure 12B As shown, the first conductive layer 410 is etched primarily in the region adjacent to the bottom of the opening 311 in the etching mask 310. Furthermore, portions of the sidewalls 312 of the opening in the etching mask 310 are etched, resulting in a reduced angle between the sidewalls and the surface of the first conductive layer 410 beneath the etching mask 310.

[0110] like Figure 12C As shown, as the etching process continues, a portion of the etching mask 310 is removed from above the surface of the conductive layer 410, so that the exposed portion of the surface of the conductive layer 410 is etched.

[0111] exist Figure 12B In the first part of the etching process shown, a first portion 431 of an opening (trench) 430 is formed in the first conductive layer 410. This first portion 431 extends from the bottom of the opening 311 of the etching mask 310 into the first conductive layer 410 and has sidewalls with a first angle α relative to a horizontal plane. For example, the first angle α is between 70° and 85°. For example, the horizontal plane is parallel to the surface 501 of the insulating layer 5.

[0112] exist Figure 12C In the second part of the etching process shown, the first portion 431 of the opening 430 extends further downward into the first conductive layer 410. Furthermore, the opening formed in the first conductive layer 410 is widened by etching the first conductive layer 410 in those areas covered by the etching mask 310 at the start of the etching process. Figure 12C In the figure, reference numeral 432 denotes a widened portion of the trench 430 formed in the second part of the etching process. The second angle β between the sidewalls of the widened portion 432 is smaller than the first angle α. According to one example, the second angle is between 20° and 30°, particularly between 21° and 25°.

[0113] At the end of the etching process for etching the third layer 4103, the trench 430 has a first trench portion 431 and a widened second trench portion 432. The first trench portion 431 has sidewalls with a first angle α relative to the horizontal plane, and the widened second trench portion 432 has a smaller second angle β relative to the horizontal plane. The overall surface of the second portion 432 is larger than the overall surface of the second portion 431, such that the second conductive layer 420 ( Figures 12A-12C (Not shown) It is mainly grown on the second portion 432, which has a relatively small second angle β relative to the horizontal plane. Compared with growing the second conductive layer 420 on a substantially vertical sidewall that may be produced by conventional etching processes, the risk of growth interference in the second conductive layer 420 formed on top of the first conductive layer 410 is significantly reduced.

[0114] according to Figure 12A-12D In one example shown, the first and second sidewall portions are substantially straight, resulting in an edge between the first and second sidewall portions where the angle in the edge region is significantly greater than 90°. According to Figure 12D In another example, shown in dashed lines, the etching process can result in a smooth transition from the sidewall of the first trench portion 431 to the sidewall of the second trench portion 432. In each case, for example, the sidewall of the second trench portion 432 has a portion with an angle β relative to the horizontal plane that is less than the first angle α and is between 20° and 30°.

[0115] For example, etchants used in etching processes include chlorine, oxygen, and / or argon.

[0116] According to one example, the etchant used in the process of etching the third layer 4103 does not etch the first layer 4101 and the second layer 4102. In this case, after the third layer 4103 is etched, another etchant is used to etch the first layer 4101 and the second layer 4102 down to the insulating layer 5. The previously etched third layer 4103 can be used as an etching mask in this etching process.

[0117] Figure 12E The image shows the result after etching the first layer 4101 and the second layer 4102 using the third layer 4103 as an etching mask. Figure 12D The layout shown.

[0118] Referring to the above, the transistor device may include a plurality of conductive vias, such as via 45 connecting the source electrode 42 to the source region 11 and the body region 12, via 46 connecting the gate trace 41 to the first field electrode 31, via 47 connecting the drain trace 43 to the second field electrode 32, or via 48 connecting the drain trace 43 to the field stop region 71.

[0119] According to one example, these vias 45, 46, 47, and 48 are formed by a first conductive layer 410, and portions of the first conductive layer 410 form first device electrode layers 411, 412, and 413. See below. Figures 13A-13C An example is provided to illustrate the method for forming vias 45, 46, 47, and 48 based on the first conductive layer 410. Each of these figures illustrates a via during the manufacturing process.

[0120] refer to Figure 13A The method includes forming a via trench 81 in the surface 501 of the insulating layer 5. The vertical dimension of the via trench depends on the type of via to be formed. That is, for forming a via 45 to connect the source electrode 42 to the source region 11 and the body region 12, or to form a via 48 to connect the drain trace 43 to the field stop region 71, the via trench 81 can extend through the insulating layer 5 into the semiconductor body 100. For forming vias 46 and 47 to connect the gate trace 41 and the drain trace 43 to the field electrodes 31 and 32, the via trench 81 can extend into the insulating layer 5 and extend to the respective field electrodes 31 and 32. Figures 13A-13C Only the surface 501 of the insulating layer 5 is shown in these figures. The semiconductor body or field electrode is not shown in these figures.

[0121] refer to Figure 13BThe method includes a first deposition process in which a first layer 4110 of the second conductive layer 410 is deposited on the sidewalls and bottom of the via trench 81 and on the surface 501 of the insulating layer 5. According to one example, the first layer 4110 is a layered layer comprising tungsten (W), such as... Figures 12A-12E The third layer 4103 is shown. The first layer 4101 and the second layer 4102 are optional, and are determined according to... Figures 13A-13C In the process, it can be formed before the formation of the first layer 4110 or it can be omitted.

[0122] The process parameters in the deposition process used to form the first layer 4110 are selected such that the first layer 4110 has a high tendency to liner the sidewalls and bottom of the via trench 81 and the surface 501 of the insulating layer 5. The thickness of the first layer 4110 (on top of the surface 501) is, for example, between 100 nm and 300 nm, particularly between 200 nm and 300 nm. Forming the first layer 4110 may include using WF6 gas as a precursor. Forming the entire via based on the process used to form the first layer 4110 may result in a less mechanically robust first conductive layer 410.

[0123] Therefore, refer to Figure 13C Use and according to Figure 13B The second layer 4120 of the first conductive layer 410 is formed using different process parameters, such that the second layer 4120 has a high tendency to grow on a horizontal plane and fill the trench 81. In addition to WF6, the second process may include nitrogen (N2) gas. Essentially, the nitrogen gas flow rates during the deposition process differ between the first and second processes. In the first process for forming the first layer 110, the nitrogen gas flow rate is lower than that in the second process. According to one example, the nitrogen flow rate in the first process is even zero.

[0124] For example, the thickness of the second layer 4120 above the surface 501 of the insulating layer 5 is between 600 nanometers and 900 nanometers. The total thickness of the first conductive layer 410 is further explained above.

[0125] A portion of the first layer 4110 and the second layer 4120 in the trench 81 forms a conductive via 8. After the second layer 4120 is formed, a void V1 can be retained in the trench 81. The void V1 can help reduce mechanical stress that may be caused by the deposition of the first conductive layer 410 in the via trench 81.

Claims

1. A transistor device, comprising: Gate traces (41) and drain traces (43) are spaced apart from each other. Each of the gate trace (41) and the drain trace (43) includes a corresponding first device electrode layer (411, 413) and a second device electrode layer (421, 423). In the gate trace (41), the first device electrode layer (411) protrudes a first distance (p11) different from zero in the direction away from the drain trace (43) below the second device electrode layer (421), and protrudes a distance smaller than the first distance (p11) in the direction of the drain trace (43) below the second device electrode layer (421). In the drain trace (43), the first device electrode layer (413) protrudes a second distance (p31) different from zero in the direction of the gate trace (41) below the second device electrode layer (423).

2. The transistor device according to claim 1, wherein, The first distance (p11) is at least 100 nanometers.

3. The transistor device according to claim 1, wherein, The second distance (p31) is at least 100 nanometers.

4. The transistor device according to any one of the preceding claims, in, Each of the electrode layers (411, 413) of the first device includes at least one of tungsten and titanium.

5. The transistor device according to any one of the preceding claims, wherein, The thickness of each of the electrode layers (411, 413) of the first device is between 0.8 micrometers and 1.2 micrometers.

6. The transistor device according to any one of the preceding claims, in, Each of the electrode layers (421, 423) of the second device comprises at least one of aluminum and copper.

7. The transistor device according to any one of the preceding claims, in, The thickness of each of the first device electrode layer and the second device electrode layer (421, 423) is between 6 micrometers and 8 micrometers.

8. The transistor device according to any one of the preceding claims, further comprising: The source electrode (42) is spaced apart from the gate electrode (41) in a direction opposite to the drain electrode trace (43). The source electrode (42) includes a first device electrode layer (412) and a second device electrode layer (422), and The first device electrode layer (412) of the source electrode (42) protrudes in the direction of the gate trace (41) below the second device electrode layer (422) of the source electrode (42).

9. The transistor device according to any one of the preceding claims, in, The distance between the gate trace (41) and the first device electrode layer (411, 412) of the source electrode (42) is between 1.5 micrometers and 3 micrometers.

10. The transistor device according to any one of the preceding claims, further comprising: Multiple transistor units (10), each transistor unit (10) includes a source region (11) connected to the source electrode (21) and a gate electrode (21) connected to the gate trace (41).

11. The transistor device according to claim 10, in, The transistor unit (10) is at least partially integrated in the semiconductor body (100), and wherein the gate line (41), the source electrode (42) and the drain line (43) are formed over an insulating layer (5) formed over the surface (101) of the semiconductor body (100).

12. The transistor device according to claim 10 or 11, in, The semiconductor body (100) includes an inner region (130) and an edge region (130) surrounding the inner region (130) in the lateral direction. The transistor unit (10) is integrated in the internal region (130), and The transistor device further includes an edge termination structure disposed in and above the edge region (140).

13. The transistor device according to claim 12, in, The edge termination structure includes an edge trench (6) that extends from the first surface (101) into the edge region (140) of the semiconductor body (100) and is filled with an insulating material (51).

14. A method comprising: Patterned conductive layer (410). The patterning of the conductive layer (410) includes: An etching mask (310) with an opening (311) is formed on the top of the conductive layer (410), wherein the opening (311) includes an inclined sidewall (312). The portion of the conductive layer (410) exposed at the bottom of the opening (311) and the portion of the etching mask (310) are etched, such that the opening (311) is widened during the etching process, and an opening (430) with a sloping edge surface is formed in the first conductive layer (410).

15. The method according to claim 14, in, The opening (430) in the conductive layer (410) is formed to have a first portion (431) and a second portion (432). Wherein, the first angle (α) between the sidewall of the first part (431) and the horizontal plane is greater than the second angle (β) between the sidewall of the second part (432) and the horizontal plane.

16. The method according to claim 15, in, The first angle (α) is between 70° and 85°.

17. The method according to claim 15 or 16, in, The second angle (β) is between 20° and 30°.

18. The method according to any one of claims 14 to 17, in, The first conductive layer (410) comprises at least one of tungsten and titanium.

19. The method according to any one of claims 14 to 18, wherein, The thickness of the first conductive layer (410) is between 0.8 micrometers and 1.2 micrometers.

20. The method according to any one of claims 14 to 19, in, The first conductive layer (410) includes: a first layer (4101) including titanium; a second layer (4102) including titanium nitride; and a third layer (4103) including tungsten. The thickness of each of the first layer and the second layer (4101, 4102) is less than 5% of the thickness of the third layer (4103). The patterning of the conductive layer (410) includes patterning the third layer (4103), and The method further includes etching the first layer and the second layer (4101, 4102) below the bottom of the opening formed in the third layer (4103).

21. The method according to any one of claims 14 to 20, wherein, The etching mask (310) includes a photoresist.

22. The method according to any one of claims 14 to 21, further comprising: After removing the etch mask (310), a second conductive layer (420) is deposited on top of the first conductive layer (410).

23. The method according to claim 22, wherein, The second conductive layer (420) comprises at least one of aluminum and copper.

24. The method according to claim 23, wherein, The thickness of the second conductive layer (420) is between 6 micrometers and 8 micrometers.

25. A method comprising: Forming a conductive via (8). The method includes: Forming through-hole trenches (81); In a first deposition process, a first tungsten layer (4110) is formed, such that the first tungsten layer (4110) lining the sidewalls and bottom of the via trench (81); and In the second deposition process, a second tungsten layer (4120) is formed on top of the first tungsten layer (4110), such that the second tungsten layer (4120) seals the via trench. In both the first and second deposition processes, WF6 is used as the precursor gas, and In this process, at least one of the first deposition process and the second deposition process additionally uses nitrogen gas. In the first deposition process, the nitrogen flow rate is lower than that in the second deposition process.

26. The method of claim 25, wherein, The first layer (4110) is formed to have a thickness between 100 nm and 300 nm.

27. The method according to claim 25 or 26, wherein, The second layer (4120) is formed to have a thickness between 600 nm and 900 nm.

28. The method according to any one of claims 25 to 27, in, The via trench (81) is formed in the surface (501) of the insulating layer.

29. The method according to claim 28, wherein, The insulating layer is an oxide layer.

30. The method according to claim 28 or 29, wherein, The via trench (81) is formed to extend through the insulating layer (5) into the semiconductor body (100), the insulating layer (5) being formed on top of the semiconductor body (100).

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