A PCIe configuration space access permission dynamic control method and system
By dynamically controlling PCIe configuration space access permissions through a hardware state machine, the problems of timing conflicts and lack of flexibility in reset operations are solved, ensuring data consistency and system stability. This approach is suitable for servers and data center equipment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHIPMOS TECHNOLOGIES (SHANGHAI) LTD
- Filing Date
- 2026-03-31
- Publication Date
- 2026-06-09
AI Technical Summary
In the prior art, the static control method for configuring space access permissions during PCIe device reset operations has the risk of timing conflicts and insufficient flexibility, resulting in data inconsistency and system instability, especially increasing the probability of system failure when the link is unstable.
A hardware state machine is used to dynamically control configuration space access permissions. By locking or unlocking permissions, the timing isolation between the reset signal and the configuration space access operation is ensured according to the PCIe link status. This includes locking permissions before reset, monitoring the link status after reset and unlocking when it is stable, and using a finite state machine and a reset signal synchronization module to coordinate the timing.
It achieves timing consistency between reset signals and configuration space access operations, reduces the risk of data corruption, and improves system stability and flexibility, making it suitable for servers and data center equipment.
Smart Images
Figure CN121935183B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of PCIe technology, specifically to a method and system for dynamic control of PCIe configuration space access permissions. Background Technology
[0002] As the core channel for high-speed data transmission in computer systems, the PCIe bus may require a reset during operation. The reset operation is a crucial step for PCIe devices to restore their initial state or reconfigure. However, during the reset process, there is a potential risk of conflict between the access timing of the configuration space and the reset signal. In existing technologies, configuration space access permissions are typically managed using a static control method, i.e., the configuration space is locked before reset and permanently unlocked after reset.
[0003] However, this static control method has the following problems: 1. Timing conflict risk: The reset signal and configuration space read / write operations may occur simultaneously, leading to data inconsistency or system instability. For example, when the PCIe link enters the Recovery state from the L0 state, if the configuration space is not locked in time, it may cause data corruption. 2. Insufficient flexibility: It cannot dynamically adjust access permissions according to the link state (such as LTSSM state), making it difficult to adapt to complex and ever-changing hardware environments.
[0004] Existing solutions allow configuration access even when the link is unstable (such as during Recovery mode), increasing the probability of system failure. Furthermore, existing solutions primarily focus on configuration space address mapping or link parameter negotiation, neglecting reset timing control and the coordination mechanism between configuration space access permissions and reset signals, thus lacking systematic protection for dynamic control methods. Summary of the Invention
[0005] To overcome the shortcomings of the prior art, this invention provides a method and system for dynamic control of PCIe configuration space access permissions.
[0006] To achieve the above objectives, a method for dynamic control of PCIe configuration space access permissions is designed, comprising the following steps:
[0007] S1, before the PCIe link reset signal is triggered, lock the read and write permissions of the configuration space through the hardware state machine;
[0008] S2, after the PCIe link reset is completed, the hardware state machine monitors the PCIe link status and dynamically unlocks the configuration space access permissions according to the link status;
[0009] S3, timing coordination, ensures timing isolation between reset signals and configuration space access operations through a hardware state machine.
[0010] The specific method for step S2 is as follows:
[0011] Determine the link status. If the link status is stable, unlock the configuration space and allow read and write operations. If the link status is unstable, keep it locked until the link becomes stable.
[0012] The specific method for determining the PCIe link reset signal before step S1 is as follows: The hardware state machine samples the level of the reset signal in real time, and when a valid transition edge of the reset signal is captured, it determines that the reset signal is about to be triggered in the subsequent clock cycle.
[0013] In step S2, a stable state includes the LTSSM state machine in the PCIe link being in states L0, L0s, or L1; an unstable state includes the PCIe link being in a state of training, recovery, or error handling.
[0014] In step S2, after the reset signal is released, the hardware state machine continuously monitors the real-time status of the PCIe link, including the link training status, link width, and link speed, to determine whether the link has reached a stable working state.
[0015] In step S3, the timing coordination step is achieved by synchronizing the reset signal to the system clock domain. The external asynchronous reset signal is synchronized to the internal clock domain through the reset signal synchronization module, thereby eliminating the metastability problem caused by cross-clock domain transmission.
[0016] To achieve the above objectives, a dynamic control system for PCIe configuration space access permissions is designed to implement the above method. The system includes:
[0017] Hardware state machine, which performs state transition control based on PCIe link status signals;
[0018] Configuration space access controller: Locks or unlocks access permissions to the configuration space under hardware state machine instructions;
[0019] Reset signal processing unit: includes a reset signal synchronization module and a timing isolation logic module, used to receive external reset signals and trigger the state machine to enter the reset process, while ensuring timing isolation between the reset signal and the configuration space access operation.
[0020] The hardware state machine is a finite state machine, and the state transition is based on the PCIe link status signal. The finite state machine includes four states: IDLE, LOCKED, WAITING, and UNLOCKED, and the state transition is performed through the link status signal and the reset signal.
[0021] The hardware state machine, configuration space access controller, and reset signal processing unit are integrated in the same clock domain of the PCIe device main control chip, and communication between modules is achieved through the register interface.
[0022] Compared with the prior art, the present invention has the following advantages:
[0023] 1. Ensure timing consistency by dynamically controlling the hardware state machine to ensure that reset signals and configuration space access operations do not interfere with each other, eliminating the risk of data inconsistency. For example, lock the configuration space during Recovery to prevent data corruption caused by rate switching.
[0024] 2. To ensure system stability, a dynamic unlocking mechanism adjusts permissions based on link status, avoiding configuration access when the link is unstable and reducing system failures. In servers or data center equipment, this mechanism significantly reduces the initialization failure rate.
[0025] 3. Enhanced flexibility, supporting collaboration with the PCIe protocol stack, suitable for high-performance communication devices such as servers and data center equipment. Through tight coupling between the state machine and the link training process, adaptive control in complex scenarios is achieved. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the process of the present invention. Detailed Implementation
[0027] The present invention will now be further described with reference to the accompanying drawings.
[0028] like Figure 1 As shown, the dynamic control method for PCIe configuration space access permissions in this embodiment includes the following steps:
[0029] S1, before the PCIe link reset signal is triggered, lock the read and write permissions of the configuration space through the hardware state machine, prohibit any configuration space access operation, ensure the integrity and consistency of the configuration space data during the reset process, and ensure that access is prohibited when the physical layer is not initialized;
[0030] S2, after the PCIe link reset is completed, the hardware state machine monitors the PCIe link status and dynamically unlocks the configuration space access permissions according to the link status;
[0031] S3, timing coordination, ensures timing isolation between the reset signal and configuration space access operations through a hardware state machine, avoiding conflicts. It eliminates metastability risks by synchronizing the reset signal to the system clock domain.
[0032] The specific method for step S2 is as follows:
[0033] Determine the link status. If the link status is stable, unlock the configuration space and allow read and write operations. If the link status is unstable, keep it locked until the link returns to stability. Prevent timing conflicts when switching link rates, such as from 2.5 GT / s to 8 GT / s.
[0034] The specific method for determining the PCIe link reset signal trigger in step S1 is as follows: The hardware state machine samples the reset signal level in real time. When a valid transition edge of the reset signal is detected, it determines that the reset signal is about to be triggered within the subsequent clock cycle. Specifically, this is achieved through the reset signal edge detection circuit of the hardware state machine. The state machine monitors the reset pin level in real time. Once a valid transition edge of the reset signal, such as a falling edge, is detected, it determines that the reset is about to take effect within the subsequent clock cycle and completes the access lock within a very short time window before the signal fully takes effect.
[0035] In step S2, stable states include the LTSSM state machine in the PCIe link being in states L0, L0s, or L1, i.e., stable states that are neither training nor recovery. In these states, secure communication is possible, and the link logic is deterministic, allowing secure access to the configuration space. Unstable states include the PCIe link being in training, recovery, or error handling states. Specifically, the LTSSM is in states such as Detect, Polling, Configuration, Recovery, Loopback, Hot Reset, Disabled, and Link Training. In these states, register contents may be being automatically rewritten by the hardware, and accessing them could lead to conflicts or data errors.
[0036] In step S2, after the reset signal is released, the hardware state machine continuously monitors the real-time status of the PCIe link, including the link training status, link width, and link speed, to determine whether the link has reached a stable working state.
[0037] In step S3, the timing coordination step is achieved by synchronizing the reset signal to the system clock domain. The external asynchronous reset signal is synchronized to the internal clock domain through the reset signal synchronization module, eliminating the metastability problem caused by cross-clock domain transmission.
[0038] The system used in this embodiment to implement the above-described dynamic control method for PCIe configuration space access permissions includes:
[0039] Hardware state machine, which performs state transition control based on PCIe link status signals;
[0040] Configuration space access controller: Works in conjunction with the hardware state machine to lock or unlock access permissions to the configuration space under the instructions of the hardware state machine;
[0041] Reset signal processing unit: includes a reset signal synchronization module and a timing isolation logic module, used to receive external reset signals and trigger the state machine to enter the reset process, while ensuring timing isolation between the reset signal and the configuration space access operation.
[0042] In practical use, a finite state machine is selected as the hardware state machine, and the state transition is based on the PCIe link status signal. The finite state machine includes four states: IDLE, LOCKED, WAITING, and UNLOCKED, and the state transition is performed through the link status signal and the reset signal.
[0043] Specifically, in the four states of the finite state machine, IDLE is the idle state, LOCKED is the locked state, WAITING is the waiting-to-recovery state, and UNLOCKED is the unlocked running state. The input signals of the finite state machine are defined as follows: rst_async_n, which is the external reset signal. rst_async_n == 0 indicates that a reset signal has been received, and rst_async_n == 1 indicates that the reset has ended. ltssm_state is the link training state code from the PCIe link signal, including the stable and unstable states in step S2. The output signals of the finite state machine are defined as follows: cfg_lock_en, which is the configuration space locking enable signal. A high level indicates locking, prohibiting access; a low level indicates unlocking, allowing access.
[0044] The specific conditions and logical relationships for the transitions between the four states of a finite state machine are as follows:
[0045] The state machine initially starts in the IDLE state. When it receives the signal rst_sync == 0, it transitions to the LOCKED state and outputs cfg_lock_en == 1 to lock the memory. If a reset request is received at this point, the configuration space is immediately locked to prevent unauthorized access.
[0046] When the state machine is in the LOCKED state, if it receives rst_sync == 1 and ltssm_state is in an unstable state, it will transition to the next state, WAITING, and output cfg_lock_en == 1 to maintain the lock. At this point, the reset is complete, but the link is still in an unstable state, entering a wait-and-observe period.
[0047] When the state machine is in the LOCKED state, it transitions to the UNLOCKED state upon receiving rst_sync == 1 and ltssm_state being in a stable state. The machine outputs cfg_lock_en == 0 to unlock the connection. At this point, the reset is complete and the link is stable, allowing for direct unlocking.
[0048] When the state machine is in the WAITING state, if ltssm_state is in an unstable state, it continues to maintain the WAITING state and keeps the configuration space locked. The core logic here is that as long as the link has not entered a stable state, no matter how long it takes, the configuration space will always be locked to prevent rate switching conflicts during the recovery period.
[0049] When the state machine is in the WAITING state, if ltssm_state is in a stable state and the stable duration is greater than the threshold time T_th, a state transition occurs. The next state is the UNLOCKED state, which outputs cfg_lock_en == 0 to unlock the connection. If the link is detected to have entered a stable state and maintained it for more than the threshold time T_th, it is confirmed to be working stably, and the configuration space is unlocked. The threshold time T_th is 1-2 μs, used to eliminate glitches.
[0050] When the state machine is in the UNLOCKED unlocked running state, a state transition occurs when rst_sync == 0, indicating that a reset signal has been received again. The next state is the LOCKED locked state, and cfg_lock_en == 1 is output to lock the connection. If a reset occurs again during operation, the lock is immediately re-locked until the reset is complete and the link returns to a stable state.
[0051] The hardware state machine, configuration space access controller, and reset signal processing unit are integrated in the same clock domain of the PCIe device master control chip, and communication between modules is achieved through the register interface.
[0052] The specific methods for verifying and testing the control method of this application are as follows: Functional verification: The behavior of the state machine under reset signal triggering and link state change scenarios is verified through a simulation test platform to ensure the locking / unlocking timing requirements of configuration space access permissions. Timing verification: Timing analysis tools are used to check the setup / hold time of the output signal of the reset signal synchronization module and the system clock to ensure that there is no metastability risk in cross-clock domain transmission. Performance testing: The power consumption, response latency, and link recovery time of the system during reset are tested in a real PCIe link environment to verify the effect of dynamic control on improving system efficiency.
[0053] Verification has shown that the method of this invention achieves timing coordination between reset signals and configuration space access through a hardware state machine, resolving timing conflicts and insufficient flexibility issues in existing technologies. Compared to existing static control methods, it ensures data consistency and improves system stability and reliability.
Claims
1. A method for dynamically controlling PCIe configuration space access permissions, characterized in that: Includes the following steps: S1, before the PCIe link reset signal is triggered, lock the read and write permissions of the configuration space through the hardware state machine; S2, after the PCIe link reset is completed, the hardware state machine monitors the PCIe link status and dynamically unlocks the configuration space access permissions according to the link status; S3, timing coordination, ensures timing isolation between reset signals and configuration space access operations through a hardware state machine; The specific method for step S2 is as follows: Determine the link status. If the link status is stable, unlock the configuration space and allow read and write operations. If the link status is unstable, keep it locked until the link becomes stable.
2. The method for dynamic control of PCIe configuration space access permissions according to claim 1, characterized in that: The specific method for determining the PCIe link reset signal before step S1 is as follows: The hardware state machine samples the level of the reset signal in real time, and when a valid transition edge of the reset signal is captured, it determines that the reset signal is about to be triggered in the subsequent clock cycle.
3. The method for dynamic control of PCIe configuration space access permissions according to claim 1, characterized in that: In step S2, the stable state includes the LTSSM state machine in the PCIe link being in states L0, L0s, and L1. Unstable states include PCIe links that are in the process of training, recovering, or error handling.
4. The method for dynamic control of PCIe configuration space access permissions according to claim 1, characterized in that: In step S2, after the reset signal is released, the hardware state machine continuously monitors the real-time status of the PCIe link, including the link training status, link width, and link speed, to determine whether the link has reached a stable working state.
5. The method for dynamically controlling PCIe configuration space access permissions according to claim 1, characterized in that: In step S3, the timing coordination step is achieved by synchronizing the reset signal to the system clock domain. The external asynchronous reset signal is synchronized to the internal clock domain through the reset signal synchronization module, thereby eliminating the metastability problem caused by cross-clock domain transmission.
6. A dynamic control system for PCIe configuration space access permissions, used to implement the dynamic control method for PCIe configuration space access permissions according to any one of claims 1-5, characterized in that: The system includes: Hardware state machine, which performs state transition control based on PCIe link status signals; Configuration space access controller: Locks or unlocks access permissions to the configuration space under hardware state machine instructions; Reset signal processing unit: includes a reset signal synchronization module and a timing isolation logic module, used to receive external reset signals and trigger the state machine to enter the reset process, while ensuring timing isolation between the reset signal and the configuration space access operation.
7. A dynamic control system for PCIe configuration space access permissions according to claim 6, characterized in that: The hardware state machine is a finite state machine, and the state transition is based on the PCIe link status signal. The finite state machine includes four states: IDLE, LOCKED, WAITING, and UNLOCKED, and the state transition is performed through the link status signal and the reset signal.
8. A dynamic control system for PCIe configuration space access permissions according to claim 6, characterized in that: The hardware state machine, configuration space access controller, and reset signal processing unit are integrated in the same clock domain of the PCIe device main control chip, and communication between modules is achieved through the register interface.