Integrated parallel-serial conversion interface circuit
By integrating a parallel-to-serial conversion interface circuit, combined with a data gating shift register, a data memory, and a cyclic shift register, the problems of bit errors and missing codes caused by high-frequency clock phase mismatch are solved, enabling direct and high-speed data drive output and improving signal quality and adaptability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- YUNNAN GUANGYI HONGXIN TECHNOLOGY CO LTD
- Filing Date
- 2025-11-28
- Publication Date
- 2026-04-28
AI Technical Summary
In the prior art, data transmission interfaces are prone to bit errors or missing bits in the output data when there is a phase mismatch in the high-frequency clock, and the differential signal quality and driving capability are insufficient, affecting the eye diagram quality of the output signal.
An integrated parallel-to-serial conversion interface circuit is adopted. By combining a data gating shift register, a data memory, a circular shift register, and a timing control module, the parallel-to-serial conversion operation is directly integrated and simplified into a data output interface circuit. This avoids the missing code or error code problems introduced by the parallel-to-serial conversion circuit, and the parallel-to-serial conversion is completed directly through the data output circuit.
It enables direct, high-speed data drive output, simplifies the design process, avoids bit errors and missing codes, and improves the quality and adaptability of the output signal.
Smart Images
Figure CN121939985A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic circuits, and in particular to an integrated parallel-to-serial conversion interface circuit. Background Technology
[0002] Today, infrared readout circuits (ROIC) and CMOS image sensors (CIS) are widely used in the imaging field. As these circuits demand larger array sizes and higher frame rates, the amount of data they need to output has increased significantly. Therefore, the matching data transmission interface circuits need to have better versatility and faster transmission rates.
[0003] In existing technologies, data transmission interfaces typically use a timing control module to control a data gating shift register to select a set of "parallel" digital signals to be output. These "parallel" signals are then converted into "serial" signals via a parallel-to-serial conversion circuit. The "serial" signals are then converted into differential signals via a driver circuit, which simultaneously enhances the signal driving capability to drive the LVDS / CML circuit. Finally, the signals are output through the LVDS / CML transmission interface. The above process is usually divided into two groups that alternate during the "parallel" to "serial" conversion to speed up the output transmission rate.
[0004] However, the need for higher data throughput and better circuit adaptability places stricter requirements on the phase of the high-frequency clock during the parallel-to-serial conversion process. Phase mismatch of the high-frequency clock during the alternating parallel-to-serial conversion will lead to bit errors or missing bits in the output data. Furthermore, it places stringent requirements on the quality of the differential signal output by the drive circuit and its driving capability. A large phase difference in the differential signal or insufficient driving capability will affect the quality of the output signal eye diagram.
[0005] Therefore, it is necessary to provide a novel parallel-to-serial conversion circuit to solve the aforementioned problems existing in the prior art. Summary of the Invention
[0006] The purpose of this invention is to provide an integrated parallel-to-serial conversion interface circuit that cleverly integrates parallel-to-serial conversion operations into the data output interface circuit, thereby achieving direct and high-speed output of digital signals.
[0007] The technical solution proposed in this invention is: an integrated parallel-to-serial conversion interface circuit, comprising a data gating shift register, a data memory, a circular shift register, a data output circuit, and a timing control module. The input terminal of the data memory receives data to be read through the data gating shift register, and the output terminal of the data memory is directly connected to the data output circuit. The circular shift register is connected to both the data memory and the data output circuit. The data gating shift register includes n registers, sequentially corresponding to addresses 0, 1, 2, 3…n, where n is the same as the total number of received parallel data sets. The first register preferentially generates a gating signal controlled by the timing control module, and then shifts the gating signal sequentially according to the clock provided by the timing control module to achieve sequential gating.
[0008] The data memory has two sets, using a RAM structure. The number of bits in each data memory set is equal to the number of bits n of data to be read. There are two sets of n-bit data memories, RAM_A and RAM_B. A data selection shift register controls the signal establishment of one set of n-bit data to be read in front of RAM_A or RAM_B, becoming the input signal for the RAM. The RAM output signal D... <1> D <2> ...D <n>Connect directly to the data output circuit and wait for logic judgment.
[0009] The circular shift register consists of a group of 2n-bit shift registers connected first to last, with the number of bits being twice the number of data to be read (2n bits). These registers are arranged sequentially and connected first to last to form a circular link. The circular shift register can provide 2n enable signals sequentially. The circular shift register receives the EN signal generated by the timing control module, causing the first shift register to output signal Q. <1> Set the output signal of the shift register to "1", set the output signal of the other shift registers to "0", and then perform the shift operation controlled by the CLK signal, sequentially setting the output signal of the shift register to "1". <2> Q <3> ...When Q<2n> is set to "1", only one bit of the output signal is set to "1", and the signal Q... <1> Q <2> ...Q<2n> is directly connected to the data output circuit for logical judgment; the cyclic shift register generates LATCH_A and LATCH_B signals to control the data establishment (latching) time of RAM_A and RAM_B.
[0010] The data output circuit consists of a pull-up transistor, a switching transistor controlled by the logic of the signal to be read from the data memory, and a switching transistor controlled by the output signal of the circular shift memory. Using half of the circuit allows for single-channel signal output, while using the entire circuit allows for differential signal output. The data output circuit can operate in the 0.6V voltage range. The data output circuit receives control logic with a default output value of "1" determined by the pull-up transistor, and the output signal D provided by the RAM memory. <1> D <2> ...The control logic of D<2n> and the Q bit provided by the circular shift register have one and only one bit set to "1" <1> Q <2> ...the loop control logic of Q<2n>, through Q <1> Q <2> ...The loop control logic of Q<2n> determines that only 1 bit of the circuit has the possibility of being pulled down to "0", while the rest are in a high impedance state.
[0011] The timing control module is connected to and controls each register in the data gating shift register and the circular shift register, as well as the timing logic between the data gating shift registers and the circular shift registers. In the data gating shift registers, the gating time is controlled by the timing control module, and the gating times of the registers are not the same. During the selection process, it must be ensured that multiple registers at different addresses are not simultaneously in the gating state. The selected data to be read is alternately stored in two sets of data memories. The circular shift register receives the CLK signal from the timing control module to control the shift operation, sequentially adjusting the Q signal. <2> Q <3> ... Set Q<2n> to "1".
[0012] The integrated parallel-to-serial conversion interface circuit provided by this invention cleverly integrates the parallel-to-serial conversion operation into the data output interface circuit, greatly simplifying the conventional design process of first performing parallel-to-serial conversion, then single-ended to differential conversion, and finally outputting through the data interface. It avoids the missing code or bit error problems introduced by the parallel-to-serial conversion circuit, and eliminates the need for the driver circuit to perform single-ended to differential conversion on the data, so that the data can directly complete the "parallel" to "serial" conversion at the output interface, realizing direct and high-speed drive output of data. Attached Figure Description
[0013] Figure 1 Schematic diagram of existing data transmission interface circuit Figure 2 Schematic diagram of the integrated parallel-to-serial conversion interface circuit for data transmission of this invention. Figure 3 The diagram below shows a schematic of a circular shift register circuit. Figure 4 Schematic diagram of the data output circuit of this invention Detailed Implementation
[0014] The technical solution and advantages of the present invention will be further described below with reference to the accompanying drawings and embodiments. In the prior art, the data transmission interface circuit is as follows: Figure 1 As shown, the timing control module typically controls the data gating shift register to select a group of "parallel" digital signals to be output. This group of "parallel" signals is then converted to "serial" signals via a parallel-to-serial converter circuit. Next, the "serial" signals are converted to differential signals by a driver circuit, simultaneously enhancing the signal driving capability to drive the LVDS / CML circuit. Finally, the output is transmitted through the LVDS / CML interface. The above process is usually performed alternately in two groups during the "parallel" to "serial" conversion to accelerate the output transmission rate.
[0015] However, the need for higher data throughput and better circuit adaptability places stricter requirements on the phase of the high-frequency clock during the "parallel" to "serial" conversion process. Phase mismatch of the high-frequency clock during the alternating "parallel" to "serial" conversion will cause bit errors or missing bits in the output data. Furthermore, it places stringent requirements on the quality of the differential signal output by the driver circuit and its driving capability. A large phase difference in the differential signal or insufficient driving capability will affect the quality of the output signal eye diagram.
[0016] See Figure 2 This invention provides an integrated parallel-to-serial conversion interface circuit for data transmission, used for data transmission of chips such as ROIC and CIS.
[0017] First, the data to be read is selected by a data strobe shift register, which is usually composed of multiple columns of registers arranged sequentially, corresponding to addresses 0, 1, 2, 3...n in order from bottom to top or from left to right. It can also be set by the user according to the actual situation.
[0018] In the specific implementation process, the first register first generates the strobe signal controlled by the timing control module, and then shifts the strobe signal sequentially according to the clock provided by the timing control module, ultimately achieving sequential strobe effect. During the strobe process, it must be ensured that multiple address registers are not in the strobe state at the same time, and the strobe data to be read will be alternately stored in the two sets of data memories.
[0019] The data storage used in this invention can adopt a conventional RAM structure. Its storage bits are determined by the number of bits in each group of data to be read. Assuming each group of data to be read has n bits, two n-bit data storage units, RAM_A and RAM_B, are required. The data strobe shift register sequentially selects each group of data to be read, IN. <1> IN <2> ...IN <n>As input signals to RAM; the circular shift register generates LATCH_A and LATCH_B signals to control the data setup (latching) timing of RAM_A and RAM_B; the output signal D <1> D <2> ...D <n>Connect directly to the data output circuit and wait for logic judgment.
[0020] In practical implementation, the data selection shift register controls a group of n bits of data to be read to complete signal establishment in front of RAM_A or RAM_B memory; after the input signal is established, the data is latched by receiving the LATCH_A or LATCH_B signal provided by the circular shift register; the stored signal is directly connected to the data output circuit, waiting for logical judgment. For ease of understanding, assume that the output signal of RAM_A memory is D. <1> D <2> ...D <n>The output signal of RAM_B memory is D.<n+1> D<n+2> ...D<2n>.
[0021] See Figure 3 The schematic diagram of the circular shift register circuit of the present invention consists of a group of 2n-bit shift registers with the first bit connected together. The number of bits is twice that of each group of data to be read, i.e., 2n bits.
[0022] In the specific implementation process, the cyclic shift register receives the EN signal generated by the timing control module, causing the first shift register to output signal Q. <1> Set the output signal of the shift register to "1", and set the output signals of the other shift registers to "0"; then, the shift operation is controlled by the CLK signal, sequentially setting the output signals of the Q registers to "1". <2> Q <3> ...Q<2n> is set to "1"; as known from the previous text, there is exactly one bit in the output signal that is set to "1".
[0023] The generated signal is directly connected to the data output circuit, where it, together with the RAM memory output signal, determines the final output signal logic. Simultaneously, it selects an appropriate circular shift register output signal to serve as LATCH_A and LATCH_B signals. That is, assuming the RAM_A memory output signal D... <1> D <2> ...D <n>Q generated by the circular shift register <1> Q <2> ...Q <n>When the signal is used for logical judgment in the data output circuit, the Q value can be utilized. <n-1>The signal also serves as the LATCH_B signal for RAM_B memory; conversely, it is assumed that the output signal D generated by RAM_B memory...<n+1> D<n+2> ...Q generated by D<2n> and the circular shift register<n+1> Q<n+2> ...When the Q<2n> signal is used for logical judgment in the data output circuit, the Q<2n-1> signal can also be used as the LATCH_B signal of the RAM_B memory. The specific choice depends on the user's actual application.
[0024] Therefore, the use of a circular shift register to sequentially provide 2n enable signals is another advantageous feature of this invention. This not only forms the basis for the integration of parallel-to-serial conversion and output interface circuitry in this invention, but also offers high scalability, applicable to commonly used parallel-to-serial conversion circuits. For example, this operation can be used to control the output of 2n RAM memories, serving as a novel approach to parallel-to-serial conversion. Furthermore, the use of a circular shift register to provide the LATCH signal reserves sufficient time for data signal establishment and reduces overlap or omission during the alternation of two sets of data, which is also an advantageous feature of this invention.
[0025] See Figure 4 The schematic diagram of the data output circuit of this invention consists of a pull-up transistor, a switching transistor controlled by the logic of the signal to be read from the RAM memory, and a switching transistor controlled by the output signal of the circular shift memory. When only half of the circuit is used, single-channel signal output can be realized. When the entire circuit is used, differential signal output can be realized. The data output circuit can operate in the 0.6V voltage domain.
[0026] In practical implementation, the data output circuit receives control logic with a default output value of "1" determined by the pull-up transistor, and the RAM memory provides the output signal D. <1> D <2> ...The control logic of D<2n> and the Q bit provided by the circular shift register have one and only one bit set to "1" <1> Q <2> ...the loop control logic of Q<2n>. Through Q... <1> Q <2> ...The loop control logic of Q<2n> determines that there is exactly one possible data bit that is pulled down to "0", while the rest are in a high-impedance state. Assume the current Q... <1> The logic is set to "1", and then ANDed with Q. <1> Matching D <1> The signal logic is used to determine whether the output data should be pulled down to "0".
[0027] The data output circuit can directly output single-channel data from the data to be output by sequentially making 2n logic judgments; if the logic of the data to be output is inverted, it can directly output differential data. The data output circuit is the core of this invention, effectively combining the parallel-to-serial conversion operation with the data output interface into one unit. < / n> < / n> < / n> < / n> < / n> < / n>
Claims
1. An integrated parallel-to-serial conversion interface circuit, characterized in that: It consists of a data gating shift register, a data memory, a circular shift register, a data output circuit, and a timing control module. The input terminal of the data memory receives the data to be read through the data gating shift register, and the output terminal of the data memory is directly connected to the data output circuit. The circular shift register is connected to both the data memory and the data output circuit.
2. The integrated parallel-to-serial conversion interface circuit according to claim 1, characterized in that: The data gating shift register includes n registers, which correspond to addresses 0, 1, 2, 3...n in sequence. The number n is the same as the total number of groups of parallel data received. The first register first generates the gating signal controlled by the timing control module, and then shifts the gating signal sequentially according to the clock provided by the timing control module to achieve sequential gating.
3. The integrated parallel-to-serial conversion interface circuit according to claim 1, characterized in that: The data memory has two sets, using a RAM structure. The number of bits in each data memory set is equal to the number of bits n of data to be read. There are two sets of n-bit data memories, RAM_A and RAM_B. A data selection shift register controls the signal establishment of one set of n-bit data to be read in front of RAM_A or RAM_B, becoming the input signal for the RAM. The RAM output signal D... <1> D <2> ...D <n> Connect directly to the data output circuit and wait for logic judgment.< / n> 4. The integrated parallel-to-serial conversion interface circuit according to claim 1, characterized in that: The circular shift register consists of a group of 2n-bit shift registers connected first to last. The number of bits is twice that of each group of data to be read, i.e., 2n bits. These registers are arranged in sequence and connected first to last to form a circular link. The circular shift register can provide 2n enable signals in sequence. The cyclic shift register receives the EN signal generated by the timing control module, causing the first shift register to output signal Q. <1> Set the output signal of the shift register to "1", set the output signal of the other shift registers to "0", and then perform the shift operation controlled by the CLK signal, sequentially setting the output signal of the shift register to "1". <2> Q <3> ...When Q<2n> is set to "1", only one bit of the output signal is set to "1", and the signal Q... <1> Q <2> ...Q<2n> is directly connected to the data output circuit for logical judgment; The circular shift register generates LATCH_A and LATCH_B signals to control the data setup (latch) timing of RAM_A and RAM_B.
5. The integrated parallel-to-serial conversion interface circuit according to claim 1, characterized in that: The data output circuit consists of a pull-up transistor, a switching transistor controlled by the logic of the signal to be read from the data memory, and a switching transistor controlled by the output signal of the circular shift memory. Using half of the circuit can realize single-channel signal output, and using the whole circuit can realize differential signal output. The data output circuit can operate in the 0.6V voltage domain. The data output circuit receives control logic with a default output value of "1" determined by the pull-up transistor, and the output signal D provided by the RAM memory... <1> D <2> ...The control logic of D<2n> and the Q bit provided by the circular shift register have one and only one bit set to "1" <1> Q <2> ...the loop control logic of Q<2n>, through Q <1> Q <2> ...The loop control logic of Q<2n> determines that only 1 bit of the circuit has the possibility of being pulled down to "0", while the rest are in a high impedance state.
6. The integrated parallel-to-serial conversion interface circuit according to claim 1, characterized in that: The timing control module is connected to each register in the data gating shift register and the circular shift register, and controls the timing logic between the data gating shift register and the circular shift register; In the data gating shift register, the gating time of the register is controlled by the control timing module, and the gating times of the registers are not the same. During the gating process, it must be ensured that multiple address registers are not in the gating state at the same time. The gated data to be read is alternately stored in two sets of data memory. The circular shift register receives the CLK signal from the timing control module to control the shift operation, sequentially adjusting the Q signal... <2> Q <3> ... Set Q<2n> to "1".