High-speed image acquisition system and method for multi-task flight test platform

Abstract

The invention relates to the technical field of high-speed image acquisition and transmission, and provides a high-speed image acquisition system of a multi-task flight test platform, which comprises two camera modules for acquiring visible light color images and completing photoelectric conversion through an image sensor, sending the obtained digital image data into a first programmable logic device, and outputting two paths of high-definition video signals through an HD-SDI (High Definition-Serial Digital Interface) after the first programmable logic device performs format conversion and image preprocessing on the digital image data; and the encoder module is used for receiving the two paths of high-definition video signals output by the two camera modules, performing compression encoding on the two paths of video signals and realizing high-speed transmission of image encoding data. The defects that an existing flight test image collecting device is low in frame frequency and transmission speed, and high-dynamic flight process details are difficult to record under the limited bandwidth condition are overcome.

Description

Technical Field

[0001] This invention relates to the technical field of high-speed image acquisition and transmission, and particularly to a high-speed image acquisition system and method for a multi-mission flight test platform. Specifically, it is an image acquisition technology based on H.265 encoding and SRIO high-speed communication interface suitable for multi-mission flight test platforms. This technology features high-quality images, high frame rate, and high transmission rate, making it suitable for recording the separation process and key mechanism actions of launch vehicles or other multi-mission flight test platforms during flight. Background Technology

[0002] In recent years, with the continuous development of aerospace technology and high-dynamic flight test technology, the application scope of launch vehicles in missions such as satellite launch, reentry and return, and flight testing has been continuously expanding. To analyze and evaluate the entire flight process, the demand for observation and recording of the flight process is also increasing. Recording the flight process using video equipment has advantages such as dynamic visualization and a large amount of information, thus becoming one of the important technical means in flight test missions.

[0003] Meanwhile, with the increasing complexity of the internal electrical systems of flight test platforms and the continuous improvement of flight speeds, especially under high-maneuverability and hypersonic conditions, traditional low-frame-rate, low-bandwidth image acquisition devices are no longer sufficient to meet the demand for detailed recording of separation events, attitude changes, and key mechanism movements. Most existing flight test observation equipment still operates at relatively low frame rates (e.g., 25fps) and low data transmission rates, making it difficult to clearly record detailed information about the observed targets during high-speed flight of the flight test platform. This limits the scope of the observation data and hinders in-depth research into flight action mechanisms and state change processes.

[0004] Furthermore, constrained by the power supply, size, weight, and communication bandwidth of the flight test platform, the image acquisition device needs to complete the acquisition and transmission of multiple high-definition image data channels within a small size and limited power consumption. How to achieve reliable transmission of two high-definition, high-frame-rate video data channels under limited bandwidth, while simultaneously achieving miniaturization, lightweight design, and low power consumption, is a pressing problem to be solved in current engineering applications.

[0005] Therefore, in order to meet the needs of flight test missions, there is an urgent need for an image acquisition device that combines high image quality, high frame rate and high transmission rate, can achieve stable transmission of two channels of high-definition dynamic image data under limited bandwidth channel conditions, and has engineering application characteristics such as miniaturization, lightweight and low power consumption, so as to meet the requirements of multi-mission flight test platforms for multi-view recording and analysis of flight processes under complex working conditions. Summary of the Invention

[0006] To address the aforementioned problems, the present invention aims to provide a high-speed image acquisition system and method for a multi-mission flight test platform. This system overcomes the shortcomings of existing flight test image acquisition devices, such as low frame rate, slow transmission speed, and difficulty in recording high-dynamic flight process details under limited bandwidth conditions. By employing a split structure, dual high-frame-rate camera acquisition, H.265 encoding compression, and an SRIO high-speed communication interface based on an optical fiber module, it achieves the encoding and high-speed transmission of two channels of high-definition, high-frame-rate video data.

[0007] The above-mentioned objective of this invention is achieved through the following technical solutions: A high-speed image acquisition system for a multi-mission flight test platform, comprising: Two camera modules are used to acquire visible light color images and perform photoelectric conversion through image sensors. The obtained digital image data is sent to a first programmable logic device. After the first programmable logic device performs format conversion and image preprocessing on the digital image data, it outputs two high-definition video signals through an HD-SDI interface. The encoder module is used to receive two high-definition video signals output from the two camera modules, compress and encode the two video signals, and achieve high-speed transmission of image encoded data; The encoder module includes a second programmable logic device, a video encoding processing chip, and an SRIO high-speed communication interface. The second programmable logic device is used to receive two high-definition video signals from the two camera modules through the HD-SDI interface, synchronize and time-match the signals, and preprocess them. The preprocessed image data is then sent to the video encoding processing chip for video compression encoding based on the H.265 standard. The second programmable logic device is also used to perform protocol framing on the encoded bitstream output by the video encoding processing chip and send the encoded bitstream to an external device through the SRIO high-speed communication interface.

[0008] Furthermore, each of the camera modules includes an optical lens, an image sensor, and the first programmable logic device. The optical lens is used to image targets in the environment surrounding the flight test platform onto the image sensor. The image sensor is used to receive the light signal imaged by the optical lens and convert it into digital image data with a first resolution and a first frame rate. The first programmable logic device is used to perform data format conversion and image preprocessing on the digital image data.

[0009] Furthermore, the resolution of the digital image data output by the image sensor is 1280×720, and the frame rate is not less than 120fps. The first resolution and the first frame rate are configured to meet the imaging requirements of the flight test platform for recording the details of target motion.

[0010] Furthermore, the image preprocessing performed by the first programmable logic device is a preprocessing suitable for the space environment, specifically including at least one of bad pixel correction, simple noise reduction, and gamma correction, and the first programmable logic device outputs the processed serial digital video signal to the encoder module through the HD-SDI interface.

[0011] Furthermore, the video encoding processing chip is connected to the second programmable logic device via a high-speed video interface, and is used to receive two channels of high-definition video data and encode and compress them based on the H.265 standard, outputting the compressed video stream. The second programmable logic device is configured with a buffer unit and a protocol control unit. The buffer unit is connected between the video encoding processing chip and the protocol control unit, and is used to buffer the encoded stream output by the video encoding processing chip and perform protocol framing. The protocol control unit is connected to the SRIO high-speed communication interface, and is used to encapsulate the encoded stream into data frames conforming to the SRIO protocol, and send control signals to the host computer or recording system through the SRIO high-speed communication interface based on the fiber optic module.

[0012] Furthermore, the SRIO high-speed communication interface is a serial high-speed communication interface implemented based on an optical fiber module. Its physical layer transmission rate is configured to be no less than a preset transmission rate threshold R. The preset transmission rate threshold R is matched with the resolution, frame rate and coding rate of the two images to ensure real-time transmission of the two encoded image data streams under limited bandwidth channel conditions.

[0013] Furthermore, the system adopts a split-type structure. The two camera modules are connected to the encoder module via high-frequency cables. The encoder module provides power to the two camera modules via the high-frequency cables, enabling the two camera modules to be deployed at different observation positions or orientations on the flight test platform in different flight test application scenarios. This allows for the simultaneous acquisition of multi-view, high-frame-rate images of the flight test platform during flight, including the separation process of the main stage and booster stage, the deployment of key mechanisms, and attitude changes. The encoder modules are centrally installed in locations suitable for wiring and heat dissipation. They are connected to the host computer or recording subsystem via an SRIO interface through optical fiber to achieve synchronous recording of two observation videos. Each module in the system uses miniaturized, low-power devices. Power management and thermal design can be performed according to the specific constraints of the flight test platform. Furthermore, the image resolution, frame rate, encoding bit rate, and interface configuration can be adjusted according to actual mission requirements.

[0014] A high-speed image acquisition method for a multi-mission flight test platform, employing a high-speed image acquisition system as described above, includes: S1: The two camera modules simultaneously acquire visible light color images, convert the acquired light signals into digital image data through their respective image sensors, and send the digital image data to the corresponding first programmable logic device; S2: The first programmable logic device performs format conversion and image preprocessing on the received digital image data, and outputs two high-definition video signals through the HD-SDI interface after processing; S3: The second programmable logic device of the encoder module receives the two high-definition video signals through the HD-SDI interface, and performs synchronization, timing adaptation, and preprocessing on the two high-definition video signals; S4: The second programmable logic device sends the two high-definition image data channels, after synchronization, timing adaptation, and preprocessing, to the video encoding processing chip; S5: The video encoding processing chip performs video compression encoding on the two channels of high-definition image data based on the H.265 standard, and outputs the encoded bitstream; S6: The second programmable logic device performs protocol framing on the encoded bitstream to form a data frame conforming to the SRIO protocol; S7: The data frame conforming to the SRIO protocol is sent to an external device through the SRIO high-speed communication interface to complete the high-speed image acquisition of the multi-mission flight test platform.

[0015] A computer device, characterized in that it includes a memory and one or more processors, wherein the memory stores computer code, and when the computer code is executed by the one or more processors, the one or more processors perform the method as described above.

[0016] A computer-readable storage medium storing computer code that, when executed, performs the method described above.

[0017] Compared with the prior art, the present invention has at least one of the following beneficial effects: (1) Using the SRIO high-speed communication interface based on fiber optic modules, the communication transmission rate can reach more than 3Gbps when the communication bandwidth allows. Even under limited bandwidth channels, it can still achieve stable transmission of two channels of high-definition dynamic image data with a resolution of 1280×720 and a frame rate of not less than 120fps; (2) The two camera modules adopt a high frame rate design, which can observe targets with high speed and record detailed information of the flight test platform during the separation process and flight maneuvers, resulting in better image visual effects; (3) The device can record high-definition color image data and compress it based on the H.265 standard. The image encoding rate and compression quality can be configured and adjusted according to the link bandwidth and task requirements, resulting in high bandwidth utilization. (4) The device adopts a split structure design. The system contains two high frame rate cameras. In actual use, it can simultaneously meet the usage requirements of two observation directions or observation scenarios. It is small in size, light in weight, and low in power consumption, making it easy to install, integrate, and expand applications on the flight test platform. Attached Figure Description

[0018] Figure 1 This is a block diagram of the overall structure of the high-speed image acquisition system of the multi-mission flight test platform of the present invention; Figure 2 This is a schematic diagram of the camera module structure of the present invention; Figure 3 This is a schematic diagram of the encoder module structure of the present invention; Figure 4 This is an overall flowchart of the high-speed image acquisition method for the multi-mission flight test platform of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms "a," "an," "the," and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0021] First Embodiment like Figure 1 As shown, this embodiment provides a high-speed image acquisition system for a multi-mission flight test platform, including: Two camera modules are used to acquire visible light color images and perform photoelectric conversion through image sensors. The obtained digital image data is sent to a first programmable logic device. After the first programmable logic device performs format conversion and image preprocessing on the digital image data, it outputs two high-definition video signals through an HD-SDI interface. The encoder module is used to receive two high-definition video signals output from the two camera modules, compress and encode the two video signals, and achieve high-speed transmission of image encoded data; Among them, such as Figure 3 As shown, the encoder module includes a second programmable logic device, a video encoding processing chip, and an SRIO high-speed communication interface. The second programmable logic device is used to receive two high-definition video signals from the two camera modules through the HD-SDI interface, perform synchronization and timing adaptation of the signals, and preprocess them. The preprocessed image data is then sent to the video encoding processing chip for video compression encoding based on the H.265 standard. The second programmable logic device is also used to perform protocol framing on the encoded bitstream output by the video encoding processing chip and send the encoded bitstream to an external device through the SRIO high-speed communication interface.

[0022] The system adopts a split layout of dual camera modules + single encoder module to adapt to the multi-view observation requirements of multi-mission flight test platforms: the two camera modules synchronously acquire visible light color images, which are then converted by the image sensor through photoelectric conversion. The first programmable logic device performs preprocessing for space environment adaptation (such as bad pixel correction and format conversion), and then outputs standardized high-definition video signals through the HD-SDI interface; the encoder module serves as the core processing unit (its internal structure is as follows...). Figure 3 As shown, after receiving two video signals through the HD-SDI interface, the second programmable logic device realizes signal synchronization and timing alignment, and then sends them to the video encoding processing chip for H.265 standard compression encoding. Finally, after the second programmable logic device performs protocol framing, the encoded bitstream is stably transmitted to the external host computer or recording device through the SRIO high-speed communication interface, taking into account both high frame rate, high-definition image quality and reliable transmission under limited bandwidth.

[0023] Furthermore, such as Figure 2 As shown, each of the camera modules includes an optical lens, an image sensor, and the first programmable logic device. The optical lens is used to image targets in the environment surrounding the flight test platform onto the image sensor. The image sensor is used to receive the light signal imaged by the optical lens and convert it into digital image data with a first resolution and a first frame rate. The first programmable logic device is used to perform data format conversion and image preprocessing on the digital image data.

[0024] Each camera module achieves high-definition image acquisition and preliminary processing through the collaborative work of an optical lens, an image sensor, and a first programmable logic device: the optical lens accurately captures the target scene around the flight test platform and images it onto the surface of the image sensor. The image sensor converts this light signal into digital image data that meets the requirements for detailed recording of flight test data (resolution and frame rate adapted to target motion observation). Subsequently, the first programmable logic device performs targeted processing on the digital image data. This includes data format conversion to adapt to subsequent transmission interfaces and image preprocessing suitable for the space environment (such as bad pixel correction and noise reduction). Finally, a standardized serial digital video signal is output through the HD-SDI interface, laying the foundation for subsequent encoding and transmission by the encoder module.

[0025] Furthermore, the resolution of the digital image data output by the image sensor is 1280×720, and the frame rate is not less than 120fps. The first resolution and the first frame rate are configured to meet the imaging requirements of the flight test platform for recording the details of target motion.

[0026] The digital image data output by the image sensor is explicitly configured with a high resolution of 1280×720 and a high frame rate of no less than 120fps. This parameter combination is specifically adapted to the needs of flight test scenarios. The 1280×720 resolution ensures the clarity of image details, while the 120fps high frame rate far exceeds the frame rate level of traditional observation equipment. It can accurately capture rapidly changing motion details such as the separation process and key mechanism actions during high-speed flight of the aircraft, ensuring that the imaging effect fully meets the core requirements of the flight test platform for recording target motion details and avoiding the loss of key information due to insufficient frame rate or resolution.

[0027] Furthermore, the image preprocessing performed by the first programmable logic device is a preprocessing suitable for the space environment, specifically including at least one of bad pixel correction, simple noise reduction, and gamma correction, and the first programmable logic device outputs the processed serial digital video signal to the encoder module through the HD-SDI interface.

[0028] The image preprocessing of the first programmable logic device is specifically designed for the characteristics of the space environment. Specifically, it solves the image quality interference problems that may occur in the space environment through one or more methods such as bad pixel correction, simple noise reduction, and gamma correction, and ensures the validity of image data. At the same time, the image data after format conversion and preprocessing will be accurately transmitted to the encoder module in the form of serial digital video signal through the HD-SDI interface, providing standardized and high-quality signal input for subsequent encoding compression and high-speed transmission.

[0029] Furthermore, the video encoding processing chip is connected to the second programmable logic device via a high-speed video interface, and is used to receive two channels of high-definition video data and encode and compress them based on the H.265 standard, outputting the compressed video stream. The second programmable logic device is configured with a buffer unit and a protocol control unit. The buffer unit is connected between the video encoding processing chip and the protocol control unit, and is used to buffer the encoded stream output by the video encoding processing chip and perform protocol framing. The protocol control unit is connected to the SRIO high-speed communication interface, and is used to encapsulate the encoded stream into data frames conforming to the SRIO protocol, and send control signals to the host computer or recording system through the SRIO high-speed communication interface based on the fiber optic module.

[0030] The video encoding processing chip establishes a connection with the second programmable logic device through a high-speed video interface. After efficiently receiving two channels of high-definition video data, it completes encoding and compression according to the H.265 standard and outputs the encoded bitstream. The buffer unit on the second programmable logic device is located between the video encoding processing chip and the protocol control unit. It is responsible for temporarily buffering the encoded bitstream to ensure transmission stability. The protocol control unit interfaces with the SRIO high-speed communication interface based on the fiber optic module, encapsulates the encoded bitstream into data frames that conform to the SRIO protocol, and sends control signals to the interface, ultimately realizing reliable transmission of the bitstream to the host computer or recording system.

[0031] Furthermore, the SRIO high-speed communication interface is a serial high-speed communication interface implemented based on an optical fiber module. Its physical layer transmission rate is configured to be no less than a preset transmission rate threshold R. The preset transmission rate threshold R is matched with the resolution, frame rate and coding rate of the two images to ensure real-time transmission of the two encoded image data streams under limited bandwidth channel conditions.

[0032] In this embodiment, the physical layer transmission rate of the SRIO high-speed communication interface is no less than 3Gbps, enabling real-time transmission of two encoded image data streams with a resolution of 1280×720 and a frame rate of no less than 120fps under limited bandwidth channel conditions. The encoding bitrate can be configured according to the actual available bandwidth of the link, the complexity of the image content, and the task requirements to balance image quality and bandwidth utilization.

[0033] The SRIO high-speed communication interface uses fiber optic modules to build a serial communication architecture. Its physical layer transmission rate is not only set to be no less than a preset threshold R (which needs to be precisely matched with the resolution, frame rate and encoding bitrate of the two images), but in this embodiment it is explicitly set to be no less than 3Gbps. It can stably achieve real-time transmission of two 1280×720 resolution encoded image data with a frame rate of no less than 120fps under limited bandwidth channels. At the same time, the encoding bitrate can be flexibly configured according to the actual available bandwidth of the link, the complexity of the image content and the task requirements, which can both ensure image quality and improve bandwidth utilization.

[0034] Furthermore, the system adopts a split-type structure. The two camera modules are connected to the encoder module via high-frequency cables. The encoder module provides power to the two camera modules via the high-frequency cables, enabling the two camera modules to be deployed at different observation positions or orientations on the flight test platform in different flight test application scenarios. This allows for the simultaneous acquisition of multi-view, high-frame-rate images of the flight test platform during flight, including the separation process of the main stage and booster stage, the deployment of key mechanisms, and attitude changes. The encoder modules are centrally installed in locations suitable for wiring and heat dissipation. They are connected to the host computer or recording subsystem via an SRIO interface through optical fiber to achieve synchronous recording of two observation videos. Each module in the system uses miniaturized, low-power devices. Power management and thermal design can be performed according to the specific constraints of the flight test platform. Furthermore, the image resolution, frame rate, encoding bit rate, and interface configuration can be adjusted according to actual mission requirements.

[0035] The system adopts a split layout design. Two camera modules are connected to the encoder module via a high-frequency cable. The encoder module also powers both camera modules through the same high-frequency cable, allowing them to be flexibly deployed at different observation positions or orientations on the flight test platform according to different flight test scenarios. This enables the system to simultaneously acquire high-frame-rate images of the separation of the main stage and booster stage, the deployment of key mechanisms, and attitude changes during the platform's flight from multiple perspectives. The encoder module is centrally installed in a location that facilitates wiring and heat dissipation. It is connected to the host computer or recording subsystem via an SRIO interface through fiber optic cable to achieve synchronous recording of two video streams. At the same time, all modules of the system use miniaturized, low-power devices, which can be adapted to the constraints of the flight test platform for power management and thermal design. Furthermore, the image resolution, frame rate, encoding bitrate, and interface configuration can be flexibly adjusted according to actual mission requirements.

[0036] Second Embodiment like Figure 4 As shown, this embodiment provides a high-speed image acquisition method for a multi-mission flight test platform, executed using a high-speed image acquisition system of the multi-mission flight test platform as described in the first embodiment, including: S1: The two camera modules simultaneously acquire visible light color images, convert the acquired light signals into digital image data through their respective image sensors, and send the digital image data to the corresponding first programmable logic device; S2: The first programmable logic device performs format conversion and image preprocessing on the received digital image data, and outputs two high-definition video signals through the HD-SDI interface after processing; S3: The second programmable logic device of the encoder module receives the two high-definition video signals through the HD-SDI interface, and performs synchronization, timing adaptation, and preprocessing on the two high-definition video signals; S4: The second programmable logic device sends the two high-definition image data channels, after synchronization, timing adaptation, and preprocessing, to the video encoding processing chip; S5: The video encoding processing chip performs video compression encoding on the two channels of high-definition image data based on the H.265 standard, and outputs the encoded bitstream; S6: The second programmable logic device performs protocol framing on the encoded bitstream to form a data frame conforming to the SRIO protocol; S7: The data frame conforming to the SRIO protocol is sent to an external device through the SRIO high-speed communication interface to complete the high-speed image acquisition of the multi-mission flight test platform.

[0037] A computer-readable storage medium stores computer code that, when executed, performs the methods described above. Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. This program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0038] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0039] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A high-speed image acquisition system for a multi-mission flight test platform, characterized in that... ,include: Two camera modules are used to acquire visible light color images and perform photoelectric conversion through image sensors. The obtained digital image data is sent to a first programmable logic device. After format conversion and image preprocessing of the digital image data, the first programmable logic device outputs two high-definition video signals through an HD-SDI interface. The encoder module is used to receive two high-definition video signals output from the two camera modules, compress and encode the two video signals, and achieve high-speed transmission of image encoded data; The encoder module includes a second programmable logic device, a video encoding processing chip, and an SRIO high-speed communication interface. The second programmable logic device is used to receive two high-definition video signals from the two camera modules through the HD-SDI interface, synchronize and time-match the signals, and preprocess them. The preprocessed image data is then sent to the video encoding processing chip for video compression encoding based on the H.265 standard. The second programmable logic device is also used to perform protocol framing on the encoded bitstream output by the video encoding processing chip and send the encoded bitstream to an external device through the SRIO high-speed communication interface.

2. The high-speed image acquisition system for the multi-mission flight test platform according to claim 1, characterized in that... Each of the camera modules includes an optical lens, an image sensor, and the first programmable logic device. The optical lens is used to image targets in the environment surrounding the flight test platform onto the image sensor. The image sensor is used to receive the light signal imaged by the optical lens and convert it into digital image data with a first resolution and a first frame rate. The first programmable logic device is used to perform data format conversion and image preprocessing on the digital image data.

3. The high-speed image acquisition system of the multi-mission flight test platform according to claim 2, characterized in that... The resolution of the digital image data output by the image sensor is 1280×720, and the frame rate is not less than 120fps. The first resolution and the first frame rate are configured to meet the imaging requirements of the flight test platform for recording the details of target motion.

4. The high-speed image acquisition system of the multi-mission flight test platform according to claim 2, characterized in that... The image preprocessing performed by the first programmable logic device is a preprocessing method suitable for the space environment, specifically including at least one of bad pixel correction, simple noise reduction, and gamma correction, and the first programmable logic device outputs the processed serial digital video signal to the encoder module through the HD-SDI interface.

5. The high-speed image acquisition system for the multi-mission flight test platform according to claim 1, characterized in that... The video encoding processing chip is connected to the second programmable logic device via a high-speed video interface. It receives two channels of high-definition video data and encodes and compresses them based on the H.265 standard, outputting the compressed video stream. The second programmable logic device is configured with a buffer unit and a protocol control unit. The buffer unit is connected between the video encoding processing chip and the protocol control unit. It is used to buffer the encoded stream output by the video encoding processing chip and perform protocol framing. The protocol control unit is connected to the SRIO high-speed communication interface. It is used to encapsulate the encoded stream into data frames conforming to the SRIO protocol and send control signals to the host computer or recording system through the SRIO high-speed communication interface based on the fiber optic module.

6. The high-speed image acquisition system for the multi-mission flight test platform according to claim 1, characterized in that... The SRIO high-speed communication interface is a serial high-speed communication interface implemented based on an optical fiber module. Its physical layer transmission rate is configured to be no less than a preset transmission rate threshold R. The preset transmission rate threshold R is matched with the resolution, frame rate and coding rate of the two images to ensure real-time transmission of the two encoded image data streams under limited bandwidth channel conditions.

7. The high-speed image acquisition system for the multi-mission flight test platform according to claim 1, characterized in that... The system adopts a split structure. The two camera modules are connected to the encoder module via high-frequency cables. The encoder module provides power to the two camera modules via the high-frequency cables, enabling the two camera modules to be deployed at different observation positions or orientations on the flight test platform in different flight test application scenarios. This allows for the simultaneous acquisition of multi-view, high-frame-rate images of the flight test platform during flight, including the separation process of the main stage and booster stage, the deployment of key mechanisms, and attitude changes. The encoder modules are centrally installed in locations suitable for wiring and heat dissipation. They are connected to the host computer or recording subsystem via an SRIO interface through optical fiber to achieve synchronous recording of two observation videos. Each module in the system uses miniaturized, low-power devices. Power management and thermal design can be performed according to the specific constraints of the flight test platform. Furthermore, the image resolution, frame rate, encoding bit rate, and interface configuration can be adjusted according to actual mission requirements.

8. A high-speed image acquisition method for a multi-mission flight test platform, executed using a high-speed image acquisition system of the multi-mission flight test platform as described in any one of claims 1-7, characterized in that... ,include: S1: The two camera modules simultaneously acquire visible light color images, convert the acquired light signals into digital image data through their respective image sensors, and send the digital image data to the corresponding first programmable logic device; S2: The first programmable logic device performs format conversion and image preprocessing on the received digital image data, and outputs two high-definition video signals through the HD-SDI interface after processing; S3: The second programmable logic device of the encoder module receives the two high-definition video signals through the HD-SDI interface, and performs synchronization, timing adaptation, and preprocessing on the two high-definition video signals; S4: The second programmable logic device sends the two high-definition image data channels, after synchronization, timing adaptation, and preprocessing, to the video encoding processing chip; S5: The video encoding processing chip performs video compression encoding on the two channels of high-definition image data based on the H.265 standard, and outputs the encoded bitstream; S6: The second programmable logic device performs protocol framing on the encoded bitstream to form a data frame conforming to the SRIO protocol; S7: The data frame conforming to the SRIO protocol is sent to an external device through the SRIO high-speed communication interface to complete the high-speed image acquisition of the multi-mission flight test platform.

9. A computer device, characterized in that... The system includes a memory and one or more processors, wherein the memory stores computer code that, when executed by the one or more processors, causes the one or more processors to perform the method as described in claim 8.

10. A computer-readable storage medium, characterized in that... The computer-readable storage medium stores computer code, and when the computer code is executed, the method of claim 8 is performed.

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