CPLD (Complex Programmable Logic Device)-based sine and cosine encoder decoding method, equipment and medium

Abstract

The invention discloses a CPLD (Complex Programmable Logic Device)-based sine and cosine encoder decoding method and device and a medium, and the method comprises the steps: executing a signal conditioning action and a dynamic setting action for an original differential signal, and obtaining a standardized setting signal; for an absolute position signal in the setting signal, calculating a corresponding initial absolute position through a preset arc tangent table, and performing scale transformation on the initial absolute position to obtain a corresponding absolute position starting point; and for increment sine and cosine signals in the setting signals, calculating corresponding subdivision position values through a preset arc tangent table, and outputting absolute position information based on a difference value between the subdivision position values at different moments through position integration. According to the invention, the precision is improved, the real-time performance is improved, the dynamic adaptability is enhanced, the system architecture is simplified, the cost is reduced, the reliability and robustness are improved, and the full-band performance is excellent.

Description

CPLD-based sine and cosine encoder decoding methods, equipment, and media Technical Field

[0001] This application relates to the field of signal decoding, specifically to a CPLD-based sine and cosine encoder decoding method, device, and medium. Background Technology

[0002] Sine and cosine encoders, as high-precision position feedback devices, are widely used in servo control systems, CNC machine tools, industrial robots, and precision measuring instruments. Compared with incremental encoders, sine and cosine encoders output continuous sine and cosine analog signals, and through electronic subdivision technology, they can achieve a resolution far exceeding the physical scale line count.

[0003] In traditional solutions, the signal is typically conditioned and then decoded using a microcontroller unit (MCU), digital signal processor (DSP), or application-specific integrated circuit (ASIC) chip. The decoding process uses a comparator to shape the AB small sine and cosine signals into pulse signals, and a coarse calibration is performed using the quadruple frequency pulse method (with an accuracy of 90 degrees within a small sine and cosine cycle). Then, the subdivision angle is calculated and compared with the calibration using the pulse method to finally calculate the encoder's high-precision mechanical subdivision position information.

[0004] However, the traditional methods mentioned above still have some shortcomings: 1. The traditional four-quadrant arctangent calculation method has limited accuracy. This method usually divides 360 degrees into four quadrants and performs arctangent calculation in each quadrant. This method does not make full use of the symmetry of trigonometric functions, resulting in low accuracy of table lookup, especially in the areas around 45 degrees, 135 degrees, 225 degrees, and 315 degrees where the error is relatively large.

[0005] 2. The real-time performance of software-implemented arctangent algorithms is poor. Software algorithms based on MCUs or DSPs require floating-point operations or iterative calculations, with processing delays typically on the order of microseconds. Combined with sampling time, this makes it difficult to meet the real-time control requirements of high-speed systems. However, at low speeds (e.g., 0.01Hz), extremely high position resolution and extremely low velocity ripple are required.

[0006] 3. Zero drift seriously affects measurement accuracy. Encoder signals can experience zero drift due to factors such as temperature changes, component aging, and electromagnetic interference. Traditional solutions often use offline calibration or fixed compensation, which is difficult to adapt to dynamically changing zero drift.

[0007] 4. Complex system architecture and high cost. Traditional solutions often use an architecture consisting of MCU and dedicated interface chips, or an architecture consisting of DSP and Complex Programmable Logic Device (CPLD), which requires multiple chips to work together, increasing system complexity and cost.

[0008] 5. The traditional methods of quadruple frequency pulse method and small sine and cosine subdivision combination method have the problem of high sampling accuracy requirements, and lack the ability to handle problems such as lost pulses and sampling errors during the operation.

[0009] Therefore, there is an urgent need for an encoder decoding method that is high-precision, high-real-time, low-cost, and can operate stably at low speeds. Summary of the Invention

[0010] To address the aforementioned issues, this application proposes a CPLD-based sine and cosine encoder decoding method, comprising: performing signal conditioning and dynamic tuning actions on the original differential signal to obtain a standardized tuning signal; calculating the corresponding initial absolute position of the absolute position signal in the tuning signal using a preset arctangent table, and performing a scaling transformation on the initial absolute position to obtain the corresponding absolute position starting point based on the scaled initial absolute position; calculating the corresponding subdivision position value of the incremental sine and cosine signals in the tuning signal using a preset arctangent table, and performing step size calculation and position accumulation on the subdivision position value based on the difference between the subdivision position values ​​at different times through position integration, and outputting absolute position information.

[0011] In one example, signal conditioning and dynamic tuning are performed on the original differential signal to obtain a standardized tuning signal. Specifically, this includes: acquiring the input original differential signal; the original differential signal includes incremental sine / cosine signals, absolute position signals, and a zero-position signal; the incremental sine / cosine signals include AB-phase sine / cosine signals, the absolute position signals include CD-phase absolute position signals, and the zero-position signal is a Z-phase zero-position signal; sampling the incremental sine / cosine signals and the absolute position signals using an analog-to-digital converter to obtain corresponding digital signals; obtaining a pulse signal from the zero-position signal using a comparator; performing preliminary filtering on the digital signals using a low-pass filter to obtain a filtered signal; and performing peak-to-peak tuning and zero-bias tuning on the filtered signal using a waveform tuning module to output a standardized tuning signal.

[0012] In one example, the waveform tuning module performs peak-to-peak tuning and zero-bias tuning on the filtered signal to output a standardized tuning signal. Specifically, this includes: initializing the full-scale range of the analog-to-digital converter and using the maximum and minimum values ​​within the full-scale range as initial stored maximum and minimum values ​​in the maximum / minimum value register; initializing the peak-to-peak compensation coefficient stored in the peak-to-peak compensation coefficient register and the initial zero-bias value stored in the zero-point register; wherein the stored maximum and minimum values ​​include the stored maximum and minimum values; repeatedly iteratively performing the maximum / minimum value update operation for each sampling period to update the stored maximum and minimum values ​​in the maximum / minimum value register using the signal maximum and minimum values ​​obtained by sampling the filtered signal; wherein the signal maximum and minimum values ​​include the signal maximum and minimum values; updating the zero-bias value stored in the zero-point register based on the stored maximum and minimum values; and updating the peak-to-peak compensation coefficient stored in the peak-to-peak compensation coefficient register based on the stored maximum and minimum values; and performing peak-to-peak tuning and zero-bias tuning on the filtered signal using the zero-bias value and the peak-to-peak compensation coefficient to output a standardized tuning signal.

[0013] In one example, for each sampling period, the extreme value update action is repeatedly and iteratively performed to update the stored extreme values ​​in the extreme value register. Specifically, this includes: sampling the filtered signal for the current sampling period, averaging the sampled signal extreme values ​​with the corresponding stored extreme values ​​in the extreme value register to obtain the corresponding extreme value averages; wherein, the extreme value averages include the maximum value average and the minimum value average; updating the corresponding stored extreme values ​​using the extreme value averages; and performing a validity check on the updated stored extreme values ​​using a preset theoretical value.

[0014] In one example, updating the zero-bias value stored in the zero-point register based on the stored maximum and minimum values ​​specifically includes: averaging the stored maximum and minimum values ​​among the stored maximum and minimum values ​​to obtain the zero-bias value corresponding to the current sampling period; averaging the zero-bias value corresponding to the current sampling period with the zero-bias value stored in the zero-point register, and updating the zero-bias value stored in the zero-point register using this average; wherein, if the zero-bias value corresponds to the B-phase sine / cosine signal or the D-phase absolute position signal, the average value is then proportionally calculated using the peak-to-peak compensation coefficient. The zero bias value stored in the zero-point register is updated; based on the stored extreme values, the peak-to-peak compensation coefficients stored in the peak-to-peak compensation coefficients are updated, specifically including: calculating the difference between the stored maximum and minimum values ​​in the stored extreme values ​​to obtain the peak-to-peak values ​​corresponding to the incremental sine / cosine signal and the absolute position signal respectively; for the incremental sine / cosine signal and the absolute position signal, the peak-to-peak compensation coefficients corresponding to themselves are calculated proportionally based on the peak-to-peak values ​​they contain, and the peak-to-peak compensation coefficients stored in the peak-to-peak compensation coefficients are updated.

[0015] In one example, for the absolute position signal in the tuning signal, its corresponding initial absolute position is calculated using a preset arctangent table, and a scaling transformation is performed on the initial absolute position. Based on the scaled initial absolute position, the corresponding absolute position starting point is obtained. Specifically, this includes: sampling the CD phase absolute position signal in the tuning signal multiple times to obtain multiple sample values; calculating multiple candidate position values ​​based on the multiple sample values ​​using a preset eight-quadrant arctangent table; performing median filtering on the multiple candidate position values ​​to obtain the corresponding initial absolute position; and scaling the initial absolute position based on the initial absolute position and the number of encoder lines acquired to map the initial absolute position to a higher-dimensional counting space to obtain the corresponding absolute position starting point.

[0016] In one example, for the incremental sine and cosine signals in the tuning signal, the corresponding subdivision position value is calculated using a preset arctangent table. Then, based on the difference between the subdivision position values ​​at different times, the subdivision position value is calculated by step size calculation and position accumulation using position integration, and the absolute position information is output. Specifically, this includes: for the AB phase sine and cosine signals in the tuning signal, obtaining their corresponding base angles through a preset arctangent table, and offsetting them according to the base angles to obtain subdivision position values; obtaining the difference between the subdivision position value at the current time and the subdivision position value at the previous time; calculating the step size of this difference based on a preset maximum single-step change threshold, and accumulating the difference using position integration and the absolute position starting point to output the absolute position information.

[0017] In one example, the method further includes: refining and segmenting the signal conditioning action, the dynamic tuning action, the scaling transformation, and other division and lookup actions in the calculation process to obtain multiple action stages; grouping the multiple action stages through a pipelined update strategy so that each group includes at least one action stage arranged in execution order; selecting the grouping method with the lowest total execution time among all grouping methods, and assigning a corresponding execution unit to each group so that the corresponding action stages in its own group can be executed in parallel through all execution units.

[0018] On the other hand, this application also proposes a CPLD-based sine and cosine encoder decoding device, comprising: at least one processor or programmable logic device; and a memory communicatively connected to the at least one processor or programmable logic device; wherein the memory stores instructions executable by the at least one processor or programmable logic device, the instructions being executed by the at least one processor or programmable logic device to enable the at least one processor or programmable logic device to perform the CPLD-based sine and cosine encoder decoding method as described in any of the above examples.

[0019] On the other hand, this application also proposes a non-volatile computer storage medium storing computer-executable instructions configured to implement the CPLD-based sine and cosine encoder decoding method as described in any of the above examples.

[0020] The CPLD-based sine and cosine encoder decoding method proposed in this application can bring the following benefits: 1. Improved accuracy: By adopting a more refined eight-quadrant arctangent lookup table method, the symmetry of trigonometric functions and the 0~360 degrees are utilized. Under the same lookup table memory resources, the accuracy is higher, and the calculation error near key points such as 45 degrees is reduced, thereby achieving higher position decoding accuracy than the traditional four-quadrant method.

[0021] 2. Improved real-time performance: The solution utilizes the hardware parallel processing capability of the CPLD and adopts a pipeline strategy to embed the angle calculation task into the logic circuit, eliminating the computational delay and interrupt response overhead of traditional MCU / DSP software solutions. It can meet the requirements of high-speed, real-time control systems, improving performance while reducing costs.

[0022] 3. Enhanced dynamic adaptability: The introduction of dynamic signal tuning enables real-time compensation for zero-point and amplitude drift caused by factors such as temperature changes and device aging, overcoming the limitations of traditional fixed compensation methods and ensuring long-term measurement stability under all operating conditions.

[0023] 4. Simplified system architecture and reduced cost: The core functions of the solution are integrated into a single CPLD chip, eliminating the need for dedicated interface chips or DSPs in traditional solutions, simplifying the system architecture, and reducing hardware complexity and overall cost.

[0024] 5. Improved reliability and robustness: Through the step size calculation and filtering mechanism in the position integration process, it can effectively identify and process erroneous data caused by signal interference or loss due to traditional quadruple frequency pulse + AB subdivision method, avoid error accumulation, and enhance the anti-interference capability and operational reliability of the system in complex industrial environments.

[0025] 6. Excellent performance across the entire frequency band: The inherent high resolution and high update rate of this hardware solution enable it to provide stable and smooth position feedback even when operating at extremely low speeds, effectively suppressing speed ripple and achieving high-performance decoding across the entire frequency band from low speed to high speed. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of this application and constitute a part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 is a flowchart illustrating a CPLD-based sine / cosine encoder decoding method in an embodiment of this application; Figure 2 is a schematic diagram of the application system framework of the CPLD-based sine / cosine encoder decoding method in one scenario of an embodiment of this application; Figure 3 is a flowchart illustrating peak-to-peak tuning and zero-bias tuning in one scenario of an embodiment of this application; Figure 4 is a schematic diagram illustrating initial value calibration in one scenario of an embodiment of this application; Figure 5 is a flowchart illustrating position integration in one scenario of an embodiment of this application; Figure 6 is an example schematic diagram of a pipeline strategy in one scenario of an embodiment of this application; Figure 7 is an example comparison schematic diagram of position integration and a traditional scheme in one scenario of an embodiment of this application; Figure 8 is a schematic diagram of a CPLD-based sine / cosine encoder decoding device in an embodiment of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0029] As shown in Figure 1, this application provides a CPLD-based sine and cosine encoder decoding method, including: S101: performing signal conditioning and dynamic tuning actions on the original differential signal to obtain a standardized tuning signal.

[0030] Signal conditioning refers to the adjustment and optimization of input signals during signal processing to ensure that the signal quality and stability meet expected standards. For example, it can include operations such as filtering and amplification.

[0031] Dynamic tuning refers to the process of adjusting and optimizing system parameters based on the system's real-time operating status and changes in the external environment, thereby ensuring that the system maintains optimal performance and stability under different operating conditions. For example, it can include real-time adjustments to relevant parameters and coefficients.

[0032] Specifically, as shown in Figure 2, after the system resets following a power-on delay, it waits for the power supply to stabilize and then enables the sampler to sample the original differential signal. During this process, data such as the encoder line count also needs to be acquired to facilitate the acquisition of the original differential signal.

[0033] Acquire the original differential input signal; the original differential signal includes incremental sine and cosine signals, absolute position signals, and zero position signals; the system contains channels A, B, C, and D. At this time, the sine and cosine signals include AB phase sine and cosine signals (including A+, A-, B+, and B-), the absolute position signal refers to the absolute position signal of the encoder's mechanical large circle, including CD phase absolute position signals (including C+, C-, D+, and D-), and the zero position signal is the Z phase zero position signal (including Z+ and Z-).

[0034] The incremental sine and cosine signals and the absolute position signal are sampled by an analog-to-digital converter (ADC) to obtain the corresponding digital signals. For the zero-position signal, a comparator is used to obtain a pulse signal. Here, the signal corresponding to channel A can be named SinA, the signal corresponding to channel B can be named CosB, the signal corresponding to channel C can be named SinC, the signal corresponding to channel D can be named CosD, and the pulse signal obtained from the Z channel signal using the comparator is called Pz.

[0035] The digital signal is initially filtered using a low-pass filter to obtain the filtered signal. Using a low-pass filter with a small filtering coefficient, the initial filtering is performed, yielding SinA_F, CosB_F, SinC_F, and CosD_F for SinA, CosB, SinC_F, and CosD_F respectively, which serve as the corresponding filtered signals for each channel.

[0036] The waveform tuning module performs peak-to-peak tuning and zero-bias tuning on the filtered signal and outputs a standardized tuning signal.

[0037] As shown in Figure 2, the filtered signal is input to the waveform tuning module to obtain the tuned waveform, which is the standardized tuning signal. The waveform tuning module is mainly responsible for two types of tuning. The first is peak-to-peak tuning, which tunes the peak-to-peak values ​​of the sine and cosine signal samples to be consistent. The second is zero-bias tuning. Considering that the frequency of the sine and cosine encoder changes with the motor speed, the traditional zero-bias integration algorithm is suitable for situations where the frequency changes with time, but not for this scenario where it changes with speed. Therefore, a method similar to amplitude tuning is used to tune the zero-point drift.

[0038] As shown in Figure 3, during the tuning process, the full-scale range of the analog-to-digital converter is initialized according to the theoretical value of the conditioning circuit, and the maximum and minimum values ​​in the full-scale range are used as the initial stored maximum and minimum values ​​in the maximum and minimum value register. The initial values ​​of the peak-to-peak compensation coefficient stored in the peak-to-peak compensation coefficient register and the initial values ​​of the zero bias value stored in the zero point register are also initialized. The stored maximum and minimum values ​​include the stored maximum value and the stored minimum value.

[0039] Taking a 12-bit analog-to-digital converter as an example, assuming full scale, the maximum and minimum values ​​of channels A, B, C, and D are 4095 and 0 respectively. Therefore, the stored maximum and minimum values ​​are also 4095 and 0 respectively. The initial value of the zero bias can be 2048.

[0040] Firstly, for each sampling period, the extreme value update action is repeatedly and iteratively executed to update the stored extreme values ​​in the extreme value register by obtaining the extreme values ​​of the signal obtained by sampling the filtered signal; wherein, the extreme values ​​of the signal include the maximum value of the signal and the minimum value of the signal.

[0041] Specifically, the filtered signal is sampled for the current sampling period, and the average of the sampled maximum and minimum values ​​is calculated with the corresponding stored maximum and minimum values ​​in the maximum and minimum value register to obtain the corresponding maximum and minimum value averages.

[0042] When the motor rotates, the maximum and minimum signal values ​​are acquired for each sampling period. The average of these maximum and minimum values ​​is then calculated by comparing them with the previously stored maximum and minimum values ​​to obtain the corresponding average maximum and minimum values. As shown in Figure 3, when this sampling period is the first sampling period, the stored maximum and minimum values ​​are 4095 and 0, respectively. The average maximum value (Cur_Smax) and average minimum value (Cur_Smin) are then calculated from these values.

[0043] The corresponding stored maximum and minimum values ​​are updated using the extreme values ​​and their mean values, respectively. As shown in Figure 3, Cur_Smax and Cur_Smin are then assigned to the extreme value register as the latest stored maximum value Cur_Smax_O and stored minimum value Cur_Smin_O. The letter O is used here and in the following text primarily to distinguish it from the number 0 encountered during the calculation process and does not imply any specific meaning.

[0044] Simultaneously, the updated storage maximum / minimum value is validated against a preset theoretical value. If the difference between the updated storage maximum / minimum value and the preset theoretical value is too large, a fault alarm is triggered. Validity checks can still be performed after subsequent storage maximum / minimum values ​​are obtained.

[0045] As shown in Figure 3, after the first sampling cycle is completed, the second sampling cycle begins. The average of the acquired signal's maximum and minimum values ​​is calculated with the stored maximum value Cur_Smax_O and the stored minimum value Cur_Smin_O, respectively, to obtain the latest stored maximum value Cur_Smax_1 and stored minimum value Cur_Smin_1. These values ​​are then assigned to the maximum / minimum value register to update the stored maximum value Cur_Smax_O and stored minimum value Cur_Smin_O. A validity check is then performed, and the process continues iteratively.

[0046] Secondly, based on the stored maximum and minimum values, the zero bias value stored in the zero-point register is updated; and based on the stored maximum and minimum values, the peak-to-peak compensation coefficient stored in the peak-to-peak compensation coefficient is updated.

[0047] Specifically, for updating the zero bias value, the mean of the stored maximum and minimum values ​​in the stored extreme values ​​is calculated to obtain the zero bias value corresponding to the current sampling period.

[0048] As shown in Figure 3, the peak-to-peak compensation coefficients for channels A and B are first defined as λ1_O (obtained by dividing the peak-to-peak value of channel A by the peak-to-peak value of channel B), and the initial value is set to 1. The peak-to-peak compensation coefficients for channels C and D are defined as λ2_O (obtained by dividing the peak-to-peak value of channel C by the peak-to-peak value of channel D), and the initial value is set to 1.

[0049] During the first acquisition cycle, the mean of the calculated maximum value Cur_Smax and the mean of the minimum value Cur_Smin (which are the same as the stored maximum value Cur_Smax_O and the stored minimum value Cur_Smin_O) are averaged to obtain the current zero bias value Cur_Szero. This value is then assigned to the zero bias value stored in the zero point register and recorded as Cur_Szero_O. Channels A to D are respectively Cur_Szero_OA, Cur_Szero_OB, Cur_Szero_OC, and Cur_Szero_OD.

[0050] The zero bias value corresponding to the current sampling period is averaged with the zero bias value stored in the zero point register, and the zero bias value stored in the zero point register is updated using this average value. If the zero bias value corresponds to the B-phase sine / cosine signal or the D-phase absolute position signal, the average value is proportionally calculated using the peak-to-peak value compensation coefficient, and then the zero bias value stored in the zero point register is updated.

[0051] In this process, channels A and B are grouped together, and channels C and D are grouped together. For the first sampling period, Cur_Szero_OA, Cur_Szero_OB, Cur_Szero_OC, and Cur_Szero_OD need to be calculated. Starting from the second sampling period, no compensation coefficients are needed for channels A and C, while channels B and D need to have their values ​​updated using compensation coefficients λ1_O and λ2_O.

[0052] This explanation uses the AB channel as an example. The purpose is to use channel A as a baseline and transform the maximum, minimum, and zero values ​​of channel B onto the channel phase. Let's assume the maximum value of channel A is 6 and the minimum value is 2, then the zero bias = (maximum + minimum) / 2 = 3. Simultaneously, let's assume the maximum value of channel B is 4 and the minimum value is 1, then the zero bias is 2.5. At this point, the peak-to-peak value of channel A = maximum - minimum = 6, and the peak-to-peak value of channel B = maximum - minimum = 3. The compensation coefficient λ1 = (peak-to-peak value of channel A / peak-to-peak value of channel B) = 2. Multiplying channel B by this compensation coefficient λ1 gives a maximum value of 4 * 2 = 8 and a minimum value of 1 * 2 = 2. The zero bias is (8 + 2) / 2 = 5 (which is also equal to the zero bias before compensation, 2.5 * λ1 = 5). Subtracting the zero bias from the sampled values ​​of both channel A and channel B transforms the sampled values ​​into the range of -4 to 4, thus facilitating the calculation of the arctangent.

[0053] Alternating with the zero bias update is the update of the peak-to-peak compensation coefficient. The difference between the stored maximum and minimum values ​​in the stored extreme values ​​is calculated to obtain the peak-to-peak values ​​corresponding to the sine and cosine signals and the absolute position signals, respectively.

[0054] The peak-to-peak value can be obtained by taking the difference between the maximum and minimum values ​​of the signal. The peak-to-peak values ​​of A and B are PeakA and PeakB, respectively, and the peak-to-peak values ​​of C and D are PeakC and PeakD, respectively.

[0055] For incremental sine and cosine signals and absolute position signals, the peak-to-peak value compensation coefficients corresponding to each signal are calculated by proportionally using the peak-to-peak values ​​contained within the signal, and the peak-to-peak value compensation coefficients stored in the peak-to-peak value compensation coefficients are updated.

[0056] The current peak-to-peak compensation coefficient λ11 is obtained by using PeakA / PeakB. The original peak-to-peak compensation coefficient λ1_O is updated by averaging λ11 with the original peak-to-peak compensation coefficient λ1_O. The current peak-to-peak compensation coefficient λ21 is obtained by using PeakC / PeakD. The original peak-to-peak compensation coefficient λ2_O is updated by averaging λ21 with the original peak-to-peak compensation coefficient λ2_O.

[0057] As shown in Figure 3, during the repeated iteration process, the peak-to-peak value and zero-bias value are adjusted for the filtered signal through the zero-bias value and peak-to-peak value compensation coefficient, and a standardized adjustment signal is output, thereby realizing dynamic adjustment of the waveform, adjustment of the peak-to-peak value, and zero-bias value of the compensation coefficient. It can be expressed as follows: the current sample value A SA remains unchanged, the sample value B SB is multiplied by λ1_O to obtain SB under the A scale; the current sample value C SC remains unchanged, the sample value D SD is multiplied by λ2_O to obtain SD under the C scale; SinA_FZ=(SA-Cur_Szero_OA;CosB_FZ=(SB-Cur_Szero_OB;SinC_FZ=(SC-Cur_Szero_OC;CosD_FZ=(SD-Cur_Szero_OD;

[0058] The signals from a sine / cosine encoder are time-independent and position-dependent. Theoretically, the sine / cosine signals do not change when the motor is stationary, making it difficult to overwrite certain initial values ​​(e.g., peak-to-peak values) by delaying the power-on time. This information needs to be acquired during motor rotation. If the motor is stationary, the theoretical values ​​set by the hardware are used as initial values. Theoretically, the peak value of a 12-bit ADC sample is 0~4095, the zero bias is 2048, and the peak compensation coefficient is 1. Here, we assume that the signals after tuning channels A to D are SinA_FZ, CosB_FZ, SinC_FZ, and CosD_FZ, respectively.

[0059] S102: For the absolute position signal in the tuning signal, calculate its corresponding initial absolute position using a preset arctangent table, and perform a scaling transformation on the initial absolute position. Based on the scaled initial absolute position, obtain the corresponding absolute position starting point.

[0060] Specifically, the absolute position signal in the setting signal includes the CD phase absolute position signal. The CD phase absolute position signal in the setting signal is sampled multiple times to obtain multiple corresponding sample values. Using a preset eight-quadrant arctangent table, multiple candidate position values ​​are calculated based on these multiple sample values.

[0061] An eight-quadrant lookup table strategy for angle values ​​is designed, utilizing the symmetry of the tangent and arctangent to generate an 8192-point tangent lookup table for 0~45 degrees, thereby saving ROM resources. For convenience, the 0~360 degree scale can be transformed into a 16-bit value of 0~65535 (the arctangent table for 0~45 degrees corresponds to 0~8191), facilitating calculations and reducing costs, thus reducing memory usage to 1 / 8. The arctangent angles of both AB and CD signals can be calculated using this eight-quadrant arctangent table, as shown in Table 1 below:

[0062] A few seconds after power-on, when the motor is stationary and the system is stable, the SinC_FZ and CosD_FZ signals are sampled multiple times and submitted to the aforementioned arctangent table. The lookup result of the arctangent table is the CD position counter MotorPostion_Counter_16Bit. Multiple initial absolute position values ​​of the sine and cosine encoders are obtained from this counter. These values ​​are theoretically very close, and here the initial absolute position value is referred to as the candidate position value.

[0063] Median filtering is performed on multiple candidate position values ​​to obtain the corresponding initial absolute positions.

[0064] As shown in Figure 4, a median filtering algorithm is applied to these initial candidate position values ​​to obtain a relatively reliable initial motor position, MotorInitialPostion_16Bit, which is referred to as the initial absolute position. Since this initial absolute position is only used upon power-up, the filtering can be relatively strong. Furthermore, according to the aforementioned arctangent table, one mechanical rotation of the motor from 0 to 360° corresponds to a value from 0 to 65535. Therefore, the filtered initial absolute position can be defined as MotorInitialPostion_16Bit. If the encoder has no CD signal, MotorInitialPostion_16Bit can be set to 0.

[0065] Based on the initial absolute position and the number of encoder lines acquired, the initial absolute position is scaled to map to a higher-dimensional counting space, thus obtaining the corresponding absolute position starting point.

[0066] The encoder line number (LineNumber) is defined as the maximum value of the high-precision mechanical position obtained after subdivision, based on the encoder line number. For example, a LineNumber of 2048 indicates a 2048-line encoder, meaning that there are 2048 small sine and cosine cycles in one revolution of the mechanical encoder, that is, 2048 value changes from 0 to 65535.

[0067] Let `MotorInterpolationPostion_SubCounter` be a position (angle) counter for channels A and B with a small sine / cosine cycle. This value is calculated directly from the arctangent of the A and B channel signals using a lookup table, ranging from 0 to 65535. Let `MotorInterpolationPostion_Counter` be a high-precision position counter for one mechanical revolution, with its scale being the scale of `MotorInterpolationPostion_SubCounter` (corresponding to 65536) multiplied by the encoder line count `LineNumber`. The maximum value of the counter, `Interpolation_Max`, is `LineNumber * 65536 - 1`, and the minimum value, `Interpolation_Min`, is 0.

[0068] To put it simply, if the MotorInterpolationPostion_Counter is at a standstill and is exactly Interpolation_Min (which is 0), then as the motor rotates one revolution, this value will increase from 0 to Interpolation_Max, then back to Interpolation_Min, and so on. In this way, the encoder accuracy is improved by 65,536 times.

[0069] Based on the specification of the high-precision mechanical position scale value, for the initial absolute position MotorInitialPostion_16Bit obtained above, its scale is transformed into the scale of the high-precision mechanical position counter MotorInterpolationPostion_Counter, that is, MotorInitialPostion_Interpolation = MotorInitialPostion_16Bit * LineNumber.

[0070] Next, this value is assigned to MotorInterpolationPostion_Counter. When the power-on preparation is complete (after waiting for the power supply to stabilize), the mechanical high-precision position counter MotorInterpolationPostion_Counter obtains the absolute position of the motor, which can then be directly provided to the synchronizer as the absolute initial position and uses the same scale as the subsequent speed calculation.

[0071] At this point, the sine and cosine encoder is equivalent to an absolute encoder with a precision of LineNumber*2^16. If the encoder has no C and D channel signals, the sine and cosine encoder is equivalent to an incremental encoder with a precision of (LineNumber*2^16) / 4 (incremental encoders generally use a 4x frequency multiplication to improve precision). In this case, the synchronizer needs to use an algorithm for angle identification.

[0072] S103: For the incremental sine and cosine signals in the tuning signal, calculate the corresponding subdivision position value through a preset arctangent table, and perform step size calculation and position accumulation on the subdivision position value based on the difference between the subdivision position values ​​at different times through position integration, and output the absolute position information.

[0073] The incremental sine and cosine signals in the tuning signal include AB phase sine and cosine signals, which are mainly used to solve the current AB position MotorInterpolationPostion_SubCounter and the AB position MotorInterpolationPostion_SubCounter at the previous sampling time, and accumulate the difference to MotorInterpolationPostion_Counter, thereby realizing the output and update of absolute position information.

[0074] Specifically, for the AB phase sine and cosine signals in the tuning signal, the corresponding base angle is obtained by mapping through a preset arctangent table, and the subdivision position value is obtained by offsetting according to the base angle.

[0075] As shown in Figure 5, MotorInterpolationPositon_SubCounter_O is used as the output of the incremental sine and cosine signal calculation module corresponding to channels A and B (referred to as AB positions) in the tuning signal, MotorInterpolationPositon_SubCounter is used as the output of the current time, and MotorInterpolationPositon_SubCounter_Reg is used as the output of the previous time.

[0076] Meanwhile, MotorInterpolationPositon_SubCounter_O is abbreviated to PO_C, MotorInterpolationPositon_SubCounter to PC_C, and PO_CMotorInterpolationPositon_SubCounter_Reg to PR_C. Let the high-precision mechanical position value (i.e., the absolute position information sought) be MotorInterpolationPositon_Counter. The maximum value of MotorInterpolationPositon_Counter is Interpolation_Max = LineNumber * 65536 - 1, and the minimum value is Interpolation_Min = 0.

[0077] Additionally, the integration direction AB_I_Dir at the current AB position is 0 for negative subtraction and 1 for positive addition; the current position increments for channels A and B are AB_I_Delta: 0~32767; the update period for AB_I_Delta is Texp. Since AB_I_Delta ranges from 0 to 32767, the rotation angle θ within Texp must not exceed 180 degrees, otherwise the integration will fail. Therefore, Texp should be minimized as much as possible.

[0078] In the specific process, when an AB position value update request is received, it means that the AB position calculation module outputs the following values: PO_C has been updated; PC_C is updated to the previous AB position value PR_C; the current AB position value is updated, and PO_C is updated to PC_C.

[0079] Obtain the difference between the current subdivision position value and the previous subdivision position value; calculate the step size based on the preset maximum single-step change threshold.

[0080] At this point, a logical judgment is made: if PO_C ≥ PR_C and PO_C - PR_C < 32768, then AB_I_Delta = PO_C - PR_C, and AB_I_Dir = 1. Here, and in the following text, 32768 is used as the maximum single-step change threshold to calculate the step size for the difference between PO_C and PR_C. For clarity, it is assumed that the encoder has 1000 lines, meaning that one motor revolution generates 1000 AB cycles. Each AB cycle is decoded at 16-bit resolution (i.e., 0~65535). Therefore, one motor revolution will generate 1000 numbers in the range of 0~65535, with a total step size of 1000 * 65536. If PO_C > PR_C and PO_C - PR_C < 32768, it means that the difference between the value of the AB channel in the previous sampling and the value of the AB channel in the current sampling is less than half of one cycle of the AB channel. This proves two things: first, the current direction is forward (since the sampling time is usually much smaller than the time it takes for the motor to complete one revolution, the relationship between the values ​​of PO_C and PR_C can be used to determine whether it is forward or reverse); second, the step size is less than half of the AB channel (that is, the step size of the current sampling is determined by the difference between the two). At this time, it can be considered as forward growth.

[0081] Otherwise, further judgment is made: if PO_C ≥ PR_C and PO_C - PR_C ≥ 32768, then AB_I_Delta = PO_C - PR_C, and AB_I_Dir = 0. In this case, although PO_C ≥ PR_C, since the current step size increase has exceeded the maximum single-step change threshold, it is considered that the current movement is not forward but represents a reverse overflow.

[0082] Otherwise, further judgment is made: if PR_C ≥ PO_C and PR_C - PO_C < 32768, then AB_I_Delta = PR_C - PO_C, and AB_I_Dir = 0. In this case, the relationship between PR_C and PO_C is reversed compared to the first case (PO_C ≥ PR_C and PO_C - PR_C < 32768), indicating a reverse trend; the current situation is a reversal. Simultaneously, PR_C - PO_C < 32768, which does not exceed the maximum single-step change threshold; therefore, this is considered a reversal growth.

[0083] Otherwise, further judgment is made: if PR_C > PO_C and PR_C - PO_C ≥ 32768, then AB_I_Delta = PR_C - PO_C, and AB_I_Dir = 1. In this case, the direction is opposite to the second case mentioned above (PO_C ≥ PR_C and PO_C - PR_C ≥ 32768), and it exceeds the maximum single-step change threshold, which can be considered as representing forward overflow.

[0084] By integrating the position and calculating the absolute position starting point, the difference is accumulated to output the absolute position information.

[0085] In the four cases mentioned above, determine whether AB_I_Dir=1 at this time.

[0086] If AB_I_Dir=1, then check if MotorInterpolationPositon_Counter+AB_I_Delta≤Interpolation_Max is true. If true, then MotorInterpolationPositon_Counter=MotorInterpolationPositon_Counter+AB_I_Delta; if false, then MotorInterpolationPositon_Counter=MotorInterpolationPositon_Counter+AB_I_Delta-Interpolation_Max.

[0087] If AB_I_Dir = 0 (i.e., not 1), then check if MotorInterpolationPositon_Counter - AB_I_Delta ≥ Interpolation_Min is true. If true, then MotorInterpolationPositon_Counter = MotorInterpolationPositon_Counter - AB_I_Delta; if false, then MotorInterpolationPositon_Counter = MotorInterpolationPositon_Counter - AB_I_Delta + MotorInterpolationPositon_Counter.

[0088] Finally, by accumulating the values, MotorInterpolationPositon_Counter is output, which is the required absolute position information (also the high-precision mechanical position value).

[0089] 1. Improved accuracy: By adopting a more refined eight-quadrant arctangent lookup table method, the symmetry of trigonometric functions and the 0-360 degree range are utilized to achieve higher accuracy with the same table lookup memory resources. This reduces calculation errors near key points such as 45 degrees, thus achieving higher position decoding accuracy than the traditional four-quadrant method.

[0090] 2. Improved real-time performance: The solution utilizes the hardware parallel processing capability of the CPLD and adopts a pipeline strategy to embed the angle calculation task into the logic circuit, eliminating the computational delay and interrupt response overhead of traditional MCU / DSP software solutions. It can meet the requirements of high-speed, real-time control systems, improving performance while reducing costs.

[0091] 3. Enhanced dynamic adaptability: The introduction of dynamic signal tuning enables real-time compensation for zero-point and amplitude drift caused by factors such as temperature changes and device aging, overcoming the limitations of traditional fixed compensation methods and ensuring long-term measurement stability under all operating conditions.

[0092] 4. Simplified system architecture and reduced cost: The core functions of the solution are integrated into a single CPLD chip, eliminating the need for dedicated interface chips or DSPs in traditional solutions, simplifying the system architecture, and reducing hardware complexity and overall cost.

[0093] 5. Improved reliability and robustness: Through the step size calculation and filtering mechanism in the position integration process, it can effectively identify and process erroneous data caused by signal interference or loss due to traditional quadruple frequency pulse + AB subdivision method, avoid error accumulation, and enhance the anti-interference capability and operational reliability of the system in complex industrial environments.

[0094] 6. Excellent performance across the entire frequency band: The inherent high resolution and high update rate of this hardware solution enable it to provide stable and smooth position feedback even when operating at extremely low speeds, effectively suppressing speed ripple and achieving high-performance decoding across the entire frequency band from low speed to high speed.

[0095] In one embodiment, the time calculation is refined, which is reflected in the update speed of the current AB position and the previous AB position. This not only prevents integral overflow caused by excessive rotation speed or too many encoder lines (if the time interval Texp between two calculations exceeds half a small sine and cosine AB cycle, it is difficult to determine whether it is forward or reverse), but also eliminates sampling error values ​​through acceleration threshold calibration (acceleration values ​​that obviously do not conform to the principles of physics are characterized as current sampling value errors and filtered out).

[0096] To improve the update speed of MotorInterpolationPostion_SubCounter for AB positions, a pipelined update strategy was designed, and the key times for obtaining the subdivision positions were analyzed: sampling time δt1, arctangent calculation time δt2 (including sampling tuning time δt21, scaling consistency time δt22, division time δt23, and table lookup time δt24).

[0097] The signal conditioning, dynamic tuning, scaling, and other computational operations such as division and table lookup are refined and divided into multiple action stages. A pipelined update strategy is used to group these action stages, ensuring that each group includes at least one action stage arranged in execution order. Among all grouping methods, the one with the lowest total execution time is selected, and each group is assigned a corresponding execution unit. This allows all execution units to execute the corresponding action stages within their respective groups in parallel.

[0098] As shown in Figure 6, sequence 1 is the process of continuing to analyze and calculate the value of MotorInterpolationPostion_SubCounter after sampling. This is an unoptimized general solution, and its time consumption is δt1+δt2, that is, the latest MotorInterpolationPostion_SubCounter is calculated every time δt1+δt2.

[0099] Numbers 2 and 3 show the example pipeline time distribution process, while numbers 4 and 5 show the comparative pipeline processes. The different pipeline stage settings all show an improvement in time compared to number 1. Furthermore, the degree of improvement varies depending on the specific circumstances of each pipeline stage setting.

[0100] In the example given in Figure 6, for sequence number 2, δt1 and δt2 are executed in parallel by different execution units. For sequences 3 and 4, δt21 is moved to the execution unit corresponding to δt1, and the next sampling is started when the execution unit that finishes later ends. For sequence number 5, δt22 is moved to the execution unit corresponding to δt1.

[0101] It can be seen that the update period of MotorInterpolationPostion_SubCounter value for sequence 4 is δt22+δt23+δt24, while the update period of MotorInterpolationPostion_SubCounter value for sequence 5 is δt1+δt21+δt22. Obviously, strategy 4 is better than strategy 5. Therefore, in the current scenario, strategy corresponding to sequence 4 can be selected.

[0102] Of course, the actual time will vary depending on the specific scenario and method. In this case, the formula for calculating the expected optimal pipeline MotorInterpolationPostion_SubCounter update cycle Texp is: Texp=Min{T1,T2,T3,T4,T5}, where T1~T5 correspond to the lowest total execution time under different grouping methods for multiple action stages. T1 = Max{δt1, δt2} (where δt1 and δt2 each correspond to a group); T2 = Max{δt1 + δt21, δt22 + δt23 + δt24} (where δt1 + δt21 corresponds to a group, and δt22 + δt23 + δt2 corresponds to a group); T3 = Max{δt1 + δt21 + δt22, δt23 + δt24} (where δt1 + δt21 + δt22 corresponds to a group, and δt23 + δt24 corresponds to a group); T4 = Max{δt1 + δt21 + δt22 + δt23, δt24} (where δt1 + δt21 + δt22 + δt23 corresponds to a group, and δt24 corresponds to a group); T5 = δt1 + δt2 (corresponding to the traditional no-optimization method of sequence number 1, i.e., no grouping).

[0103] Of course, if δt1 can be further subdivided, it can be further optimized, but I will not go into details here.

[0104] In one embodiment, as shown in Figure 7, this embodiment first employs a low-filtering + peak-to-peak value, zero-bias dynamic tuning algorithm to dynamically adjust the peak-to-peak value and zero bias of the sampled data in real time, whereas traditional solutions either do not add correction or only add static correction when powered on.

[0105] Secondly, using the 45-degree lookup table method can save 7 / 8 of the memory lookup table space, reducing the chip's storage requirements.

[0106] Next, the AB subdivision location pipeline module is used to increase the update frequency Texp of the AB subdivision location, further reducing the chip requirements.

[0107] Finally, the AB integration algorithm is used to obtain the high-precision mechanical position. In contrast, the traditional method generally adopts a combination of AB conversion to pulse fourth harmonic coarse positioning and AB subdivision for precise positioning. This is a coupled correction algorithm. When pulse counter pulses are lost due to disturbances, it will continuously output incorrect positions. It does not have the ability of the AB integration algorithm to eliminate slight disturbances and needs to be corrected by Z / R signals. As shown in Figure 7, it is a comparison between the sine-cosine coupled algorithm in the traditional method and the sine-cosine integration algorithm in the embodiment of this application.

[0108] In the traditional approach, assuming a small cycle of AB is 0~360°, the cycle of AB is divided into four parts by a fourth harmonic, each part being 90 degrees. The fourth harmonic can subdivide the AB cycle into a maximum of 1 / 4, but it cannot subdivide within the 1 / 4. Such subdivision requires the arctangent of AB to achieve subdivision within the 1 / 4.

[0109] When there is no disturbance or the disturbance is small, assuming the current position is in the 100+5 / 8th AB cycle, due to the precision limitation of subdivision, the quadruple frequency method can only calculate up to 100+4 / 8. The next position that can be calculated is 100+6 / 8, and so on. At this time, the quadruple frequency method outputs 100+4 / 8, but by subdividing AB to find the current position is 5 / 8 of an AB cycle, 100+4 / 8 is corrected to 100+5 / 8, which conforms to the logical output.

[0110] However, when disturbances occur, if a measurement error occurs that exceeds 90 degrees (i.e., 1 / 4 of an AB cycle), it becomes impossible to determine which measurement is correct.

[0111] Still assuming the current correct position is 100 + 5 / 8 AB cycles, and that the fourth harmonic method measures 100 + 4 / 8 AB cycles, performing arctangent subdivision on AB results in an error due to interference, yielding a current position of 7 / 8 AB cycles. At this point, if 4 / 8 AB cycles is correct, the correct arctangent subdivision position must be between 4 / 8 and 6 / 8, thus 7 / 8 AB cycles is incorrect. Conversely, if the arctangent subdivision position of 7 / 8 AB cycles is correct, the fourth harmonic position must be at 6 / 8 (7 / 8 is between 6 / 8 and 8 / 8), then 4 / 8 AB cycles at the fourth harmonic position is incorrect. Since both explanations are valid, theoretically, it's impossible to determine which is correct. However, users at this point find it difficult to determine whether 4 / 8 or 7 / 8 AB cycles is correct.

[0112] In the embodiments of this application, when there is no disturbance or the disturbance is small, the current angle can be directly obtained by integral calculation through AB without the need to compare the fourth harmonic and subdivision AB values.

[0113] When there is a disturbance during the integral calculation, the first stage directly performs the integral calculation through AB. The second stage assumes that there is a disturbance in the sampling of this incremental calculation: the correct increment is Y = M3–M1, and the increment measured due to the disturbance is EY = M2–M1. The third stage calculates the increment as Z = M4–M2.

[0114] The calculated result is X+EY+Z=X+M2–M1+M4-M2=X+M4–M1. The erroneous measurement value M2 is canceled out. Therefore, the integral method has a natural ability to eliminate disturbances. In the absence of continuous disturbances and when the disturbance amount is large, it will not lead to the accumulation of disturbances. The disturbance amount only affects the local area.

[0115] As shown in Figure 8, this application also proposes a CPLD-based sine and cosine encoder decoding device, including: at least one processor or programmable logic device; and a memory communicatively connected to the at least one processor or programmable logic device; wherein the memory stores instructions executable by the at least one processor or programmable logic device, the instructions being executed by the at least one processor or programmable logic device to enable the at least one processor or programmable logic device to perform the CPLD-based sine and cosine encoder decoding method as described in any of the above embodiments.

[0116] This application also proposes a non-volatile computer storage medium storing computer-executable instructions configured to implement the CPLD-based sine and cosine encoder decoding method as described in any of the above embodiments.

[0117] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device and medium embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the description of the method embodiments.

[0118] The devices and media provided in this application are one-to-one with the methods. Therefore, the devices and media also have similar beneficial technical effects as their corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0119] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A sine / cosine encoder decoding method based on CPLD, characterized in that, include: Signal conditioning and dynamic tuning are performed on the original differential signal to obtain a standardized tuning signal. For the absolute position signal within the tuning signal, its initial absolute position is calculated using a preset arctangent table, and a scaling transformation is performed on the initial absolute position. The starting point of the corresponding absolute position is obtained based on the scaled initial absolute position. For the incremental sine and cosine signals within the tuning signal, its corresponding subdivision position value is calculated using a preset arctangent table. Through position integration, based on the difference between the subdivision position values ​​at different times, the step size of the subdivision position value is calculated and the position is accumulated, outputting the absolute position information.

2. The method according to claim 1, characterized in that, The process involves performing signal conditioning and dynamic tuning on the original differential signal to obtain a standardized tuning signal. Specifically, this includes: acquiring the input original differential signal; the original differential signal includes incremental sine / cosine signals, absolute position signals, and a zero-position signal; the incremental sine / cosine signals include AB-phase sine / cosine signals, the absolute position signals include CD-phase absolute position signals, and the zero-position signal is a Z-phase zero-position signal; sampling the incremental sine / cosine signals and the absolute position signals using an analog-to-digital converter to obtain corresponding digital signals; obtaining a pulse signal from the zero-position signal using a comparator; performing preliminary filtering on the digital signals using a low-pass filter to obtain a filtered signal; and performing peak-to-peak value tuning and zero-bias tuning on the filtered signal using a waveform tuning module to output a standardized tuning signal.

3. The method according to claim 2, characterized in that, The waveform tuning module performs peak-to-peak tuning and zero-bias tuning on the filtered signal, outputting a standardized tuning signal. Specifically, this includes: initializing the full-scale range of the analog-to-digital converter and using the maximum and minimum values ​​within the full-scale range as initial stored maximum and minimum values ​​in the maximum / minimum value register; initializing the peak-to-peak compensation coefficient stored in the peak-to-peak compensation coefficient register and the initial zero-bias value stored in the zero-point register; wherein the stored maximum and minimum values ​​include the stored maximum and minimum values; repeatedly iteratively performing the maximum / minimum value update operation for each sampling period, updating the stored maximum and minimum values ​​in the maximum / minimum value register using the signal maximum and minimum values ​​obtained from sampling the filtered signal; wherein the signal maximum and minimum values ​​include the signal maximum and minimum values; updating the zero-bias value stored in the zero-point register based on the stored maximum and minimum values; and updating the peak-to-peak compensation coefficient stored in the peak-to-peak compensation coefficient register based on the stored maximum and minimum values; and performing peak-to-peak tuning and zero-bias tuning on the filtered signal using the zero-bias value and the peak-to-peak compensation coefficient, outputting a standardized tuning signal.

4. The method according to claim 3, characterized in that, For each sampling period, the extreme value update action is repeatedly and iteratively executed to update the stored extreme values ​​in the extreme value register. Specifically, this includes: sampling the filtered signal for the current sampling period, averaging the sampled signal extreme values ​​with the corresponding stored extreme values ​​in the extreme value register to obtain the corresponding extreme value averages; wherein, the extreme value averages include the average of the maximum value and the average of the minimum value; updating the corresponding stored extreme values ​​using the extreme value averages; and performing a validity check on the updated stored extreme values ​​using a preset theoretical value.

5. The method according to claim 4, characterized in that, Based on the stored extreme values, the zero-bias values ​​stored in the zero-point register are updated, specifically including: averaging the stored maximum and minimum values ​​among the stored extreme values ​​to obtain the zero-bias value corresponding to the current sampling period; averaging the zero-bias value corresponding to the current sampling period with the zero-bias values ​​stored in the zero-point register, and updating the zero-bias values ​​stored in the zero-point register using this average; wherein, if the zero-bias value corresponds to the B-phase sine / cosine signal or the D-phase absolute position signal, the average is proportionally calculated using the peak-to-peak value compensation coefficient, and the zero-bias value stored in the zero-point register is updated; based on the stored extreme values, the peak-to-peak value compensation coefficients stored in the peak-to-peak value compensation coefficients are updated, specifically including: calculating the difference between the stored maximum and minimum values ​​among the stored extreme values ​​to obtain the peak-to-peak values ​​corresponding to the incremental sine / cosine signal and the absolute position signal, respectively; proportionally calculating the peak-to-peak value compensation coefficients corresponding to the incremental sine / cosine signal and the absolute position signal using their own peak-to-peak value components, and updating the peak-to-peak value compensation coefficients stored in the peak-to-peak value compensation coefficients.

6. The method according to claim 2, characterized in that, For the absolute position signal in the tuning signal, its corresponding initial absolute position is calculated using a preset arctangent table, and a scaling transformation is performed on the initial absolute position. Based on the scaled initial absolute position, the corresponding absolute position starting point is obtained. Specifically, this includes: sampling the CD phase absolute position signal in the tuning signal multiple times to obtain multiple sample values; calculating multiple candidate position values ​​based on the multiple sample values ​​using a preset eight-quadrant arctangent table; performing median filtering on the multiple candidate position values ​​to obtain the corresponding initial absolute position; and scaling the initial absolute position based on the initial absolute position and the number of encoder lines acquired to map the initial absolute position to a higher-dimensional counting space to obtain the corresponding absolute position starting point.

7. The method according to claim 2, characterized in that, For the incremental sine and cosine signals in the tuning signal, the corresponding subdivision position value is calculated using a preset arctangent table. Then, based on the difference between the subdivision position values ​​at different times, the subdivision position value is calculated by step size calculation and position accumulation using position integration, and the absolute position information is output. Specifically, this includes: for the AB phase sine and cosine signals in the tuning signal, the corresponding base angle is obtained by mapping using a preset arctangent table, and the subdivision position value is obtained by offsetting according to the base angle; the difference between the subdivision position value at the current time and the subdivision position value at the previous time is obtained; based on a preset maximum single-step change threshold, the step size of this difference is calculated, and the difference is accumulated using position integration and the absolute position starting point, and the absolute position information is output.

8. The method according to claim 1, characterized in that, The method further includes: refining and dividing the signal conditioning action, the dynamic tuning action, the scaling transformation, and other division and lookup actions in the calculation process to obtain multiple action stages; grouping the multiple action stages through a pipelined update strategy so that each group includes at least one action stage arranged in execution order; selecting the grouping method with the lowest total execution time among all grouping methods, and assigning a corresponding execution unit to each group so that the corresponding action stages in its own group can be executed in parallel through all execution units.

9. A CPLD-based sine / cosine encoder decoding device, characterized in that, include: At least one processor or programmable logic device; and a memory communicatively connected to the at least one processor or programmable logic device; wherein the memory stores instructions executable by the at least one processor or programmable logic device to enable the at least one processor or programmable logic device to perform the CPLD-based sine and cosine encoder decoding method as described in any one of claims 1 to 8.

10. A non-volatile computer storage medium storing computer-executable instructions, characterized in that, The computer-executable instructions are configured to implement the CPLD-based sine and cosine encoder decoding method as described in any one of claims 1 to 8.

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