Substrate, system and method for stacked chip testing

Abstract

The invention discloses a substrate, a system and a method for testing stacked chips. The substrate comprises a substrate body with a bare chip setting area, a plurality of independent bonding pad units arranged in a surrounding manner, and a connecting unit. The core is that the number of the bonding pad units is preset to be not less than the maximum stacking layer number of the to-be-tested chip, and the interface connecting points of the connecting units are independently and correspondingly connected with the bonding pad connecting points of different bonding pad units through internal wiring of the substrate. According to the testing system and method based on the substrate, through combination of channel reservation on hardware and selective resource allocation on software, compatibility testing on multiple layers of stacked chips by a single testing platform is achieved, and accurate and independent measurement on each layer of bare chips under power supply isolation is supported. According to the invention, the test efficiency and flexibility are improved, the test cost is reduced, and the test quality and reliability of the three-dimensional stacked chip are ensured.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a substrate, system, and method for testing stacked chips. Background Technology

[0002] As integrated circuit technology evolves towards three dimensions, multi-die stacking packaging technology has become a key path to improve chip integration and performance. Before such products leave the factory, each layer of bare chips in the stacked structure must undergo rigorous electrical testing and functional verification to ensure the yield and reliability of the final product.

[0003] Currently, industry testing of stacked bare chips primarily relies on dedicated test substrates. These test substrates act as intermediaries, with one end connected to the pads of each layer of the bare chip via wire bonding, and the other end connected to automated testing equipment, thus establishing test channels. However, existing technologies have a significant drawback: the design of the test substrate is strictly tied to the number of stacked layers of the bare chip. That is, for a four-layer stacked bare chip, a substrate with four independent test channels is required; for an eight-layer stacked bare chip, a separate substrate with eight independent test channels is needed, and so on. This "one-to-one" dedicated design model brings many technical problems that urgently need to be solved: Low testing efficiency: When testing products with different layers, the production line must frequently stop and replace the corresponding test substrates. The replacement process involves a series of operations such as mechanical alignment, connector insertion and removal, and test program reloading, which seriously consumes valuable production time and reduces the overall testing throughput.

[0004] High R&D and manufacturing costs: Each dedicated test substrate requires an independent design, simulation, processing, and verification cycle, resulting in high R&D costs. At the same time, manufacturers need to maintain inventory of multiple substrates for various possible stacking numbers, leading to increased capital tied up and warehousing management costs.

[0005] Poor flexibility and slow response: When faced with rapidly iterating chip products, especially new models where the number of stacked layers may change, dedicated test substrates cannot be quickly adapted. The cycle from submitting a test request to obtaining a usable dedicated substrate is lengthy, severely slowing down the product launch time.

[0006] Waste of testing resources: Dedicated substrates become idle after their corresponding chip models are discontinued, resulting in a waste of testing hardware resources. Summary of the Invention

[0007] This invention provides a substrate, system, and method for testing stacked chips, to solve the problems of poor versatility, low testing efficiency, and high cost of existing test substrates.

[0008] In a first aspect, a substrate for stacked chip testing is provided, comprising: The substrate body has a bare chip placement area for placing stacked bare chips under test; Multiple independent pad units are disposed around the bare chip placement area. Each pad unit includes multiple pad connection points for electrical connection to the edge pads of the corresponding layer in the stacked bare chips via wire bonding. The connection unit, disposed on the substrate body, includes multiple interface connection points for connecting to the test circuit board; The number of pad units is greater than or equal to the number of bare chip layers in the stacked bare chip under test; each interface connection point in the connection unit is connected to the pad connection point in a different pad unit through the traces in the substrate body.

[0009] Secondly, a stacked chip testing system is provided, including: A substrate used for stacked chip testing, as described above; The test circuit board is connected to the interface connection point of the connection unit of the substrate, and is used to provide test signals and receive test feedback.

[0010] Thirdly, a stacked chip testing method is provided, which is applied to the aforementioned stacked chip testing system. The method includes: Place the stacked bare chips under test in the bare chip setting area of ​​the substrate body; The edge pads of each layer of bare chip in the stacked bare chip under test are connected to different pad units on the substrate body by wire bonding. Connect the interface connection point of the connection unit of the substrate body to the test circuit board; By connecting the unit and the wiring inside the substrate body, the test resources of the test device are selectively connected to the pad unit corresponding to the target bare chip layer, and the target bare chip layer is tested. When testing the target bare chip layer, test power is applied only to the target bare chip layer currently being tested.

[0011] The aforementioned solution for the substrate, system, and method used for stacked chip testing creatively constructs a "channel resource pool" by setting up a sufficient number of independent pad units, achieving compatibility testing of bare chips with multiple stacking layers on a single hardware platform. Its beneficial effects are specifically manifested in the following ways: 1. Significantly enhanced versatility and flexibility: a single substrate can cover the testing of all chips within a certain layer range, completely eliminating the "one chip, one board" model and greatly improving testing efficiency and production line response speed; 2. Significantly reduced overall cost: the universal design reduces the R&D, manufacturing, and inventory costs of dedicated substrates and improves the utilization rate of high-end testing equipment; 3. Excellent scalability: the substrate can integrate control chip interfaces and multiple connection units, facilitating adaptation to different testing architectures and future needs. This invention systematically solves the core challenges of efficiency, cost, and quality in stacked chip testing and possesses significant industrial application value. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the front structure of a substrate used for stacked chip testing in one embodiment of the present invention.

[0014] Figure 2 This is a schematic diagram of the placement of the bare chip to be stacked on the substrate for stacked chip testing in one embodiment of the present invention.

[0015] Figure 3 This is a schematic diagram of the reverse side structure of a substrate used for stacked chip testing in one embodiment of the present invention.

[0016] Figure 4 This is a structural block diagram of a stacked chip testing system according to an embodiment of the present invention.

[0017] Figure 5 This is a schematic diagram of a stacked chip testing system according to an embodiment of the present invention.

[0018] Figure 6 This is a flowchart illustrating a stacked chip testing method according to an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Please see Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a substrate for stacked chip testing provided in an embodiment of the present invention. The substrate for stacked chip testing includes a substrate body 100, a plurality of independent pad units 120, and connection units 130.

[0021] The substrate body 100 has a mounting surface for placing a stack of bare chips 200 under test (see [link]). Figure 2 The bare die setup area 110; multiple independent pad units 120 are disposed around the bare die setup area 110, each pad unit 120 including multiple pad connection points 121 for bonding wires 140 (see [reference]). Figure 2 Each of the following is electrically connected to the edge pad of the bare chip in the corresponding layer of the stacked bare chip 200: The connection unit 130 is disposed on the substrate body 100 and includes multiple interface connection points for connecting to the test circuit board; wherein, the number of pad units 120 is greater than or equal to the number of bare chip layers of the stacked bare chip 200 under test; each interface connection point in the connection unit 130 is connected to the pad connection point 121 in different pad units 120 through the traces in the substrate body 100.

[0022] Specifically, the substrate body 100 is typically manufactured using a multilayer printed circuit board process, exhibiting excellent mechanical strength and electrical performance. A bare chip placement area 110 is located at the center of its top surface. This area is precisely designed to hold and secure the stacked bare chips 200 to be tested. The dimensions and surface treatments (such as adhesion layers) of area 110 are matched to the package dimensions of the target chip.

[0023] The pad units 120 are key physical structures for achieving compatibility. They are arranged independently around the bare die placement area 110. Each pad unit 120 is itself a collection of numerous miniature metal contacts, which are defined as pad connection points 121. The size, spacing, and surface treatment of each pad connection point 121 meet the requirements of gold or copper wire bonding 140, for achieving a one-to-one electrical connection with the edge pads of the corresponding layer on the bare die 200 via wire bonding 140.

[0024] The connection unit 130 serves as a bridge for interaction between the test substrate 100 and the external environment (mainly the automated test equipment ATE 300). It is located on the substrate body 100 and includes a series of interface connection points. These interface connection points can take the form of a high-density board-to-board connector female, a spring probe contact array, or a solder ball array, etc. Their core function is to establish a reliable electrical connection with the electrical cables or probe modules of the test circuit board.

[0025] It's important to understand that the total number of pad cells 120 is designed to be greater than or equal to the maximum number of layers the bare die 200 under test may have. For example, if the chip to be tested has a maximum of 8 layers, then at least 8 pad cells must be arranged on the substrate. This quantitative relationship is a mathematical expression of a "general-purpose" design. For chips with fewer than 8 layers (such as 5 layers), only 5 pad cells are used during testing, and the remaining cells remain electrically floating, without affecting the testing functionality.

[0026] This invention, through the creative configuration of a sufficient number of independent pad units 120, constructs a "channel resource pool," enabling compatibility testing of bare chips with multiple stacking layers on a single hardware platform. Its beneficial effects are specifically manifested in: 1. Significantly enhanced versatility and flexibility: a single substrate can cover the testing of all chips within a certain layer range, completely eliminating the "one chip, one board" model and greatly improving testing efficiency and production line response speed; 2. Significantly reduced overall cost: the universal design reduces the R&D, manufacturing, and inventory costs of dedicated substrates, and improves the utilization rate of high-end testing equipment; 3. Excellent scalability: the substrate can integrate control chip interfaces and multiple connection units, facilitating adaptation to different testing architectures and future needs. This invention systematically solves the core challenges of efficiency, cost, and quality in stacked chip testing, possessing significant industrial application value.

[0027] Furthermore, based on the above embodiments, in other embodiments, such as Figure 1 As shown, multiple independent pad units 120 are symmetrically arranged on opposite sides of the bare chip setting area 110.

[0028] Specifically, the multiple pad units 120 are preferably arranged symmetrically on opposite sides (e.g., upper and lower sides) of the bare chip setting area 110. For example, assuming there are 8 pad units, four pad units can be arranged on the upper side of the substrate body 100 and four pad units can be arranged on the lower side of the substrate body 100, forming a stable symmetrical layout. The symmetrical layout makes the length and direction of the bonding wires 140 leading from different layers of the stacked bare chips 200 more uniform. The uniform wire loop design reduces the difficulty of the bonding process, improves the consistency of the mechanical strength of all solder points, and reduces test failures caused by poor bonding. Moreover, the symmetrical input / output layout helps to make the routing layout from the pad units 120 to the connection units 130 inside the substrate more regular and orderly, reducing wiring congestion and crossing, which is beneficial to achieving better impedance control and electromagnetic compatibility performance.

[0029] Furthermore, based on the above embodiments, in other embodiments, the substrate body 100 includes multiple stacked metal layers, and the interface connection points are connected to the corresponding pad connection points 121 through traces and metal vias in the metal layers.

[0030] Specifically, the substrate body 100 is not a simple single-layer or double-layer board, but rather consists of multiple stacked metal layers separated by insulating media (such as FR-4, ABF, etc.). The hundreds or thousands of point-to-point connections between the interface connection points of the connection unit 130 and the pad connection points 121 of the pad unit 120 are achieved through the coordinated routing of these three-dimensionally distributed metal layer traces and vertically interconnected metal vias. Multilayer routing technology enables the accommodation and routing of a massive number of independent test channels within a limited substrate area, providing the physical basis and technical guarantee for compatible multilayer stacked chip testing. Furthermore, through professional stack-up design, dedicated power, ground, and signal layers can be planned. This provides a low-impedance return path, effective shielding, and a stable power supply for the test signal 400, thereby ensuring the integrity of high-frequency, high-sensitivity test signals and avoiding the impact of substrate performance limitations on test results.

[0031] Furthermore, based on the above embodiments, in other embodiments, such as Figure 3 As shown, the substrate body 100 also has a control chip connection area 170 on the side facing away from the bare chip setting area 110. The control chip connection area 170 has a plurality of control chip connection pins 171, and the control chip connection pins 171 are connected to the pad connection points 121 of the pad unit 120 through the traces in the substrate body 100.

[0032] Specifically, an additional control chip connection area 170 is provided on the back side of the substrate body 100 (i.e., the side facing away from where the bare chip is placed). This area has an array of control chip connection pins 171, the arrangement, spacing, and electrical definitions of which are fully compatible with the pin layout of a specific system control chip (e.g., a SoC or FPGA used to generate memory test sequences). Crucially, these control chip connection pins 171 are also connected to the pad connection points 121 of the pad unit 120 via internal substrate traces, specifically for interfacing with control logic.

[0033] In this embodiment, the control chip and its minimum system can be directly integrated or docked onto the test substrate through the control chip connection area 170, forming a fully functional "test slave board". This greatly simplifies the system architecture, reduces external cables and connectors, and improves the reliability and portability of the entire test module.

[0034] Furthermore, based on the above embodiments, in other embodiments, the number of pad units 120 is 8.

[0035] In this embodiment, the total number of pad units 120 is explicitly designed to be 8. This number is not arbitrarily chosen, but is based on an in-depth analysis of global 3D stacked memory chip (such as HBM2e, HBM3) and logic chip stacking technology routes. Currently and in the medium term, 4-layer, 6-layer, and 8-layer are the mainstream and competitive focus in the market, with 8-layer being the most technically challenging and high-value-added product node. Designing the total number of pad units 120 to be 8 can optimally cover the testing needs of mainstream products.

[0036] Furthermore, based on the above embodiments, in other embodiments, the number of connection units 130 is multiple.

[0037] Specifically, multiple physically independent connection units are provided on the test substrate 100. These connection units can be specialized in their electrical functions. For example, all power and ground pins can be concentrated on a dedicated power connection unit, while high-speed data signals and clock signals can be placed on another signal connection unit. This physical separation can minimize the interference of high-current switching on sensitive small signals, which is a key measure to improve test accuracy, especially power supply noise and timing measurement accuracy. Preferably, the number of these connection units is set to two.

[0038] Please see Figure 4 As shown, Figure 4This is a schematic diagram of the structure of a stacked chip testing system provided in an embodiment of the present invention. The stacked chip testing system includes: a substrate 10 for stacked chip testing as described in any of the above embodiments; and an interface connection point between a test circuit board 20 and a connection unit of the substrate 10, used to provide test signals and receive test feedback.

[0039] Specifically, test circuit board 20 (see [link]). Figure 5 middle B As shown, the core of the system's control and resources includes: a control chip 21, which can be a System-on-a-Chip (SoC), a Microcontroller (MCU), or a Field-Programmable Gate Array (FPGA). This control chip internally stores test algorithm programs to generate the instruction sequences, data graphs, and control timing required for testing each layer of the stacked bare chips under test. Test resource circuitry includes a power management circuit for powering the entire test module, a drive circuit for providing programmable test power to the stacked bare chips under test, and measurement circuitry (such as ADCs and comparators) for signal acquisition and preliminary judgment.

[0040] To achieve efficient and reliable interconnection between the test circuit board 20 and the test substrate 10, and to physically support the control chip's access to each layer of the stacked bare chips, this embodiment incorporates specific designs on the test substrate 10: Please see Figure 5 middle A As shown, a control chip connection area 170 is specifically provided on the back side of the substrate body of the test substrate 10 (i.e., the side facing away from the bare chip setting area 110). The physical layout (such as size and connector type) of this area 170 matches the output interface of the test circuit board 20.

[0041] Multiple control chip connection pins 171 are arranged in an array on the control chip connection area 170. The number, spacing, electrical sequence, and functional definition of these pins 171 precisely correspond to the pin layout of the control chip described on the test circuit board 20. For example, each data input / output (I / O) pin, address pin, or control pin of the control chip has a unique corresponding control chip connection pin 171 on the control chip connection area 170.

[0042] The key internal connection structure is that each of the control chip connection pins 171 is independently and point-to-point connected to a specific pad connection point 121 in a specific pad unit 120 at the front end through the complex multi-layer wiring structure inside the test substrate 10 (including precision traces in multiple metal layers and metal vias for interlayer interconnection). This internal connection network is consistent with the connection network from the interface connection point 131 of the connection unit 130 to the pad connection point 121 in terms of design and manufacturing principle; both are pre-defined physical channels.

[0043] The established electrical connection path is as follows: test commands and data issued by the control chip on the test circuit board 20 are output from its pins, transmitted via the board-to-board connector to the corresponding control chip connection pin 171 on the back of the test substrate 10, and then routed through a dedicated trace channel inside the substrate to the pad unit 120 bound to the target bare chip layer, and finally applied to the corresponding pad of the bare chip in that layer through wire bonding. The response signal is transmitted back to the control chip along the same path.

[0044] This embodiment, by adding a dedicated control chip connection area 170 and corresponding internal wiring, enables external control chips to directly and independently access each layer of the stacked bare chips without complex adapters or shared buses. This provides an efficient hardware channel for implementing complex, inter-layer interactive test algorithms. The test substrate 10 and the test circuit board 20 carrying the control chip together constitute a fully functional "test daughter card" or "test socket." Users can replace or upgrade the test circuit board 20 according to different test requirements (such as testing different storage protocols) without redesigning the entire test interface hardware, greatly improving the modularity and reusability of the system. Integrating the control chip and its related circuits into a separate test circuit board 20, and then connecting it to the test substrate 10 via a robust board-to-board connector, replaces numerous discrete cable connections. This simplifies the overall structure of the test head, reduces connection points, and improves the mechanical stability and long-term reliability of the system.

[0045] Please see Figure 6 As shown, Figure 6 This is a flowchart illustrating a stacked chip testing method provided in an embodiment of the present invention. The stacked chip testing method is applied to the stacked chip testing system described in the above embodiment, and includes: Step S1: Place the stacked bare chip to be tested in the bare chip setting area of ​​the substrate body.

[0046] Specifically, the stacked bare chips to be tested (usually after wafer-level preliminary testing) are precisely aligned and fixed to the bare chip placement area on the test substrate. This area is typically treated with special surface treatments or designed with micromechanical fixtures to ensure that the chip remains in place during subsequent precision operations and testing, laying the foundation for reliable electrical connections.

[0047] Step S2: Connect the edge pads of each layer of bare chips in the stacked bare chips under test to different pad units on the substrate body by wire bonding.

[0048] Specifically, this step is crucial for constructing the physical test path. Using high-precision automated wire bonding equipment, the independent edge pads of each layer of the stacked bare chips are connected to different, specific pad units on the test substrate via fine metal wires (such as gold wires). This embodiment follows a strict "one layer to one unit" mapping rule. For example, all signal and power pads on the bottom layer of the stack are wire bonded to the first pad unit; the pads of the adjacent second layer are connected to the second pad unit; and so on for subsequent layers. This ensures that each layer of bare chips in the stack exclusively occupies all connection points of a single pad unit physically and electrically. If the total number of preset pad units on the test substrate (e.g., eight) exceeds the actual number of layers of the chip under test (e.g., five), the wire bonding operation only uses the required number of pad units (e.g., the first five), leaving the remaining units electrically unconnected. This operation intuitively demonstrates the versatility advantage of the substrate's "resource pool" design.

[0049] Step S3: Connect the interface connection point of the connection unit of the substrate body to the test circuit board.

[0050] Specifically, the test substrate with completed chip wire bonding is connected to the test circuit board carrying control and resource functions to form a complete test loop. The input / output interfaces of the control chip (such as a SoC or FPGA) on the test circuit board are connected to the control chip connection area on the back of the test substrate via a high-reliability board-to-board connector. This provides the control logic with signal channels directly to each bare chip layer. Similarly, the outputs of the test resource circuits (including precision programmable power supplies, measurement modules, etc.) on the test circuit board are connected to the connection units on the front of the test substrate via connectors. Thus, the energy and measurement loops required for testing are established.

[0051] Step S4: By connecting the wiring inside the unit and the substrate body, selectively connect the test resources of the test device to the pad unit corresponding to the target bare chip layer, and test the target bare chip layer. When testing the target bare chip layer, test power is applied only to the target bare chip layer currently being tested.

[0052] Specifically, through the coordinated control of the test circuit board, the following cyclic process is executed until all layers have been tested: 1. Channel Selection: The control logic in the test circuit board issues commands to selectively connect only the test resource circuits (signal sources, measurement units) to the pad cell corresponding to the current target layer through the wiring network embedded in the substrate. For example, when testing the first layer, all test resources are connected only to the first pad cell; when testing the second layer, the connection is switched to the second pad cell.

[0053] 2. Power Isolation: A strict power isolation strategy is implemented during channel selection. The test resource circuitry applies operating voltage and current only to the power pins of the current target layer, while the power management circuitry ensures that the power networks of all non-test layers are forced to be off or in a high-impedance state. This is the core guarantee against crosstalk between layers through the silicon substrate, vias, or parasitic paths.

[0054] 3. Test Execution and Evaluation: On an established and isolated dedicated channel, pre-defined test vectors (such as functional test patterns and parameter measurement signals) are applied to the target layer bare chip, and its response is collected. Test content may include open / short circuit tests, logic function verification, static / dynamic current measurement, and key timing parameter tests.

[0055] 4. Result Recording and Layer Switching: Record the test results for this layer (pass / fail and detailed parameters). After completing the test for the current layer, the control logic safely disconnects its power and signals, and switches to the next target layer for testing according to the process described in 1-3 above.

[0056] This invention, through a "one layer, one channel" hardware foundation and a "layer-by-layer testing" method, ensures that any functional or parameter failure can be clearly attributed to a specific bare chip layer or inter-layer interconnect, providing unprecedented clarity for process improvement and failure analysis. Regardless of the total number of stacked bare chip layers, the same standard process of "selection, isolation, testing, and switching" is followed. This greatly simplifies the development of automated test programs and makes the operation of the test system unified and efficient, significantly improving the overall test throughput.

[0057] Furthermore, based on the above embodiments, in other embodiments, testing the target bare chip layer includes at least one of: open / short circuit testing, functional testing, current testing, and timing testing.

[0058] Furthermore, based on the above embodiments, in other embodiments, after completing the layer-by-layer testing of each bare chip layer, the following steps are also included: Power is simultaneously applied to at least two bare die layers vertically interconnected through through-silicon vias, a test signal is sent from one of the bare die layers, and the signal integrity is received and verified on the other bare die layer.

[0059] Specifically, after completing all tests and confirming that each bare chip in the stack is functionally intact, a supplementary test specifically targeting the quality of inter-layer interconnects is performed on chips using through-silicon vias (TSVs) for vertical electrical interconnection. TSVs are the "vertical conductors" of a three-dimensional stack, and their manufacturing involves complex processes such as deep hole etching, insulating layer deposition, and copper filling, which can easily introduce defects such as open circuits, short circuits, high resistance, and impedance mismatches. These defects do not affect the functionality of the bare chip itself, but can directly lead to inter-layer communication failure or signal degradation. In this embodiment, operating power is simultaneously applied to two (or more) bare chip layers (e.g., Die A for transmitting data and Die B for receiving data) that need to be interconnected through the same set of TSVs, and the relevant signal channels are connected. This differs from the "single-layer power-on" principle in layer-by-layer testing. The specific process includes: 1. Send a test signal with known characteristics (e.g., a pulse with steep edges or a square wave of a specific frequency) from the driver of a layer (e.g., Die A) through the target TSV channel.

[0060] 2. At the receiving end of another interconnected layer (such as Die B), the transmitted signal is captured through pad units and independent channels.

[0061] 3. The analysis unit of the test circuit board measures and analyzes key parameters such as the amplitude of the received signal, rise / fall time, overshoot / undershoot, signal integrity eye diagram, and transmission delay.

[0062] Finally, compare the measurement results with the model or datasheet of a good TSV. For example, severe signal amplitude attenuation may indicate that the TSV resistance is too high or there is a partial open circuit; severe waveform distortion may mean impedance mismatch; abnormal delay may indicate that parasitic parameters are too large.

[0063] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A substrate for testing stacked chips, characterized in that, include: The substrate body has a bare chip placement area for placing stacked bare chips under test; Multiple independent pad units are disposed around the bare chip placement area. Each pad unit includes multiple pad connection points for electrically connecting to the edge pads of the corresponding layer of the stacked bare chips via wire bonding. A connection unit, disposed on the substrate body, includes multiple interface connection points for connecting to a test circuit board; The number of pad units is greater than or equal to the number of bare chip layers in the stacked bare chip under test; each interface connection point in the connection unit is connected to the pad connection point in a different pad unit through the traces in the substrate body.

2. The substrate for stacked chip testing according to claim 1, characterized in that, The plurality of independent pad units are symmetrically arranged on opposite sides of the bare chip setting area.

3. The substrate for stacked chip testing according to claim 1, characterized in that, The substrate body includes multiple stacked metal layers, and the interface connection points are connected to the corresponding solder pad connection points through traces and metal vias in the metal layers.

4. The substrate for stacked chip testing according to claim 1, characterized in that, The substrate body also has a control chip connection area on the side facing away from the bare chip setting area. The control chip connection area is provided with a plurality of control chip connection pins, which are connected to the pad connection points of the pad unit through the traces in the substrate body.

5. The substrate for stacked chip testing according to claim 1, characterized in that, The number of pad units is 8.

6. The substrate for stacked chip testing according to claim 1, characterized in that, The number of connection units is multiple.

7. A stacked chip testing system, characterized in that, include: The substrate for stacked chip testing as described in any one of claims 1 to 6; The test circuit board is connected to the interface connection point of the connection unit of the substrate, and is used to provide test signals and receive test feedback.

8. A method for testing stacked chips, characterized in that, It is applied to the stacked chip testing system of claim 7, wherein the method includes: Place the stacked bare chips under test in the bare chip setting area of ​​the substrate body; The edge pads of each layer of bare chip in the stacked bare chip under test are respectively connected to different pad units on the substrate body by wire bonding; Connect the interface connection point of the connection unit of the substrate body to the test circuit board; Through the connection unit and the wiring inside the substrate body, the test resources of the test device are selectively connected to the pad unit corresponding to the target bare chip layer, and the target bare chip layer is tested. When testing the target bare chip layer, test power is applied only to the target bare chip layer currently being tested.

9. The stacked chip testing method according to claim 8, characterized in that, The testing of the target bare chip layer includes at least one of the following: open / short circuit testing, functional testing, current testing, and timing testing.

10. The stacked chip testing method according to claim 8, characterized in that, After completing the layer-by-layer testing of each bare chip layer, the following is also included: Power is simultaneously applied to at least two bare die layers vertically interconnected through through-silicon vias, a test signal is sent from one of the bare die layers, and the signal integrity is received and verified on the other bare die layer.

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