Board card test tool circuit board

Abstract

The invention discloses a board card testing tool circuit board, and relates to the technical field of board card testing, and the board card testing tool circuit board comprises a first processor circuit, a second processor circuit, an FPGA circuit, and a testing circuit. The first processor circuit is respectively connected with the second processor circuit and the FPGA circuit, the test circuit is connected with the FPGA circuit, and the tested board card is respectively connected with the test circuit and the second processor; the first processor circuit is used for responding to the obtained upper computer instruction, sending a first test instruction to the second processor circuit and sending a second test instruction to the FPGA circuit; the second processor circuit is used for responding to the obtained first test instruction and executing a direct-current voltage acquisition task aiming at the tested board card; the FPGA circuit is used for receiving the test instruction sent by the first processor and driving the test circuit to execute a test task for the tested board card; and the test circuit is used for performing interface detection, output waveform detection, nozzle data line detection and LVDS data path detection on the tested board card.

Description

A circuit board for board testing fixture Technical Field

[0001] This invention relates to the field of circuit board testing technology, and in particular to a circuit board for circuit board testing fixtures. Background Technology

[0002] The inkjet printing circuit board is the core control component of an inkjet printer, and the integrity and stability of its hardware functions directly determine the printer's print quality and operational reliability. Therefore, the circuit board must undergo comprehensive troubleshooting verification before leaving the factory to ensure that it meets actual usage requirements.

[0003] In the existing technology, the factory verification of inkjet printing boards adopts a test mode of whole machine mounting and printhead connection. This test mode requires fixing the board to be tested on a complete inkjet printer and connecting a printhead filled with ink. The actual printing operation is performed by driving the printer to observe whether the printing effect is normal, so as to determine whether there is a hardware failure of the board.

[0004] However, this testing mode relies on the entire inkjet printer and a dedicated printhead. The tested board cannot be independently verified without the entire machine, which limits the testing scenarios to the number of available machines and site conditions. Furthermore, each test requires a significant amount of time for board disassembly and assembly, as well as machine debugging, resulting in extremely poor testing flexibility.

[0005] Therefore, there is an urgent need for a circuit board testing solution that does not rely on the entire inkjet printer and printhead, can achieve automated and accurate testing, and is adapted to the needs of mass production. Summary of the Invention

[0006] In view of the above-mentioned technical status, the present invention provides a circuit board testing fixture to provide a circuit board testing solution that can achieve automated and accurate testing and adapt to the needs of mass production without relying on the entire inkjet printer and printhead.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a board test fixture circuit board, comprising: a first processor circuit, a second processor circuit, an FPGA circuit, and a test circuit; the first processor circuit is connected to the second processor circuit and the FPGA circuit respectively, the test circuit is connected to the FPGA circuit, and the board under test is connected to the test circuit and the second processor circuit respectively; the first processor circuit is used to send a first test instruction to the second processor circuit and a second test instruction to the FPGA circuit in response to receiving instructions from a host computer; the second processor circuit is used to execute a DC voltage acquisition task for the board under test in response to receiving the first test instruction; the FPGA circuit is used to receive the test instruction sent by the first processor circuit and drive the test circuit to execute the test task for the board under test; the test circuit is used to perform interface detection, output waveform detection, nozzle data line detection, and LVDS data path detection for the board under test.

[0008] In one optional embodiment of this application, it further includes: a voltage divider circuit, which is connected to the second processor circuit and the board under test respectively; the voltage divider circuit is used to divide the DC voltage to be tested output by the board under test that exceeds the reference voltage range of the second processor circuit, and send the divided voltage signal to the second processor circuit so that the second processor circuit can complete the DC voltage acquisition.

[0009] In one optional embodiment of this application, the test circuit includes: a high-speed A / D conversion circuit, an input detection circuit, an output control circuit, and an LVDS serial-to-parallel conversion circuit; the output control circuit is used to output high and low level signals to the board under test to perform interface detection for the grating reader interface, input sensor interface, and paper sensor interface of the board under test; the high-speed A / D conversion circuit is used to acquire the waveforms of the multiple drive units of the board under test under the control of the FPGA circuit to perform output waveform detection on the board under test; the input detection circuit is used to receive the output signal of the board under test and send the output signal of the board under test to the FPGA circuit to perform nozzle data line detection on the FPGA; the LVDS serial-to-parallel conversion circuit is used to send a high-speed serial signal to the board under test to perform LVDS data path detection on the board under test.

[0010] In one optional embodiment of this application, the test circuit further includes a correction switching circuit; wherein the correction switching circuit is connected to the output control circuit, the board under test, and one end of an external multimeter, the other end of the external multimeter is connected to the RS232 serial port of the board test fixture, and the other end of the RS232 serial port is connected to the first processor circuit; the correction switching circuit is used to switch the voltage of different channels of the board under test to the external multimeter under the control of the FPGA circuit; after the external multimeter measures the voltage, it generates voltage measurement data and transmits the voltage measurement data to the first processor circuit through the RS232 serial port, whereby the first processor circuit completes the voltage correction.

[0011] In one optional embodiment of this application, it further includes: a programming serial port; the programming serial port is connected to the first processor circuit, the FPGA circuit, and the board under test respectively; the programming serial port is used to send a preset programming program to the board under test under the coordinated control of the first processor circuit and the FPGA circuit.

[0012] In one optional embodiment of this application, it further includes: a FLASH circuit; the FLASH circuit is connected to the first processor circuit; the FLASH circuit is used to store the running program of the first processor circuit, the configuration program of the FPGA circuit, and the test program of the board under test, for the first processor circuit to read and call.

[0013] In one optional embodiment of this application, the first processor circuit is further configured to read and start the running program stored in the FLASH circuit; read the configuration program in the FLASH circuit and transmit the configuration program to the FPGA circuit to complete the functional initialization of the FPGA circuit; and read the test program of the board under test stored in the FLASH circuit and, under the cooperative control of the FPGA circuit, send the test program to the board under test through the programming serial port.

[0014] In one optional embodiment of this application, it further includes: a USB interface; the USB interface is connected to the host computer and the first processor circuit respectively; the USB interface is used to establish a communication connection between the host computer and the first processor circuit, so that the host computer can send test commands and programming control commands to the first processor circuit through the USB interface, and the first processor circuit can upload test data and programming status information to the host computer through the USB interface.

[0015] In one optional embodiment of this application, it further includes: a power module circuit and a switching circuit; the power module circuit is connected to the first processor circuit, the FPGA circuit, and the test circuit respectively; the switching circuit is connected to the power module circuit, the first processor circuit, and the board under test respectively; the power module circuit is used to receive power supply voltage, convert the power supply voltage into an adaptive voltage for the processor circuit, the FPGA circuit, and the test circuit, and input the adaptive voltage into the first processor circuit, the FPGA circuit, and the test circuit respectively; the switching circuit is used to control the power supply to the board under test under the control of the first processor circuit.

[0016] Compared with existing technologies, the circuit board for board testing provided by this invention, through the collaborative architecture of a first processor circuit, a second processor circuit, an FPGA circuit, and a test circuit, eliminates the need for the board under test to be fixed to the entire inkjet printer or connected to an inkjet printhead. It only needs to directly interface with the test circuit and the second processor circuit. The first processor circuit issues test commands, and the test of the board is completed based on the second processor circuit and the test circuit. This eliminates the strong dependence of traditional testing on the entire machine and printhead, greatly reduces the constraints of the test scenario, and improves the flexibility of testing. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and constitute a part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 is a structural diagram of a circuit board for a board test fixture provided in an embodiment of this application.

[0018] Figure 2 is a structural diagram of the circuit board of the board test fixture provided in the embodiment of this application. Detailed description

[0019] First processor circuit-1, Second processor circuit-2, FPGA circuit-3, Test circuit-4, High-speed A / D conversion circuit-5, Input detection circuit-6, Output control circuit-7, LVDS serial-to-parallel conversion circuit-8, Voltage divider circuit-9, Correction switching circuit-10, External multimeter-11, RS232 serial port-12, FLASH circuit-13, USB interface-14, Programming serial port-15, Power module circuit-16, Switching circuit-17. Detailed Implementation

[0020] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0021] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0023] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0024] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0025] This application provides a circuit board for board testing. Please refer to Figure 1, which is a structural diagram of the circuit board for board testing provided in this application.

[0026] As shown in Figure 1, the board test fixture includes: a first processor circuit 1, a second processor circuit 2, an FPGA circuit 3, and a test circuit 4.

[0027] The first processor circuit 1 is connected to the second processor circuit 2 and the FPGA circuit 3 respectively, the test circuit 4 is connected to the FPGA circuit 3, and the board under test is connected to the test circuit 4 and the second processor circuit 2 respectively.

[0028] The first processor circuit 1 can be understood as the core control circuit of the embodiment of this application. In actual application, it is equipped with an ARM chip, a large-capacity data memory (DDR), and a high-speed cache chip (SRAM) to undertake the overall coordination task of the board test fixture.

[0029] In this embodiment of the application, the first processor circuit 1 is configured to send a first test instruction to the second processor circuit 2 and a second test instruction to the FPGA circuit 3 in response to receiving instructions from the host computer.

[0030] The second processor circuit 2 can be understood as the auxiliary execution circuit of this application embodiment. In actual application, it is equipped with an ARM chip with relatively weak processing power to respond to the first test instruction of the first processor and execute the DC voltage acquisition task of the board under test.

[0031] FPGA circuit 3 is a field-programmable gate array, a semiconductor circuit module that can define logic functions through configuration data. In one embodiment of this application, FPGA circuit 3 is used to receive test instructions sent by the first processor circuit 1 and drive the test circuit 4 to execute test tasks for the board under test, so as to serve as a high-speed execution unit to process multiple test tasks in parallel and make up for the limitations of ARM chips in real-time control and multi-channel signal processing.

[0032] Test circuit 4 is a functional circuit that is responsible for interacting with the board under test and performing specific testing operations. Specifically, test circuit 4 is used to perform interface testing, output waveform testing, nozzle data line testing, and LVDS data path testing for the board under test.

[0033] Furthermore, please refer to Figure 2, which is a structural diagram of the circuit board of the board test fixture provided in the embodiment of this application.

[0034] As shown in Figure 2, the test circuit 4 includes: a high-speed A / D conversion circuit 5, an input detection circuit 6, an output control circuit 7, and an LVDS serial-to-parallel conversion circuit 8.

[0035] The test circuit is a functional execution cluster that directly interfaces with the board under test (DUT). Its core lies in breaking down the DUT's hardware functionality into multiple specialized sub-circuits. Each sub-circuit focuses on testing a specific type of core hardware, and then, through unified driving and control by the FPGA circuit, achieves efficient parallel or time-sharing testing. This replaces the traditional verification logic of the entire device plus the printhead, allowing for verification of the board's hardware functionality through electrical signal interaction without actual printing operations.

[0036] Specifically, the output control circuit 7 is used to output high and low level signals to the board under test to perform interface detection for the grating read head interface, input sensor interface and paper sensor interface of the board under test.

[0037] The output control circuit, as the signal output terminal of the board test fixture circuit board, outputs preset high and low level signals (such as 3.3V high level and 0V low level) to the designated interface (grating reader interface, input sensor interface, paper sensor interface) of the board under test when the corresponding test command is issued by the FPGA circuit, simulating the external trigger signal when the board is working normally.

[0038] By detecting the response status of the board under test to the high and low level signals, it is possible to determine whether there are faults such as open circuits, short circuits, or functional failures in the board's input interface, such as whether a normal response signal is fed back and whether the interface is conductive. In this way, it is possible to verify whether the connection interface between the board and external functional components (grating reader, input sensor, paper sensor) is normal, and to ensure that the board can receive and respond to the trigger signals of external devices.

[0039] The high-speed A / D conversion circuit 5 is used to acquire the waveforms of the multiple drive units of the board under test under the control and switching of the FPGA circuit, so as to detect the output waveform of the board under test.

[0040] The high-speed A / D conversion circuit 5, as the unit for converting analog signals to digital signals, is connected to the multi-channel drive unit of the board under test (corresponding to the inkjet printing board, a total of 8 drive units, including the printhead drive, motor drive, etc. of the inkjet printing board) in a time-division manner under the channel switching control of the FPGA circuit. It collects the analog waveform signals output by each drive unit, converts them into digital waveform data, and then feeds them back to the first processor circuit 1 through the FPGA circuit. This verifies whether the waveform output of the drive unit meets the design standards (such as whether the waveform amplitude, frequency, and phase are normal) and troubleshoots the circuit faults of the drive unit (such as waveform distortion caused by power transistor damage, signal attenuation, etc.).

[0041] The input detection circuit 6 is used to receive the output signal of the board under test and send the output signal of the board under test to the FPGA circuit to perform nozzle data line detection on the FPGA.

[0042] The input detection circuit 6 serves as the signal receiving end of the circuit board of the board test fixture. It connects to the nozzle data line interface of the board under test, receives the signal output by the board through the nozzle data line, and transmits the signal to the FPGA circuit after internal shaping and filtering. The FPGA then feeds back the signal to the first processor circuit 1 for signal analysis, thereby verifying whether the nozzle data line of the board can output a signal normally (such as whether there is an open circuit or a short circuit between signals), ensuring that the signal transmission path between the board and the nozzle is normal.

[0043] The LVDS serial-to-parallel conversion circuit is used to send a high-speed serial signal to the board under test to perform LVDS data path detection on the board under test.

[0044] The LVDS serial-to-parallel conversion circuit is mainly used to convert parallel signals into high-speed serial signals. The FPGA circuit first outputs a parallel test signal, which is then converted into a high-speed serial LVDS signal by this circuit and transmitted to the board under test. If the board can normally respond with a response signal after receiving the signal, it indicates that the LVDS data path is smooth, thereby verifying the signal conversion and transmission capabilities of the LVDS interface, ensuring that the high-speed data transmission path of the board (such as the transmission channel of print data and control commands) is normal, and meeting the high bandwidth and low latency data transmission requirements during inkjet printing.

[0045] Furthermore, the circuit board for board testing also includes: voltage divider circuit 9.

[0046] The purpose of voltage divider circuit 9 is to solve the problem of mismatch in the range of measurements acquired by the second processor circuit.

[0047] Specifically, the voltage divider circuit 9 is connected to the second processor circuit and the board under test respectively, which is equivalent to building an adaptation bridge between the high voltage of the board under test and the low range acquisition of the second processor.

[0048] The second processor circuit is essentially a low-performance ARM chip with a fixed reference voltage range. Directly acquiring a DC voltage from the board under test that exceeds this range will damage the second processor circuit and prevent accurate measurement. In this embodiment, the voltage divider circuit 9 is used to divide the DC voltage output from the board under test that exceeds the reference voltage range of the second processor circuit, and sends the divided voltage signal to the second processor circuit so that the second processor circuit can complete the DC voltage acquisition.

[0049] In practical applications, the second processor circuit is only responsible for receiving and acquiring the voltage signal after voltage division, and does not directly process high voltage; the voltage divider circuit is a pure hardware adapter module that only completes the voltage step-down conversion to ensure the safety of the entire DC voltage acquisition process.

[0050] In one optional embodiment of this application, the test circuit 4 further includes a correction switching circuit 10.

[0051] The correction switching circuit 10 is connected to the output control circuit 7, the board under test, and one end of the external multimeter 11. The other end of the external multimeter 11 is connected to the RS232 serial port of the board test fixture, and the other end of the RS232 serial port is connected to the first processor circuit 1.

[0052] The correction switching circuit 10 is used to switch the voltage of different channels of the board under test to the external multimeter 11 under the control of the FPGA circuit.

[0053] After the external multimeter 11 measures the voltage, it generates voltage measurement data and transmits the voltage measurement data to the first processor circuit through the RS232 serial port 12. The first processor circuit then performs voltage correction.

[0054] In practical applications, when the test process reaches the voltage correction stage, the first processor circuit sends a voltage correction command to the FPGA circuit. The FPGA circuit controls the internal switch of the correction switching circuit according to the command, turns on the voltage path of the board under test, and transmits the voltage of the corresponding voltage path of the board under test to the probe of the external multimeter 11 for measurement.

[0055] After the external multimeter 11 completes the measurement, it sends the voltage measurement data to the first processor circuit through the RS232 serial port 12. The first processor circuit transmits the measured value of the multimeter to the board under test through the LVDS serial-to-parallel conversion circuit 8, saves it as the calculation parameters of the fitting curve, and uses it as the basis for correcting the output voltage value of the board under test.

[0056] Furthermore, the board test fixture circuit board also includes: FLASH circuit 13; FLASH circuit 13 is connected to the first processor circuit; FLASH circuit 13 is used to store the running program of the first processor circuit, the configuration program of the FPGA circuit, and the test program of the board under test, for the first processor circuit to read and call.

[0057] The FLASH circuit 13 can be understood as the program and data carrier of the fixture, storing the running program of the first processor circuit, the configuration program of the FPGA circuit, and the test program of the board under test. After the fixture is powered on, the first processor circuit first reads the running program and starts it, so as to have the ability to control the entire test process. The first processor circuit also reads the configuration program stored in the FLASH and transmits it to the FPGA circuit to complete the functional initialization of the FPGA, enabling it to drive the test circuit, control channel switching, and ensure the timing of programming. After the test process starts, the first processor circuit also reads the test program of the board under test from the FLASH and then sends the test program to the board under test, so that the board under test has the ability to start and adapt to the functional logic of the fixture test.

[0058] To establish a communication connection between the tooling and the host computer, the board of the test tooling also includes a USB interface 14; the USB interface 14 is connected to the host computer and the first processor circuit respectively; the USB interface is used to establish a communication connection between the host computer and the first processor circuit, so that the host computer can send test commands and programming control commands to the first processor circuit through the USB interface, and the first processor circuit can upload test data and programming status information to the host computer through the USB interface.

[0059] Furthermore, to enable the distribution of test programs, the board test fixture circuit board also includes a programming serial port 15. The programming serial port 15 is connected to the first processor circuit, the FPGA circuit, and the board under test.

[0060] In this embodiment, the programming serial port 15 serves as a program transmission channel between the tooling and the board under test, undertaking the bidirectional transmission of programming instructions and program data.

[0061] Specifically, the programming serial port 15 is used to send the preset programming program to the board under test under the coordinated control of the first processor circuit and the FPGA circuit.

[0062] In practical applications, the process of burning programs is not controlled by a single unit, but rather by the coordinated operation of the first processor circuit and the FPGA circuit 3.

[0063] Specifically, the first processor circuit, as the main control unit, is responsible for reading the preset programming program from the FLASH circuit and sending instructions such as start programming, transmit program data, and stop programming to the programming serial port; at the same time, it receives the program reception success or failure signal from the board under test to determine whether programming is complete.

[0064] FPGA circuit 3 serves as a coordinating unit, responsible for providing the chip select signal required for programming, ensuring that the board under test is in programming mode during programming.

[0065] In practical applications, the preset programming program includes: Boot program, ARM test program, FPGA test program, ARM program and FPGA program.

[0066] The Boot program can be understood as the basic boot program of the board under test. After being written, the board under test completes its own hardware initialization and establishes a communication connection with the tooling.

[0067] The ARM test program and the FPGA test program are functional programs adapted for tooling testing. After being written, the ARM chip and FPGA module of the board under test will work according to the test logic, enabling the tooling to accurately detect hardware faults of the board.

[0068] The official ARM and FPGA programs are the factory-installed functional programs for the actual operation of the board under test, and are only written after all hardware tests have passed. After writing, the board under test has the core function of inkjet printing and can be shipped directly without additional configuration.

[0069] Furthermore, in order to ensure the power supply of the board for board testing, the board for board testing fixture also includes: a power module circuit 16 and a switch circuit 17; the power module circuit 16 is connected to the first processor circuit, the FPGA circuit and the test circuit respectively; the switch circuit 17 is connected to the power module circuit, the first processor circuit and the board under test respectively.

[0070] The power module circuit 16 is used to receive the power supply voltage, convert the power supply voltage into the adaptation voltage of the processor circuit, FPGA circuit and test circuit, and input the adaptation voltage into the first processor circuit, FPGA circuit and test circuit respectively.

[0071] The switching circuit 17 is used to control the power supply to the board under test under the control of the first processor circuit.

[0072] In practical applications, the externally input power supply voltage (such as the 24V DC voltage commonly used in tooling) often cannot directly meet the operating requirements of each circuit. For example, the first processor circuit and the FPGA circuit may require precise voltages of 3.3V and 5V, respectively, while the high-speed A / D conversion circuit in the test circuit may require an analog voltage of ±12V. The power module circuit 16 integrates voltage regulator chips, DC-DC converters, and other devices to convert the external input voltage into multiple sets of adapted stable voltages, which are then supplied to the first processor circuit, the FPGA circuit, and the test circuit to ensure the stable operation of each unit.

[0073] When the first processor circuit receives the start test command from the host computer, it sends a conduction signal to the switch circuit 17. The switch circuit closes, and the power module circuit 16 outputs the appropriate voltage (such as the 42V voltage required by the board under test) to the board under test. The board under test is powered on and started, preparing for subsequent program burning and hardware testing.

[0074] If a hardware fault is detected on the board during the test, the first processor circuit can send a disconnect signal, and the switch circuit will cut off the power supply to the board under test to prevent the faulty board from being continuously powered on and causing secondary damage. If all tests pass and the formal program is completed, the switch circuit can cut off the power according to the instruction to end the test process.

[0075] In summary, the circuit board for board testing provided in this application, through the collaborative architecture of the first processor circuit, the second processor circuit, the FPGA circuit, and the test circuit, eliminates the need for the board under test to be fixed to the entire inkjet printer or connected to the ink refill head. It only needs to directly interface with the test circuit and the second processor circuit. The first processor circuit issues test commands, and the test of the board is completed based on the second processor circuit and the test circuit. This eliminates the strong dependence of traditional testing on the entire machine and the printhead, greatly reduces the constraints of the test scenario, and improves the flexibility of testing.

[0076] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A circuit board for board testing fixtures, characterized in that, include: The circuit consists of a first processor circuit, a second processor circuit, an FPGA circuit, and a test circuit. The first processor circuit is connected to the second processor circuit and the FPGA circuit respectively, the test circuit is connected to the FPGA circuit, and the board under test is connected to the test circuit and the second processor circuit respectively. The first processor circuit is used to send a first test instruction to the second processor circuit and a second test instruction to the FPGA circuit in response to receiving instructions from the host computer. The second processor circuit is used to execute a DC voltage acquisition task for the board under test in response to receiving the first test instruction. The FPGA circuit is used to receive the test instruction sent by the first processor circuit and drive the test circuit to execute the test task for the board under test. The test circuit is used to perform interface detection, output waveform detection, nozzle data line detection, and LVDS data path detection for the board under test.

2. The circuit board for board testing according to claim 1, characterized in that, Also includes: The voltage divider circuit is connected to the second processor circuit and the board under test respectively. The voltage divider circuit is used to divide the DC voltage output by the board under test that exceeds the reference voltage range of the second processor circuit, and send the divided voltage signal to the second processor circuit so that the second processor circuit can complete the DC voltage acquisition.

3. The circuit board for board testing according to claim 1, characterized in that, The test circuit includes: a high-speed A / D conversion circuit, an input detection circuit, an output control circuit, and an LVDS serial-to-parallel conversion circuit. The output control circuit outputs high and low level signals to the board under test (DUT) to perform interface detection on the DUT's grating reader interface, input sensor interface, and paper sensor interface. The high-speed A / D conversion circuit, under the control of the FPGA circuit, acquires waveforms from multiple drive units of the DUT to perform output waveform detection. The input detection circuit receives the output signal from the DUT and sends it to the FPGA circuit for printhead data line detection. The LVDS serial-to-parallel conversion circuit sends a high-speed serial signal to the DUT to perform LVDS data path detection.

4. The circuit board of the board testing fixture according to claim 3, characterized in that, The test circuit further includes a correction switching circuit; wherein the correction switching circuit is connected to the output control circuit, the board under test, and one end of an external multimeter, the other end of the external multimeter is connected to the RS232 serial port of the board test fixture, and the other end of the RS232 serial port is connected to the first processor circuit; the correction switching circuit is used to switch the voltage of different channels of the board under test to the external multimeter under the control of the FPGA circuit; after the external multimeter measures the voltage, it generates voltage measurement data, and transmits the voltage measurement data to the first processor circuit through the RS232 serial port, whereby the first processor circuit completes the voltage correction.

5. The circuit board for board testing according to claim 1, characterized in that, Also includes: Programming the serial port; The programming serial port is connected to the first processor circuit, the FPGA circuit, and the board under test, respectively. The programming serial port is used to send the preset programming program to the board under test under the coordinated control of the first processor circuit and the FPGA circuit.

6. The circuit board for board testing according to claim 1, characterized in that, Also includes: FLASH circuit; The FLASH circuit is connected to the first processor circuit; the FLASH circuit is used to store the running program of the first processor circuit, the configuration program of the FPGA circuit, and the test program of the board under test, so that the first processor circuit can read and call them.

7. The circuit board for board testing fixtures according to claim 6, characterized in that, The first processor circuit is further configured to read and start the running program stored in the FLASH circuit; read the configuration program in the FLASH circuit and transmit the configuration program to the FPGA circuit to complete the functional initialization of the FPGA circuit; and read the test program of the board under test stored in the FLASH circuit and, under the cooperative control of the FPGA circuit, send the test program to the board under test through the programming serial port.

8. The circuit board for board testing according to claim 1, characterized in that, Also includes: USB interface; The USB interface is connected to the host computer and the first processor circuit respectively; the USB interface is used to establish a communication connection between the host computer and the first processor circuit, so that the host computer can send test commands and programming control commands to the first processor circuit through the USB interface, and the first processor circuit can upload test data and programming status information to the host computer through the USB interface.

9. The circuit board for board testing fixture according to claim 1, characterized in that, Also includes: Power module circuit and switching circuit; The power module circuit is connected to the first processor circuit, the FPGA circuit, and the test circuit respectively; the switch circuit is connected to the power module circuit, the first processor circuit, and the board under test respectively; the power module circuit is used to receive the power supply voltage, convert the power supply voltage into the adaptation voltage of the processor circuit, the FPGA circuit, and the test circuit, and input the adaptation voltage into the first processor circuit, the FPGA circuit, and the test circuit respectively; the switch circuit is used to control the power supply to the board under test under the control of the first processor circuit.

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