Function test-based reference source trimming method and system

Abstract

The invention provides a reference source trimming method and system based on function testing, and relates to the technical field of integrated circuit testing, and the method comprises the steps: constructing a trimming vector and a target vector of a to-be-detected chip; presetting a trimming value sequence containing a plurality of trimming values; sequentially writing the trimming values into a writing unit of a trimming vector, and verifying whether an actual output value of a reading unit is consistent with an expected value or not after the vector is trimmed; if yes, executing the target vector, recording a test result corresponding to the current trimming value, and continuing to iterate the next trimming value; after all the trimming values in the to-be-trimmed value sequence are traversed, screening and writing effective trimming values and corresponding test results, positioning jump points at which the test results are changed from a qualified state to a failure state or from the failure state to the qualified state, and determining the trimming value corresponding to the jump points as a critical trimming value; and outputting the critical trimming value. According to the invention, the accuracy and feasibility of the trimming result can be guaranteed, and support is provided for chip working boundary exploration and subsequent modular application.

Description

A benchmark source tuning method and system based on functional testing Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and in particular to a reference source tuning method and system based on functional testing. Background Technology

[0002] In the field of integrated circuit chip manufacturing and testing, reference source tuning is a core step in ensuring chip performance consistency and stability. By precisely adjusting the configuration parameters of modules such as reference voltage and reference current within the chip, it ensures that the chip output meets design expectations, laying the foundation for subsequent modular applications and multi-chip collaborative operation. As chip functions become increasingly complex, test items have gradually differentiated into two categories: quantitative parameter testing (such as voltage and current output testing) and functional effectiveness testing (such as interface communication and logic operation testing). How to adapt reference source tuning methods to the needs of different types of test items has become an important issue in improving chip test coverage and accuracy.

[0003] To address the core requirement of reference source calibration, existing technologies typically preset specific quantization target measurement values, input different combinations of high and low level signals through the chip input interface, collect the corresponding output quantization values ​​of the chip, and select the calibration value corresponding to the value closest to the target value as the optimal solution.

[0004] However, the aforementioned existing technologies have shortcomings: their tuning logic essentially relies on quantifiable test data. For test items without quantifiable data, existing methods cannot identify the critical state of a function transitioning from failure to pass or from pass to failure, nor can they accurately capture the corresponding critical tuning values. This results in insufficient tuning accuracy of functional test items, making it difficult to explore the boundaries of chip operating conditions, which in turn affects the reliability of subsequent modular applications and fails to meet the refined tuning requirements of integrated circuit testing for functional items. Summary of the Invention

[0005] This invention provides a benchmark source tuning method and system based on functional testing. By separating the tuning vector and the target vector, verifying the validity of the tuning value writing, and capturing the jump points of the functional results, it can accurately obtain the critical tuning values ​​of the functional test items, ensure the accuracy and feasibility of the tuning results, and provide support for exploring the chip working boundary and subsequent modular applications.

[0006] To achieve the above objectives, embodiments of the present invention employ the following technical solutions: Firstly, a benchmark source tuning method based on functional testing is provided. The method includes: constructing a tuning vector of a chip under test, the tuning vector comprising a write unit and a read unit; the write unit comprising a chip memory address, a write instruction, and a tuning value; the read unit comprising the same chip memory address, a read instruction, and an expected value as the write unit; the tuning vector following a preset communication protocol of the chip under test and performing data transmission through specified input / output pins of the chip under test; determining a target vector of the chip under test, the target vector being a functional vector whose test results exhibit a qualified or failed state depending on the tuning value, the test results of the target vector being used to reflect the effectiveness of the chip's target function corresponding to the tuning value; pre-setting a tuning value sequence containing multiple tuning values, and initializing the tuning value sequence. The column index points to the first adjustment value in the sequence. Starting from the first adjustment value, the adjustment value corresponding to the current index is written to the write unit of the adjustment vector in sequence. After the adjustment vector is executed, it is verified whether the actual output value of the read unit is consistent with the expected value. If they are inconsistent, the test corresponding to the current adjustment value is stopped, the index is incremented to point to the next adjustment value and the iteration continues. If they are consistent, the target vector is executed and the test result corresponding to the current adjustment value is recorded. The index is incremented to point to the next adjustment value and the iteration continues until all adjustment values ​​in the adjustment value sequence are traversed. After all adjustment values ​​in the adjustment value sequence have been traversed, the valid adjustment values ​​and corresponding test results are filtered and written. The jump point where the test result changes from qualified to failed or from failed to qualified is located. The adjustment value corresponding to the jump point is determined as the critical adjustment value. The critical adjustment value is output to the data result file or written to the internal storage area of ​​the chip under test.

[0007] The method provided by this invention constructs a trimming vector containing write-read units, determines the target vector that changes with the trimming value, iteratively traverses and verifies the trimming values, locates the transition point to determine the critical value, and outputs and stores the critical value. First, it utilizes the write-read closed loop of the trimming vector to ensure that the trimming value is correctly received by the chip. Then, by iteratively traversing all trimming values ​​and synchronously recording the functional results, it solves the problem of having only binary results without quantized data. Finally, by accurately extracting the critical trimming value by locating the transition point, it fills the technical gap that traditional methods cannot obtain the critical trimming value, realizes the accurate trimming of the chip reference source, and effectively improves the stability and reliability of the chip's target function.

[0008] In one possible implementation of the first aspect, the trimming value is N-bit binary data, where N is greater than or equal to 1, and the trimming value sequence contains 0 to 2. N All N-bit binary combinations corresponding to -1.

[0009] The method provided by this invention, on the one hand, adapts to the adjustment accuracy requirements of different chip reference sources through the N-bit binary design, thereby improving the adaptability of the method; on the other hand, the sequence covers all possible combinations of adjustment values, ensuring that no adjustment value is missed, avoiding the omission of transition points due to the failure to test some adjustment values, providing a complete data foundation for subsequent accurate positioning of critical adjustment values, and further improving the accuracy and comprehensiveness of critical adjustment values.

[0010] In one possible implementation of the first aspect, the preset communication protocol of the chip under test is the I2C protocol or the SPI protocol; when the preset communication protocol of the chip under test is the I2C protocol, the designated input / output pins are the SDA pin and the SCL pin; when the preset communication protocol of the chip under test is the SPI protocol, the designated input / output pins are the MOSI pin, the MISO pin, and the SCK pin.

[0011] The method provided by this invention explicitly presets the communication protocol as I2C or SPI, and specifies the corresponding pins: First, I2C and SPI are the most widely used communication protocols in the chip field, which are compatible with the hardware interfaces of most chips under test, greatly improving the versatility of the method; Second, by specifying the pins corresponding to the protocol, data transmission interruption caused by incorrect pin selection is avoided, ensuring that the tuning vector can stably transmit tuning values ​​and verification data, reducing test time caused by transmission failure, and improving the stability and efficiency of the tuning process.

[0012] In one possible implementation of the first aspect, the step of verifying whether the actual output value of the readout unit is consistent with the expected value after executing the adjustment vector includes: using a high level or a low level as a judgment benchmark, wherein a high level of the actual output value corresponds to a binary bit 1 of the adjustment value and a low level corresponds to a binary bit 0 of the adjustment value; if the combination of high and low levels of the actual output value completely matches the expected value, then it is determined that the actual output value is consistent with the expected value.

[0013] The method provided by this invention uses the binary 1 corresponding to a high level and the binary 0 corresponding to a low level as the judgment criterion, and requires that the high and low level combinations of the actual output value and the expected value are completely matched before a consistency is determined. This judgment standard is clear and quantifiable, avoiding the misjudgment scenario where partial matching is valid. It ensures that only the trimmed value correctly received by the chip enters the subsequent target vector test, filters out the interference of invalid trimmed values ​​on the test data, improves the accuracy of the validity verification of the trimmed value writing, and lays a reliable data foundation for the subsequent accurate positioning of the transition point.

[0014] In one possible implementation of the first aspect, the internal storage area of ​​the chip to be tested is a non-volatile storage area, which includes an electrically erasable programmable read-only memory or a one-time programmable memory.

[0015] The method provided by this invention writes critical adjustment values ​​into a non-volatile memory area: EEPROM supports multiple erase and write operations, facilitating subsequent chip parameter adjustments; OTP has the characteristics of one-time write and long-term stable storage, suitable for scenarios where parameter adjustments are not required. The two storage types adapt to different application needs; at the same time, non-volatile storage ensures that critical adjustment values ​​are not lost after the chip is powered off, and the reference source can be directly read upon the next power-on without repeated adjustment, significantly reducing the operation and time costs of subsequent chip applications and improving the ease of chip use.

[0016] In one possible implementation of the first aspect, the location of the transition point where the test result changes from a qualified state to a failed state or from a failed state to a qualified state includes: sorting the selected valid correction values ​​in ascending order according to their corresponding binary values, and synchronously associating the test results corresponding to each correction value; comparing the test results corresponding to adjacent sorted correction values ​​one by one, and if the corresponding test results are a qualified state and a failed state respectively, then determining the transition position of the two adjacent correction values ​​as a transition point.

[0017] The method provided by this invention first sorts the valid correction values ​​written in ascending binary order, and then compares the test results of adjacent correction values ​​one by one: the ordered sorting ensures that the correction values ​​are arranged in sequence according to the parameter gradient, making the trend of functional results clearer; the comparison of adjacent results one by one avoids the omission of adjacent correction values ​​due to disordered order, ensuring that all possible jump points can be accurately located, providing accurate jump point basis for subsequent determination of critical correction values, and improving the reliability of critical value location.

[0018] In one possible implementation of the first aspect, determining the adjustment value corresponding to the jump point as the critical adjustment value includes: if there is only one jump point, determining the adjustment value that changes the test result from a failed state to a qualified state from two adjacent adjustment values ​​corresponding to the jump point as the critical adjustment value; if there are multiple jump points, filtering all adjustment values ​​corresponding to the jump points, and determining the adjustment value with the smallest binary value that changes the test result from a failed state to a qualified state as the critical adjustment value.

[0019] The method provided by this invention clearly defines the following rules: for single-hop change points, the adjustment value that turns failure into success is selected; for multi-hop change points, the adjustment value that turns failure into success and has the smallest binary value is selected. The single-hop change point rule ensures that the critical value that makes the function just passable is selected, avoiding insufficient or redundant parameters. The multi-hop change point rule selects the smallest adjustment value, which can reduce the parameter consumption of the chip reference source while ensuring the function passes, taking into account both functional stability and the chip's low power consumption requirements, and improving the optimality of the adjustment result.

[0020] In one possible implementation of the first aspect, the target function of the chip corresponding to the target vector includes a chip interface communication function or a chip logic operation function; when the target function of the chip is a chip interface communication function, the test result of the target vector determines the qualified state or the failed state by judging whether the data transmission between the chip and the external device is successful; when the target function of the chip is a chip logic operation function, the test result of the target vector determines the qualified state or the failed state by judging whether the output result of the chip logic operation is consistent with the preset theoretical result.

[0021] The method provided by this invention clearly defines the target functions, including chip interface communication functions and logic operation functions, and provides corresponding judgment criteria: the interface communication function is judged by whether the data transmission is successful, and the logic operation function is judged by whether the output result is consistent with the theoretical value. On the one hand, it covers the two most core functional test scenarios of the chip, greatly expanding the applicability of the method; on the other hand, the clear judgment criteria avoid the misunderstanding of the results by different testers, ensure the consistency of test results, and improve the universality of the method and the reliability of the test results.

[0022] Secondly, the present invention provides a benchmark source tuning system based on functional testing. The system includes: a tuning vector construction module, configured to: construct a tuning vector of a chip under test, the tuning vector comprising a write unit and a read unit; the write unit comprising a chip memory address, a write instruction, and a tuning value; the read unit comprising the same chip memory address, a read instruction, and an expected value as the write unit; the tuning vector follows a preset communication protocol of the chip under test and performs data transmission through designated input / output pins of the chip under test; a target vector determination module, configured to: determine a target vector of the chip under test, the target vector being a functional vector whose test result changes with the tuning value, resulting in a qualified or failed state; the test result of the target vector being used to reflect the effectiveness of the chip's target function corresponding to the tuning value; and a test result verification module, configured to: preset a tuning value sequence containing multiple tuning values, and initialize the tuning value sequence index. The first adjustment value in the sequence is pointed to. Starting from the first adjustment value, the adjustment value corresponding to the current index is written to the write unit of the adjustment vector in sequence. After the adjustment vector is executed, the actual output value of the read unit is verified to be consistent with the expected value. If they are inconsistent, the test corresponding to the current adjustment value is stopped, the index is incremented to point to the next adjustment value and the iteration continues. If they are consistent, the target vector is executed and the test result corresponding to the current adjustment value is recorded. The index is incremented to point to the next adjustment value and the iteration continues until all adjustment values ​​in the adjustment value sequence are traversed. The adjustment value determination module is used to: after all adjustment values ​​in the adjustment value sequence have been traversed, filter and write the valid adjustment values ​​and the corresponding test results, locate the jump point where the test result changes from qualified to failed or from failed to qualified, and determine the adjustment value corresponding to the jump point as the critical adjustment value. The result generation module is used to: output the critical adjustment value to the data result file or write it to the internal storage area of ​​the chip to be tested.

[0023] Thirdly, an electronic device is provided, the electronic device including a memory and one or more processors; the memory is coupled to the processors; wherein the memory stores computer program code, the computer program code including computer instructions, which, when executed by the processor, cause the electronic device to perform the method as described in any implementation of the first aspect.

[0024] Fourthly, a computer-readable storage medium is provided, including computer instructions that, when executed on an electronic device, cause the electronic device to perform a method as described in any implementation of the first aspect.

[0025] Fifthly, a computer program product is provided that, when run on a computer, causes the computer to perform the method in any implementation of the first aspect.

[0026] Understandably, the beneficial effects achieved by the system of the second aspect, the electronic device of the third aspect, the computer-readable storage medium of the fourth aspect, and the computer program product of the fifth aspect provided above can be referred to with reference to the beneficial effects of the first aspect and any of its possible design embodiments, which will not be repeated here. Attached Figure Description

[0027] Figure 1 is a schematic diagram of an electronic device provided in an embodiment of the present invention; Figure 2 is a flowchart of a reference source tuning method based on functional testing provided in an embodiment of the present invention; Figure 3 is a flowchart of another reference source tuning method based on functional testing provided in an embodiment of the present invention; Figure 4 is a schematic diagram of a tuning system provided in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be described below with reference to the accompanying drawings. In the description of the present invention, unless otherwise stated, " / " indicates that the objects before and after are in an "or" relationship. For example, A / B can represent A or B. The "or" in the present invention is merely a description of the relationship between the related objects, indicating that three relationships can exist. For example, A or B can represent: A alone, A and B simultaneously, and B alone. A and B can be singular or plural. Furthermore, in the description of the present invention, unless otherwise stated, "multiple" refers to two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items.

[0029] Furthermore, to facilitate a clear description of the technical solutions of the embodiments of the present invention, the terms "first" and "second" are used in the embodiments of the present invention to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0030] In this embodiment of the invention, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this embodiment of the invention should not be construed as superior or more advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner for ease of understanding.

[0031] In the field of integrated circuit chip manufacturing and testing, reference source tuning is a core step in ensuring chip performance consistency and stability. By precisely adjusting the configuration parameters of modules such as reference voltage and reference current within the chip, it ensures that the chip output meets design expectations, laying the foundation for subsequent modular applications and multi-chip collaborative operation. As chip functions become increasingly complex, test items have gradually differentiated into two categories: quantitative parameter testing (such as voltage and current output testing) and functional effectiveness testing (such as interface communication and logic operation testing). How to adapt reference source tuning methods to the needs of different types of test items has become an important issue in improving chip test coverage and accuracy.

[0032] To address the core requirement of reference source calibration, existing technologies typically preset specific quantization target measurement values, input different combinations of high and low level signals through the chip input interface, collect the corresponding output quantization values ​​of the chip, and select the calibration value corresponding to the value closest to the target value as the optimal solution.

[0033] However, the aforementioned existing technologies have shortcomings: their tuning logic essentially relies on quantifiable test data. For test items without quantifiable data, existing methods cannot identify the critical state of a function transitioning from failure to pass or from pass to failure, nor can they accurately capture the corresponding critical tuning values. This results in insufficient tuning accuracy of functional test items, making it difficult to explore the boundaries of chip operating conditions, which in turn affects the reliability of subsequent modular applications and fails to meet the refined tuning requirements of integrated circuit testing for functional items.

[0034] In view of this, embodiments of the present invention provide a benchmark source tuning method and system based on functional testing. The method includes: constructing a tuning vector of a chip under test, the tuning vector including a write unit and a read unit; the write unit including a chip memory address, a write instruction, and a tuning value, the read unit including the same chip memory address, a read instruction, and an expected value as the write unit; the tuning vector follows a preset communication protocol of the chip under test and performs data transmission through designated input / output pins of the chip under test; determining a target vector of the chip under test, the target vector being a functional vector whose test results change with the tuning value, exhibiting a qualified or failed state, the test results of the target vector being used to reflect the effectiveness of the chip's target function corresponding to the tuning value; and pre-setting a tuning value sequence containing multiple tuning values, initializing a tuning value sequence index to point to the sequence. The first adjustment value is used. Starting from the first adjustment value, the adjustment value corresponding to the current index is written to the write unit of the adjustment vector in sequence. After the adjustment vector is executed, it is verified whether the actual output value of the read unit is consistent with the expected value. If they are inconsistent, the test corresponding to the current adjustment value is stopped, the index is incremented to point to the next adjustment value and the iteration continues. If they are consistent, the target vector is executed and the test result corresponding to the current adjustment value is recorded. The index is incremented to point to the next adjustment value and the iteration continues until all adjustment values ​​in the adjustment value sequence are traversed. After all adjustment values ​​in the adjustment value sequence have been traversed, the valid adjustment values ​​and corresponding test results are filtered and written. The jump point where the test result changes from qualified to failed or from failed to qualified is located. The adjustment value corresponding to the jump point is determined as the critical adjustment value. The critical adjustment value is output to the data result file or written to the internal storage area of ​​the chip under test.

[0035] The method provided by this invention constructs a trimming vector containing write-read units, determines the target vector that changes with the trimming value, iteratively traverses and verifies the trimming values, locates the transition point to determine the critical value, and outputs and stores the critical value. First, it utilizes the write-read closed loop of the trimming vector to ensure that the trimming value is correctly received by the chip. Then, by iteratively traversing all trimming values ​​and synchronously recording the functional results, it solves the problem of having only binary results without quantized data. Finally, by accurately extracting the critical trimming value by locating the transition point, it fills the technical gap that traditional methods cannot obtain the critical trimming value, realizes the accurate trimming of the chip reference source, and effectively improves the stability and reliability of the chip's target function.

[0036] In some embodiments, a benchmark source tuning method based on functional testing provided by the present invention can be executed by a benchmark source tuning system 100 based on functional testing (hereinafter referred to as tuning system 100).

[0037] As an example, the tuning system 100 can be any electronic device 200 with data processing capabilities, such as a general-purpose computer, personal computer, laptop computer, switch, or tablet computer. The specific implementation of the tuning system 100 is not limited here.

[0038] Figure 1 shows a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present invention. The electronic device 200 includes a processor 210, a memory 220, and a communication interface 230.

[0039] Processor 210 may include one or more processing cores. Processor 210 connects to various parts within electronic device 200 using various interfaces and lines, and performs various functions and processes data of electronic device 200 by running or executing instructions, programs, code sets, or instruction sets stored in memory 220, and by calling data stored in memory 220. Optionally, processor 210 may be implemented using at least one of the following hardware forms: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA).

[0040] The memory 220 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 220 may include a non-transitory computer-readable storage medium. The memory 220 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 220 may include a program storage area. This program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as video acquisition, feature extraction, and process detection), and instructions for implementing the various method embodiments described above.

[0041] Communication interface 230 is used to communicate with other devices, equipment or communication networks, such as data storage devices, image processing devices or Ethernet, wireless access network (RAN), wireless local area network (WLAN), etc.

[0042] In terms of physical implementation, the aforementioned devices (such as processor 210, memory 220, and communication interface 230) can each be devices within the same device (such as a laptop computer). Alternatively, at least two of these devices can be located within the same device, i.e., as different devices within the same device, similar to the deployment of devices or components in a distributed system.

[0043] It is understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device 200. In other embodiments of the present invention, the electronic device 200 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0044] The following description, in conjunction with the accompanying drawings, illustrates a benchmark source tuning method based on functional testing provided by an embodiment of the present invention.

[0045] Figure 2 is a flowchart of a reference source tuning method based on functional testing provided by an embodiment of the present invention. Optionally, this method can be executed by the electronic device 200 shown in Figure 1. The method may include the following steps: S1, constructing a tuning vector of the chip to be tested, wherein the tuning vector includes a write unit and a read unit.

[0046] Specifically, the writing unit includes a chip memory address, a write instruction, and a trimming value; the reading unit includes the same chip memory address, a read instruction, and an expected value as the writing unit; the trimming vector follows the preset communication protocol of the chip under test and performs data transmission through the specified input / output pins of the chip under test.

[0047] In one possible implementation, the trimming value is N-bit binary data, where N is greater than or equal to 1, and the trimming value sequence contains 0 to 2. N All N-bit binary combinations corresponding to -1.

[0048] The method provided by this invention, on the one hand, adapts to the adjustment accuracy requirements of different chip reference sources through the N-bit binary design, thereby improving the adaptability of the method; on the other hand, the sequence covers all possible combinations of adjustment values, ensuring that no adjustment value is missed, avoiding the omission of transition points due to the failure to test some adjustment values, providing a complete data foundation for subsequent accurate positioning of critical adjustment values, and further improving the accuracy and comprehensiveness of critical adjustment values.

[0049] In some embodiments, the preset communication protocol of the chip under test is the I2C protocol or the SPI protocol; when the preset communication protocol of the chip under test is the I2C protocol, the specified input / output pins are the SDA pin and the SCL pin; when the preset communication protocol of the chip under test is the SPI protocol, the specified input / output pins are the MOSI pin, the MISO pin, and the SCK pin.

[0050] It should be noted that the above-mentioned preset communication protocols and input / output pins are merely illustrative examples, and the embodiments of the present invention do not impose any particular restrictions on the specific implementation of the preset communication protocols and input / output pins.

[0051] The method provided by this invention explicitly presets the communication protocol as I2C or SPI, and specifies the corresponding pins: First, I2C and SPI are the most widely used communication protocols in the chip field, which are compatible with the hardware interfaces of most chips under test, greatly improving the versatility of the method; Second, by specifying the pins corresponding to the protocol, data transmission interruption caused by incorrect pin selection is avoided, ensuring that the tuning vector can stably transmit tuning values ​​and verification data, reducing test time caused by transmission failure, and improving the stability and efficiency of the tuning process.

[0052] S2. Determine the target vector of the chip to be detected.

[0053] Specifically, the target vector is a functional vector in which the test results change to a qualified or unqualified state as the adjustment value changes. The test results of the target vector are used to reflect the effectiveness of the chip's target function corresponding to the adjustment value.

[0054] It can also be understood as: the target vector is a functional vector in which the test result presents a binary state of pass or fail as the adjustment value changes.

[0055] In some embodiments, the target function of the chip corresponding to the target vector includes a chip interface communication function or a chip logic operation function; when the target function of the chip is a chip interface communication function, the test result of the target vector determines the qualified state or the failed state by judging whether the data transmission between the chip and the external device is successful; when the target function of the chip is a chip logic operation function, the test result of the target vector determines the qualified state or the failed state by judging whether the output result of the chip logic operation is consistent with the preset theoretical result.

[0056] The method provided by this invention clearly defines the target functions, including chip interface communication functions and logic operation functions, and provides corresponding judgment criteria: the interface communication function is judged by whether the data transmission is successful, and the logic operation function is judged by whether the output result is consistent with the theoretical value. On the one hand, it covers the two most core functional test scenarios of the chip, greatly expanding the applicability of the method; on the other hand, the clear judgment criteria avoid the misunderstanding of the results by different testers, ensure the consistency of test results, and improve the universality of the method and the reliability of the test results.

[0057] S3. Preset a sequence of adjustment values ​​containing multiple adjustment values, initialize the adjustment value sequence index to point to the first adjustment value in the sequence; starting from the first adjustment value, write the adjustment value corresponding to the current index into the write unit of the adjustment vector in sequence, and after executing the adjustment vector, verify whether the actual output value of the read unit is consistent with the expected value.

[0058] In one possible implementation, the step of verifying whether the actual output value of the readout unit is consistent with the expected value after executing the adjustment vector includes: using a high level or a low level as a judgment benchmark, wherein a high level of the actual output value corresponds to a binary bit 1 of the adjustment value and a low level corresponds to a binary bit 0 of the adjustment value; if the combination of high and low levels of the actual output value completely matches the expected value, then it is determined that the actual output value is consistent with the expected value.

[0059] The method provided by this invention uses the binary 1 corresponding to a high level and the binary 0 corresponding to a low level as the judgment criterion, and requires that the high and low level combinations of the actual output value and the expected value are completely matched before a consistency is determined. This judgment standard is clear and quantifiable, avoiding the misjudgment scenario where partial matching is valid. It ensures that only the trimmed value correctly received by the chip enters the subsequent target vector test, filters out the interference of invalid trimmed values ​​on the test data, improves the accuracy of the validity verification of the trimmed value writing, and lays a reliable data foundation for the subsequent accurate positioning of the transition point.

[0060] S4. If inconsistent, stop the test corresponding to the current adjustment value, increment the index to point to the next adjustment value and continue iterating; if consistent, execute the target vector and record the test result corresponding to the current adjustment value, increment the index to point to the next adjustment value and continue iterating until all adjustment values ​​in the adjustment value sequence have been traversed; S5. After all adjustment values ​​in the adjustment value sequence have been traversed, filter and write valid adjustment values ​​and corresponding test results, locate the jump point where the test result changes from a qualified state to a failed state or from a failed state to a qualified state, and determine the adjustment value corresponding to the jump point as the critical adjustment value; For example, see Table 1, which is a correspondence table between adjustment values ​​and test results of target vectors provided by an embodiment of the present invention. It includes multiple adjustment values ​​and the test results of the target vector corresponding to each adjustment value. Among them, the test results of adjustment values ​​0100 and 0101 change from a failed state to a qualified state, so adjustment value 0100 is determined as the jump point, that is, adjustment value 0101 is the critical adjustment value.

[0061] Table 1 In one possible implementation, the location of the transition point where the test result changes from a qualified state to a failed state or from a failed state to a qualified state includes: sorting the selected valid correction values ​​in ascending order according to their corresponding binary values, and synchronously associating the test results corresponding to each correction value; comparing the test results corresponding to adjacent sorted correction values ​​one by one, and if the corresponding test results are a qualified state and a failed state respectively, then determining the transition position of the two adjacent correction values ​​as the transition point.

[0062] The method provided by this invention first sorts the valid correction values ​​written in ascending binary order, and then compares the test results of adjacent correction values ​​one by one: the ordered sorting ensures that the correction values ​​are arranged in sequence according to the parameter gradient, making the trend of functional results clearer; the comparison of adjacent results one by one avoids the omission of adjacent correction values ​​due to disordered order, ensuring that all possible jump points can be accurately located, providing accurate jump point basis for subsequent determination of critical correction values, and improving the reliability of critical value location.

[0063] Furthermore, determining the adjustment value corresponding to the jump point as the critical adjustment value includes: if there is only one jump point, determining the adjustment value that changes the test result from a failed state to a qualified state from the two adjacent adjustment values ​​corresponding to the jump point as the critical adjustment value; if there are multiple jump points, filtering all the adjustment values ​​corresponding to the jump points, and determining the adjustment value with the smallest binary value that changes the test result from a failed state to a qualified state as the critical adjustment value.

[0064] The method provided by this invention clearly defines the following rules: for single-hop change points, the adjustment value that turns failure into success is selected; for multi-hop change points, the adjustment value that turns failure into success and has the smallest binary value is selected. The single-hop change point rule ensures that the critical value that makes the function just passable is selected, avoiding insufficient or redundant parameters. The multi-hop change point rule selects the smallest adjustment value, which can reduce the parameter consumption of the chip reference source while ensuring the function passes, taking into account both functional stability and the chip's low power consumption requirements, and improving the optimality of the adjustment result.

[0065] S6. Output the critical adjustment value to the data result file or write it to the internal storage area of ​​the chip to be tested.

[0066] In one possible implementation, the internal storage area of ​​the chip under test is a non-volatile storage area, which includes electrically erasable programmable read-only memory or one-time programmable memory.

[0067] The method provided by this invention writes critical adjustment values ​​into a non-volatile memory area: EEPROM supports multiple erase and write operations, facilitating subsequent chip parameter adjustments; OTP has the characteristics of one-time write and long-term stable storage, suitable for scenarios where parameter adjustments are not required. The two storage types adapt to different application needs; at the same time, non-volatile storage ensures that critical adjustment values ​​are not lost after the chip is powered off, and the reference source can be directly read upon the next power-on without repeated adjustment, significantly reducing the operation and time costs of subsequent chip applications and improving the ease of chip use.

[0068] As can be seen from S1-S6 above, the method provided by the present invention constructs a trimming vector containing write-read units, determines the target vector that changes with the trimming value, iteratively traverses and verifies the trimming value, locates the jump point to determine the critical value, and outputs and stores the critical value. First, it uses the write-read closed loop of the trimming vector to ensure that the trimming value is correctly received by the chip. Then, by iteratively traversing all trimming values ​​and synchronously recording the functional results, it solves the problem of only binary results without quantized data. Finally, by accurately extracting the critical trimming value by locating the jump point, it fills the technical gap that traditional methods cannot obtain the critical trimming value, realizes the accurate trimming of the chip reference source, and effectively improves the stability and reliability of the chip's target function.

[0069] In summary, the beneficial effects of the method provided by the embodiments of the present invention are as follows: First, the method provided by the present invention can ensure the validity of the adjustment value writing: through the write-read bidirectional verification mechanism, it ensures that the adjustment value is correctly recognized by the chip, avoids functional test misjudgment caused by incorrect adjustment value writing, solves the problem of unreliable adjustment value transmission in existing methods, and improves the reliability of the adjustment process. Second, the method provided by the present invention can realize critical adjustment of functional tests: breaking through the dependence of existing methods on quantitative measurement values, it accurately captures the result jump critical point of functional test items and obtains critical adjustment values, filling the technical gap that functional test items cannot be adjusted, and providing core data support for exploring the chip's operating condition boundaries (such as minimum power consumption, maximum stability). Finally, the method provided by the present invention can effectively improve the feasibility of adjustment results: by separating the execution flow of the adjustment vector and the target vector, the one-to-one correspondence between the adjustment value and the functional result is clarified, avoiding confusion between the results of the two vector functions. At the same time, the adjustment result can be directly written to the chip storage area or reused in subsequent test items, improving the practicality and scalability of the adjustment result.

[0070] To facilitate understanding of this solution, the following specific example will be used to further explain and illustrate the method provided in the embodiments of the present invention.

[0071] In one example, referring to Figure 3, the method provided by this embodiment of the invention includes the following steps: Step 1: Construct a trimming vector, clarify the write unit (memory address, write instruction, trimming value data width N) and the read unit (memory address, read instruction, expected read data), and determine the communication protocol (I2C / SPI) and the corresponding chip input / output pins; Step 2: Determine the target vector, which must satisfy the characteristic that "the test result changes with the trimming value, showing a Pass / Fail switching", and clarify the judgment criteria for vector execution (e.g., successful reception of data in I2C communication is Pass, and failure to receive data within the timeout period is Fail); Step 3: Initialize the trimming value sequence index i=0, and the trimming value... For i, the corresponding N-bit binary data (e.g., when N=4, i=0 corresponds to 0000, i=1 corresponds to 0001, ..., i=15 corresponds to 1111); Step 4: Write the current adjustment value into the write unit of the adjustment vector, execute the adjustment vector, and check whether the output result of the read unit is consistent with the expected H / L of the written data: If inconsistent (Fail): record the current adjustment value write failure, i=i+1, jump to step 6; If consistent (Pass): proceed to step 5; Step 5: Execute the target vector, and record the target vector test result (Pass / Fail) corresponding to the current adjustment value according to the preset judgment standard, i=i+1; Step 6: Determine whether i is greater than or equal to 2 N(Whether all trimmed value sequences are covered): If no: jump to step 4; if yes: proceed to step 7; Step 7: traverse the test results of the target vector corresponding to all valid trimmed values ​​(successfully written trimmed values), locate the result transition point (the result corresponding to adjacent trimmed values ​​changes from Pass to Fail or from Fail to Pass); if there are multiple transition points, select the smallest trimmed value that changes from Fail to Pass as the final trimmed value (or select the largest trimmed value that changes from Pass to Fail according to actual needs); Step 8: output the final trimmed value to the data result file or write it to the non-volatile memory area inside the chip to complete the trimming process.

[0072] To further illustrate the technical solution of the present invention, taking "reference source adjustment for chip I2C interface communication function" as an example, a specific embodiment is provided as follows: In another example, the chip to be tested is a microcontroller chip with an I2C interface. The communication stability of its I2C interface depends on the parameter configuration (adjustment value) of the internal reference voltage module. The communication function test only outputs Pass (communication successful) / Fail (communication failed) results. The critical adjustment value needs to be obtained through the method of the present invention.

[0073] Further, the implementation parameters are as follows: Adjustment vector parameters: Storage address: Reference voltage module configuration register address 0x01 (8-bit address); Communication protocol: I2C protocol, corresponding chip pins are SDA (P0_0) and SCL (P0_1); Adjustment value bit width N=4 (i.e., 0000~1111, a total of 16 adjustment values); Write unit: Instruction 0x02 (write instruction) + adjustment value (4 bits, such as 0000); Read unit: Instruction 0x03 (read instruction) + expected read data (consistent with the write adjustment value, such as writing 0000 and expecting to read 0000, corresponding H / L is LLLL).

[0074] Target vector parameters: Function type: Single-byte data write + read function between chip I2C interface and external EEPROM (address 0xA0); Judgment criteria: Pass if the external EEPROM successfully receives the data written by the chip and the chip successfully reads the data (consistent with the written data); Fail if there is no response after timeout or the read data is incorrect.

[0075] Furthermore, the specific implementation process, based on the above example, is as follows: Constructing the tuning vector: Define the write unit (0x02 + tuning value) and read unit (0x03 + expected data) according to the above parameters, and bind the I2C pins SDA and SCL; Determining the target vector: Write the I2C communication vector, including the complete process of start signal, EEPROM address, write data, stop signal, start signal, EEPROM address, read data, and stop signal; Iterative testing: i=0, tuning value 0000: Execute the tuning vector, read data 0000 (Pass), execute the target vector, communication timeout (Fail), record (0000, Fail); i=1, tuning value 0001: Read data 0001 (Pass), target... Vector communication timeout (Fail), record (0001, Fail); i=5, adjustment value 0101: read data 0101 (Pass), target vector communication successful (Pass), record (0101, Pass); i=6~15, adjustment values ​​0110~1111: read data all Pass, target vector all Pass; critical value extraction: the jump point is i=4 (adjustment value 0100, Fail) → i=5 (adjustment value 0101, Pass), select the minimum adjustment value 0101 that "changes from Fail to Pass" as the final adjustment value; result output: write the adjustment value 0101 to the chip OTP storage area and output it to the test data file test_result.csv.

[0076] Through this embodiment, the critical adjustment value 0101 of the chip's I2C communication function was successfully obtained. The reference voltage parameter corresponding to this value is the minimum configuration for the stable operation of the chip's I2C interface. This provides an accurate basis for the optimization of the reference source parameters in the subsequent low-power scenario of the chip. Moreover, there were no misjudgments caused by errors in writing adjustment values ​​throughout the process, and the accuracy of the adjustment result reached 100%.

[0077] The foregoing mainly describes the solutions of the embodiments of the present invention from a methodological perspective. It is understood that, in order to achieve the above-mentioned functions, the tuning system 100 includes at least one of the hardware structures and software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of the present invention can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present invention.

[0078] In this embodiment of the invention, the tuning system 100 can be divided into functional units according to the above method example. For example, the tuning system 100 can be divided into functional units corresponding to various functions, or two or more functions can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software functional unit. It should be noted that the unit division in this embodiment of the invention is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0079] For example, Figure 4 shows a schematic diagram of the hardware structure of a trimming system provided in an embodiment of the present invention. The trimming system 100 includes: a trimming vector construction module 110, used to: construct a trimming vector of a chip under test, the trimming vector including a writing unit and a reading unit; the writing unit includes a chip storage area address, a writing instruction and a trimming value, the reading unit includes the same chip storage area address, a reading instruction and an expected value as the writing unit; the trimming vector follows a preset communication protocol of the chip under test and performs data transmission through a specified input / output pin of the chip under test; a target vector determination module 120, used to: determine the target vector of the chip under test, the target vector being a functional vector in which the test result presents a qualified state or a failed state as the trimming value changes, the test result of the target vector being used to reflect the effectiveness of the chip target function corresponding to the trimming value; and a test result verification module 130, used to: preset a trimming value sequence containing multiple trimming values, initialize the trimming value sequence index to point to the first trimming value of the sequence. Starting from the first adjustment value, the adjustment value corresponding to the current index is sequentially written into the write unit of the adjustment vector. After executing the adjustment vector, it is verified whether the actual output value of the read unit is consistent with the expected value. If they are inconsistent, the test corresponding to the current adjustment value is stopped, the index is incremented to point to the next adjustment value and the iteration continues. If they are consistent, the target vector is executed and the test result corresponding to the current adjustment value is recorded. The index is incremented to point to the next adjustment value and the iteration continues until all adjustment values ​​in the adjustment value sequence are traversed. The adjustment value determination module 140 is used to: after all adjustment values ​​in the adjustment value sequence have been traversed, filter and write valid adjustment values ​​and corresponding test results, locate the jump point where the test result changes from qualified to failed or from failed to qualified, and determine the adjustment value corresponding to the jump point as the critical adjustment value. The result generation module 150 is used to: output the critical adjustment value to the data result file or write it to the internal storage area of ​​the chip to be tested.

[0080] It should be understood that specific descriptions of the above-mentioned optional methods can be found in the foregoing method embodiments, and will not be repeated here. Furthermore, explanations of any of the above-provided tuning systems 100 and descriptions of their beneficial effects can be found in the corresponding method embodiments, and will not be repeated here.

[0081] This invention also provides a computer-readable storage medium storing at least one computer instruction, which is loaded and executed by a processor to implement the methods of the various embodiments described above. Explanations of the relevant content and descriptions of the beneficial effects of any of the computer-readable storage media provided above can be found in the corresponding embodiments described above, and will not be repeated here.

[0082] This invention also provides a chip. This chip integrates a control circuit for implementing the functions of the aforementioned adjustment system 100 and one or more ports. Optionally, the functions supported by this chip are as described above and will not be repeated here.

[0083] Those skilled in the art will understand that the program for implementing all or part of the steps of the above embodiments, which can be executed by a program instructing related hardware, can be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a random access memory, etc. The processing unit or processor mentioned above can be a central processing unit, a general-purpose processor, an application-specific integrated circuit (ASIC), a microprocessor (DSP), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0084] This invention also provides a computer program product containing instructions that, when executed on a computer, cause the computer to perform any of the methods described in the above embodiments. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this invention is generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., SSD), etc.

[0085] It should be noted that the devices for storing computer instructions or computer programs provided in the embodiments of the present invention, such as, but not limited to, the aforementioned memory, computer-readable storage medium, and communication chip, are all non-transitory. Those skilled in the art should recognize that the functions described in the embodiments of the present invention in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable storage medium or transmitted as one or more instructions or code on a computer-readable storage medium. Computer-readable storage media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of computer programs from one place to another. Storage media can be any available medium accessible to general-purpose or special-purpose computers.

[0086] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A benchmark source tuning method based on functional testing, characterized in that, The method includes: constructing a trimming vector for the chip under test, the trimming vector comprising a write unit and a read unit; the write unit comprising a chip memory address, a write instruction, and a trimming value, the read unit comprising the same chip memory address, a read instruction, and an expected value as the write unit; the trimming vector following a preset communication protocol of the chip under test and performing data transmission through designated input / output pins of the chip under test; determining a target vector for the chip under test, the target vector being a functional vector whose test results exhibit a qualified or failed state as the trimming value changes, the test results of the target vector being used to reflect the effectiveness of the chip's target function corresponding to the trimming value; pre-setting a trimming value sequence containing multiple trimming values, initializing the trimming value sequence index to point to the first trimming value in the sequence; starting from the first trimming value, ... Next, the adjustment value corresponding to the current index is written to the write unit of the adjustment vector. After executing the adjustment vector, it is verified whether the actual output value of the read unit is consistent with the expected value. If they are inconsistent, the test corresponding to the current adjustment value is stopped, the index is incremented to point to the next adjustment value, and the iteration continues. If they are consistent, the target vector is executed and the test result corresponding to the current adjustment value is recorded. The index is incremented to point to the next adjustment value, and the iteration continues until all adjustment values ​​in the adjustment value sequence are traversed. After all adjustment values ​​in the adjustment value sequence have been traversed, valid adjustment values ​​and corresponding test results are filtered and written. The jump point where the test result changes from qualified to failed or from failed to qualified is located, and the adjustment value corresponding to the jump point is determined as the critical adjustment value. The critical adjustment value is output to the data result file or written to the internal storage area of ​​the chip under test.

2. The method according to claim 1, characterized in that, The adjustment value is N-bit binary data, where N is greater than or equal to 1, and the adjustment value sequence contains 0 to 2. N All N-bit binary combinations corresponding to -1.

3. The method according to claim 1, characterized in that, The preset communication protocol of the chip under test is either I2C or SPI. When the preset communication protocol of the chip under test is I2C, the specified input / output pins are SDA and SCL. When the preset communication protocol of the chip under test is SPI, the specified input / output pins are MOSI, MISO, and SCK.

4. The method according to claim 1, characterized in that, The step of verifying whether the actual output value of the readout unit is consistent with the expected value after executing the adjustment vector includes: using a high level or a low level as the judgment benchmark, wherein a high level of the actual output value corresponds to a binary bit 1 of the adjustment value and a low level corresponds to a binary bit 0 of the adjustment value; if the combination of high and low levels of the actual output value completely matches the expected value, then it is determined that the actual output value is consistent with the expected value.

5. The method according to claim 1, characterized in that, The internal storage area of ​​the chip under test is a non-volatile storage area, which includes electrically erasable programmable read-only memory or one-time programmable memory.

6. The method according to claim 1, characterized in that, The transition point from a qualified state to a failed state or vice versa in the positioning test results includes: sorting the selected valid correction values ​​in ascending order of their corresponding binary values, and synchronously associating the test results corresponding to each correction value; comparing the test results corresponding to adjacent sorted correction values ​​one by one, and if the corresponding test results are qualified and failed respectively, then determining the transition position of the two adjacent correction values ​​as the transition point.

7. The method according to claim 1, characterized in that, Determining the adjustment value corresponding to the jump point as the critical adjustment value includes: if there is only one jump point, determining the adjustment value that changes the test result from a failed state to a qualified state from the two adjacent adjustment values ​​corresponding to the jump point as the critical adjustment value; if there are multiple jump points, filtering all the adjustment values ​​corresponding to the jump points, and determining the adjustment value with the smallest binary value that changes the test result from a failed state to a qualified state as the critical adjustment value.

8. The method according to claim 1, characterized in that, The target function of the chip corresponding to the target vector includes chip interface communication function or chip logic operation function; when the target function of the chip is chip interface communication function, the test result of the target vector determines the qualified state or the failed state by judging whether the data transmission between the chip and the external device is successful. When the target function of the chip is the chip logic operation function, the test result of the target vector is used to determine whether the chip logic operation output result is consistent with the preset theoretical result to determine the qualified state or the failed state.

9. A reference source tuning system based on functional testing, characterized in that, The system includes: a trimming vector construction module, used to: construct a trimming vector of the chip under test, the trimming vector including a write unit and a read unit; the write unit includes a chip memory address, a write instruction and a trimming value, the read unit includes the same chip memory address, a read instruction and an expected value as the write unit; the trimming vector follows a preset communication protocol of the chip under test and performs data transmission through designated input / output pins of the chip under test; a target vector determination module, used to: determine the target vector of the chip under test, the target vector being a functional vector whose test result changes with the trimming value to present a qualified or failed state, the test result of the target vector being used to reflect the effectiveness of the chip's target function corresponding to the trimming value; a test result verification module, used to: preset a trimming value sequence containing multiple trimming values, initialize the trimming value sequence index to point to the first trimming value in the sequence; and verify the test result from the first... Starting with each adjustment value, the adjustment value corresponding to the current index is sequentially written into the write unit of the adjustment vector. After executing the adjustment vector, the actual output value of the read unit is verified to be consistent with the expected value. If they are inconsistent, the test corresponding to the current adjustment value is stopped, the index is incremented to point to the next adjustment value, and the iteration continues. If they are consistent, the target vector is executed and the test result corresponding to the current adjustment value is recorded. The index is incremented to point to the next adjustment value, and the iteration continues until all adjustment values ​​in the adjustment value sequence are traversed. The adjustment value determination module is used to: after all adjustment values ​​in the adjustment value sequence have been traversed, filter and write valid adjustment values ​​and corresponding test results, locate the jump point where the test result changes from qualified to failed or from failed to qualified, and determine the adjustment value corresponding to the jump point as the critical adjustment value. The result generation module is used to: output the critical adjustment value to the data result file or write it to the internal storage area of ​​the chip under test.

10. An electronic device, characterized in that, include: processor; A memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the benchmark source tuning method based on functional testing as described in any one of claims 1-8.

Images