Data corruption tracking for memory reliability

Abstract

The invention relates to data corruption tracking for memory reliability. Techniques related to improving memory reliability, for example, in the context of memory circuits with limited reliability features, are disclosed. In some embodiments, memory controller circuitry is configured to communicate via an interface with memory circuitry that supports link error detection. The memory controller circuitry may transmit a combination of data and parity for the first data block based on the corruption indicator, the combination of data and parity causing the memory circuitry to detect an uncorrectable write interface error. Subsequent reading of the location may thus cause an uncorrectable error indication. In some embodiments, this may advantageously allow the memory controller circuitry to propagate a corruption indicator in the memory circuitry as an uncorrectable error without the need to additionally track the indicator by the memory circuitry or memory controller.

Description

[0001] Case Separation Statement This application is a divisional application of Chinese Patent Application No. 202380020119.2, filed on January 12, 2023, entitled "Data Corruption Tracking for Memory Reliability". Technical Field

[0002] This disclosure relates generally to the reliability of computer memory, and more specifically to tracking corrupted data and logging data errors. Background Technology

[0003] The reliability of data stored in memory is critical across various computing contexts. In a data server context, various memory reliability characteristics can be implemented, for example, using redundant storage devices / interfaces, numerous ECC fields, etc. These techniques may be inappropriate in non-server contexts due to power consumption and circuit area considerations. However, in those contexts, improving memory reliability may still be desirable. Data can travel through various circuits (e.g., in on-chip systems), and tracking the state of corrupted data as it moves through the system can be challenging. Furthermore, it can be difficult to effectively track and log memory errors and their sources. Summary of the Invention

[0004] According to some embodiments of this disclosure, apparatus and methods for tracking corrupted data and recording data errors are provided. Attached Figure Description

[0005] Figure 1 This is a generalized block diagram illustrating an exemplary memory system according to some implementation schemes.

[0006] Figure 2 This is a block diagram illustrating an example memory controller circuit system configured to enforce uncorrectable errors when writing to memory circuitry, according to some implementation schemes.

[0007] Figure 3 This is a block diagram illustrating example memory circuit elements configured to detect and correct correctable errors according to some implementation schemes.

[0008] Figure 4 This is a block diagram illustrating an example circuit of a system that can propagate a damage indicator according to some implementation schemes.

[0009] Figure 5 This is a block diagram illustrating a memory controller circuit including an erasure-on-demand circuitry system according to some implementation schemes.

[0010] Figure 6This is a block diagram illustrating an example memory cache controller configured to track uncorrectable and correctable errors according to some implementation schemes.

[0011] Figure 7 This is a generalized diagram illustrating an example of an uncorrectable error logger data structure based on some implementation schemes.

[0012] Figure 8A This is a generalized diagram illustrating how error-correcting data structures can be corrected based on some implementation examples.

[0013] Figure 8B This is a block diagram illustrating an example memory cache controller configured to output a first signal and a second signal according to some implementation schemes.

[0014] Figure 9 This is a flowchart illustrating an example method for generating a signal based on a tracked correctable error, according to some implementation schemes.

[0015] Figure 10 This is a flowchart illustrating an example method for releasing correctable error tracker entries according to some implementation schemes.

[0016] Figure 11 This is a flowchart illustrating another example method based on some implementation schemes.

[0017] Figure 12 This is a flowchart illustrating another example method based on some implementation schemes.

[0018] Figure 13 This is a block diagram illustrating an example computing device based on some implementation schemes.

[0019] Figure 14 These are illustrations illustrating example applications of systems and devices disclosed according to some implementation schemes.

[0020] Figure 15 This is a block diagram of an example computer-readable medium illustrating storage circuit design information according to some implementation schemes. Detailed Implementation

[0021] In the disclosed embodiments discussed in detail below, the computing device is configured to track the corruption status of data traveling through various circuits (this status may be referred to herein as a corruption indicator or "poisoned" indicator, which may indicate an uncorrectable detected error) and log memory errors encountered.

[0022] In some implementations, the memory controller enforces an uncorrectable error when writing poisoned data to the memory circuitry (e.g., DRAM) to maintain the poisoned state when reading the same location from the memory circuitry later. This allows for tracking of poisoned data stored in memory and then retrieved without requiring dedicated memory cell fields or separate memory controller tracking structures. Generally, the disclosed techniques can improve memory reliability with limited or negligible increases in area and power consumption.

[0023] In some implementations, the memory is LPDDR5 memory, configured to detect both link errors and on-chip errors. The memory controller can enforce a write link error correction code (ECC) error to maintain the poisoned state in this context.

[0024] In some implementations, the memory circuitry is configured to correct correctable on-chip errors and, for example, indicate to the memory controller via a Decoded Status Flag (DSF) interface that correctable errors have been corrected. It is important to note that a correctable error is a detected error for which error correction information (e.g., using an ECC mechanism) provides sufficient information to correct the error (as opposed to an uncorrectable error, which has been detected but for which there is insufficient information to correct). However, the memory circuitry can correct data in transit and leave incorrect data in the memory cell. Therefore, in some implementations, the erase-on-demand circuitry system is configured to initiate an operation that causes an internal read / correct / write operation in the memory circuitry system to correct the stored data. This reduces the likelihood of further errors that could render the data uncorrectable (e.g., a second bit flip in the memory that supports correction of a single bit flip rather than multiple bit flips).

[0025] In some implementations, the device is configured to track and log both uncorrectable and correctable errors (e.g., via a separate table structure) and can take various actions based on various error thresholds. In some implementations, the device includes a memory cache and a memory cache controller, with the memory cache controller configured to track errors. In some implementations, correctable and uncorrectable errors are also tracked at the error source (e.g., within certain processor clusters and their caches). The memory cache controller can aggregate error information and trigger various signals in response to certain thresholds. Various disclosed techniques can allow the identification of potential problems (e.g., threshold counts associated with a specific physical address can indicate faulty DRAM cells).

[0026] In various implementations, the disclosed techniques can advantageously improve the memory reliability of devices in which server-level memory reliability techniques would be impractical.

[0027] Overview of memory systems Figure 1 This is a block diagram illustrating an exemplary memory system according to some embodiments. In the illustrated embodiment, system 100 includes memory controller circuitry 101 and a plurality of memory circuits 104-106 (note that any of the memory circuits can be implemented in various numbers in other embodiments, and each memory circuit can include various different numbers of memory banks). In the illustrated embodiment, memory controller circuitry 101 is configured to communicate with memory circuitry 104 via bus 108.

[0028] In the illustrated embodiments, memory control circuitry 101 receives access requests 109 via multiple virtual channels 110. In some embodiments, the virtual channels carry different types of requests and have different quality of service requirements. Requests from certain agents may be sent via a specific virtual channel, or agents may be configured to send requests via multiple different virtual channels. In some embodiments discussed in further detail below, virtual channels include real-time channels, low-latency channels, and high-capacity (or best-effort) channels.

[0029] In the illustrated embodiments, the memory controller circuitry 101 includes a queuing circuitry 102, an arbitration circuitry 103, and a priority tracking structure 111. In some embodiments, the queuing circuitry 102 is configured to queue received requests. In some embodiments, the arbitration circuitry 103 is configured to select which requests are allowed to access certain memory banks 107. In some embodiments, the arbitration circuitry 103 is configured to use information from the priority tracking structure 111 to determine which requests should be granted access.

[0030] In some implementations, arbitration circuit 103 is configured to implement a category-based arbitration scheme. In some implementations, each virtual channel is assigned a category value (e.g., C0 to C3 in some implementations, but any category of various numbers of categories can be implemented in other implementations). Arbitration circuit 103 can assign a category to each virtual channel for each memory bank. In some implementations, each virtual channel starts at C3 for each memory bank, and arbitration circuit 103 is configured to prioritize channel C3 over other channels. A least recently used (LRU) scheme can be used to select from virtual channels of the same category for each memory bank. In some implementations, a low category, such as C1 or C0, is always provided to certain low-priority virtual channels.

[0031] When a virtual channel wins arbitration and is granted access to a specific memory bank, in some embodiments, the memory controller 101 decrements the category of the virtual channel for that memory bank (e.g., from C3 to C2 or from C2 to C1). In some embodiments, when a virtual channel has already been decremented to a level below a certain level for each memory bank to which it has a request (e.g., to C2 or below), the memory controller 101 is configured to increment all categories of the virtual channel by one level (e.g., from C2 to C3). It should be noted that when “each” memory bank in a set of multiple memory banks is discussed herein, the disclosed techniques may be applied to that set of memory banks, but not necessarily to all memory banks in a device or system. For example, other memory banks in the same device may be controlled by other memory controllers or devices.

[0032] In some implementations, the memory controller 101 also implements a credit system to allow a certain number of requests per virtual channel for a given read or write round, for example, based on the requested or allocated bandwidth of different virtual channels. This credit system can influence which virtual channels are actually sending requests to the arbitration circuit 103 during a given round.

[0033] In various implementations, category-based arbitration schemes can provide fair access to a given memory bank from multiple virtual channels, while rounding off among memory banks to avoid the latency associated with fast, sequential access to the same memory bank.

[0034] In the illustrated embodiment, memory circuits 104-106 each include a plurality of memory banks 107a-107n. Memory circuits 104-106 can be implemented using any of a variety of suitable memory technologies. Memory circuits 104-106 may require periodic refreshing, for example, in the case of implementation as dynamic random access memory (DRAM). Furthermore, it may be effective to extend access requests to different memory banks, for example, because there may be latency between successive accesses to different pages of the same memory bank. Therefore, in general, arbitration circuit 103 attempts to grant access to one memory bank in the set of memory banks that has not yet been accessed within a threshold time interval.

[0035] Example of an overdrive used to spread poisoning indicators Figure 2This is a block diagram illustrating a memory controller circuitry system configured to enforce uncorrectable errors during writes to memory circuitry, according to some embodiments. In the illustrated embodiment, the computing system includes memory controller circuitry 101 and memory circuitry 104. Note that these circuits can be manufactured separately and connected during the assembly of the computing device. Memory controller circuitry 101 includes control circuitry system 230. Memory circuitry 103 includes write link ECC check circuitry system 220, circuitry system 250 configured to write data / parity combinations for write link uncorrectable errors (UE), CE correction circuitry system 245, error correction code (ECC) calculation circuitry system 255, and units 260A-260N.

[0036] In the illustrated embodiment, the write link ECC check 220 includes circuitry configured to check the parity of write data transmitted from memory controller 101. For example, circuitry 220 may generate a parity value based on received data and check if it matches the received parity value. As shown, circuitry 220 may indicate whether data transmitted via the link exhibits an uncorrectable error (UE), a correctable error (CE), or no error (NE). For correctable write link errors, CE correction circuitry 245 can correct the error. Circuitry 255 is configured to generate ECC information for data without errors or with corrected CE and stores the data and parity information in memory cell 260. Elements 245 and 255 are shown using dashed lines and may be omitted in some embodiments. As shown, memory circuitry 104 is configured to store data and parity information in a given memory cell 260 (note that depending on the memory technology of memory circuitry 104, sideband or inline techniques may be used to store data and parity information).

[0037] In the illustrated implementation, circuitry 250 is configured to handle uncorrectable errors on the write link. Specifically, circuitry 250 is configured to write a data parity check combination to unit 260, which will trigger a UE (e.g., via reference below) when the unit is later read. Figure 3 (On-chip ECC check discussed). Data and parity values ​​may or may not match the actual data and parity received from the memory controller circuitry via a link. The written data and parity values ​​may be vendor-specific, allowing the original uncorrectable data to be omitted.

[0038] In some implementations, control circuitry 230 is configured to override write link ECC to enforce uncorrectable errors for poisoned data. For example, control circuitry 230 can intentionally cause write link ECC verification circuitry 220 to detect the UE via a combination of link write data and parity checks. This can propagate a poisoning indicator for the data, ensuring that the indicator persists when a read of that location triggers a UE. It should be noted that the poisoned data may have already been corrupted in another circuit (e.g., a link between a cache, processor, and another component), and tracing the corrupted data can prevent its misuse. In this scenario, memory controller circuitry 101 may disregard the actual value of the corrupted data.

[0039] In other implementations, control circuitry 230 may use other techniques to override link ECC. For example, instead of providing a data / parity combination that represents the UE, control circuitry 230 may assert a signal indicating override, and memory circuitry 104 may write the data / parity combination to unit 260 in response to detecting an override signal.

[0040] Figure 3 This is a block diagram illustrating an example read link and on-chip error detection circuitry system according to some embodiments. In the illustrated embodiment, memory controller 101 includes read link ECC check circuitry system 315, and memory circuitry 104 includes CE correction circuitry system 345 and ECC check circuitry system 355.

[0041] In some implementations, the read link ECC verification circuitry 325 is configured to generate and verify parity information similarly to the write link ECC verification circuitry 220. In some implementations, on-chip or read link errors can be detected and reported by the read link ECC verification circuitry 325, as discussed in detail below.

[0042] In the illustrated embodiment, the ECC verification circuitry 355 is configured to read data and parity information for a memory cell, generate a parity value based on the data, and verify that the parity values ​​match. In the illustrated embodiment, the CE correction circuitry 345 is configured to correct CEs detected by the circuitry 355. The UE can be reported via a Decoding Status Flag (DSF), which can be transmitted via the same interface as the link parity information. In some embodiments, the Decoding Status Flag allows the memory circuitry 104 to indicate whether it has detected an error in a memory cell. Therefore, the memory circuitry 104 can indicate via the DSF for a given location whether a CE has been corrected, the UE has been corrected, or there is no error. It should be noted that various components of the device (e.g., SoC components) can similarly detect and correct CEs.

[0043] For a UE reading data, memory controller circuitry 101 can mark the data as poisoned. Similarly, the UE can be detected at various circuits within the device, leading to a poisoning indication for that data in the circuitry supporting such indication. For a CE, memory controller circuitry 101 can trigger an on-demand erase operation, as described below. Figure 5 It was discussed in detail.

[0044] It should be noted that the various error detection and correction techniques discussed herein are for illustrative purposes and are not intended to limit the scope of this disclosure. In other embodiments, any of a variety of suitable ECC or parity schemes can be implemented. Generally, in the context of an ECC scheme supporting the correction of CEs with up to N incorrect bits, errors on more than N bits can correspond to a UE. Similarly, although separate parity and data lines are shown, in other embodiments any of a variety of suitable link interfaces can be implemented, and these fields can share the interface.

[0045] It should be noted that in some cases, memory circuitry 104 can be the original source of an uncorrectable error causing a poisoning indicator in memory controller 101. This can raise the question of whether the poisoning indicator will propagate when data is rewritten to a known faulty cell. If this is a soft or transient memory error, the poisoned uncorrectable error can propagate when data is rewritten to the cell. If this is a hard or persistent memory circuitry error, there are two possibilities. First, the rewriting of the cell can still store the data / parity combination corresponding to the uncorrectable error, and the propagation of the poisoning indicator is safe. Second, the cell can eventually store the data / parity combination corresponding to a correctable error, which cannot propagate the poisoning indicator when the cell is read. In this scenario, since the error in memory circuitry 104 initially caused the poisoning indicator, the entire error problem can be handled by the software that memory controller circuitry 101 may have notified when generating the original poisoning indicator. Furthermore, a hard memory fault can also be detected during a zeroing operation in which all zeros are written to the memory location. Any detection technique could allow the operating system to take pages offline, for example, to avoid further errors due to hard or persistent memory faults. If the operating system is quite pessimistic in responding to uncorrectable errors by taking pages offline, it is highly unlikely that a memory-initiated uncorrectable error would cause a failure of the poison indicator.

[0046] Example propagation of poisoning indicators It should be noted that overdrive link ECC is an example of poison indicator propagation, but poison indicators can propagate through various circuit elements and operations, as discussed in detail below.

[0047] Figure 4 This is a block diagram illustrating an example circuit system configured to spread a poisoning indication, such as in a SoC. In the illustrated example, the system includes a memory controller 101, a memory circuit 104, a memory cache controller 410, a structure 420, and an agent 440.

[0048] Various agent, memory cache controller 410, and memory controller circuitry 101 communicate via structure 420. In some embodiments, the structure may include fields (e.g., bits) for poisoning indicators for data transmitted via the structure. This allows circuitry to propagate poisoning indicators via the structure. In other embodiments, structure 420 may not include dedicated fields for poisoning indicators, but various circuitry may encode poisoning indicators in the data transmitted via the structure for decoding by receiving circuitry.

[0049] The memory cache controller 410 can control a memory cache, which can be the cache furthest from one or more processors in the cache / memory hierarchy (e.g., one or more lower-level L1, L2, L3 caches, etc., may exist). The memory cache (not shown) can be configured to write evicted data to memory circuitry 104 and read data from memory circuitry 104 for cache misses. The memory cache controller 410 can be configured to detect corrupted data in the memory cache and mark that data as poisoned. The memory cache controller 410 can also be configured to maintain a poisoning indicator for data that was corrupted elsewhere before being stored in the memory cache.

[0050] The memory controller 101 can also generate poisoning indicators for data based on the matching of the data's address with a channel address mask. This allows for the intentional insertion of various types of errors, for example, for debugging purposes, and errors (including CE and UE) can be injected when receiving data from or writing data to the memory. The mask can allow triggering across a range of addresses. This can be important for testing purposes, given that CE is relatively uncommon and UE is even less common. Therefore, injecting errors can facilitate testing of various memory reliability characteristics.

[0051] The memory controller 101 may also include a write queue field to track poisoning indicators. The memory controller 101 may perform various operations on queued accesses to improve efficiency. For example, the memory controller 101 may forward write data from the write queue to a read queue entry at the same location to avoid accessing the memory circuitry 104 for a read. As another example, the memory controller 101 may merge accesses to improve efficiency, avoid hazards (e.g., WAW, WARAW, etc.), or both. In some embodiments, the memory controller circuitry 101 is configured to properly maintain the poisoning indicator through such operations.

[0052] Agent 440 can be various circuits, such as processors, graphics processors, I / O controllers, etc. Agent 440 can similarly initiate or maintain poisoning indicators for the data processed by them.

[0053] Consider the following example paths that data can take through the system. A data block can be marked as poisoned by the memory cache controller 410 based on an error in the memory cache. A poisoning indicator can be transmitted to the memory controller 101 via structure 420 in conjunction with data written to memory. The memory controller 101 can combine this poisoning indicator with any poisoning indicators generated due to channel address masking (e.g., by indicating poisoning if any poisoning indicator is set). The memory controller 101 can propagate the poisoning indicator along with the written data to the write queue circuitry. Similarly, the memory controller 101 can propagate the poisoning indicator for any write-to-read forwarding from a write queue entry to a read queue. Similarly, the memory controller 101 can propagate any poisoning indicator for the merged data to the merged operation for any access merging operation. Write link overshoot can cause data corresponding to an uncorrectable error to be stored in a memory cell. When read later, the memory controller circuitry 101 can mark the data as poisoned in response to detecting a DSF value for an uncorrectable error, and the poisoning indicator can propagate to various circuitry within the system.

[0054] Compared to memory controller circuitry that maintains dedicated information about which memory cells are poisoned or dedicated fields in memory cells for tracking this information, the disclosed technique can advantageously reduce the area and power consumption in the memory cache controller while accurately propagating poisoning indicators.

[0055] Overview and limitations of LPDDR5 memory It should be noted that the various techniques discussed herein are particularly relevant in the context of LPDDR5 memory circuitry, but similar techniques can be used in a variety of memory technologies. Generally speaking, LPDDR5 memory can provide good performance for a variety of applications (e.g., mobile devices) with relatively low power consumption. This memory technology and these applications can be combined with various memory reliability characteristics implemented in other contexts (such as server applications incorporating significant redundancy and ECC functionality). The following discussion illustrates certain LPDDR5 features that may be relevant to this disclosure.

[0056] The fifth-generation Low Power Double Data Rate (LPDDR) SDRAM technology was initially released in the first half of 2019. It succeeds its predecessor, LPDDR4 / 4X, and offers speeds up to 6400 Mbps (1.5x faster). Furthermore, through several power-saving advancements, LPDDR5 can provide up to 20% power reduction compared to previous generations. LPDDR5 offers features such as link ECC schemes, scalable clock architecture, multiple frequency setpoints (FSPs), decision feedback equalization (DFE) to mitigate inter-symbol interference (ISI), write-X functionality, flexible memory bank architecture, and inline on-chip ECC. LPDDR5 systems typically do not offer server-grade reliability features such as Single Device Data Correction (SDDC), memory mirroring and redundancy, on-demand erase, patrol erase, data poisoning, redundant links, clock and power monitoring / redundancy / failover, CE isolation, inline redundancy with automatic failover, Dual Device Data Correction (DDDC), etc.

[0057] Example of an on-demand erase circuit system In some implementations, memory circuitry 104 is configured to detect correctable errors in memory cell data and correct these errors before providing the read data to memory controller 101. However, erroneous data can remain uncorrected in the memory cell. The likelihood of uncorrectable errors for such data may increase. For example, if the system is configured to correct single-bit errors but not multi-bit errors (or more generally, not errors exceeding a threshold number of single-bit errors), data that has already exhibited correctable errors may be more likely to be further corrupted and exhibit uncorrectable errors.

[0058] Therefore, in some embodiments, the memory controller circuit 101 is configured to perform on-demand erasure so that the memory circuit 104 corrects the data stored in the memory cells. The memory circuit 104 may support one or more types of write operations to efficiently perform the correction.

[0059] Figure 5 This is a block diagram illustrating an example on-demand erase circuitry system according to some embodiments. In the illustrated embodiment, the memory controller 101 includes an on-demand erase circuitry system 510, which in turn includes a snooping circuitry system 520 and a calibration CE circuitry system 530. Figure 5 The remaining elements can be configured as discussed above with respect to similarly numbered elements in the previous figures.

[0060] In the illustrated embodiment, the on-demand erase circuitry system 510 is configured to detect corrected errors from memory circuitry 104 and trigger memory circuitry 104 to correct the errors. Specifically, in the illustrated embodiment, the snooping circuitry system 510 is configured to snoop on the DSF status of read operations performed by memory controller 101. When memory circuitry 104 detects and corrects a CE, the DSF associated with the data will indicate that the CE has been corrected. The DSF is an example encoding that can be used for LPDDR5, but is not intended to limit the scope of this disclosure. In general, the snooping circuitry system can utilize any of a variety of appropriate fields to determine when memory circuitry 104 corrects errors in memory cells without updating the memory cells to the corrected value. In some embodiments, the snooping circuitry system 520 collects the DRAM channel address corresponding to each detected CE.

[0061] In response to the detection of a CE (Cutoff Detection), the snooping circuitry 520 notifies the CE correction circuitry 530, which triggers an internal correction in the memory circuitry 104. In the illustrated example, the trigger is a full mask partial write to the location representing the CE, which causes an internal read / correction / write (without changing the correction value of the data) in the memory circuitry 104 for that memory cell. Generally, the memory circuitry 104 may support commands such as a full mask partial write operation, which instructs a read location, corrects the CE for that location, and writes the corrected value back to that location.

[0062] The disclosed technology allows for simplification of the memory circuitry 104 compared to memory circuitry with built-in erase, while still providing on-demand erase functionality in some scenarios.

[0063] In some implementations, multiple on-demand erase corrections at the same location can indicate a faulty memory cell, and the operating system can take the corresponding page offline. However, for transient or soft errors, the on-demand erase techniques discussed herein can reduce the rate at which a CE (Constant Error Detection) in a memory circuit cell becomes a UE (User Error Detection).

[0064] The on-demand erase functionality can be programmable, for example, to disable on-demand erase. In some implementations, on-demand erase can not be performed in one or more modes where DSF is disabled. In some implementations, the state of on-demand erase can be locked so that it cannot be changed after boot.

[0065] It should be noted that the memory controller circuit 101 can arbitrate on-demand erase operations together with other access operations. In some embodiments, on-demand erase operations have a relatively low Quality of Service (QoS) level or category compared to one or more other types of services, which can reduce or avoid interference with the QoS of that service. In some cases, on-demand erase operations can be abandoned. In some embodiments, the snooping circuit system can track information from multiple CEs at once, but can only allow a threshold number of on-demand erase operations to be in transit at a given time (e.g., one).

[0066] In some implementations, the on-demand erase circuitry system 510 includes a forwarding progress counter that accumulates over time and can increase the priority of an on-demand erase operation when the on-demand erase operation reaches a threshold.

[0067] In some implementations, the on-demand erase circuitry 510 includes a timeout timer that starts when on-demand erase writes are enqueued into the write queue and can force a write round when the timeout timer reaches a threshold. The on-demand erase circuitry 510 can also disable on-demand erase in response to certain operating conditions, such as the write queue already having a threshold number of valid entries.

[0068] In some implementations, the data associated with the erase-on-demand write is not accessible to software (e.g., the data is read, corrected, and written internally in memory circuitry 104). In some implementations, the erase-on-demand operation is not controlled by software but is entirely controlled by hardware (e.g., the snooping circuitry system 520 and the correction CE circuitry system 530 can operate according to a finite state machine).

[0069] In some implementations, the erase-on-demand circuitry 510 is configured to record erase-on-demand operations. For example, the erase-on-demand circuitry 510 may include a software-accessible configuration register indicating a count of the DSF with a CE state (which can be maintained independently for different channels), a count of successfully completed erase-on-demand writes, and a count of abandoned erase-on-demand writes. These counters can be zeroed upon reset, by software, or by both. In some implementations, the counters are only available in debug operating mode. As used herein, the term "software" broadly refers to program instructions executed by one or more processors and includes user applications, firmware, operating systems, etc.

[0070] Example error tracking technology Figure 6This is a block diagram illustrating an example memory cache controller configured to track and log correctable and uncorrectable errors and output software-visible signaling according to some embodiments. In the illustrated embodiment, the memory cache controller 410 includes an uncorrectable error (UE) recorder 610 and a correctable error (CE) tracker 620.

[0071] In the illustrated implementation, UE recorder 610 is configured to record detected memory errors and track certain information (e.g., physical address, error source, client identifier, etc., as discussed in detail below). In the illustrated implementation, UE recorder 610 is specifically configured to record detected uncorrectable memory errors. In some implementations, UE recorder 610 tracks the source of uncorrectable errors. In some implementations, UE recorder 610 does not aggregate addresses and is not content-addressable.

[0072] In the illustrated implementation, CE tracker 620 is configured to record detected memory errors and track certain information (e.g., physical address, error count at that address, client identifier, etc.). In the illustrated implementation, CE tracker 620 is specifically configured to record detected correctable memory errors. In some implementations, CE tracker 620 implements a count field that indicates the number of correctable errors that have occurred corresponding to a given physical address. In some implementations, CE tracker 620 aggregates addresses and is content-addressable.

[0073] In the illustrated implementation, the memory cache controller 410 is configured to generate software-visible signals. These signals can notify the software of the tracker / recorder content that a content-related threshold has been met, or generally indicate to the software that an action may need to be taken (e.g., to clear an entry, mark data as poisoned, take a page offline, etc.).

[0074] It should be noted that in other embodiments, the disclosed recording / tracking circuitry may be implemented in a location other than or in place of the memory cache controller 410. However, tracking in the memory cache controller 410 can be particularly advantageous because the memory cache controller can operate using physical memory channel addresses. This information may not be available to other circuitry, therefore tracking at the memory cache controller can provide detailed information to the software while avoiding the need to transmit this information to other circuitry elements.

[0075] Generally speaking, the disclosed trace structure can advantageously provide the software with a variety of useful information that is not available in traditional implementations, which can allow the software to take appropriate corrective actions when errors are detected.

[0076] Figure 7 This is a diagram illustrating an example UE recorder data structure configured to record uncorrectable memory errors according to some embodiments. In the illustrated embodiment, the example UE recorder data structure 610 includes a validity field, a physical address field, a client identifier field, and an error source field.

[0077] In the illustrated implementation, the validity field indicates whether a data entry is valid. In some implementations, all entries in the UE recorder data structure 610 are initially set to invalid.

[0078] In the illustrated implementation, the physical address field contains memory address information about a data entry for a specific memory cell that enables the data bus to access the memory. This information can be particularly useful when the memory cell is a source of error.

[0079] In the illustrated implementation, the client identifier field identifies a client circuitry in the SoC that previously accessed the data. For example, this field could indicate a client structure identifier for a communication structure.

[0080] In the illustrated implementation, the error source field includes address information about a data entry that identifies the source of a memory error. Non-limiting example error sources that can be encoded include: a UE reading from DRAM, memory cache read data with an uncorrectable error (based on error check or poisoning indicator), or snooping response poisoned data (e.g., when snooping on another cache determines the control location of that other cache and has already marked the data as poisoned).

[0081] In some implementations, an overflow signal (e.g., a bit) is asserted when no free entry exists in the UE recorder and a UE is detected. In some implementations, the overflow bit can be sticky and persistent until it is cleared (e.g., via a write-to-clear operation). The software can initiate corrective actions based on the overflow signal to mitigate the risk of damage associated with subsequent UEs not being able to record.

[0082] In some implementations, the software can invalidate an entry, for example, by writing 1 to clear it, after it has read the entry from the UE recorder data structure 610.

[0083] Figure 8A This is a diagram illustrating an example CE tracker data structure configured to track correctable memory errors according to some embodiments. In the illustrated embodiment, the example CE tracker data structure 620 includes a validity field, a physical address field, a client identifier field, and a count field.

[0084] The valid field, physical address field, and client identifier field can track information similar to that described above in the context of UE recorder data structure 610. In some implementations, CE tracker 620 utilizes a content-addressable memory (CAM) structure, where at least a portion of the physical address is used as a tag to determine whether a hit exists on a valid entry and to increment its count, as referenced below. Figure 9 The subject of discussion.

[0085] In the illustrated implementation, the count field indicates the number of correctable errors detected for the corresponding physical address in the interval following the last clearing of the entry.

[0086] Figure 8B This is a block diagram illustrating an example memory cache controller configured to track CE errors and output signals based on meeting or exceeding certain thresholds. In the illustrated embodiment, the memory cache controller 410 includes a CE tracker 620 and outputs a first signal corresponding to an effective occupancy threshold and a second signal corresponding to a count threshold.

[0087] In the illustrated implementation, the control circuitry is configured to assert a signal indicating a valid occupancy threshold when the number of valid entries in the CE tracker 620 meets a threshold. It should be noted that in different specific implementations, a “meeting” threshold can correspond to being equal to or exceeding that threshold (e.g., having a value one level larger or smaller than the threshold).

[0088] In the illustrated implementation, the control circuitry is configured to assert a signal indicating a counting threshold when a counting field at a specific physical address in the CE tracker 620 reaches a value that satisfies a counting threshold.

[0089] The software can perform various corrective actions based on these signals, including stopping an activity when a valid occupancy threshold is met, or accessing one or more CE tracker entries when a count threshold is met.

[0090] Example technology for assigning and releasing CE tracker entries Figure 9 This is a flowchart illustrating an example method for assigning a new CE. Figure 9 The methods shown can be used in conjunction with any of the computer circuit systems, systems, devices, components, or parts disclosed herein. In various embodiments, some of the method elements shown may be executed concurrently in a different order than shown, or may be omitted. Additional method elements may also be executed as needed.

[0091] At 910, in the illustrated embodiment, the control circuitry (e.g., of the memory cache controller 410) receives a new CE.

[0092] At 920, in the illustrated implementation, the control circuitry determines whether the new CE is hit or miss in the CE tracker. For a hit, the process proceeds to 950, and for a miss, the process proceeds to 930.

[0093] At 930, in the illustrated implementation, for a missed CE in the CE tracker, the control circuitry assigns an entry in the CE tracker to the new CE and initializes its count (e.g., initializes it to 1 or a default value).

[0094] At 940, in the illustrated implementation, the control circuitry determines whether an occupancy threshold has been met (e.g., the number of valid entries in the CE tracker is determined by whether the occupancy threshold has been met after the entries were assigned at 930). If so, the control circuitry asserts a signal indicating that the valid occupancy threshold has been met.

[0095] In some implementations, in response to the signal, the software takes a snapshot of the visible valid entries and can clear the entries to free up space in the CE tracker. In some implementations, a new CE may not be tracked if no free entries exist in the CE tracker. It should be noted that in some cases, entries may not be visible to the software. For example, the control circuitry may only allow the software to access all or part of an entry after one of a published thresholds has been hit.

[0096] At 950, in the illustrated implementation, for a hit in the CE tracker, the control circuitry increments the count value for the hit entry and updates the client identifier of that entry to the most recent client associated with the error. In other implementations, the client identifier field may track multiple client identifiers, and the control circuitry may add the most recent client identifier to the list of identifiers.

[0097] At 960, in the illustrated embodiment, the control circuitry determines whether a count threshold has been met due to the increment at 950. If so, the control circuitry asserts a signal indicating that the count threshold has been met. In some embodiments, this signal can warn the software of a potentially faulty DRAM cell, which can allow the software to take various actions, such as taking the page containing that cell offline.

[0098] Figure 10 This is a flowchart illustrating an example method for releasing a CE tracker entry. Figure 10 The methods shown can be used in conjunction with any of the computer circuit systems, systems, devices, components, or parts disclosed herein. In various embodiments, some of the method elements shown may be executed concurrently in a different order than shown, or may be omitted. Additional method elements may also be executed as needed.

[0099] At 1010, in the illustrated implementation, the control circuitry determines whether the CE tracker is accessible by software. If yes, the process proceeds to 1020. If no, the control circuitry may not take further action.

[0100] At 1020, in the illustrated implementation, after verifying that the CE tracker is accessible by software, the control circuitry reads one or more entries. In some implementations, a protocol is initiated to take a snapshot of all visible valid entries in the CE tracker structure.

[0101] At 1030, in the illustrated implementation, the control circuitry determines whether to release one or more entries in the CE tracker. In some implementations, the release is performed by software, for example, using a write-1 to clear mechanism.

[0102] In some implementations, the release of one or more entries in the CE tracker is determined by software. The software has an option not to release entries. According to some implementations, the software can move CE tracker information to another data structure to make space available in the CE tracker. This may be useful, for example, in cases where there are a large number of unique CE addresses or when the threshold is reduced.

[0103] Example Method Figure 11 This is a flowchart illustrating an example method for tracking corrupted data according to some implementation schemes. Figure 11 The methods shown can be used in conjunction with any of the computer circuit systems, systems, devices, components, or parts disclosed herein. In various embodiments, some of the method elements shown may be executed concurrently in a different order than shown, or may be omitted. Additional method elements may also be executed as needed.

[0104] At 1110, in the illustrated embodiment, the memory controller circuitry communicates with the memory circuitry via an interface. The memory circuitry can implement both link error correction and on-chip error correction. In some embodiments, the memory circuitry supports error detection for the interface (e.g., write link ECC), which causes a combination of data and parity to be written to the target memory location for a detected uncorrectable write interface error, wherein this combination corresponds to the uncorrectable error.

[0105] At 1120, in the illustrated embodiment, the memory controller circuitry arbitrates requests from the requesting agent circuitry to access the memory circuitry, including a first request to write first data to a first location in the memory circuitry.

[0106] At 1130, in the illustrated embodiment, the memory controller circuitry maintains corruption indicators for data blocks, including a first corruption indicator indicating that first data has been determined to be corrupt. In some embodiments, a proxy circuit in the proxy circuitry is configured to generate the first corruption indicator, for example, based on the detected UE.

[0107] In some implementations, the device including the memory controller circuitry is configured to maintain a corruption indicator through a plurality of operations, which include any combination of the following operations: propagating the corruption indicator after merging one or more requests to resolve the hazard; propagating the corruption indicator for a write-to-read forwarding operation from a write queue; converting the corruption indicator into an enforced uncorrectable write interface error; transmitting the corruption indicator from the memory cache controller circuitry to the memory controller circuitry; and propagating a corruption indicator determined based on an address mask.

[0108] At 1140, in the illustrated embodiment, the memory controller circuitry transmits a data and parity combination for the first data block, which causes the memory circuitry to detect an uncorrectable write interface error.

[0109] At 1150, in the illustrated embodiment, after a write request for the first request, the memory controller circuitry reads the memory location and generates a corruption indicator for the read data in response to a report from the memory circuitry of an uncorrectable error in the read data.

[0110] In some embodiments, the on-demand erase circuitry is configured to detect corrected errors indicated by the memory circuitry, whereby the incorrect data remains stored in the memory cells of the memory circuitry, and in response to the detection of a corrected error, initiate an on-demand erase write operation to the memory circuitry, causing an internal read, error correction of the correctable error, and writing of the corrected data within the memory circuitry. In some embodiments, the write operation is a full mask write operation to the detected DRAM address of the corrected error. In some embodiments, the on-demand erase circuitry is configured to record in one or more software-accessible registers the number of detected correctable errors and the number of successful on-demand erase writes. In some embodiments, the detection of corrected errors is based on a decoding status flag reported by the memory circuitry, indicating whether the provided data has no errors, has correctable errors, or has uncorrectable errors.

[0111] In some embodiments, the memory circuitry includes an error circuitry configured to: for write operations, verify parity information for write data that is not erroneous; and correct detected correctable errors associated with the interface. In some embodiments, the memory circuitry includes an error circuitry configured to: for read operations, correct detected errors associated with the read location; and report detected uncorrectable errors associated with the read location via the interface.

[0112] Figure 12 This is a flowchart illustrating an example method for tracking the number of correctable errors detected, according to some implementation schemes. Figure 12 The methods shown can be used in conjunction with any of the computer circuit systems, systems, devices, components, or parts disclosed herein. In various embodiments, some of the method elements shown may be executed concurrently in a different order than shown, or may be omitted. Additional method elements may also be executed as needed.

[0113] At 1210, in the illustrated embodiment, data operated on by one or more processors is cached in a memory cache.

[0114] At 1220, in the illustrated implementation, multiple tracking circuit entries are used to track the number of detected correctable errors associated with multiple corresponding locations.

[0115] At 1230, in the illustrated implementation, in response to detecting the number of correctable errors for a particular location, a signal identifying the particular location is generated to one or more processors.

[0116] In some implementations, an assertion identifies a signal at a specific location to indicate that a count threshold has been hit. This signal can warn the software of the presence of pages in which potentially faulty DRAM may be nearing failure.

[0117] In some implementations, an alarm signal is generated in response to the number of valid entries in the trace circuit entries matching or exceeding an occupancy threshold. In some implementations, in response to matching or exceeding the occupancy threshold, the software is enabled to access one or more trace circuit entries.

[0118] In some implementations, one or more trace circuit entries can be released in response to software signaling.

[0119] In some implementations, multiple circuit entries include a corresponding client identifier field indicating the client associated with a given correctable error. In some implementations, multiple UE tracking circuit entries are used to track detected UEs associated with multiple corresponding locations of data.

[0120] In some implementations, UE tracking circuit entries include a source field that identifies the source of a given UE. In some implementations, the source field is configured to encode sources that include at least the following sources: memory errors, memory cache errors, and snooping responses. In some implementations, multiple UE tracking circuit entries are not tagged, and multiple tracking circuit entries are tagged using at least a portion of an address for a given location.

[0121] In some implementations, the device is configured to maintain a corruption indicator for data blocks, wherein the corruption indicator indicates that the data block has been determined to be corrupt.

[0122] Example device See now Figure 13 A block diagram illustrating an example embodiment of device 1300 is shown. In some embodiments, the components of device 1300 may be included within a system-on-a-chip. In some embodiments, device 1300 may be included in a battery-powered mobile device. Therefore, the power consumption of device 1300 may be an important design consideration. In the illustrated embodiment, device 1300 includes a structure 1310, a computing complex 1320, an input / output (I / O) bridge 1350, a cache / memory controller 1345, a graphics unit 13135, and a display unit 1365. In some embodiments, in addition to or in place of the illustrated components, device 1300 may include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0123] Structure 1310 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various components of device 1300. In some embodiments, portions of structure 1310 may be configured to implement various different communication protocols. In other embodiments, structure 1310 may implement a single communication protocol, and components coupled to structure 1310 may internally switch from a single communication protocol to other communication protocols.

[0124] In the illustrated embodiments, computing complex 1320 includes a bus interface unit (BIU) 1325, a cache 1330, and cores 1335 and 1340. In various embodiments, computing complex 1320 may include a variety of numbers of processors, processor cores, and caches. For example, computing complex 1320 may include one, two, or four processor cores, or any other suitable number. In one embodiment, cache 1330 is a collection of associated L2 caches. In some embodiments, cores 1335 and 1340 may include internal instruction and data caches. In some embodiments, coherence units (not shown) in architecture 1310, cache 1330, or elsewhere in device 1300 may be configured to maintain coherence between the various caches of device 1300. BIU 1325 may be configured to manage communication between computing complex 1320 and other elements of device 1300. Processor cores such as cores 1335 and 1340 may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions.

[0125] The cache / memory controller 1345 can be configured to manage data transfer between the structure 1310 and one or more caches and memories. For example, the cache / memory controller 1345 can be coupled to an L3 cache, which in turn can be coupled to system memory. In other embodiments, the cache / memory controller 1345 can be directly coupled to memory. In some embodiments, the cache / memory controller 1345 may include one or more internal caches.

[0126] As used herein, the term "coupled to" can indicate one or more connections between elements, and coupling can include intermediate elements. For example, in Figure 13 In this context, the graphics unit 1375 can be described as being "coupled" to memory via structure 1310 and cache / memory controller 1345. In contrast, in... Figure 13 In the exemplary implementation, the graphics unit 1375 is "directly coupled" to the structure 1310 because there are no intermediate elements.

[0127] The graphics unit 1375 may include one or more processors, such as one or more graphics processing units (GPUs). For example, the graphics unit 1375 may receive graphics-oriented instructions, such as OpenGL. ® Metal or Direct3D ®Instructions. The graphics unit 1375 can execute dedicated GPU instructions or perform other operations based on received graphics-oriented instructions. The graphics unit 1375 can typically be configured to process large blocks of data in parallel and can construct an image in a frame buffer for output to a display, which may be included in a device or may be a separate device. The graphics unit 1375 may include transformation, lighting, triangle, and rendering engines in one or more graphics processing pipelines. The graphics unit 1375 can output pixel information for displaying the image. In various embodiments, the graphics unit 1375 may include a programmable shader circuitry system that may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and computation tasks (which may be graphics-dependent or not).

[0128] Display unit 1365 can be configured to read data from a frame buffer and provide a stream of pixel values ​​for display. In some embodiments, display unit 1365 can be configured as a display pipeline. Additionally, display unit 1365 can be configured to blend multiple frames to produce an output frame. Furthermore, display unit 1365 may include one or more interfaces (e.g., MIPI) for coupling to a user display (e.g., a touchscreen or an external display). ® Or embedded display port (eDP)).

[0129] I / O bridge 1350 may include various elements configured to implement features such as Universal Serial Bus (USB) communication, security, audio, and low-power always-on functionality. I / O bridge 1350 may also include interfaces such as pulse width modulation (PWM), general purpose input / output (GPIO), serial peripheral interface (SPI), and internal integrated circuit (I2C). Various types of peripheral devices and devices can be coupled to device 1300 via I / O bridge 1350.

[0130] In some embodiments, device 1300 includes a network interface circuitry (not explicitly shown) that can be connected to structure 1310 or I / O bridge 1350. The network interface circuitry can be configured to communicate via various networks, which can be wired networks, wireless networks, or both. For example, the network interface circuitry can be configured to communicate via a wired local area network (LAN), a wireless LAN (e.g., via WiFi), or a wide area network (e.g., the Internet or a virtual private network). In some embodiments, the network interface circuitry is configured to communicate via one or more cellular networks using one or more radio access technologies. In some embodiments, the network interface circuitry is configured to communicate using device-to-device communication (e.g., Bluetooth or WiFi Direct). In various embodiments, the network interface circuitry can provide device 1300 with connectivity to various types of other devices and networks.

[0131] Figure 13 Various components can utilize the disclosed techniques. For example, a memory cache controller 410, a memory controller circuit 101, or both can be included in component 1345. Structure 1310 can support a corruption indicator. Various proxy circuits, such as graphics unit 1375, computing complex 1320, etc., can detect data poisoning and propagate the poisoning indicator. In various embodiments, the disclosed techniques can advantageously improve memory reliability.

[0132] Example Application Now go to Figure 14 This illustrates various types of systems that may include any of the circuits, devices, or systems discussed above. The system or device 1400, which may utilize one or more of the techniques described herein in combination or otherwise, can be used in a wide range of fields. For example, the system or device 1400 can be used as part of the hardware of a system such as a desktop computer 1410, a laptop computer 1420, a tablet computer 1430, a cellular or mobile phone 1440, or a television 1450 (or a set-top box coupled to a television).

[0133] Similarly, the disclosed components can be used in wearable devices 1460, such as smartwatches or health monitoring devices. In many embodiments, a smartwatch can perform a variety of different functions—for example, access to email, cellular services, calendars, health monitoring, etc. Wearable devices can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also envisioned, including devices worn around the neck, implantable devices, and glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality.

[0134] System or device 1400 can also be used in a variety of other contexts. For example, system or device 1400 can be used in the context of a server computer system (such as a dedicated server) or on shared hardware implementing cloud-based services 14130. Furthermore, system or device 1400 can be implemented in a wide range of dedicated everyday devices, including common household devices 1480 such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). Components can also be implemented in various modes of transportation. For example, system or device 1400 can be used in control systems, guidance systems, entertainment systems, etc., of various types of vehicles 1490.

[0135] Figure 14 The applications illustrated herein are merely exemplary and are not intended to limit the potential future applications of the disclosed systems or devices. Other example applications include, but are not limited to, portable gaming devices, music players, data storage devices, and unmanned aerial vehicles.

[0136] Example computer-readable media Various example circuits have been described in detail above in this disclosure. It is intended that this disclosure cover not only embodiments including such circuit systems, but also computer-readable storage media including design information specifying such circuits. Therefore, this disclosure is intended to support claims that cover not only means including the disclosed circuit systems, but also storage media specifying circuit systems in a format recognized by a manufacturing system configured to produce hardware (e.g., integrated circuits) including the disclosed circuit systems. Claims regarding such storage media are intended to cover entities that, for example, generate circuit designs but do not manufacture those designs themselves.

[0137] Figure 15This is a block diagram illustrating an example non-transitory computer-readable storage medium for storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 1520 is configured to process design information 1515 stored on a non-transitory computer-readable medium 1510 and to manufacture an integrated circuit 1530 based on the design information 1515.

[0138] The non-transitory computer-readable storage medium 1510 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1510 may be an installation medium, such as a CD-ROM, floppy disk, or magnetic tape device; computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory, such as flash memory; magnetic media, such as a hard disk drive or optical storage device; registers, or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 1510 may include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1510 may include two or more memory media that may reside in different locations, such as different computer systems connected via a network.

[0139] Design information 1515 can be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 1515 can be used by semiconductor manufacturing system 1520 to manufacture at least a portion of integrated circuit 1530. The format of design information 1515 can be recognized by at least one semiconductor manufacturing system 1520. In some embodiments, design information 1515 may also include one or more cell libraries specifying the synthesis, layout, or both of integrated circuit 1530. In some embodiments, the design information is specified, wholly or partially, in the form of a netlist specifying cell library elements and their connectivity. Design information 1515 acquired separately may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, design information 1515 may specify circuit elements to be manufactured but not their physical layout. In this case, design information 1515 may need to be combined with layout information to actually manufacture the specified circuit system.

[0140] In various implementations, integrated circuit 1530 may include one or more custom macrocells, such as memory, analog or mixed-signal circuitry, etc. In this case, design information 1515 may include information associated with the included macrocells. Such information may include, but is not limited to, a circuit diagram capture database, mask design data, behavioral models, and device or transistor-level netlists. As used herein, mask design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0141] The semiconductor manufacturing system 1520 may include any of the various suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or by using ultraviolet treatment to modify the dielectric constant), etc. The semiconductor manufacturing system 1520 may also be configured to perform various tests on the manufactured circuits for proper operation.

[0142] In various embodiments, integrated circuit 1530 is configured to operate according to a circuit design specified by design information 1515, which may include any of the functions described herein. For example, integrated circuit 1530 may include Figure 1 To Figure 8 and Figure 13 Any of the various components shown herein. Additionally, integrated circuit 1530 can be configured to perform the various functions described herein in conjunction with other components. Furthermore, the functionality described herein can be performed by multiple interconnected integrated circuits.

[0143] As used herein, a phrase in the form of “design information specifying the design of a circuit configured to…” does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated action or will include the specified components.

[0144] *** This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0145] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with an embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. Given the existence of possible factors outside this disclosure, any potential advantages described herein should not be construed as a claim limitation that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to show one or more types of improvements available to the designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0146] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The embodiments disclosed in this invention are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow for the coverage of the claims of the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art who are aware of the effective effects of this disclosure.

[0147] For example, features in this application can be combined in any suitable manner. Therefore, new claims may be made for any such combination of features during the proceedings of this patent application (or a patent application claiming priority thereto). Specifically, referring to the appended claims, features of dependent claims may be combined with features of other dependent claims, including claims dependent on other independent claims, where appropriate. Similarly, features from the respective independent claims may be combined where appropriate.

[0148] Thus, although the appended dependent claims may be drafted such that each dependent claim depends from a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated, and such combinations may be claimed in this patent application or in another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0149] In appropriate circumstances, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0150] *** Because the present disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the following paragraphs, as well as the definitions provided throughout the present disclosure, will be used to determine how claims drafted based on the present disclosure are to be interpreted.

[0151] References to items in the singular form (i.e., a noun or noun phrase preceded by "a," "an," or "the") are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. A "plurality" of items means a collection of two or more items.

[0152] The word "may" is used herein in an allowed sense (i.e., having the potential to, being able to), rather than in a mandatory sense (i.e., must).

[0153] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to."

[0154] When the term "or" is used in the present disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the statement "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0155] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0156] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit”, “second circuit”, “specific circuit”, “given circuit”, etc.) refer to different instances of the feature. Furthermore, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0157] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on another factor such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0158] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor along with other unspecified factors. Consider the phrase “responding to B to execute A.” This phrase specifies that B is a factor that triggers the execution of A or a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be performed jointly in response to B and C. This phrase is also intended to cover implementations where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0159] *** Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be “configured” to perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as “configured” to perform a task refers to a physical thing used to perform that task, such as a device, circuit, system with processor units, and memory storing executable program instructions. This phrase is not used herein to refer to intangible things.

[0160] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated.

[0161] The term "configured as" is not intended to mean "configurable as". For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA may be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0162] For the purposes of this U.S. patent application, the statement in the claims that the structure is “configured” to perform one or more tasks is expressly intended for the claim element. No Referencing 35 USC § 112(f). If an applicant wishes to invoke part 112(f) in the course of filing a U.S. patent application based on this disclosure, it will use the structure “component for [performing function]” to describe the elements of the claims.

[0163] Different “circuits” may be described in this disclosure. These circuits or “circuit systems” constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuit systems may be custom-designed or taken from standard libraries. In various specific implementations, circuit systems may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits or circuit systems.

[0164] Therefore, the circuits / units / components and other elements disclosed in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0165] In various implementations, as described in the preceding paragraphs, circuits, cells, and other elements can be defined by the functions or operations they are configured to perform. The arrangement of these circuits / cells / components relative to each other and the manner in which they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill in the art, by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry system. The integrated circuit can include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented within the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0166] The fact that a circuit of the same specifications can be implemented using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0167] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

Claims

1. An apparatus comprising: The memory circuit system includes: A memory unit configured to store data; An interface circuit system, the interface circuit system including a first interface configured to transmit data and a second interface configured to transmit parity check information for the data; An on-chip error correction code (ECC) circuit system, wherein the on-chip ECC circuit system is configured as follows: Check for errors in the data read from the memory unit; and Correct the detected correctable errors to generate corrected data; A link ECC circuit system, the link ECC circuit system being configured to transmit link parity information via the second interface; The memory circuit system is configured as follows: The requesting circuit is provided with read data via the first interface, including one or more sets of corrected data from the on-chip ECC circuitry; and Provide Decoding Status Flags (DSF), including: In response to the absence of an error for a given set of read data, the DSF is set to a first value; In response to a given set of read data being provided by the on-chip ECC circuitry system after a correctable error has been detected and corrected by the on-chip ECC circuitry system, the DSF is set to a second value; In response to the on-chip ECC circuitry detecting an uncorrectable error, the DSF is set to a third value; and The DSF is transmitted via the second interface in the same way as the link parity information.

2. The apparatus of claim 1, wherein the memory circuit system is an LPDDR5 circuit.

3. The apparatus of claim 1, wherein the on-chip ECC circuitry is configured to correct single-bit errors but not multi-bit errors.

4. The apparatus of claim 1, wherein the memory circuitry is configured to disable DSF reporting in one or more operating modes.

5. The apparatus of claim 1, wherein the memory circuitry is configured to perform a requested mask write operation to read data from a specified memory cell, correct one or more correctable errors in the data read from the specified memory cell, and write the corrected data back to the specified memory cell.

6. The apparatus of claim 1, wherein the memory circuitry is configured to maintain a count of correctable errors and to perform an action in response to determining that the count satisfies a first threshold.

7. The apparatus of claim 6, wherein the action is an action related to reporting.

8. The apparatus of claim 6, wherein the memory circuitry is further configured to perform the action based on the detection of an uncorrectable error.

9. The apparatus of claim 6, wherein the memory circuitry is further configured as follows: Maintain region-specific counts of correctable errors for memory regions; and The action is performed in response to the region-specific count meeting the second threshold.

10. The apparatus according to claim 1, further comprising: The request circuit is a memory controller circuit included in the device, and the memory controller circuit is configured to receive the DSF from the memory circuit system.

11. An apparatus comprising: The memory controller circuit includes: An interface circuit system, the interface circuit system including a first interface configured to receive read data from a memory circuit and a second interface configured to receive parity information for the data; A link ECC circuit system configured to receive link parity check information via the second interface and check whether the link parity check information contains a link error; A control circuit system configured to receive a Decoding Status Flag (DSF) from the memory circuit via the second interface, identical to the link parity information, wherein: The first value of the DSF indicates that no error was detected for the read data; The second value of the DSF indicates that correctable errors have been detected and corrected by the on-chip error correction code (ECC) circuitry of the memory circuitry to generate the read data; and The third value of the DSF indicates that an uncorrectable error in the read data has been detected by the on-chip ECC circuitry of the memory circuitry.

12. The apparatus of claim 11, wherein the interface circuitry supports one or more LPDDR5 interfaces.

13. The apparatus of claim 11, wherein the control circuitry is configured to issue a mask write operation, the mask write operation being configured to specify reading data from a specified memory cell, correcting one or more correctable errors in the data read from the specified memory cell, and writing the corrected data back to the specified memory cell.

14. The apparatus of claim 11, further comprising: The memory circuitry is configured to provide read data to the requesting circuitry via the interface circuitry system, including one or more sets of data corrected by the on-chip ECC circuitry system.

15. A method comprising: Data is stored in one or more memory cells using a memory circuit system; The on-chip error correction code (ECC) circuitry of the memory circuitry is used to check whether there are errors in the data read from the memory cell. The on-chip ECC circuit system is used to correct detected correctable errors to generate corrected data. The memory circuitry provides read data and Decoding Status Flag (DSF) information to the requesting circuit, wherein the read data is provided via a first interface and the DSF information is provided via a second interface, including: In response to the absence of an error in the first set of provided read data, a first value of the DSF is provided; In response to the fact that a correctable error has been detected and corrected by the on-chip ECC circuitry to provide a second set of read data, a second value of the DSF is provided; and In response to the on-chip ECC circuitry detecting an uncorrectable error, a third value of the DSF is provided; and The memory circuitry provides link ECC parity information via the second interface, similar to the DSF information.

16. The method of claim 15, further comprising: The memory circuitry system performs a mask write operation to read data from a specified memory cell, corrects one or more correctable errors in the data read from the specified memory cell, and writes the corrected data back to the specified memory cell.

17. An apparatus comprising: Memory circuitry; One or more processors, the one or more processors being configured to execute program instructions, wherein at least a portion of the program instructions access data in the memory circuitry; A tracking circuit system that implements multiple tracking circuit entries; as well as A control circuit system configured to use a plurality of uncorrectable error (UE) tracking circuit entries to track detected uncorrectable errors associated with a plurality of corresponding memory locations, wherein the UE tracking circuit entries include a source field that identifies the source of a given UE.

18. The apparatus of claim 17, wherein the source field is configured to encode a source comprising at least the following sources: memory errors and snooping responses.

19. The apparatus of claim 18, wherein the source field is further configured to encode memory cache errors.

20. The apparatus of claim 17, wherein the UE tracking circuit entry includes a physical address field indicating the memory location of an uncorrectable error.

21. The apparatus of claim 17, wherein the UE tracking circuit entry includes a client identifier field indicating a client circuit system that has accessed the corresponding data.

22. The apparatus of claim 21, wherein the client identifier is a structure identifier of a communication structure circuit system for supporting communication between multiple clients.

23. The apparatus of claim 17, wherein the UE tracking circuit entry includes a valid field indicating whether error information in a given entry is valid.

24. The apparatus of claim 17, wherein the plurality of UE tracking circuit entries are not marked.

25. The apparatus of claim 17, further comprising: The control circuit system is configured to: Maintain corruption indicators for data blocks, including a first corruption indicator for indicating that first data has been determined to be corrupted based on an uncorrectable error; as well as Based on the first damage indicator, a combination of data and parity check is transmitted via the memory interface for the first data block, the combination of data and parity check causing the memory circuitry to detect an uncorrectable write interface error.

26. The apparatus of claim 17, further comprising a control circuitry configured to assert an overflow indicator in response to all entries in the UE tracking circuitry being full.

27. The apparatus of claim 17, further comprising a control circuitry system configured to invalidate an entry in response to a software signal indicating that software has read an entry from the UE tracking circuitry entries.

28. A method comprising: Instructions are executed by one or more processors of a computing device, wherein at least some of the program instructions access data in memory; as well as The control circuitry of the computing device uses a tracking circuitry system that implements multiple tracking circuitry entries to track detected uncorrectable errors associated with multiple corresponding memory locations, wherein the tracking circuitry entries include a source field that identifies the source of a given uncorrectable error (UE).

29. The method of claim 28, wherein the source field encodes a source that includes at least the following sources: memory errors and snooping responses.

30. The method of claim 29, wherein the source field further encodes memory cache errors.

31. The method of claim 28, wherein the tracing includes recording a physical address field for indicating the location of a memory error that cannot be corrected.

32. The method of claim 28, wherein the tracking includes recording a client identifier field for indicating a client circuit system that has accessed the corresponding data.

33. The method of claim 28, further comprising: Maintain corruption indicators for data blocks, including a first corruption indicator for indicating that first data has been determined to be corrupted based on an uncorrectable error; as well as Based on the first corruption indicator, a combination of data and parity check is transmitted via the memory interface for the first data block, the combination of data and parity check causing the memory to detect an uncorrectable write interface error.

34. The method of claim 28, further comprising asserting an overflow indicator in response to all entries in the UE tracking circuit entry being full.

35. The method of claim 28, further comprising deactivating the entry in response to a software signal indicating that the software has read one of the entries in the UE tracking circuit entry.

36. An apparatus comprising: One or more processors, the one or more processors being configured to execute program instructions; Memory cache; The memory cache controller circuit system is configured to: The data operated by the one or more processors is cached in the memory cache; Using multiple tracking circuit entries, the number of detected correctable errors associated with multiple corresponding locations of data processed by the memory cache controller circuitry system is tracked, wherein a given correctable error among the detected correctable errors includes at most a threshold number of bit errors; as well as In response to the detection of a correctable error for a threshold number of locations, a signal for identifying the specific location is generated to the one or more processors.

37. The apparatus of claim 36, wherein the memory cache controller circuitry is further configured to: An alarm signal is generated in response to determining that the number of valid entries in the tracking circuit entries indicating at least one correctable error meets the occupancy threshold.

38. The apparatus of claim 37, wherein the memory cache controller circuitry is further configured to: In response to the determination, the software is enabled to access one or more trace circuit entries.

39. The apparatus of claim 38, wherein the memory cache controller circuitry is further configured to: In response to software signaling, release one or more trace circuit entries from the trace circuit entries.

40. The apparatus of claim 36, wherein the plurality of trace circuit entries includes a corresponding client identifier field indicating a client associated with a given correctable error.

41. The apparatus of claim 36, wherein the memory cache controller circuitry is further configured to: Multiple uncorrectable error (UE) tracking circuit entries are used to track detected uncorrectable errors associated with multiple corresponding locations of data processed by the memory cache controller circuitry.

42. The apparatus of claim 41, wherein the UE tracking circuit entry includes a source field for identifying the source of a given UE.

43. The apparatus of claim 42, wherein the source field is configured to encode a source comprising at least the following sources: memory error, memory cache error, and snooping response.

44. The apparatus of claim 41, wherein the plurality of UE tracking circuit entries are not marked, and wherein the plurality of tracking circuit entries for which a correctable error is detected are marked using at least a portion of an address at a given location.

45. The apparatus of claim 41, wherein the apparatus is configured to maintain a corruption indicator for a data block, wherein the corruption indicator is used to indicate that the data block has been determined to be corrupted.

46. ​​The apparatus of claim 36, wherein the apparatus is a computing device, the computing device further comprising: Central processing unit; monitor; and Network interface circuit system.

47. A method comprising: The memory cache controller circuitry caches data operated by one or more processors in the memory cache. Using multiple tracking circuit entries, the number of detected correctable errors associated with multiple corresponding locations of data processed by the memory cache controller circuitry system is tracked, wherein a given correctable error among the detected correctable errors includes at most a threshold number of bit errors; as well as In response to the detection of a correctable error for a threshold number of locations, a signal for identifying the specific location is generated to the one or more processors.

48. The method of claim 47, further comprising: In response to determining that the number of valid entries in the tracking circuitry indicating at least one correctable error meets an occupancy threshold, the memory cache controller circuitry generates an alarm signal to the software, the alarm signal indicating a potential future occupancy problem.

49. The method of claim 48, further comprising: In response to the occupancy threshold being met, the software is enabled to access one or more trace circuit entries.

50. The method of claim 47, further comprising: Multiple uncorrectable error (UE) tracking circuit entries are used to track detected uncorrectable errors associated with multiple corresponding locations of data processed by the memory cache controller circuitry.

51. An apparatus comprising: Memory circuitry; One or more processors, the one or more processors being configured to execute program instructions, wherein at least a portion of the instructions access data in the memory circuitry; A tracking circuit system, wherein the tracking circuit system implements multiple tracking circuit entries; and The control circuit system is configured to: Using the plurality of tracking circuit entries, the number of detected correctable errors associated with a plurality of corresponding data locations accessed by the one or more processors is tracked; as well as In response to detecting a correctable number of errors for a specific memory location, a signal is generated to at least one of the one or more processors, wherein the signal is used to identify the specific memory location.

52. The apparatus of claim 51, further comprising: Memory cache; The control circuit system includes a memory cache controller circuit system, which is configured to: The data operated by the one or more processors is cached in the memory cache; as well as The number of detectable correctable errors is tracked based on data cached in the memory cache.

53. The apparatus of claim 51, wherein the control circuit system is further configured to: An alarm signal is generated in response to the number of valid entries in the tracking circuit entries meeting the occupancy threshold.

54. The apparatus of claim 53, wherein the control circuit system is further configured to: In response to the occupancy threshold being met, software access to one or more trace circuit entries is enabled.

55. The apparatus of claim 54, wherein the control circuit system is further configured to: In response to software signaling, release one or more trace circuit entries from the trace circuit entries.

56. The apparatus of claim 51, wherein the plurality of tracking circuit entries includes a corresponding client identifier field for indicating a client associated with a given correctable error.

57. The apparatus of claim 51, wherein the control circuit system is further configured to: Multiple uncorrectable error (UE) tracking circuit entries are used to track detected uncorrectable errors associated with multiple corresponding memory locations.

58. The apparatus of claim 57, wherein the UE tracking circuit entry includes a source field for identifying the source of a given UE.

59. The apparatus of claim 58, wherein the source field is configured to encode a source comprising at least the following sources: memory errors and snooping responses.

60. The apparatus of claim 57, wherein the plurality of UE tracking circuit entries are not tagged, and wherein the plurality of tracking circuit entries for which a correctable error is detected are tagged using at least a portion of an address at a given location.

61. The apparatus of claim 51, wherein the apparatus is configured to maintain a corruption indicator for a data block, wherein the corruption indicator is used to indicate that the data block has been determined to be corrupted.

62. The apparatus of claim 51, wherein the apparatus is a computing device, the computing device further comprising: Central processing unit; monitor; as well as Network interface circuit system.

63. A method comprising: The computing system executes program instructions, at least some of which access data in memory; The computing system uses multiple tracking entries to track the number of detected correctable errors associated with multiple corresponding data locations accessed by one or more processors of the computing system; as well as In response to detecting a correctable number of errors for a specific memory location, a signal is generated to at least one of the one or more processors, wherein the signal is used to identify the specific memory location.

64. The method of claim 63, further comprising: The computing system generates an alarm signal in response to the number of valid entries in the tracked entries meeting an occupancy threshold.

65. The method of claim 64, further comprising: In response to meeting the occupancy threshold, the computing system enables software access to one or more tracking entries.

66. The method of claim 65, further comprising: In response to software signaling, the computing system releases one or more tracking entries from the tracking entries.

67. The method of claim 63, wherein the plurality of tracking entries includes a corresponding client identifier field for indicating the client associated with a given correctable error.

68. The method of claim 63, further comprising: The computing system uses multiple uncorrectable error (UE) tracking entries to track detected uncorrectable errors associated with multiple corresponding memory locations.

69. The method of claim 63, further comprising: The computing system maintains a corruption indicator for the data block, wherein the corruption indicator is used to indicate that the data block has been determined to be corrupt.

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