Apparatus and method for generating syndrome and partial coefficient information in parallel

Abstract

An error correction device according to the technical idea of the present disclosure includes: a syndrome generation circuit configured to receive data and generate a plurality of syndromes for the data; a partial coefficient generation circuit configured to generate, while the plurality of syndromes are generated, partial coefficient information about a part of coefficients of an error location polynomial by using the data; an error location determination circuit configured to determine the coefficients of the error location polynomial based on the plurality of syndromes and the partial coefficient information, and obtain a location of an error in the data by using the error location polynomial; and an error correction circuit configured to correct the error in the data according to the location of the error.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0067163, filed on June 3, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to an error correction apparatus and method for generating compensator and partial coefficient information in parallel. Background Technology

[0004] An error correction decoder can perform error correction coding (ECC) to correct erroneous bits in information data.

[0005] As communication speeds and data throughput increase, the number of error bits in the information data may increase. Due to this increase in error bits, the error correction delay required from when the error correction decoder receives the information data until it outputs corrected data may be prolonged. Summary of the Invention

[0006] The problem solved by the technical idea of ​​this disclosure is to reduce error correction delay by generating a corrector for partial coefficients and the equation for the error location in parallel.

[0007] The error correction apparatus according to aspects of this disclosure includes: a corrector generation circuit configured to receive data and generate a plurality of correctors for the data; a partial coefficient generation circuit configured to generate partial coefficient information relating to a portion of the coefficients of an error location polynomial by using the data while generating the plurality of correctors; an error location determination circuit configured to determine the coefficients of the error location polynomial based on the plurality of correctors and the partial coefficient information, and to obtain the location of the error in the data by using the error location polynomial; and an error correction circuit configured to correct the error in the data according to the location of the error.

[0008] The error correction method according to aspects of this disclosure includes: reading data from a storage cell array; generating multiple correctors for the data; generating partial coefficient information related to a portion of the coefficients of an error location polynomial using the data while generating the multiple correctors; determining the coefficients of the error location polynomial based on the multiple correctors and the partial coefficient information; obtaining the location of the error in the data by using the error location polynomial; and correcting the error in the data based on the location of the error.

[0009] The volatile storage device according to aspects of this disclosure includes: a memory cell array including a plurality of memory cells; and an error correction engine configured to correct data read from the memory cell array, wherein the error correction engine includes: a corrector generation circuit configured to generate a plurality of correctors using the data read from the memory cell array; a partial coefficient generation circuit configured to generate partial coefficient information relating to a portion of the coefficients of an error location polynomial while generating the plurality of correctors; an error location determination circuit configured to determine the coefficients of the error location polynomial based on the plurality of correctors and the partial coefficient information, and to obtain the location of an error in the data by using the error location polynomial; and an error correction circuit configured to correct the error in the data based on the location of the error. Attached Figure Description

[0010] Embodiments of the invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which similar reference numerals denote similar elements. In the drawings:

[0011] Figure 1 This is a block diagram illustrating an error correction device according to an exemplary embodiment of the present disclosure;

[0012] Figure 2 This is a flowchart illustrating an error correction method according to an exemplary embodiment of the present disclosure;

[0013] Figure 3 This is a diagram illustrating the time delay for error correction according to exemplary embodiments of the present disclosure;

[0014] Figure 4 This is a diagram illustrating a collimator generation circuit according to exemplary embodiments of the present disclosure;

[0015] Figure 5 This is a diagram illustrating an error-correcting polynomial generation circuit according to exemplary embodiments of the present disclosure;

[0016] Figure 6 This is a diagram illustrating a portion of the coefficient generation circuit according to an exemplary embodiment of the present disclosure;

[0017] Figure 7 This is a diagram illustrating an error correction device according to exemplary embodiments of the present disclosure;

[0018] Figure 8 This is a diagram illustrating a portion of the coefficient generation circuit according to an exemplary embodiment of the present disclosure;

[0019] Figure 9 This is a diagram illustrating an error-correcting polynomial generation circuit according to an exemplary embodiment of the present disclosure;

[0020] Figure 10This is a block diagram illustrating a storage device including an ECC engine that performs comparator generation and partial coefficient generation in parallel, according to an exemplary embodiment of the present disclosure;

[0021] Figure 11 It is shown Figure 10 Block diagram of the ECC encoding circuit;

[0022] Figure 12 It is shown Figure 10 Block diagram of the ECC decoding circuit;

[0023] Figure 13 This is a diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present invention;

[0024] Figure 14 This is a block diagram illustrating an example of applying a semiconductor memory device for parallel generation of partial coefficients and correctors according to an exemplary embodiment of the present invention to a mobile system; and

[0025] Figure 15 This is a block diagram illustrating an example of applying a semiconductor memory device for parallel generation of partial coefficients and correctors according to an exemplary embodiment of the present invention to a computing system. Detailed Implementation

[0026] In the following sections, various embodiments of the invention are disclosed with reference to the accompanying drawings.

[0027] Figure 1 This is a block diagram illustrating an error correction device according to an exemplary embodiment of the present disclosure.

[0028] refer to Figure 1 The error correction device 100-1 may include a corrector generation circuit 200, a partial coefficient generation circuit 300-1, an error location polynomial generation circuit 400-2, an error location determination circuit 500, an error correction circuit 600, and a data buffer 700.

[0029] Error correction device 100-1 can receive a data polynomial R(x) and correct errors in the data polynomial R(x). Error correction device 100-1 can output a corrected data polynomial C(x) in which errors have been corrected. The data polynomial R(x) can be source data configured to perform error correction functions in error correction device 100-1. For example, the data polynomial R(x) can correspond to a vector representation of read data RData[0:63] and parity bits ECCP[0:7], which will be referred to later. Figure 10 Describe it.

[0030] The data buffer 700 can temporarily store the received data polynomial R(x) and provide the data polynomial R(x) to the error correction circuit 600.

[0031] The corrector generation circuit 200 can receive a data polynomial R(x) and generate a corrector polynomial S(x). The corrector polynomial S(x) can be a polynomial indicating whether an error exists in the data polynomial R(x). When the corrector polynomial S(x) is 0, there may be no error in the data polynomial R(x). When the corrector polynomial S(x) is not 0, there may be an error in the data polynomial R(x).

[0032] When the corrector polynomial S(x) is 0, the data polynomial R(x) temporarily stored in the data buffer 700 can be output to the outside of the error correction device 100-1 without additional error correction.

[0033] When the calibrator polynomial S(x) is not 0, the calibrator polynomial S(x) can be sent to the error position polynomial generation circuit 400-2.

[0034] Partial coefficient generation circuit 300-1 can generate partial coefficient information, Partial_Coef_info, related to a portion of the coefficients of the error location polynomial. This Partial_Coef_info can be sent to error location polynomial generation circuit 400-2. Partial coefficient generation circuit 300-1 generates the Partial_Coef_info in parallel with the corrector generation circuit 200, which generates the corrector polynomial S(x), thereby reducing the latency required to correct errors in the data polynomial R(x).

[0035] The error location polynomial generation circuit 400-2 can generate an error location polynomial Λ(x) for searching for the location of errors in the data polynomial R(x) based on the corrector polynomial S(x) and partial coefficient information Partial_Coef_info. The error location polynomial generation circuit 400-2 can reduce the time delay required to generate the coefficients of the error location polynomial Λ(x) by using the corrector polynomial S(x) and partial coefficient information Partial_Coef_info together.

[0036] The error location polynomial generation circuit 400-2 can be referred to as the key equation solver. It can generate the error location polynomial Λ(x) using algorithms such as the Berlekamp-Massey algorithm, the successive stepwise (SBS) algorithm, the Euclidean algorithm, and a modified Euclidean algorithm. The circuit then sends the error location polynomial Λ(x) to the error location determination circuit 500.

[0037] The error location determination circuit 500 can calculate the error location based on the error location polynomial Λ(x) and generate an error polynomial E(x) based on the calculation result. The error location determination circuit 500 can send the generated error polynomial E(x) to the error correction circuit 600.

[0038] The error correction circuit 600 can correct errors in the data polynomial R(x) received from the data buffer 700 based on the error polynomial E(x), and output the error-corrected data polynomial C(x).

[0039] Figure 2 This is a flowchart illustrating an error correction method according to an exemplary embodiment of the present disclosure.

[0040] refer to Figure 2 In operation S201, data can be read from the storage cell array. This data may include information data and parity data. The parity data may be used to correct the information data.

[0041] In operation S203, the corrector generation circuit 200 can generate multiple correctors for the read data. A corrector can be data indicating whether an error exists in the data. If the corrector is 0, there may be no error in the data. If the corrector is not 0, there may be an error in the data.

[0042] In operation S205, the partial coefficient generation circuit 300-1 can generate partial coefficient information in parallel with the generation of multiple correctors using the read data. This partial coefficient information relates to a portion of the coefficients of the error position polynomial. The error position polynomial can be a polynomial with the error position in the read data as a root or the reciprocal of a root. The partial coefficient information can be information related to the coefficients of the error position polynomial, including nonlinear operations. The partial coefficient information can also be information related to the coefficients of the error position polynomial, including the power value of any corrector. The partial coefficient information can be generated by performing the first summation operation in a double summation operation used to calculate the power value of the corrector.

[0043] In operation S207, the error location polynomial generation circuit 400-2 can determine the error location polynomial based on the corrector and partial coefficient information, and the error location determination circuit 500 can obtain the error location. The error location can be obtained by taking the reciprocal of the roots of the error location polynomial.

[0044] In operation S209, the error correction circuit 600 can correct errors by flipping the bit corresponding to the error position in the data.

[0045] Figure 3This is a diagram illustrating the delay for error correction according to an exemplary embodiment of the present disclosure.

[0046] refer to Figure 3 In the image (a), the corrector generation circuit 200 can generate multiple correctors for the data during the corrector generation time Ts. The error location polynomial generation circuit 400-1 can receive multiple correctors from the corrector generation circuit 200 and generate the coefficients of the error location polynomial during the coefficient generation time 1Tc1.

[0047] refer to Figure 3 In image (b), the partial coefficient generation circuit 300-1 can generate partial coefficients for a portion of the coefficients of the polynomial at the error location during the partial coefficient generation time Tp. The partial coefficient generation time Tp can overlap with the corrector generation time Ts. For example, the partial coefficient generation circuit 300-1 can generate partial coefficients in parallel with the corrector generation operation of the corrector generation circuit 200. Although the corrector generation time Ts is described as longer than the partial coefficient generation time Tp, the partial coefficient generation time Tp can increase depending on whether the partial coefficient generation circuit 300-1 generates a portion of the coefficients of the polynomial at the error location. In other words, in some example embodiments, the partial coefficient generation time Tp can be longer than the corrector generation time Ts.

[0048] The error location polynomial generation circuit 400-2 can generate the coefficients of the error location polynomial during the coefficient generation time 2Tc2. Because some coefficients of the error location polynomial have already been generated, the time delay required to generate the coefficients of the error location polynomial can be reduced. For example, the coefficient generation time 2Tc2 can be shorter than the coefficient generation time 1Tc1. As a result, when partial coefficients and the corrector are generated in parallel, the time delay required for error correction can be reduced.

[0049] Figure 4 This is a diagram used to illustrate the corrector generation circuit.

[0050] refer to Figure 4 The calibrator generation circuit 200 may include the 0th calibrator generation circuit 210 to the (2t-1)th calibrator generation circuit 230.

[0051] The corrector generation circuit 200 can receive a data polynomial R(x) and generate a corrector polynomial S(x). When the received vector is [r0 r1 r2 ... r...], the corrector generation circuit can generate a corrector polynomial S(x). N-1 When the data polynomial R(x) is expressed as [Equation 1], the corrector S, which serves as the coefficient of the corrector polynomial S(x), is... k It can be represented as [Equation 2], and the corrector polynomial S(x) can be represented as [Equation 3].

[0052] Equation 1

[0053]

[0054] Here, N can be the number of bits in the received vector.

[0055] Equation 2

[0056]

[0057] Here, α can be a primitive element of the Galois field. For example, α can be a Galois field GF(2). 3 The primitive element of GF((2)). Galois domain GF((2) 3 )={0,1,α 1 , ..., α 6 For example, GF(2) 3 ) can include 2 3 Each element.

[0058] Equation 3

[0059]

[0060] Here, t can be the number of error correction bits available for the error correction device.

[0061] The 0th corrector generation circuit 210 can generate the 0th corrector S0. The 1st corrector generation circuit 220 can generate the first corrector S1. The (2t-1)th corrector generation circuit 230 can generate the (2t-1)th corrector S... 2t-1 The caliper generation circuit 200 can generate the 0th caliper S0 to the (2t-1)th caliper S in parallel. 2t-1 .

[0062] The 0th corrector generation circuit 210 to the (2t-1)th corrector generation circuit 230 may each include an AND operation unit 240, an XOR operation unit 250, and a shift register 260. The AND operation unit 240 may be a Galois multiplier that performs an AND operation on the elements of the received vector and the elements of the Galois field. The XOR operation unit 250 may perform an XOR operation on the AND value and the next element of the received vector. The shift register 260 may shift the value received from the XOR operation unit 250 and temporarily store the shifted value.

[0063] Figure 5 This is a diagram used to describe the error correction polynomial generation circuit.

[0064] refer to Figure 5When the number of error bits in the received vector is 2 or greater, the error position polynomial generation circuit 400-1 can use the first corrector S1 and the third corrector S3 to generate the error position polynomial. Specifically, when the received vector has 2 or more error bits, the error correction polynomial Λ(x) can be expressed as [Equation 4].

[0065] Equation 4

[0066] Λ(x)=Λ2x 2 +Λ1x+Λ0=(S1 3 +S3)x 2 +S1 2 x+S1

[0067] The constant term Λ0 of the error correction polynomial Λ(x) is the first corrector S1; the coefficient Λ1 of the first-order term is S1. 2 It is the square of the first corrector; and the coefficient Λ2 of the second-order term is S1 as the cube of the first corrector. 3 The sum of the third corrector S3.

[0068] The error location polynomial generation circuit 400-1 may include a second power operation unit 401 and a third power operation unit 402. The second power operation unit 401 may include an AND gate and an XOR gate to receive the first corrector S1 and calculate S1. 2 The third power operation unit 402 may include AND gates and XOR gates to receive the first corrector S1 and calculate S1. 3 .

[0069] When generating the error position polynomial Λ(x), a large time delay may be required to compute the power of the corrector. For example, S1 3 This can be represented as Equation 5.

[0070] Equation 5

[0071]

[0072] Here, Part of it involves double summation, and the time required to perform double summation may account for a large portion of the time required to generate the erroneous position polynomial Λ(x).

[0073] Therefore, the error correction device according to this disclosure performs a portion of the double summation operation for calculating the power of the corrector in parallel with the corrector calculation, thereby reducing the time delay required to generate the error position polynomial Λ(x). In this disclosure, a portion of the double summation operation may be a partial coefficient.

[0074] The error correction device according to this disclosure can perform dual summation operations in parallel with the compensator calculation. Operations. For example, by generating in parallel with the comparator based on the received vector [r0 r1 r2...r N-1 Calculate the coefficients as part of the calculation. This can reduce the time required to calculate the power of the corrector.

[0075] Figure 6 This is a diagram illustrating a partial coefficient generation circuit according to an exemplary embodiment of the present disclosure.

[0076] refer to Figure 6 The partial coefficient generation circuit 300-1 can receive the received vector [r0 r1r2...r N-1 And generate partial coefficient information Partial_Coef_info. The partial coefficient generation circuit 300-1 may include performing operations based on the value of index i. A multi-part summation circuit. For example, the 0th part summation circuit 301-1 can perform the summation when i is 0. The operation, and the summation circuit 301-2 of part (N-2), can perform the operation when i is N-2. Operation. The partial coefficient generation circuit 300-1 can generate partial coefficient information (Partial_Coef_info) by summing all the outputs of multiple partial summing circuits.

[0077] Figure 7 This is a diagram illustrating an error correction device according to another exemplary embodiment of the present disclosure.

[0078] refer to Figure 7 The error correction device 100-2 may include a corrector generation circuit 200, a partial coefficient generation circuit 300-2, an error location polynomial generation circuit 400-2, an error location determination circuit 500, an error correction circuit 600, and a data buffer 700. (Already referenced) Figure 1 The error location polynomial generation circuit 400-2, the error location determination circuit 500, the error correction circuit 600, and the data buffer 700 are described, so their descriptions will be omitted.

[0079] The partial coefficient generation circuit 300-2 can receive the correction term S_term from the correction generation circuit 200. The correction term S_term can be obtained when calculating the correction S... k The terms required for the summation operation. Specifically, refer to [Equation 2], the correction term S_term can be r i α ik Here, i can be from 0 to N-1, and k can be from 0 to 2t-1. N is the length of the received vector, and t can be the number of bits that can be corrected.

[0080] The corrector generation circuit 200 can store the corrector term S_term in the data register 260 during the corrector generation process. The corrector generation circuit 200 can also send the corrector term S_term to the partial coefficient generation circuit 300-2 while generating the corrector polynomial. The partial coefficient generation circuit 300-2 can use the corrector term S_term to generate partial coefficient information Partial_Coef_info.

[0081] The size of the partial coefficient generation circuit 300-2 can be reduced by using the correction term S_term generated by the correction term generation circuit 200 to generate the partial coefficient information Partial_Coef_info.

[0082] Figure 8 This is a diagram illustrating a partial coefficient generation circuit according to another exemplary embodiment of the present disclosure.

[0083] refer to Figure 8 The partial coefficient generation circuit 300-2 can receive the correction term S_term from the correction term generation circuit 200 and generate partial coefficient information Partial_Coef_info.

[0084] and Figure 6 Unlike the partial coefficient generation circuit 300-1, the partial coefficient generation circuit 300-2 may include multiple partial summation circuits, which perform calculations based on the value of index i. Operations. For example, since the operation of iteratively summing the correction terms is performed, the correction terms received from the correction term generation circuit 200 can be used to generate partial coefficient information Partial_Coef_info. The partial summing circuit 302-1 can perform the operation when i is 0. The operation is performed, and the summing circuit 302-2 in the (N-2)th part can be executed when i is N-2. The partial coefficient generation circuit 300-2 generates partial coefficient information (Partial_Coef_info) by summing all the outputs of multiple partial summing circuits.

[0085] Partial coefficient information (Partial_Coef_info) is generated by using the correction term S_term generated by the correction term generation circuit 200. The size of the partial coefficient generation circuit 300-2 can be smaller than [the size of the circuit]. Figure 6 The partial coefficient generation circuit is 300-1 in size.

[0086] Specifically, in Figure 6In the partial coefficient generation circuit 300-1, among the multiple partial summing circuits, the 0th partial summing circuit 301-1 performs XOR and AND operations N times, and the (N-2)th partial summing circuit 301-2 performs XOR and AND operations once. Therefore, the multiple partial summing circuits perform all N(N+1) operations.

[0087] In comparison, Figure 8 In the partial coefficient generation circuit 300-2, among the multiple partial summing circuits, the 0th partial summing circuit 302-1 performs N XOR operations, and the (N-2)th partial summing circuit 301-2 performs one XOR operation. Therefore, the multiple partial summing circuits perform all... This operation is performed once. Therefore, the size of the partial coefficient generation circuit 300-2 can be less than [the required number of operations]. Figure 6 The partial coefficient generation circuit is 300-1 in size.

[0088] Figure 9 This is a diagram illustrating an error-correcting polynomial generation circuit according to an exemplary embodiment of the present disclosure.

[0089] refer to Figure 9 The error position polynomial generation circuit 400-2 can receive the corrector from the corrector generation circuit 200, receive partial coefficient information Partial_Coef_info from the partial coefficient generation circuit 300-1 or 300-2, and the coefficients for generating the error correction polynomial.

[0090] The error correction polynomial generation circuit 400-2 may include a second power operation unit 401 and a third power operation unit 402-1. The second power operation unit 401 may include an AND gate and an XOR gate to receive the first corrector S1 and calculate S1. 2 The 3rd power operation unit 402-1 can use the partial coefficient information Partial_Coef_info to calculate S1. 3 .

[0091] Specifically, referring to Equation 5, the third power operation unit 402-1 can perform division as a partial coefficient. Other than the operations.

[0092] Due to the partial coefficients as part of the double summation operation Λ(x) can be pre-calculated by partial coefficient generation circuits 300-1 or 300-2, thus reducing the delay required to generate polynomials at incorrect positions.

[0093] Figure 10This is a block diagram illustrating a semiconductor memory device including an error correction code (ECC) engine that performs corrector generation and partial coefficient generation in parallel, according to an exemplary embodiment.

[0094] refer to Figure 10 The semiconductor memory device 900 may include a memory cell array 1100 and an ECC engine 1000. The memory cell array 1100 may include a general cell array 1110 and an ECC cell array 1120. The general cell array 1110 may be a memory cell array in which write data WData[0:63] is stored, while the ECC cell array 1120 may be a memory cell array in which parity bits ECCP[0:7] are stored.

[0095] The ECC engine 1000 includes an ECC encoding circuit 1010 and an ECC decoding circuit 1020. The ECC encoding circuit 1010 can generate parity bits ECCP[0:7] for write data WData[0:63] to be written to the memory cells of the ordinary cell array 1110. The parity bits ECCP[0:7] can be stored in the ECC cell array 1120.

[0096] The ECC decoding circuit 1020 can use the read data RData[0:63] read from the storage cell of the general cell array 1110 and the parity check bits ECCP[0:7] read from the ECC cell array 1120 to correct the erroneous bit data and output the error-corrected data (Data[0:63]).

[0097] The ECC decoding circuit 1020 can generate a corrector in parallel with the partial coefficients to correct errors in the read data RData[0:63]. The partial coefficients can be a portion of the coefficients of the erroneous position polynomial. The ECC decoding circuit 1020 can reduce the latency required to generate the erroneous position polynomial by generating the corrector in parallel with the partial coefficients.

[0098] Figure 11 This illustrates an exemplary embodiment. Figure 10 A diagram of the ECC encoding circuit.

[0099] refer to Figure 11The ECC encoding circuit 1010 may include a parity generator 712 that receives 64 bits of write data WData[0:63] and basic bits B[0:7], and generates parity bits ECCP[0:7] using an XOR array operation. The basic bits B[0:7] are the bits used to generate the parity bits ECCP[0:7] for the 64 bits of write data WData[0:63], and may, for example, consist of bits b′00000000. The basic bits B[0:7] may be replaced with other specific bits instead of bits b′000000000.

[0100] Figure 12 This illustrates an exemplary embodiment. Figure 10 The diagram shows the ECC decoding circuit.

[0101] refer to Figure 12 The ECC decoding circuit 1020 includes a corrector generation circuit 802, a partial coefficient generation circuit 803, an error location polynomial generation circuit 804, an error location determination circuit 806, and an error correction circuit 808. The corrector generation circuit 802 can receive 64 bits of read data RData[0:63] and 8 bits of parity check bits ECCP[0:7], and uses XOR array operations to generate corrector data S[0:7]. The read data RData[0:63] and parity check bits ECCP[0:7] can be vector representations of the data polynomial R(x). The corrector data S[0:7] can be a vector representation of the corrector polynomial S(x). The partial coefficient generation circuit 803 can receive the read data RData[0:63] and parity check bits ECCP[0:7], and uses XOR and AND operations to generate partial coefficient information Partial_Coef_info. The error location polynomial generation circuit 804 can use the correction sub-data S[0:7] and partial coefficient information Partial_Coef_info to calculate the coefficients of the error location equation. The error location equation is an equation that uses the reciprocal of the erroneous bit as its root. The error location determination circuit 806 can calculate the location of the bit error by using the calculated error location equation. The error correction circuit 808 can receive 64-bit read data RData[0:63], correct the error by inverting the logical values ​​of the erroneous bits in the 64-bit read data RData[0:63] according to the bit error location information, and output the error-corrected 64-bit data Data[0:63]. The 64-bit data Data[0:63] can be a vector representation of the correction data polynomial C(x).

[0102] Figure 13 This is a diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present invention.

[0103] refer to Figure 13 The semiconductor memory device 900 may include control logic 910, refresh address generator 915, address buffer 920, memory bank control logic 930, row address multiplexer 940, column address (CA) latch 950, row decoder, memory cell array, column decoder, sense amplifier, input / output (I / O) gating circuit 990, data input / output (I / O) buffer 995, and ECC engine 1000.

[0104] The memory cell array may include first memory cell arrays to fourth memory cell arrays 980a, 980b, 980c, and 980d. The row decoder may include first memory cell row decoders to fourth memory cell row decoders 960a, 960b, 960c, and 960d, respectively, connected to the first memory cell arrays to fourth memory cell arrays 980a, 980b, 980c, and 980d. The column decoder may include first memory cell column decoders to fourth memory cell column decoders 970a, 970b, 970c, and 970d, respectively, connected to the first memory cell arrays to fourth memory cell arrays 980a, 980b, 980c, and 980d. The sense amplifier may include first memory cell sense amplifiers to fourth memory cell sense amplifiers 985a, 985b, 985c, and 985d, respectively, connected to the first memory cell arrays to fourth memory cell arrays 980a, 980b, 980c, and 980d. The first to fourth memory arrays 980a, 980b, 980c and 980d, the first to fourth memory row decoders 960a, 960b, 960c and 960d, the first to fourth memory column decoders 970a, 970b, 970c and 970d, and the first to fourth memory read amplifiers 985a, 985b, 985c and 985d can respectively constitute the first to fourth memory arrays. Figure 9 An example of a semiconductor memory device 900 including four memory cells is shown; however, according to embodiments, the semiconductor memory device 900 may include any number of memory cells.

[0105] Additionally, according to the example embodiment, the semiconductor memory device 900 may be a dynamic random access memory, such as double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, Rambus dynamic random access memory (RDRAM), etc., or may be any volatile memory device that requires refresh operations.

[0106] Control logic 910 can control the operation of semiconductor memory device 900. For example, control logic 910 can generate control signals to cause semiconductor memory device 900 to perform write or read operations. Control logic 910 may include: a command decoder 911 for decoding commands CMD received from the memory controller; and a mode register 912 for setting the operating mode of semiconductor memory device 900. For example, command decoder 911 can decode write enable signals ( / WE), row address strobe signals ( / RAS), column address strobe signals ( / CAS), chip select signals ( / CS), etc., to generate control signals corresponding to commands CMD.

[0107] The control logic 910 can also receive a clock signal (CLK) and a clock enable signal (CKE) for synchronously driving the semiconductor memory device 900. The control logic 910 can control the refresh address generator 915 to perform an automatic refresh operation in response to a refresh command, or control the refresh address generator 915 to perform a self-refresh operation in response to a self-refresh entry command.

[0108] The refresh address generator 915 can generate a refresh address REF_ADDR corresponding to the row of memory cells to be refreshed. Therefore, the refresh current and refresh power of the semiconductor memory device 900 can be reduced.

[0109] Address buffer 920 can receive address ADDR, including bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from the memory controller. Furthermore, address buffer 920 can provide the received bank address BANK_ADDR to the bank control logic 930, the received row address ROW_ADDR to the row address multiplexer 940, and the received column address COL_ADDR to the column address latch 950.

[0110] The memory bank control logic 930 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. In response to the memory bank control signal, the memory bank row decoders corresponding to the memory bank address BANK_ADDR in the first to fourth memory bank row decoders 960a, 960b, 960c and 960d can be activated, and the memory bank column decoders corresponding to the memory bank address BANK_ADDR in the first to fourth memory bank column decoders 970a, 970b, 970c and 970d can be activated.

[0111] The memory bank control logic 930 can generate a memory bank group control signal in response to determining the memory bank address BANK_ADDR of the memory bank group. In response to the memory bank group control signal, the row decoders of the memory bank groups corresponding to the memory bank address BANK_ADDR in the first to fourth memory bank row decoders 960a, 960b, 960c, and 960d can be activated, and the column decoders of the memory bank groups corresponding to the memory bank address BANK_ADDR in the first to fourth memory bank column decoders 970a, 970b, 970c, and 970d can also be activated.

[0112] The row address multiplexer 940 can receive the row address ROW_ADDR from the address buffer 920 and the refresh row address REF_ADDR from the refresh address generator 915. The row address multiplexer 940 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR. The row address output from the row address multiplexer 940 can be applied to the first memory bank row decoders to the fourth memory bank row decoders 960a, 960b, 960c, and 960d, respectively.

[0113] The bank row decoders activated by the bank control logic 930 in the first to fourth bank row decoders 960a, 960b, 960c, and 960d can decode the row address output from the row address multiplexer 940 to activate the word line corresponding to that row address. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address.

[0114] Column address latch 950 can receive column address COL_ADDR from address buffer 920 and can temporarily store the received column address COL_ADDR. Column address latch 950 can gradually increment the column address COL_ADDR received in burst mode. Column address latch 950 can apply the temporarily stored or gradually incremented column address COL_ADDR to column decoders 970a, 970b, 970c and 970d of the first to fourth memory banks, respectively.

[0115] In the first to fourth bank column decoders 970a, 970b, 970c and 970d, the bank column decoder activated by the bank control logic 930 can activate the sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output gating circuit 990.

[0116] In addition to circuitry for selecting input and output data, the input / output gating circuit 990 may also include input data mask logic, a read data latch for storing data output from the first memory array to the fourth memory arrays 980a, 980b, 980c and 980d, and a write driver for writing data to the first memory array to the fourth memory arrays 980a, 980b, 980c and 980d.

[0117] Data read from one of the first to fourth memory arrays 980a, 980b, 980c, and 980d can be sensed and amplified by a sense amplifier and stored in a read data latch. The data DQ stored in the read data latch can be provided to the memory controller via a data input / output buffer 995. Data DQ to be written to one of the first to fourth memory arrays 980a, 980b, 980c, and 980d can be provided from the memory controller to the data input / output buffer 995. The data DQ provided to the data input / output buffer 995 can be written to a memory array via a write driver.

[0118] Figure 14 This is a block diagram illustrating an example of applying a semiconductor memory device that generates partial coefficients and correctors in parallel according to an exemplary embodiment of the present invention to a mobile system.

[0119] refer to Figure 14 The mobile system 1400 includes an application processor 1410, a connection unit 1420, a first storage device 1430, a second storage device 1440, a user interface 1450, and a power supply 1460 interconnected via a bus 1402. The first storage device 1430 may be configured as a volatile memory (VM) device, and the second storage device 1440 may be configured as a non-volatile memory (NVM) device. According to embodiments, the mobile system 1400 can be any mobile system, such as a mobile phone, smartphone, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, music player, portable game console, navigation system, etc.

[0120] Application processor 1410 can execute applications that provide internet browsing, games, videos, etc. According to embodiments, application processor 1410 may include one processor core (single-core) or may include multiple processor cores (multi-core). For example, application processor 1410 may include dual-core, quad-core, or hexa-core processors. Furthermore, according to embodiments, application processor 1410 may also include internal or external cache memory.

[0121] The connection unit 1420 can perform wireless or wired communication with external devices. For example, the connection unit 1420 can perform Ethernet communication, Near Field Communication (NFC), Radio Frequency Identification (RFID) communication, mobile telecommunications, memory card communication, Universal Serial Bus (USB) communication, etc. For example, the connection unit 1420 may include a baseband chipset and can support the following communications: for example, Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Wideband Code Division Multiple Access (WCDMA), High-Speed ​​Packet Access (HSPA), etc.

[0122] The first memory device 1430, as a volatile memory device, can store data processed by the application processor 1410 or can be used as working memory. The first memory device 1430 may include: a memory cell array comprising multiple memory cells; and an ECC engine for performing ECC operations on data read from the memory cells. The ECC engine may include partial coefficient generation circuitry for generating partial coefficient information related to a portion of the coefficients of the error location polynomial in parallel while generating multiple correctors for the read data. The first memory device 1430 can reduce the latency required to generate the error correction polynomial by generating partial coefficients and correctors in parallel.

[0123] The first storage device 1430 can output an error signal, enabling the mobile system 1400 to identify errors that occur during installation and use within the mobile system 1400. Therefore, considering the number of error signals and ECC operations, the mobile system 1400 can replace the first storage device 1430 when it is determined that the first storage device 1430 is unsuitable for mobile system operation. Thus, the mobile system 1400 can replace the first storage device 1430 before a system failure is caused by it, thereby ensuring stable system operation.

[0124] The second storage device 1440, as a non-volatile storage device, can store a boot image for booting the mobile system 1400. For example, the second storage device 1440 can be implemented using electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), or similar memory.

[0125] User interface 1450 may include one or more input devices (e.g., a keypad or touchscreen) and / or one or more output devices (e.g., speakers and display devices). Power supply 1460 may supply operating voltage. Furthermore, according to embodiments, mobile system 1400 may also include a camera image processor (CIP) and may also include storage devices such as memory cards, solid-state drives (SSDs), hard disk drives (HDDs), and CD-ROMs.

[0126] Figure 15 This is a block diagram illustrating an example of applying a semiconductor memory device for parallel generation of partial coefficients and correctors according to an exemplary embodiment of the present invention to a computing system.

[0127] refer to Figure 15 The computing system 1500 includes a processor 1510, an input / output hub 1520, an input / output controller hub 1530, a memory module 1540, and a graphics card 1550. According to embodiments, the computing system 1500 can be any computing system, such as a personal computer (PC), server computer, workstation, laptop computer, mobile phone, smartphone, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, digital television, set-top box, music player, portable game console, navigation system, etc.

[0128] Processor 1510 can perform various computing functions, such as specific calculations or tasks. For example, processor 1510 can be a microprocessor or a central processing unit (CPU). According to embodiments, processor 1510 may include one processor core (single-core) or may include multiple processor cores (multi-core). For example, processor 1510 may include dual-core, quad-core, hexa-core, etc. Additionally, although... Figure 15 A computing system 1500 including a processor 1510 is shown, but according to an embodiment, the computing system 1500 may include multiple processors. Furthermore, according to an embodiment, the processor 1510 may also include internal or external cache memory.

[0129] Processor 1510 may include memory controller 1500 for controlling the operation of memory module 1540. Memory controller 1511 in processor 1510 may be referred to as an integrated memory controller (IMC). According to an embodiment, memory controller 1511 may be in input / output hub 1520. Input / output hub 1520 including memory controller 1511 may be referred to as a memory controller hub (MCH).

[0130] The memory module 1540 may include: a memory cell array including multiple memory cells; an ECC engine that performs ECC operations on the memory cells and outputs an error address corresponding to the error bits corrected by the ECC operations; and an error notification unit that compares the error address with existing bad cell information and outputs an error signal when the error address does not match the existing bad cell information.

[0131] Memory module 1540 may include: a memory cell array comprising multiple memory cells; and an ECC engine for performing ECC operations on the memory cells. The ECC engine may include partial coefficient generation circuitry for generating partial coefficient information related to a portion of the coefficients of the error location polynomial in parallel while generating multiple correctors for read data. Memory module 1540 can reduce the latency required to generate the error correction polynomial by generating partial coefficients and correctors in parallel.

[0132] The memory module 1540 can output error signals, allowing the computing system 1500 to identify errors that occur during installation and use. Therefore, considering the number of error signals and ECC operations, the computing system 1500 can replace the memory module 1540 when it is determined that the memory module 1540 is unsuitable for system operation. Thus, the computing system 1500 can replace the memory module 1540 before system failures caused by it occur, thereby ensuring stable system operation.

[0133] The input / output hub 1520 can manage data transfer between devices such as the graphics card 1550 and the processor 1510. The input / output hub 1520 can be connected to the processor 1510 through various types of interfaces. For example, the input / output hub 1520 and the processor 1510 can be connected to each other through various standard interfaces, such as Front Side Bus (FSB), System Bus, HyperTransport, Lighting Data Transfer (LDT), QuickPath Interconnect (QPI), Universal System Interface, Peripheral Component Interface - Express (PCIe), etc. Although in Figure 15 The diagram shows a computing system 1500 including an input / output hub 1520, but according to an embodiment, the computing system 1500 may include multiple input / output hubs.

[0134] The input / output hub 1520 can provide various interfaces for connecting to devices. For example, the input / output hub 1520 can provide an Accelerated Graphics Port (AGP) interface, a PCIe interface, a Communication Streaming Architecture (CSA) interface, etc.

[0135] Graphics card 1550 can be connected to input / output hub 1520 via AGP or PCIe. Graphics card 1550 can control a display device (not shown) for displaying images. Graphics card 1550 may include an internal processor for processing image data and internal semiconductor memory devices. According to an embodiment, input / output hub 1520 may include a graphics device located inside input / output hub 1520 and a graphics card 1550 located outside input / output hub 1520, or may include the graphics device as an alternative to graphics card 1550. The graphics device in input / output hub 1520 may be referred to as integrated graphics. Furthermore, input / output hub 1520, which includes a memory controller and a graphics device, may be referred to as a graphics and memory controller hub (GMCH).

[0136] The input / output controller hub 1530 can perform data buffering and interface arbitration, enabling efficient operation of various system interfaces. The input / output controller hub 1530 can be connected to the input / output hub 1520 via an internal bus. For example, the input / output hub 1520 and the input / output controller hub 1530 can be connected via a Direct Media Interface (DMI), hub interface, Enterprise Southbridge Interface (ESI), PCIe interface, etc.

[0137] The input / output controller hub 1530 can provide various interfaces for connecting to peripheral devices. For example, the input / output controller hub 1530 can provide a Universal Serial Bus (USB) port, a Serial Advanced Technology Attachment (ATA) port, a General Purpose Input / Output (GPIO) port, a Low Pin Count (LPC) bus, a Serial Peripheral Interface (SPI), PCI, PCIe, etc.

[0138] According to an embodiment, two or more components of the processor 1510, the input / output hub 1520, or the input / output controller hub 1530 may be implemented as a single chipset.

[0139] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An error correction device, comprising: A corrector generation circuit is configured to receive data and generate multiple correctors for the data; A partial coefficient generation circuit is configured to receive the data and, while the corrector generation circuit generates the plurality of correctors, generate partial coefficient information relating to a portion of the first coefficient among the coefficients of the polynomial at the error location by using the data; An error location polynomial generation circuit is configured to receive the partial coefficient information and the plurality of correctors, determine a first coefficient based on the partial coefficient information and the plurality of correctors, determine a second coefficient among the coefficients of the error location polynomial other than the first coefficient based on the plurality of correctors, and generate the error location polynomial based on the first coefficient, the second coefficient, and the plurality of correctors. An error location determination circuit is configured to obtain the location of an error in the data by using the error location polynomial; as well as An error correction circuit is configured to correct the error in the data based on the location of the error.

2. The error correction device according to claim 1, wherein, The partial coefficient generation circuit generates information related to the first coefficient, including nonlinear operations, among the coefficients of the error position polynomial while the plurality of correctors are being generated, as the partial coefficient information.

3. The error correction device according to claim 2, wherein, The partial coefficient generation circuit generates information related to the first coefficient, including the power value of the target corrector, among the coefficients of the polynomial at the error position, as the partial coefficient information while the plurality of correctors are being generated.

4. The error correction device according to claim 3, wherein, The partial coefficient generation circuit generates the partial coefficient information by performing a first summation operation in a double summation operation for calculating the power value of the target corrector while the plurality of correctors are being generated.

5. The error correction device according to claim 4, wherein, The power value of the target corrector is calculated by performing the second summation operation in the double summation operation using the partial coefficient information.

6. The error correction device according to claim 1, wherein, The partial coefficient generation circuit generates the partial coefficient information by using the already generated correction items among the multiple correction items within the target correction item while the multiple correction items are being generated.

7. The error correction device according to claim 6, wherein, The corrector generation circuit sends the generated corrector item from among the multiple corrector items in the target corrector to the partial coefficient generation circuit, wherein the target corrector is a corrector among the multiple correctors.

8. An error correction method, comprising: Read data from the storage cell array; Multiple correctors are generated for the data; While generating the plurality of correctors, the data is used to generate partial coefficient information relating to a portion of the first coefficient among the coefficients of the error location polynomial; The first coefficient is determined based on the partial coefficient information and the plurality of correctors; The second coefficient, in addition to the first coefficient, is determined based on the coefficients of the polynomial at the error location. The error location polynomial is generated based on the first coefficient, the second coefficient, and the plurality of correctors; The location of the error in the data is obtained by using the error location polynomial; as well as The error in the data is corrected based on its location.

9. The error correction method according to claim 8, wherein, While generating the plurality of correctors, using the data to generate partial coefficient information related to a portion of the first coefficients of the error position polynomial includes: Information relating to the first coefficient, including nonlinear operations, among the coefficients of the polynomial at the error location is generated as the partial coefficient information.

10. The error correction method according to claim 9, wherein, The partial coefficient information is information related to the first coefficient, including the power value of the target corrector, among the coefficients of the error position polynomial.

11. The error correction method according to claim 10, wherein, The partial coefficient information is generated by the first summation operation in a double summation operation used to calculate the power value of the target corrector.

12. The error correction method according to claim 11, wherein, The power value of the target corrector is calculated by performing the second summation operation in the double summation operation using the partial coefficient information.

13. The error correction method according to claim 8, wherein, While generating the plurality of correctors, using the data to generate partial coefficient information related to a portion of the first coefficients of the error position polynomial includes: While generating the plurality of correctors, the partially generated corrector items among the plurality of corrector items within the target corrector are used to generate the partial coefficient information.

14. A volatile storage device, comprising: A storage cell array, comprising multiple storage cells; as well as An error correction engine is configured to correct data read from the storage cell array. The error correction engine includes: A corrector generation circuit is configured to generate multiple correctors using data read from the memory cell array; A partial coefficient generation circuit is configured to generate partial coefficient information related to a portion of the first coefficient among the coefficients of the coefficients of the error position polynomial by using the data while the correction generation circuit generates the plurality of corrections. An error location polynomial generation circuit is configured to receive the partial coefficient information and the plurality of correctors, determine a first coefficient based on the partial coefficient information and the plurality of correctors, determine a second coefficient among the coefficients of the error location polynomial other than the first coefficient based on the plurality of correctors, and generate the error location polynomial based on the first coefficient, the second coefficient, and the plurality of correctors. An error location determination circuit is configured to obtain the location of an error in the data using the error location polynomial; and An error correction circuit is configured to correct the error in the data based on the location of the error.

15. The volatile storage device according to claim 14, wherein, The partial coefficient generation circuit generates information related to the first coefficient, including nonlinear operations, among the coefficients of the error position polynomial while the plurality of correctors are being generated, as the partial coefficient information.

16. The volatile storage device according to claim 15, wherein, The partial coefficient generation circuit generates information related to the first coefficient, including the power value of the target corrector, among the coefficients of the polynomial at the error position, as the partial coefficient information while the plurality of correctors are being generated.

17. The volatile storage device according to claim 16, wherein, The partial coefficient generation circuit generates the partial coefficient information by performing a first summation operation in a double summation operation for calculating the power value of the target corrector while the plurality of correctors are being generated.

18. The volatile storage device according to claim 17, wherein, The power value of the target corrector is calculated by performing the second summation operation in the double summation operation using the partial coefficient information.

19. The volatile storage device according to claim 14, wherein, The partial coefficient generation circuit generates the partial coefficient information by using the already generated correction items among the multiple correction items within the target correction item while the multiple correction items are being generated.

20. The volatile storage device according to claim 19, wherein, The corrector generation circuit sends the generated corrector item from among the multiple corrector items in the target corrector to the partial coefficient generation circuit, wherein the target corrector is a corrector among the multiple correctors.

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