Simulation method for dual-active bridge converter
By discretizing and optimizing the admittance matrix calculation of the DAB converter, and combining Norton's equivalent method and backward Euler method, the real-time simulation problem of the DAB converter at high switching frequencies was solved, achieving efficient and reliable simulation results and shortening the development cycle.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHAANXI AVIATION ELECTRICAL
- Filing Date
- 2026-02-02
- Publication Date
- 2026-05-01
AI Technical Summary
Traditional simulation tools cannot meet the real-time requirements of DAB converters at high switching frequencies. Existing FPGA simulations suffer from problems with model accuracy and development efficiency. The binary resistor method has a large computational load, and the LC equivalent model introduces switching transient oscillation errors, leading to simulation divergence.
The DAB converter is decomposed using a discretization equivalent method, a state vector solution model is established, the inverse matrix calculation of the admittance matrix is optimized, topology discretization is performed by combining Norton equivalence and backward Euler method, the equivalent admittance of the switches is optimized, accurate switch state update logic and historical current initialization are designed, and efficient simulation is achieved by using FPGA parallel processing.
It achieves high-precision, real-time DAB converter simulation, solves the numerical oscillation problem caused by switching action, improves simulation efficiency and reliability, and shortens the development cycle.
Smart Images
Figure CN121960197A_ABST
Abstract
Description
A Simulation Method for a Dual Active Bridge Converter Technical Field
[0001] This application belongs to the field of power electronics simulation technology, and specifically relates to a simulation method for a dual active bridge converter. Background Technology
[0002] A dual active bridge (DAB) DC-DC converter is a device that consists of two H-bridges composed of multiple switching devices and a high-frequency transformer. It transmits power through the phase difference between the primary and secondary sides. It has the advantages of bidirectional energy flow, high power density and easy soft switching, and is widely used in electric vehicles, microgrids and energy storage systems.
[0003] Traditional simulation tools such as PLECS and Simulink typically have simulation step sizes on the microsecond level, which cannot meet the real-time requirements of DAB converters at high switching frequencies, especially in complex power electronic systems containing multiple DAB converters. Real-time simulation of DAB converters in such scenarios is usually required to accelerate their development and functional verification. However, the large number of power electronic devices connected to the power system poses a significant challenge to real-time electromagnetic transient simulation technology.
[0004] Existing technologies can simulate DAB converters using FPGAs, but this approach still suffers from problems such as large equivalent model errors and long development cycles in terms of model accuracy and development efficiency. Current binary resistor methods require recalculating the inverse of the node admittance matrix during switching states, resulting in high computational complexity and difficulty meeting real-time requirements. Furthermore, existing LC equivalent models introduce switching transient oscillation errors, leading to slow convergence, and their neglect of high-frequency transformer nonlinearity easily causes current waveform distortion. The accumulation of initialization errors from historical currents can also easily trigger simulation divergence. Summary of the Invention
[0005] The purpose of this application is to provide a simulation method for a dual active bridge converter to solve or mitigate at least one of the problems in the background art.
[0006] The technical solution of this application is: a simulation method for a dual active bridge converter, comprising:
[0007] Step S10: The DAB converter is split at the transformer. The front-end module, back-end module and transformer of the split DAB converter are discretized and equivalent, thereby establishing the state vector solution model of the front-end module and the back-end module.
[0008] Step S20: Determine the admittance matrix of each node in the pre-stage module and the post-stage module, and calculate the inverse matrix of the admittance matrix;
[0009] Step S30: Update the state of the switch based on the PWM signal and the voltage and current of the switch branch;
[0010] Step S40: Initialize the historical current of the switch branch, and calculate the historical current of the switch branch and other components based on the state of the switch. Combine the historical current of the switch branch and the historical current of other components to form the node injection current vector.
[0011] Step S50: Based on the state vector solution model of the front-end module and the back-end module, the inverse matrix of the admittance matrix and the current vector are calculated to obtain the state vector of each node of the front-end module and the back-end module, thereby completing the simulation of the dual active bridge converter.
[0012] In at least one embodiment of this application, when the transformer is discretized and equivalent, controlled source equivalent models of the transformer's leakage inductance and magnetizing inductance, i.e., iron loss resistance, are established respectively.
[0013] In at least one embodiment of this application, in step S10, a discretization method combining Norton equivalent and backward Euler methods is used to perform equivalent transformation on the switching devices in the front-end and back-end modules. Specifically, the conduction of the switching device is considered as an equivalent inductance, and the deactivation of the switching device is considered as an equivalent capacitance. Then, a numerical integration algorithm is used to convert the equivalent inductance and equivalent capacitance into a Norton equivalent model in the form of a parallel combination of equivalent conductance and historical current terms. This specifically includes:
[0014] For inductive components:
[0015] ;
[0016] Among them, u s L is the inductor voltage. s i is the equivalent inductance of the switching device. s This refers to the current in the switch branch;
[0017] Discretization based on the backward Euler method yields:
[0018] ;
[0019] Where h is the step size, n represents the current iteration step, n+1 represents the next iteration step, and G... s For the equivalent admittance of the switch, j s Given historical currents, and satisfying the following:
[0020] ;
[0021] Similarly, discretizing the capacitor element using the backward Euler method yields:
[0022] ;
[0023] In the formula, C s The equivalent capacitance of the switch;
[0024] The discretization form of the capacitor element is similar to that of the inductor element, where:
[0025] ;
[0026] After discretization, the admittance matrix of each node in the topology contains only the intrinsic parameters of the circuit and the equivalent admittance of the switches, and is independent of the historical currents of the equivalent inductance and equivalent capacitance. To ensure that the admittance matrix is a constant matrix that does not change with the switching state, it must satisfy the following:
[0027] ;
[0028] The historical currents during switch opening and closing are:
[0029] ;
[0030] In the LC equivalent model of the DAB converter, based on the nodal voltage method, the equivalent transformer satisfies:
[0031] ;
[0032] In the formula, u sec i is the secondary voltage of the transformer. p This refers to the primary current of the transformer.
[0033] Based on the decomposition and dimensionality reduction process of the preceding module, the admittance matrix of each node in the preceding module is 7×7, and its state equation is:
[0034] (11)
[0035] Similarly, based on the decomposition and dimensionality reduction process of the subsequent modules, the admittance matrix of each node in the subsequent modules is 6×6, and its state equation is:
[0036] (12)
[0037] In the above formula, G c1 G is the equivalent admittance of the filter capacitor in the preceding circuit; c2 G is the equivalent admittance of the filter capacitor in the subsequent circuit; L G is the equivalent capacitance of a series inductor. Lm G is the equivalent admittance of the transformer's magnetizing inductance; RL G represents the equivalent admittance corresponding to the leakage inductance and resistance referred to the secondary side of the transformer. R U1 is the equivalent capacitance of the load; u1 to u6 are the node voltages of nodes 1 to 6, respectively; r is the internal resistance of the converter input voltage, and U1 is the converter input voltage.
[0038] The state variables X1 and X2 to be determined at each node of the preceding and following modules at each time step satisfy the following:
[0039] ;
[0040] In the formula, , B1 and B2 are the inverse matrices of the admittance matrices of each node in the front-end module and the back-end module, respectively, and the current vectors of each node in the front-end module and the back-end module, respectively.
[0041] In at least one embodiment of this application, the equivalent admittance of the equal switches is further optimized, the process including:
[0042] If the switch is turned on and in a steady state at the k-th simulation step, determine the energy stored in the switch:
[0043] ;
[0044] To approximate an ideal switch as closely as possible, at the k-th simulation step, the equivalent inductance L s The energy stored in the upper part becomes the equivalent capacitance C with zero energy in the next simulation step. s The historical current satisfies the following:
[0045] ;
[0046] If the switch is turned off and in a steady state at the k-th simulation step, the energy stored in the switch is:
[0047] ;
[0048] Similarly, the energy stored on the switching transistor disappears when the switching state changes, and the historical current satisfies:
[0049] ;
[0050] The total loss during the switch switching process is:
[0051] ;
[0052] The final total loss during the switch switching process is:
[0053] ;
[0054] To minimize the oscillation error during transient switching, the equivalent admittance G is... s The optimal value of the equivalent admittance of the switch is obtained by differentiation:
[0055] .
[0056] In at least one embodiment of this application, the process of updating the switch state in step S30 is as follows:
[0057] (1) Switch on logic:
[0058] ;
[0059] The switch is turned on when the nth wave emission state pwm and the switch branch voltage u_sw_old satisfy the above formula; otherwise, the switch is turned off.
[0060] (2) Diode detection logic:
[0061] ;
[0062] The logic for determining whether a diode is on or off is solely determined by the branch voltage across the diode. When the switching branch voltage u_sw_old is greater than 0, the diode is on; when the switching branch voltage is less than 0, the diode is off.
[0063] The simulation method for dual active bridge converters proposed in this application solves the problem of numerical oscillation caused by switching action, and realizes efficient and reliable closed-loop testing with the physical controller. Attached Figure Description
[0064] To more clearly illustrate the technical solutions provided in this application, the accompanying drawings will be briefly described below. Obviously, the drawings described below are merely some embodiments of this application.
[0065] Figure 1 is a schematic diagram of the simulation method of the dual active bridge converter of this application.
[0066] Figure 2 is a schematic diagram of the basic topology of the DAB converter in this application.
[0067] Figure 3 is a schematic diagram of the LC equivalent model in this application.
[0068] Figure 4 is a schematic diagram of the equivalent model of the DAB converter in this application.
[0069] Figure 5 is a schematic diagram of the DAB converter simulation system architecture of this application.
[0070] Figure 6 is a schematic diagram of the parallel computing structure of the FPGA internal dot product operation unit in this application. Detailed Implementation
[0071] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below with reference to the accompanying drawings.
[0072] This application provides a DAB converter simulation method, which solves the numerical oscillation problem caused by the operation of switching devices by constructing a high-precision, real-time DAB converter simulation model, and realizes efficient and reliable closed-loop testing with the physical controller.
[0073] As shown in Figure 1, the DAB converter simulation method provided in this application includes the following process:
[0074] Step S10: The DAB converter is split at the transformer. The front-end module, the back-end module, and the transformer of the split DAB converter are discretized and equivalent, thereby establishing the state vector solution model of the front-end module and the back-end module.
[0075] Figure 2 shows a schematic diagram of the basic topology of a DAB converter. The basic topology mainly includes a primary-side full-bridge H1 composed of four switching devices S1~S4, a secondary-side full-bridge H2 composed of switching devices S5~S8, an inductor L, and a high-frequency transformer T. The numerous power electronic devices and complex topology result in a large node matrix for the DAB converter. Therefore, this application employs a hierarchical + parallel processing mechanism in the mathematical model design of the DAB converter to reduce computational resource consumption and improve simulation speed.
[0076] As shown in Figure 2, the switching devices S1-S8 are discretized and equivalent based on LC equivalence in this application. When performing LC equivalence modeling, this application decomposes the topology of the DAB converter into three subsystems or modules: the input full-bridge, the high-frequency transformer, and the output full-bridge, and further decomposes them at the high-frequency transformer. At this point, the admittance matrix G1 of each node in the front-end module is of order 7, and the admittance matrix G2 of each node in the back-end module is of order 6, achieving dimensionality reduction of the state equation. The basic form of its state equation is shown in formula (1):
[0077] (1)
[0078] In the formula, X1 and X2 are the state variables of each node of the front-end module and the back-end module, respectively, and B1 and B2 are the current vectors injected into each node of the front-end module and the back-end module, respectively.
[0079] In this application, the equivalent process of transformer T is as follows:
[0080] The operating state of an ideal transformer can be defined as follows: (2)
[0081] Where u1 and u2 are the primary and secondary voltages, i1 and i2 are the primary and secondary currents, and m is the turns ratio.
[0082] In this application, to reduce the nonlinear effects of the high-frequency transformer, a controlled source equivalent model of leakage inductance, magnetizing inductance, and iron loss resistance is established, as shown in Figure 3, where L m Let RL be the magnetizing inductance of the transformer, and RL be the branch resistance and leakage inductance referred to the secondary side. The equivalent of the actual transformer is based on formula (1), which transmits the port voltage from the primary side to the secondary side and the branch current from the secondary side to the primary side.
[0083] Figure 3 shows a schematic diagram of the LC equivalent model of the DAB converter. This application adopts a discretization method combining Norton equivalent and backward Euler, treating the conduction of the switching device as an equivalent small inductance and the disconnection as an equivalent small capacitor. Then, it uses a numerical integration algorithm to convert it into a Norton equivalent model in the form of parallel connection of equivalent conductance and historical current term.
[0084] For inductive components:
[0085] (3)
[0086] Among them, u s L is the inductor voltage. s i is the equivalent inductance of the switching device. s This represents the current in the switch branch.
[0087] Discretization based on the backward Euler method yields:
[0088] (4)
[0089] Where h is the step size, n represents the current iteration step, n+1 represents the next iteration step, and G... s For the equivalent admittance of the switch, j s Given historical currents, and satisfying the following:
[0090] (5)
[0091] Similarly, by discretizing the capacitance characteristic equation using the backward Euler method, we can obtain:
[0092] (6)
[0093] In the formula, C s This is the equivalent capacitance of the switch.
[0094] It can be seen from formulas (5) and (6) that the discretization form of the capacitor element is similar to that of the inductor element, where:
[0095] (7)
[0096] After discretization, the admittance matrix of each node in the topology contains only the intrinsic parameters of the circuit and the equivalent admittance of the switches, and is independent of the historical currents of the equivalent inductance and equivalent capacitance. To ensure that the admittance matrix is a constant matrix that does not change with the switching state, it must satisfy the following:
[0097] (8)
[0098] The historical currents during switch opening and closing are:
[0099] (9)
[0100] In the LC equivalent model of the DAB converter, based on the nodal voltage method, the equivalent transformer satisfies:
[0101] (10)
[0102] In the formula, u sec i is the secondary voltage of the transformer. p This refers to the primary current of the transformer.
[0103] Based on the decomposition and dimensionality reduction method of the above subsystems or modules and KCL, the admittance matrix of each node of the front-end module is 7×7, and its state vector equation is:
[0104] (11)
[0105] Similarly, based on the decomposition and dimensionality reduction and KCL, the admittance matrix of each node in the subsequent module is 6×6, and its state vector equation is:
[0106] (12)
[0107] In the above formula, G c1 G is the equivalent admittance of the filter capacitor in the preceding circuit; c2 G is the equivalent admittance of the filter capacitor in the subsequent circuit; L G is the equivalent capacitance of a series inductor. Lm G is the equivalent admittance of the transformer's magnetizing inductance; RL G represents the equivalent admittance corresponding to the leakage inductance and resistance referred to the secondary side of the transformer. R U1 is the equivalent capacitance of the load; u1 to u6 are the node voltages of nodes 1 to 6, respectively; r is the internal resistance of the converter input voltage, and U1 is the converter input voltage.
[0108] According to formulas (1) and (11) to (12), the dimension of the admittance matrix of the front-end module and the back-end module is equal to the sum of the number of power electronic switches, inductors, and capacitors in the topology. In order to find the state variables X1 and X2 composed of the branch current, voltage, and phase-shifting inductor in each branch of the front-end module and the back-end module, it is necessary to invert the admittance matrix based on the historical current terms of the topology of the front-end module and the current vectors B1 and B2 of the driving signal. Since the admittance matrices G1 and G2 of each node of the front-end module and the back-end module are constant matrices, their inverse matrix values can be stored in advance after inverting them, and the state variables X1 and X2 to be found at each node of the front-end module and the back-end module at each time can be obtained according to formula (13):
[0109] (13)
[0110] In this application, in order to reduce the transient error of the switching branch, the equivalent inductance L of the switch is... s Equivalent capacitance C s It should be as small as possible to shorten the transient process. From equations (5) and (7), we can see that the switching equivalent admittance G... s With equivalent capacitance C s Proportional to, and with the equivalent inductance L s Inversely proportional, changing the equivalent admittance G s It is impossible to reduce the equivalent inductance L at the same time s Equivalent capacitance C s Therefore, the equivalent admittance G needs to be adjusted. s Optimizations were implemented to address oscillations during transient switching processes.
[0111] If the switch is turned on and in a steady state at the k-th simulation step, the energy stored in the switch is determined by formula (14):
[0112] (14)
[0113] To approximate an ideal switch as closely as possible, at the k-th simulation step, the equivalent inductance L s The energy stored in the upper part becomes the equivalent capacitance C with zero energy in the next simulation step. s Historical currents satisfy the following formula:
[0114] (15)
[0115] If the switch is turned off and in a steady state at the k-th simulation step, the energy stored in the switch is:
[0116] (16)
[0117] Similarly, the energy stored on the switching transistor disappears when the switching state changes, and the historical current satisfies:
[0118] (17)
[0119] The total loss during the switch switching process is:
[0120] (18)
[0121] Combining formulas (8) and (18), the total loss during the switching process can be obtained:
[0122] (19)
[0123] To minimize the oscillation error during transient switching, the equivalent admittance G is... s Taking the derivative, the optimal value of the switch's equivalent admittance is obtained as follows:
[0124] (20)
[0125] Step S20: Determine the admittance matrix of each node in the preceding and following modules, and calculate the inverse matrix of the admittance matrix.
[0126] Step S30: Update the state of the switch based on the PWM signal and the voltage and current of the switch branch.
[0127] When modeling the power electronic switching devices in a DAB converter, it is necessary to determine the update rules for the switching states. PWM signals directly participate in the determination of switching states, such as those of IGBTs and MOSFETs. Furthermore, the switching state is also related to branch voltage and current. In contrast, the conduction status of a diode is determined solely by the polarity of the branch voltage. The update logic is as follows:
[0128] (1) Switch conduction logic ( =1): ;(twenty one)
[0129] The switch is turned on when the nth wave emission state pwm and the switch branch voltage u_sw_old satisfy formula (21); otherwise, the switch is turned off.
[0130] (2) Diode detection logic: ;(twenty two)
[0131] The logic for determining whether a diode is turned on or off is determined solely by the branch voltage across the diode, as shown in formula (22). When the switching branch voltage u_sw_old is greater than 0, the diode is turned on; when the switching branch voltage is less than 0, the diode is turned off.
[0132] Step S40: Initialize the historical current of the switch branch, and calculate the historical current of the switch branch and other components based on the state of the switch. Combine the historical current of the switch branch and the historical current of other components to form the current vector injected by the node.
[0133] The historical current is related to the state of the switch. In this application, the historical current during switch switching is initialized by preloading the steady-state operating point. After the switch state changes, the historical current of the first simulation step is configured to the steady-state current value after the last switch state change. The historical current at other times can be calculated according to formula (9).
[0134] Step S50: Based on the state vector solution model of the front-end module and the back-end module, the inverse matrix of the admittance matrix and the current vector are calculated to obtain the state vector of each node of the front-end module and the back-end module, and the simulation of the dual active bridge converter is completed.
[0135] This application uses FPGA for DAB converter simulation calculations. Figure 5 shows a schematic diagram of the hardware-in-the-loop simulation system architecture for the DAB converter in this application. The FPGA development process is implemented in the System Generator development environment, adopting a hierarchical + parallel pipeline architecture. The state vector solution models of the front and rear modules of the DAB converter are built, and synthesizable HDL code or IP cores are directly generated. In System Generator, Gateway In is used as the input interface for external PWM signals, and Gateway Out outputs the results of the real-time simulation model. The DAB converter model is implemented as follows: the core part of its solution model is implemented through the internal dot product operation unit of the FPGA parallel structure. The solution process is as follows:
[0136] (1) First, allocate memory space in the FPGA to pre-store the inverse matrix of the calculated admittance matrix. and ;
[0137] (2) Then the state of the switch is obtained based on the 8 PWM signals, branch voltage, and branch current;
[0138] (3) After initializing the historical current of the 8 switch branches and calculating their historical current and the historical current of other components (such as inductor and capacitor branches), combine the historical current of the switch branches with the historical current of other components to generate the node injection current vector.
[0139] (4) As shown in Figure 6, according to formula (13), a 13-way multiplier is configured according to the principle of parallel operation, and the admittance inverse matrix of each node of the front-end module and the back-end module is converted into the inverse matrix. and Each row vector is multiplied by the current vectors B1 and B2 injected into each node, and the results of the multipliers in each path are accumulated to finally obtain the state vectors X1 and X2 of each node in the front-end module and the back-end module.
[0140] The dual active bridge (DAB) converter simulation method provided in this application solves the numerical oscillation problem caused by switching action through the following measures, achieving efficient and reliable closed-loop testing with the physical controller:
[0141] 1) Model dimensionality reduction and equivalence: The DAB converter system is reasonably decomposed and dimensionality reduced to reduce the complexity of the model, establish an efficient equivalent model of the transformer, and reduce the consumption of computing resources.
[0142] 2) High-precision topology discretization: A discretization strategy combining Norton equivalence and backward Euler is adopted to model the DAB converter topology, ensuring the stability of numerical calculations;
[0143] 3) Precise modeling of transient processes:
[0144] a) Switch state update logic: Design precise switch state update logic to capture switch on and off events.
[0145] b) Optimization of admittance matrix: For the instantaneous switching, the equivalent admittance of the switch is optimized based on energy loss to effectively suppress transient numerical oscillations caused by switching action and reduce transient switching error.
[0146] c) Initialization of historical current: This ensures a seamless transition of the simulation state after switching, accurately simulates the transient behavior of the DAB converter during various operating mode switching processes, and ensures that the simulation model can quickly and accurately enter a new steady-state or transient process after switching states.
[0147] 4) High-efficiency FPGA implementation: Utilizing the parallel processing capabilities of FPGAs, sub-microsecond simulation step sizes are achieved, accurately reflecting the fast dynamic characteristics of DAB converters and providing a realistic testing environment for the controller. Optimized discretization methods and transient processing techniques ensure simulation accuracy under all operating conditions. Simultaneously, the development of DAB circuit solution models and automatic code generation based on the System Generator tool significantly improves the efficiency and reliability of FPGA hardware implementation, optimizes hardware resource utilization, greatly simplifies the development, debugging, and deployment of FPGA simulation models, shortens the development cycle, and resolves the contradiction between computational efficiency and transient accuracy in hardware-in-the-loop simulation.
[0148] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A simulation method for a dual active bridge converter, characterized in that, include: Step S10: The DAB converter is split at the transformer. The front-end module, back-end module, and transformer of the split DAB converter are discretized and equivalently represented to establish the state vector solution model of the front-end module and the back-end module. Step S20: The admittance matrix of each node of the front-end module and the back-end module is determined, and the inverse matrix of the admittance matrix is calculated. Step S30: The state of the switch is updated according to the PWM signal and the voltage and current of the switch branch. Step S40: The historical current of the switch branch is initialized, and the historical current of the switch branch and other components is calculated based on the state of the switch. The historical current of the switch branch and the historical current of other components are combined to form the current vector injected by the node. Step S50: Based on the state vector solution model of the front-end module and the back-end module, the inverse matrix of the admittance matrix and the current vector are calculated to obtain the state vector of each node of the front-end module and the back-end module, thereby completing the simulation of the dual active bridge converter.
2. The simulation method for a dual active bridge converter as described in claim 1, characterized in that, When discretizing the transformer, controlled source equivalent models of the transformer's leakage inductance and magnetizing inductance, i.e., iron loss resistance, are established respectively.
3. The simulation method for a dual active bridge converter as described in claim 2, characterized in that, In step S10, a discretization method combining Norton equivalent and backward Euler methods is used to perform equivalent transformations on the switching devices in the front-end and back-end modules. Specifically, the conduction of a switching device is considered as an equivalent inductance, and the deactivation of a switching device is considered as an equivalent capacitance. Then, a numerical integration algorithm is used to transform the equivalent inductance and equivalent capacitance into a Norton equivalent model in parallel form of equivalent conductance and historical current terms. This specifically includes: for inductive elements: ; where u s L is the inductor voltage. s i is the equivalent inductance of the switching device. s The current in the switching branch is given; discretization based on the backward Euler method yields: Where h is the step size, n represents the current iteration step, n+1 represents the next iteration step, and G... s For the equivalent admittance of the switch, j s Given historical currents, and satisfying the following: Similarly, discretizing the capacitor element using the backward Euler method yields: In the formula, C s Let be the equivalent capacitance of the switch; the discrete form of the capacitor element is similar to the discretization result of the inductor element, where: After discretization, the admittance matrix of each node in the topology only contains the intrinsic parameters of the circuit and the equivalent admittance of the switches, and is independent of the historical currents of the equivalent inductance and equivalent capacitance. To ensure that the admittance matrix is a constant matrix that does not change with the switching state, it must satisfy the following: The historical current during switch opening and closing is as follows: In the LC equivalent model of the DAB converter, based on the nodal voltage method, the equivalent transformer satisfies: In the formula, u sec i is the secondary voltage of the transformer. p Let be the primary current of the transformer; based on the decomposition and dimensionality reduction process of the preceding module, the admittance matrix of each node of the preceding module is 7×7, and its state equation is: Similarly, based on the decomposition and dimensionality reduction process of the subsequent modules, the admittance matrix of each node in the subsequent modules is 6×6, and its state equation is: In the above formula, G c1 G is the equivalent admittance of the filter capacitor in the preceding circuit; c2 G is the equivalent admittance of the filter capacitor in the subsequent circuit; L G is the equivalent capacitance of a series inductor. Lm G is the equivalent admittance of the transformer's magnetizing inductance; RL G represents the equivalent admittance corresponding to the leakage inductance and resistance referred to the secondary side of the transformer. R U1 is the equivalent capacitance of the load; u1 to u6 are the node voltages from node 1 to node 6, respectively; r is the internal resistance of the converter input voltage, and U1 is the converter input voltage; the state variables X1 and X2 to be determined for each node of the preceding and following modules at each moment satisfy: In the formula, 、 B1 and B2 are the inverse matrices of the admittance matrices of each node in the front-end module and the back-end module, respectively, and the current vectors of each node in the front-end module and the back-end module, respectively.
4. The simulation method for a dual active bridge converter as described in claim 3, characterized in that, It also includes optimizing the equivalent admittance of the switch, the process of which includes: if the switch is turned on and in a steady state at the k-th simulation step, determining the energy stored in the switch: To approximate an ideal switch as closely as possible, at the k-th simulation step, the equivalent inductance L... s The energy stored in the upper part becomes the equivalent capacitance C with zero energy in the next simulation step. s The historical current satisfies the following: If the switch is turned off and in a steady state at the k-th simulation step, the energy stored in the switch is: Similarly, the energy stored on the switching transistor disappears when the switching state changes, and the historical current satisfies: The total loss during the switch switching process is: The final total loss during the switchover process is: To minimize the oscillation error during transient switching, the equivalent admittance G is... s The optimal value of the equivalent admittance of the switch is obtained by differentiation: 。 5. The simulation method for a dual active bridge converter as described in claim 4, characterized in that, The process of updating the switch state in step S30 is as follows: (1) Switch on logic: When the nth wave emission state pwm and the switch branch voltage u_sw_old satisfy the above formula, the switch is turned on; otherwise, the switch is turned off; (2) Diode judgment logic: The logic for determining whether a diode is on or off is solely determined by the branch voltage across the diode. When the switching branch voltage u_sw_old is greater than 0, the diode is on; when the switching branch voltage is less than 0, the diode is off.