Display module, test method thereof and display device

Abstract

The invention provides a display module and a testing method thereof and a display device.The display module of one embodiment comprises a display panel and a flexible circuit board electrically connected with the display panel, the display panel comprises a plurality of first pins, the flexible circuit board comprises a plurality of second pins, and the first pins and the second pins are electrically connected in a one-to-one correspondence mode; the plurality of second pins comprise a plurality of test pins which are arranged adjacently, the flexible circuit board further comprises a test network, the test network comprises a plurality of first wires and signal ports which are electrically connected with the first wires in a one-to-one correspondence mode, the signal ports are used for receiving test signals, and the adjacent test pins are electrically isolated. According to the display module provided by the embodiment of the invention, the adjacent test pins are electrically isolated, so that the display stability is improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display module and its testing method, as well as a display device. Background Technology

[0002] As the application scenarios of display products become more and more diverse, displays are gradually developing towards a trend of becoming thinner and lighter with narrower bezels. The peripheral wiring area will become narrower and narrower, and the defects in the peripheral circuit structure will be more frequent. Therefore, it is necessary to conduct relevant tests on the display array substrate during the manufacturing process to ensure the yield of the display.

[0003] Currently, after reliability testing, the display exhibits defects in the X-axis horizontal RB (red and blue) bright lines and the Y-axis vertical G (green) bright lines. Summary of the Invention

[0004] To address at least one of the aforementioned problems, a first aspect of this disclosure provides a display module, comprising: a display panel and a flexible circuit board electrically connected to the display panel.

[0005] The display panel includes multiple first pins, and the flexible circuit board includes multiple second pins. The multiple first pins and multiple second pins are electrically connected in a one-to-one correspondence. The multiple second pins include multiple test pins arranged adjacent to each other.

[0006] The flexible circuit board also includes a test network, which comprises multiple first traces and signal ports electrically connected to each of the first traces. The signal ports are used to receive or output test signals.

[0007] There is electrical isolation between adjacent test pins.

[0008] Optionally, at least one of the multiple test pins receives a high-frequency signal during testing, and / or the test signal is used to perform electrical testing on the gate drive circuit in the display panel.

[0009] Optionally, the flexible circuit board includes multiple first pads, multiple second pads, and multiple second traces, wherein the number of first pads, second pads, and second traces are all equal.

[0010] The first end of the second trace is electrically connected to the first pad, and the second end is electrically connected to the test pin.

[0011] The second pad is electrically connected to the end of the first trace that is not electrically connected to the signal port, and the first pad and the second pad are electrically isolated.

[0012] Optionally, the flexible circuit board includes a first conductive layer and a second conductive layer.

[0013] The first pad and the second pad are located on the first conductive layer, or the first pad and the second pad are located on the second conductive layer.

[0014] Optionally, the distance between the first pad and the second pad connected to the first trace and the second trace that receive the same test signal is in the range of 0.12mm-0.5mm.

[0015] Optionally, the flexible circuit board includes a main circuit board and an auxiliary circuit board.

[0016] The main circuit board and the auxiliary circuit board are electrically isolated, and

[0017] The test pins and test networks are set on the auxiliary circuit board, and the end of the first trace that is not electrically connected to the signal port is electrically connected to the corresponding test pin.

[0018] Optionally, the first pin electrically connected to the test pin is located on one side of other first pins besides the first pin electrically connected to the test pin.

[0019] Optionally, the auxiliary circuit board includes a plurality of second traces electrically connected to each of the first traces, and the auxiliary circuit board includes a plurality of conductive layers.

[0020] The first and second traces corresponding to the electrical connection are located on the same conductive layer, and adjacent first traces and / or adjacent second traces are located on different conductive layers. Optionally, the flexible circuit board includes a first region and a second region.

[0021] The first region includes a first conductive layer, a second conductive layer, and a first insulating layer located between the first conductive layer and the second conductive layer. The second region includes a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer, which are sequentially stacked.

[0022] The test network is set up in the second area, and the end of the first trace that is not electrically connected to the signal port is electrically connected to the corresponding second pin.

[0023] Optionally, the second pin is disposed on the first conductive layer, and the test network is disposed on the third conductive layer.

[0024] The second region also includes multiple vias and conductive parts disposed in the vias.

[0025] The via extends from the surface of the first insulating layer near the first conductive layer to the surface of the second insulating layer away from the first conductive layer. The test pin is electrically connected to the first trace via the conductive portion.

[0026] The flexible circuit board also includes a third trace, which is electrically connected to the other second pins except for the test pins. The orthographic projection of the via in the first insulating layer does not overlap with the orthographic projection of the third trace in the first insulating layer.

[0027] Optionally, the second region includes: a row of the vias and at least two rows of the signal ports.

[0028] The multiple vias and the signal ports in each row of signal ports are arranged in roughly the same direction.

[0029] The test network also includes a plurality of fourth traces that are electrically connected to each of the vias, and the other end of each fourth trace, which is electrically connected to an adjacent via, is electrically connected to a signal port located in a different row.

[0030] A second aspect of this disclosure provides a display device including the display module described above.

[0031] A third aspect of this disclosure provides a testing method applied to the display module described above, comprising:

[0032] Connect the first and second pads one by one, and test signals are input or output to the display panel through the signal port for testing.

[0033] Optionally, electrically connecting the first pad and the second pad in a one-to-one correspondence includes:

[0034] A zero-resistance resistor is mounted between the first and second pads.

[0035] or

[0036] Multiple windows are opened in the display module, each window exposing the first pad, the second pad, and the area between the first and second pads to be electrically connected, and

[0037] A metal layer is coated on the window.

[0038] The beneficial effects of this disclosure are as follows:

[0039] This disclosure addresses existing problems by providing a display module, its testing method, and a display device. It also provides multiple second pins that are electrically connected to a first pin in the display panel, each second pin including a test pin, with electrical isolation between adjacent test pins. This ensures that even after the test network is corroded following a resilience test, it will not affect the circuit structure in the display panel, preventing the occurrence of RB and G bright lines. Furthermore, it improves the stability of the display module under extreme environments, demonstrating broad application prospects. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This diagram illustrates the structure of a display module according to an embodiment of the present disclosure.

[0042] Figure 2 A schematic diagram showing the structure of the bonding area of ​​the display panel in a display module according to an embodiment of the present disclosure is provided.

[0043] Figure 3 and Figure 4 A partial wiring diagram is shown during a reliability test of a flexible circuit board in a display module according to an embodiment of the present disclosure.

[0044] Figure 5 A partial wiring diagram of a flexible circuit board in a display module according to another embodiment of the present disclosure is shown;

[0045] Figure 6 A schematic diagram of the structure of a display module according to another embodiment of the present disclosure is shown;

[0046] Figure 7 A schematic diagram of the structure of a display module according to another embodiment of the present disclosure is shown;

[0047] Figure 8 Show Figure 7 A partial cross-sectional schematic diagram of the embodiment shown;

[0048] Figure 9 A partial wiring diagram of a flexible circuit board in a display module according to an embodiment of the present disclosure is shown. Detailed Implementation

[0049] To more clearly illustrate this disclosure, the preferred embodiments and accompanying drawings will be used for further description. Similar components in the drawings are indicated by the same or similar reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.

[0050] It should be noted that the terms "having," "comprising," and "including" used in this disclosure are all open-ended, meaning that when a module is described as "having," "comprising," or "including" a first element, a second element, and / or a third element, it indicates that the module includes other elements besides the first, second, and / or third elements. Furthermore, the ordinal numbers "first," "second," and "third" used in this disclosure are not intended to define a specific order, but only to distinguish between the various parts. In this disclosure, when describing layer A and layer B as "co-located," it means that layer A and layer B are manufactured using the same materials and processes.

[0051] The inventors discovered that display products exhibited defects such as X-axis horizontal RB bright lines and Y-axis vertical G bright lines after undergoing the 85 / 85 signal strength test. Through a series of analyses, it was determined that in the defective display products, short circuits occurred between signal lines GCK and GND, and between signal lines NCB and NOUT, on the flexible circuit board electrically connected to the display panel. Signal lines GCK, NCB, and NOUT are all traces within the test network of the Gate Driver on Array (GOA) circuit in the display module. Specifically, signal lines GCK and NCB are clock signal lines in the GOA test network, signal line NOUT is the output signal line of the GOA test network, and signal line GND is the ground signal line. Furthermore, the signals received by these signal lines are all high-frequency signals. Among them, the abnormality of signal line GCK caused the vertical bright G line on the right side of the display panel, and signal line NCB affected signal line NOUT, causing the horizontal bright RB line. X-ray inspection revealed that the traces of signal lines GCK / GCB had varying degrees of corrosion, and other GOA signal lines also had varying degrees of corrosion and a significant risk of corrosion.

[0052] Further investigation revealed that the display panel is typically electrically connected to corresponding pins on the flexible circuit board via pins in the bonding area. The flexible circuit board contains test network traces for GOA (Gate of Arrival) testing. These traces receive external test signals and transmit the feedback signals via test pins on the flexible circuit board to the pins in the bonding area, thus feeding them into the GOA of the display panel for electrical testing. It is evident that the pins used for GOA testing include one or more groups of adjacent pins. Due to the adjacent pin arrangement, the routing of the connected test network is very tight. Not only are the signal lines GCK, NCB, and NCB in the GOA test network high-frequency signal lines, but other signal lines in the GOA test network are also high-frequency signal lines. The output waveforms of these signal lines can reach voltage differences of over 14V. During the reliability test, because the flexible circuit board operates in a high-temperature and high-humidity environment for a long time, the signal lines receive high-frequency signals with large voltage differences for a long time. As a result, the GOA test network is the most susceptible to corrosion in the entire display module. Consequently, the GOA test network in the display module after the reliability test has been corroded and short-circuited, resulting in defects such as X horizontal RB bright lines and Y vertical G bright lines.

[0053] In addition to the test network for GOA in LTPO display panels, the test networks for GOA in other types of display panels, despite the different specific signals, also have the same characteristics of adjacent pins, high-frequency signals, and large voltage differences, and therefore also have the problem of RB bright lines and G bright lines defects.

[0054] To address at least one of the above problems, embodiments of this disclosure provide a display module, including: a display panel and a flexible circuit board electrically connected to the display panel.

[0055] The display panel includes multiple first pins, and the flexible circuit board includes multiple second pins. The multiple first pins and the multiple second pins are electrically connected in a one-to-one correspondence. The multiple second pins include multiple test pins arranged adjacent to each other.

[0056] The flexible circuit board also includes a test network, which comprises multiple first traces and signal ports electrically connected to each of the first traces. The signal ports are used to receive or output test signals.

[0057] There is electrical isolation between adjacent test pins.

[0058] In this embodiment, by providing a plurality of second pins that are electrically connected one-to-one with the first pins in the display panel, the plurality of second pins include test pins and test networks, and the electrical isolation between adjacent test pins, the test network will not affect the circuit structure in the display panel after being corroded after the reliability test, thus avoiding the occurrence of RB bright lines and G bright lines, and also improving the stability of the display module in extreme environments.

[0059] The display module of this disclosure embodiment will be described in detail below with reference to specific examples.

[0060] In a specific example, refer to Figure 1 As shown, the display module includes a display panel 1 and a flexible circuit board 2 electrically connected to the display panel 1. The display panel 1 includes a plurality of first pins 11, and the flexible circuit board 2 includes a plurality of second pins 21 electrically connected to the plurality of first pins 11 in a one-to-one correspondence. The plurality of second pins 21 include a plurality of test pins 21-1 arranged adjacent to each other.

[0061] In the embodiments of this disclosure, the multiple second pins 21 including multiple adjacent test pins 21-1 means that there are adjacent test pins among the multiple second pins 21, and is not intended to limit all test pins to be adjacent. That is, the test pins in the embodiments of this disclosure include... Figure 1 The setup shown indicates that multiple test pins can exist in the second pin 21, for example... Figure 1 As shown, the first group of test pins 21-1 (black-filled rectangle) on the left and the second group of test pins 21-1 on the right are not adjacent to each other, but all test pins in the first group of test pins 21-1 are adjacent to each other and all test pins in the second group of test pins 21-1 (black-filled rectangle) are adjacent to each other.

[0062] Reference Figure 2 As shown, since the second pin 21 is set to correspond one-to-one with the first pin 11, the first pin 11, which is electrically connected to the test pin 21-1, is also divided into two groups.

[0063] Continue to refer to Figure 1 As shown, the flexible circuit board 2 also includes a test network 22 corresponding to a plurality of adjacent test pins 21-1. The test network includes a plurality of first traces 221 and signal ports 222 electrically connected to each of the first traces 221. The signal ports 222 are used to receive or output test signals. Test signals received through the signal ports 222 include, for example, various clock signals and power signals. Test signals output through the signal ports 222 include, for example, feedback test output signals. All of these test signals are used to perform electrical tests on the response circuit module in the display panel. (Refer to...) Figure 1 The example shown includes two sets of adjacent test pins 21-1, which in turn also include two sets of test networks 22.

[0064] Of course, the number of groups of multiple test pins arranged adjacent to each other in this embodiment is not limited to this. Figure 1The number of test network groups shown is not intended to be limited to two; the specific setting method depends on the design needs of the actual product.

[0065] Specifically, in embodiments of this disclosure, adjacent test pins 21-1 are electrically isolated. Optionally, at least one of the plurality of test pins receives a high-frequency signal during testing, and / or the test signal is used to perform electrical testing on the gate drive circuit in the display panel 1.

[0066] With this setting, for the second pin 21-1 that receives high-frequency signals in display module testing processes such as reliability testing, or for the second pin 21-1 used to test the gate drive circuit in display module testing processes such as reliability testing, even if the signal line transmitting high voltage and high frequency signals has undergone reliability corrosion after being exposed to high temperature and high humidity environments for a long time, the test pin can be kept electrically isolated, thereby preventing the related circuit modules of the display panel from being affected by corrosion. This avoids display defects such as RB bright lines and G bright lines, and improves the stability of the display panel under extreme conditions.

[0067] In this specific example, refer to Figure 1 As shown, the flexible circuit board 2 includes multiple first pads 23, multiple second pads 24, and multiple second traces 25, with the number of first pads 23, second pads 24, and second traces 25 being equal. Specifically, the first end of the second trace 25 is electrically connected to the first pad 23, and the second end is electrically connected to the test pin 21-1. The second pad 24 is electrically connected to the end of the first trace 221 that is not electrically connected to the signal port 222. The first pads 23 and the second pads 24 are electrically isolated.

[0068] In this embodiment, by setting the first pad 23 and the second pad 24 for electrical isolation, it is ensured that each test pin 21-1 is electrically isolated from its corresponding first trace 221. This ensures that if any first trace 221 in the test network 22 is corroded after the reliability test, causing a short circuit between the first traces 221, the test pins 21-1 can always be electrically isolated. This avoids the related circuit modules of the display panel from being affected by corrosion, improves the signal quality in the flexible circuit board 2, and avoids display defects such as RB bright lines and G bright lines. In addition, by setting the first pad 23 and the second pad 24 for electrical isolation to isolate the test pins 21-1 from the corresponding test network, the stability of the display panel under extreme conditions during use can also be improved.

[0069] Optionally, the first pad 23 and the second pad 24 together form a resistor pad. During reliability testing, the first pad 23 and the second pad 24 are used to mount a 0Ω resistor to electrically connect the corresponding first trace 221, the second pad 24, the first pad 23, the second trace 25, and the test pin 21-1. In the mass production stage, this resistor is not mounted to provide electrical isolation between the test pins 21-1.

[0070] With this setup, during reliability testing, the signal port 222, electrically connected via the first trace 221, receives the test signal and transmits it to the test pin 21-1 via the path formed by the second pad 24, resistor, first pad 23, and second trace 25. The signal is then transmitted to the corresponding circuit under test in the display panel 1 via the electrical connection between the test pin 21-1 and the first pin 11. Alternatively, the self-test signal obtained from the test can be output from the pin 21-1 to the signal port 222 via the path formed by the second trace 25, first pad 23, resistor, and second pad 24. By accessing the high-frequency test signal through the signal port 222 and detecting the signal waveform at the corresponding signal port, it is possible to assist in the debugging of circuits (e.g., GOA) in the display panel.

[0071] Alternatively, considering the manufacturing process of mounting resistors, the first pad 23 and the second pad 24 should be on the same conductive layer.

[0072] Specifically, the flexible circuit board 2 includes a first conductive layer and a second conductive layer, with the first pad 23 and the second pad 24 located on the first conductive layer or the first pad and the second pad located on the second conductive layer.

[0073] Additionally, refer to Figure 1 As shown, the distance 'a' between the first pad 23 and the second pad 24 is limited by the package size of the resistor used.

[0074] Optionally, to save space occupied by the first pad 23, the second pad 24, and the resistor to be mounted thereon, the resistor should be a surface mount resistor. For example, the resistor can be a 0201 package resistor with a smaller package size. To ensure good mounting performance with conventional 0201 package resistors, the distance between the first pad and the second pad connected to the first and second traces that receive the same test signal can be 0.12mm-0.5mm. For example, the distance 'a' between the first pad 23 and the second pad 24 can be 0.12mm-0.26mm to meet the package size of Panasonic's 0201 surface mount resistor, or the distance 'a' between the first pad 23 and the second pad 24 can be 0.27mm-0.5mm to meet the package size of KEMET's 0201 surface mount resistor.

[0075] Of course, the above size range is only illustrative and is not intended to be limiting. When using 0201 packaged surface mount resistors from other companies, or other larger packaged surface mount resistors where space permits, the distance 'a' between the first pad 23 and the second pad 24 will satisfy other ranges.

[0076] Figure 3 A partial wiring diagram of an exemplary flexible display module illustrates the structure of the flexible circuit board in this embodiment, which utilizes a first pad and a second pad for electrical isolation. Figure 4 Example shown Figure 3 The flexible circuit board in the test utilizes the structure after the first and second pads are connected by signal during the signal resilience test.

[0077] It should be noted that, for clarity, Figure 3 and Figure 4 The present invention only illustrates a set of first pads 23 and second pads 24 and the circuit connection formed by the set of first pads 23 and second pads 24, but this application is not intended to be limited thereto. In actual applications, the number of first pads 23 and second pads 24 depends on the number of test pins 21-1 that need to be electrically isolated, which will not be elaborated here.

[0078] Specifically, in this example, from Figure 3 As can be seen in the diagram, a test pin 21-1, along with its electrically connected second trace 25 and first pad 23, are marked with a bright yellow line and a block. From Figure 3 As can be seen, the first pad 23 and the second pad 24 are conventional square pads used to mount resistors. At this time, the first pad 23 and the second pad 24 are in the stage where no resistor is mounted. The test pin 21-1 is electrically isolated from the corresponding first trace 221 and signal port 222 by utilizing the electrically isolated first pad 23 and the second pad 24.

[0079] in addition, Figure 3 The diagram also shows other first traces 221 and second traces 222 of the test network. Those skilled in the art will understand that, although not shown in the screenshot, these first traces 221 and second traces 222 also have corresponding first pads 23 and 24. Furthermore, Figure 3 The document also shows the larger signal ports FOP_TEST_L1 and FOP_TEST_L2, which are used for testing other circuit modules in the display module and will not be discussed further in this document.

[0080] Reference Figure 4 As shown in the diagram, the circuit structures where electrical connections occur are also marked with bright yellow lines and blocks. From Figure 4As can be seen, the first pad 23 and the second pad 24 are conventional square pads used to mount resistors. After mounting a 0Ω resistor between the first pad 23 and the second pad 24, the system is in the reliability test stage. The test pin 21-1 forms an electrical path by electrically connecting the first pad 23 and the second pad 24, which are electrically connected by the resistor, with the corresponding first trace 221 and signal port 222. This path can be used to receive or output test signals to complete the reliability test of the corresponding circuit structure in the display panel 1.

[0081] More preferably, refer to Figure 4 As shown, the flexible circuit board 2 also includes a component area (such as...) Figure 4 (The blue box in the middle) The component area includes multiple components, which are electrically connected to other second pins via signal lines. The first pad 23 and the second pad 24 should be positioned on the side of the component area close to the second pin 21, or the first pad 23 and the second pad 24 should be positioned between the component area and the second pin 21. That is, the first pad 23 and the second pad 24 should be positioned as close as possible to the second pin 21. Such a setting can minimize the impact of the GOA test line on the circuit in the display panel.

[0082] This method achieves electrical isolation between all first traces 221 and all test pins 21-1, thus preventing the corrosion-induced short circuit of the first traces 221 from affecting the test pins 21-1. This, in turn, avoids display defects such as RB and G bright lines on the display panel 1, and also enhances the electromagnetic compatibility capabilities of the flexible circuit board against electrostatic discharge and radio frequency interference. Simultaneously, this structure protects the display function of the display panel without affecting the reliability testing function. Furthermore, it only requires two pads between electrically connected traces on the existing structure, resulting in a simple structure with minimal modifications compared to existing designs and no significant increase in design and manufacturing costs.

[0083] Alternatively, the first pad 23 and the second pad 24 are not used to mount resistors, but together form a group of closely spaced pads. During reliability testing, by creating windows above the first pad 23 and the second pad 24 in the packaging process (e.g., coverlay), and printing conductive layers such as conductive solder paste in the surface mount technology (SMT) process, the first pad 23 and the second pad 24 can be shorted together during reflow soldering, thereby electrically connecting the corresponding first trace 221, second pad 24, first pad 23, second trace 25, and test pin 21-1. In mass production, simply removing the coverlay or ink covering above this pad group and not applying conductive layers such as solder paste during the SMT process allows for electrical isolation between the test pins 21-1.

[0084] With this setup, during reliability testing, the signal port 222, electrically connected via the first trace 221, receives the test signal and transmits it to the test pin 21-1 via the path formed by the second pad 24, the first pad 23, and the second trace 25. The signal is then transmitted to the corresponding circuit under test in the display panel 1 via the electrical connection between the test pin 21-1 and the first pin 11. Alternatively, the self-test signal obtained from the test can be output from the pin 21-1 to the signal port 222 via the path formed by the second trace 25, the first pad 23, and the second pad 24. By accessing the high-frequency test signal through the signal port 222 and detecting the signal waveform at the corresponding signal port, it is possible to assist in the debugging of circuits (e.g., GOA) in the display panel.

[0085] It is also worth mentioning that in this example, the reliability test phase does not require a resistor, which is less expensive than a structure that incorporates a resistor.

[0086] In this example, the specific connection method for electrical isolation and point connection between the test network 22 and the test pin 21-1 through the pad group formed by the first pad 23 and the second pad 24 is as follows: Figure 3 and Figure 4 The method shown is similar and will not be repeated here.

[0087] Figure 5 This illustrates another example of partial wiring on a flexible circuit board that satisfies a pad group structure.

[0088] Reference Figure 5 As shown, unlike the pad structure with resistors, when using a pad group structure without resistors, the shape of the first pad 23 and the second pad 24 is not limited to the resistor package. In other words, the first pad 23 and the second pad 24 can be in various shapes during the design.

[0089] It should be noted that the first pad 23 and the second pad 24 form a pad group used to electrically isolate the test network 22 from the test pad 21-1 to protect the circuit structure in the display panel 1. Therefore, the distance 'a' between the first pad 23 and the second pad 24 should be sufficient to provide effective electrical isolation protection. Thus, the distance between the first pad 23 and the second pad 24 should be greater than the minimum process dimension for patterning; that is, the distance 'a' between the first pad 23 and the second pad 24 should be greater than or equal to 0.1 mm.

[0090] In addition, considering the manufacturing process, in order to form an effective short-circuit connection during surface mount technology (SMT) by printing conductive layers and during reflow soldering, the distance between the first pad 23 and the second pad 24 should be as close as possible.

[0091] Of course, taking into account the manufacturing process, the first pad 23 and the second pad 24 should be located on the same conductive layer. Specifically, the flexible circuit board 2 includes a first conductive layer and a second conductive layer, and the first pad 23 and the second pad 24 are located on the first conductive layer or the first pad 23 and the second pad 24 are located on the second conductive layer.

[0092] In some alternative embodiments, refer to Figure 6 As shown, the flexible circuit board electrically connected to the display panel 1 includes a main circuit board 2-1 and an auxiliary circuit board 2-2.

[0093] The main circuit board 2-1 and the auxiliary circuit board 2-2 are electrically isolated, meaning they are two independently configured circuit boards. The display panel 1 includes multiple first pins 11', and the flexible circuit board includes multiple second pins 21' corresponding to the multiple first pins 11'. The multiple second pins 21' include multiple adjacent test pins 21-1', and a test network 22' corresponding to the test pins 21-1' is disposed on the auxiliary circuit board 2-2.

[0094] The test network 22' includes multiple first traces 221 and signal ports 222 that are electrically connected to each of the first traces 221. The end of the first trace 222 that is not electrically connected to the signal port 222 is electrically connected to the corresponding test pin 21-1'.

[0095] Specifically, refer to Figure 6 As shown, the first pin 11-1' electrically connected to the test pin 21-1' is located on one side of the other first pins 11' besides the first pin 11-1' electrically connected to the test pin 21-1', so that all test networks related to the test pin 21-1' can be set on the auxiliary circuit board 2-2.

[0096] It should be noted that Figure 6 The components and wiring in the main circuit board 2-1 are omitted. Those skilled in the art will understand that the main circuit board 2-1 includes the components and wiring required for display and / or touch control of the display panel 1.

[0097] By using the above configuration, and employing a separate auxiliary circuit board 2-2 to independently configure the test network 22' associated with the adjacent test pins 21-1', the wiring providing various signals required for normal display of the display panel 1 can be physically isolated from the test network 22' which provides high-frequency signals and / or GOA test signals. Furthermore, by providing the separate auxiliary circuit board 2-2, the wiring space of the test network 22' is directly increased. This ensures that even if the first trace 221 in the test network 22' corrodes under the high temperature and humidity conditions of the reliability test, it will not short-circuit with other adjacent first traces 221. Thus, even when the other end of the first trace 221 is electrically connected to the test pins 21-1', the test pins 21-1' in the display module remain electrically isolated, thereby preventing display defects such as RB bright lines and G bright lines on the display panel 1. Simultaneously, this configuration also ensures the product stability of the display module under extreme environments.

[0098] It is worth mentioning that in this embodiment, the flexible circuit board with holes is the same for the display module in the reliability testing stage and the display module in the mass production stage, which reduces the difficulty of the manufacturing process and lowers the process cost.

[0099] Reference Figure 6 As shown, since the test networks 22' are all set on the auxiliary circuit board 2-2, the wiring space in the auxiliary circuit board 2-2 is more flexible.

[0100] Optionally, such as Figure 6 As shown, the auxiliary circuit board 2-2 also includes a plurality of second traces 25 that are electrically connected to the first trace 221 in a one-to-one correspondence. One end of each second trace 25 is electrically connected to the end of the first trace 221 that is not electrically connected to the signal port 222, and the other end is electrically connected to the test pin 21-1'. The auxiliary circuit board 2-2 includes a plurality of conductive layers, the corresponding first traces and second traces are located on the same conductive layer, and two adjacent first traces and / or two adjacent second traces are located on different conductive layers.

[0101] For example, the second trace 25 includes trace 25-1 electrically connected to the (2n-1)th test pin 21-1' and trace 25-2 electrically connected to the 2nth test pin 21-1'. The first trace 221 includes first trace 221-1 electrically connected to trace 25-1 and first trace 221-2 electrically connected to trace 25-2. The auxiliary circuit board 2-2 includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first and second conductive layers. Traces 25-1 and first trace 221-1 are disposed on the first conductive layer, and traces 25-2 and first trace 221-2 are disposed on the second conductive layer. Simultaneously, the signal ports 222 can also be configured as at least two rows, with first trace 221-1 electrically connected to the even-numbered row of signal ports 222 and first trace 221-2 electrically connected to the odd-numbered row of signal ports 222, where n is an integer greater than or equal to 1. Of course, the first trace 221-1 can also be electrically connected to the even-numbered row signal port 222, and the first trace 221-2 can also be electrically connected to the even-numbered row signal port 222. Of course, this is just an example; the odd-numbered trace can also be electrically connected to the even-numbered row signal port.

[0102] With the above settings, the spatial flexibility of the auxiliary circuit board 2-2 can be fully utilized, the wiring distance between adjacent test pins 21-1' can be increased, and electrical isolation between adjacent test pins 21-1' can be ensured.

[0103] Figure 7 and Figure 8 Another optional embodiment is provided, which differs from the embodiment described above in that the flexible circuit board includes a first region 2-1 and a second region 2-2. The first region 2-1 includes a first conductive layer L11, a second conductive layer L12, and a first insulating layer L21 located between the first conductive layer L11 and the second conductive layer L12. The second region 2-2 includes a first conductive layer L11, a first insulating layer L21, a second conductive layer L12, a second insulating layer L22, and a third conductive layer L13 stacked sequentially. A test network is set in the second region 2-2, and one end of the first trace 221 that is not electrically connected to the signal port is electrically connected to the corresponding second pin 21-1.

[0104] In this embodiment, by adding a wiring layer to a local area of ​​the flexible circuit board and placing the test network in that local area, the test network, which is easily corroded and short-circuited during reliability testing, is placed in the added wiring layer. This utilizes the increased wiring space provided by the additional wiring layer to increase the spacing between the first traces in the test network. Therefore, even if the first trace of the test network corrodes after the reliability test, short circuits between adjacent traces will not occur, thus providing electrical isolation between adjacent test pins in the display module. This prevents display defects such as RB and G bright lines on the display panel 1. Simultaneously, this configuration also enhances the electromagnetic compatibility (EMC) capabilities of the flexible circuit board against electrostatic discharge (ESD) and radio frequency interference (RF interference), ensuring product stability of the display module under extreme environments.

[0105] It is also worth mentioning that in this embodiment, the flexible circuit board with vias for the display module in the reliability testing stage is the same as that in the mass production stage, which reduces the difficulty of the manufacturing process and lowers the process cost. At the same time, the layout of the first pins related to the test network does not need to be rearranged, that is, this structure does not affect the layout and wiring in the display panel 1 itself, thereby reducing the design cost.

[0106] Optionally, combined Figure 8 and Figure 9 As shown, the second pin 21 is disposed in the first conductive layer L11, the test network is disposed in the third conductive layer L13, and the second region 2-2 also includes multiple vias TK and conductive parts disposed in the vias TK. The vias TK extend from the surface of the first insulating layer L1 near the first conductive layer L1 to the surface of the second insulating layer L22 away from the first conductive layer L11. The test pin 21-1 is electrically connected to the first trace 221 via the conductive parts. The flexible circuit board also includes a third trace 26, which is electrically connected to the other second pins 21 except for the test pin 21-1. The orthographic projection of the vias TK in the first insulating layer L21 and the orthographic projection of the third trace 26 in the first insulating layer L21 do not overlap.

[0107] This setting ensures that the conductive parts in the via TK can avoid the third trace 26, thereby ensuring that the test network does not interfere with the circuit structure in the display panel 1.

[0108] Further optional, refer to Figure 9 As shown, in order to increase the wiring space of the test network by utilizing the vertically added conductive layer, thereby increasing the spacing between the first traces 221, the second region 2-2 ( Figure 9The area within the green box includes: a row of vias TK and two rows of signal ports 222. The number of signal ports 222 can also be multiple rows. The arrangement direction of the multiple vias TK and the signal ports 222 in each row is roughly the same. The test network also includes multiple fourth traces 223 electrically connected to each via TK. One end of each fourth trace 223 is electrically connected to an adjacent via TK, and the other end of each fourth trace 223 is electrically connected to the signal ports 222 located in different rows.

[0109] Specifically Figure 9 For example, the test network also includes multiple fourth traces 223 electrically connected to vias TK one-to-one. One end of a fourth trace 223 electrically connected to the (2n-1)th via is electrically connected to the other end of a signal port 222 in the odd-numbered row. The other end of a fourth trace 223 electrically connected to the 2nth via is electrically connected to the signal port 222 in the even-numbered row of the second row, where n is an integer greater than or equal to 1. Of course, the connection order of the fourth traces 223 to the odd and even rows can be interchanged; that is, the other end of a fourth trace 223 electrically connected to the (2n-1)th via is electrically connected to the signal port 222 in the even-numbered row, and the other end of a fourth trace 223 electrically connected to the 2nth via is electrically connected to the signal port 222 in the odd-numbered row.

[0110] Further reference Figure 9 As shown, specifically, the second region 2-2 in the example figure includes a test network for two sets of GOA electrical tests. The identifier in signal port 222 indicates the signal received or output by that signal port 222. Figure 9 As shown, one set of signal ports 222 for electrical testing of GOA includes an output port EOUT, a first clock port ECB, a second clock port ECX, and an initial signal port HSTV. Another set of signal ports 222 for electrical testing of GOA includes an output port GOUT, a first clock port CLK1, a second clock port HCB, and an initial signal port HSTV. Of course, the naming convention for the signal ports is merely exemplary and is not intended to be limiting. Furthermore, Figure 9 The diagram also shows the signal traces corresponding to the other second pins besides the test pin 21-1. For example, ELVSS represents the signal trace that provides a low-level power signal, ELVDD represents the signal trace that provides a high-level power signal, and GND represents the ground line. Of course, this is just an example, and the way these signal traces are laid out may be different for different examples.

[0111] Corresponding to the display module in the above embodiment that uses the first pad 23 and the second pad 24 to electrically isolate the test network and the test pin 21-1, this disclosure embodiment also provides a test method for the display module, including: electrically connecting the first pad and the second pad one-to-one, and performing electrical tests on the display panel by inputting or outputting test signals through a signal port.

[0112] Optionally, electrically connecting the first pad and the second pad in a one-to-one correspondence includes mounting a zero-resistance resistor between the first pad and the second pad.

[0113] Specifically, during the debugging phase of the display module, a zero-resistance surface mount resistor is soldered or bonded between the first pad and the second pad. This surface mount resistor can be a surface mount resistor with a 0201 package process, or other surface mount resistors that meet the package design dimensions of the first pad and the second pad.

[0114] Alternatively, electrically connecting the first pad and the second pad one-to-one includes: opening multiple windows in the display module, each window exposing the first pad, the second pad, and the area between the first pad and the second pad to be electrically connected, and coating the window with a metal layer.

[0115] Specifically, during the sample debugging stage, an overlay window is created above the first and second pads. This window needs to expose both pads and the area between them simultaneously. During the SMT process, solder paste is printed onto the overlay. During reflow soldering, the solder paste short-circuits together due to their close proximity, thus forming an electrical connection between the first and second pads.

[0116] With the above settings, the test network is isolated by using the first and second pads. This not only meets the reliability test requirements but also improves the stability of the display module, enhances the display effect, extends the product life, and strengthens the electromagnetic compatibility of the flexible circuit board against electrostatic discharge and radio frequency interference. It also improves the stability of power lines / signal lines in certain extreme environments.

[0117] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which implements the display module described above.

[0118] Since the display module included in the display device provided in this embodiment corresponds to the display module provided in the above-mentioned embodiments, the usage method provided in this embodiment is also applicable to the previous embodiments, and will not be described in detail in this embodiment.

[0119] In this embodiment, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, in-vehicle display, digital photo frame, or navigator. By loading the above display module, the display device can avoid display defects and improve product stability and lifespan.

[0120] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A display module, characterized in that, include: The display panel and the flexible circuit board electrically connected to the display panel. The display panel includes multiple first pins, and the flexible circuit board includes multiple second pins. The multiple first pins and the multiple second pins are electrically connected in a one-to-one correspondence. The multiple second pins include multiple test pins arranged adjacent to each other. The flexible circuit board further includes a test network corresponding to the plurality of test pins. The test network includes a plurality of first traces and signal ports electrically connected to each of the first traces. The signal ports are used to receive or output test signals. The adjacent test pins are electrically isolated.

2. The display module according to claim 1, characterized in that, At least one of the plurality of test pins receives a high-frequency signal during testing, and / or the test signal is used to perform an electrical test on the gate drive circuit in the display panel.

3. The display module according to claim 1, characterized in that, The flexible circuit board includes multiple first pads, multiple second pads, and multiple second traces, wherein the number of first pads, second pads, and second traces are all equal. The first end of the second trace is electrically connected to the first pad, and the second end is electrically connected to the test pin. The second pad is electrically connected to the end of the first trace that is not electrically connected to the signal port, and the first pad and the second pad are electrically isolated.

4. The display module according to claim 3, characterized in that, The flexible circuit board includes a first conductive layer and a second conductive layer. The first pad and the second pad are located on the first conductive layer, or the first pad and the second pad are located on the second conductive layer.

5. The display module according to claim 4, characterized in that, The distance between the first pad and the second pad connected to the first and second traces that receive the same test signal is in the range of 0.12mm-0.5mm.

6. The display module according to claim 1, characterized in that, The flexible circuit board includes a main circuit board and an auxiliary circuit board, wherein... The main circuit board and the auxiliary circuit board are electrically isolated, and The test pin and the test network are disposed on the auxiliary circuit board, and the end of the first trace that is not electrically connected to the signal port is electrically connected to the corresponding test pin.

7. The display module according to claim 6, characterized in that, The first pin electrically connected to the test pin is located on one side of the other first pins besides the first pin electrically connected to the test pin.

8. The display module according to claim 6, characterized in that, The auxiliary circuit board includes a plurality of second traces that are electrically connected to each of the first traces in a one-to-one correspondence, and the auxiliary circuit board includes a plurality of conductive layers. The first and second traces corresponding to the electrical connection are located on the same conductive layer, and two adjacent first traces and / or two adjacent second traces are located on different conductive layers.

9. The display module according to claim 1, characterized in that, The flexible circuit board includes a first region and a second region. The first region includes a first conductive layer, a second conductive layer, and a first insulating layer located between the first conductive layer and the second conductive layer. The second region includes the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, and a third conductive layer, which are sequentially stacked. The test network is set in the second region, and the end of the first trace that is not electrically connected to the signal port is electrically connected to the corresponding second pin.

10. The display module according to claim 9, characterized in that, The second pin is disposed on the first conductive layer, and the test network is disposed on the third conductive layer. The second region also includes a plurality of vias and conductive portions disposed in the vias. The via extends from the surface of the first insulating layer near the first conductive layer to the surface of the second insulating layer away from the first conductive layer. The test pin is electrically connected to the first trace via the conductive portion. The flexible circuit board further includes a third trace, which is electrically connected to the other second pins of the second pins except for the test pin. The orthographic projection of the via in the first insulating layer does not overlap with the orthographic projection of the third trace in the first insulating layer.

11. The display module according to claim 10, characterized in that, The second region includes: a row of the vias and at least two rows of the signal ports. The multiple vias and the signal ports in each row of signal ports are arranged in roughly the same direction. The test network also includes a plurality of fourth traces that are electrically connected to each of the vias, and the other end of each fourth trace, which is electrically connected to an adjacent via, is electrically connected to a signal port located in a different row.

12. A display device, characterized in that, The display module includes any one of claims 1-11.

13. A testing method for a display module applied to any one of claims 3-5, characterized in that, include: The first pad and the second pad are electrically connected one-to-one, and the test signal is input or output through the signal port to test the display panel.

14. The test method according to claim 13, characterized in that, Connecting the first pad and the second pad one-to-one includes: A zero-resistance resistor is mounted between the first pad and the second pad. or Multiple windows are opened in the display module, each window exposing a first pad, a second pad, and the area between the first pad and the second pad to be electrically connected. A metal layer is coated in the window.

Images