Display panel and electronic device including the same

Abstract

Disclosed are a display panel and an electronic device including the same, the display panel including: a plurality of pixels arranged along a first direction; a first type stage including a plurality of first buffer circuits respectively outputting a plurality of first type scan signals to the plurality of pixels; a second type stage including a plurality of second buffer circuits respectively outputting a plurality of second type scan signals to the plurality of pixels; and a plurality of carry clock lines disposed between the first buffer circuit and the second buffer circuit and extending in the first direction. The plurality of first buffer circuits are arranged along a first direction, and the plurality of second buffer circuits are arranged along the first direction.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0152513, filed on October 31, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The embodiments of this disclosure described herein relate to a display panel having a non-display area of ​​reduced width and an electronic device including the display panel. Background Technology

[0003] Various multimedia electronic devices, such as TVs, mobile phones, tablet PCs, navigation systems, and game consoles, include display panels for displaying images. Based on market demand, research is underway to reduce the areas on the display panel where images are not displayed (non-display areas or border areas). Summary of the Invention

[0004] Embodiments of this disclosure provide a display panel having a non-display area with a reduced width, and an electronic device including the display panel.

[0005] According to an embodiment, the display panel includes: a plurality of pixels arranged along a first direction; a first type level including a plurality of first buffer circuits that output a plurality of first type scan signals to the plurality of pixels respectively; a second type level including a plurality of second buffer circuits that output a plurality of second type scan signals to the plurality of pixels respectively; and a plurality of carry clock lines disposed between the first buffer circuits and the second buffer circuits and extending in the first direction, wherein the plurality of first buffer circuits are arranged along the first direction and the plurality of second buffer circuits are arranged along the first direction.

[0006] The display panel may further include: a plurality of first-type clock lines electrically connected to a first-type level; and a plurality of second-type clock lines electrically connected to a second-type level, wherein the plurality of first-type clock lines and the plurality of second-type clock lines may be spaced apart from each other in a second direction intersecting the first direction, and a plurality of carry clock lines may be disposed between the first-type clock lines and the second-type clock lines.

[0007] The first type level can be set between multiple first type clock lines and multiple carry clock lines, and the second type level can be set between multiple second type clock lines and multiple carry clock lines.

[0008] The first type level may further include a first logic circuit that controls the operation of multiple first buffer circuits, and the second type level may further include a second logic circuit that controls the operation of multiple second buffer circuits. The multiple first buffer circuits may be disposed between multiple first type clock lines and the first logic circuit, and the multiple second buffer circuits may be disposed between multiple second type clock lines and the second logic circuit.

[0009] Multiple first-type clock lines, first-type levels, multiple carry clock lines, second-type levels, multiple second-type clock lines, and multiple pixels can be arranged sequentially in the second direction.

[0010] The display panel may also include voltage lines disposed between multiple second-type clock lines and multiple pixels, and the voltage lines may extend along a first direction.

[0011] The display panel may also include voltage lines disposed between the first type level and the second type level, and the voltage lines may extend along the first direction.

[0012] The display panel may also include multiple signal lines electrically connected to the first type level and the second type level, and the multiple signal lines may be arranged between multiple first buffer circuits and multiple second buffer circuits.

[0013] The display panel may further include: a first connecting line extending in a second direction intersecting the first direction; and a second connecting line spaced apart from the first connecting line along the second direction and extending along the second direction, wherein the first connecting line may be electrically connected to a first signal line and a first type level among a plurality of signal lines, and the second connecting line may be electrically connected to the first signal line and the second type level among a plurality of signal lines.

[0014] The display panel may also include integrated logic circuitry, which is disposed between multiple signal lines and multiple carry clock lines and controls the operation of multiple first buffer circuits and multiple second buffer circuits.

[0015] The display panel may further include: a plurality of first-type scan lines electrically connected to a plurality of first buffer circuits in a one-to-one correspondence; and a plurality of second-type scan lines electrically connected to a plurality of second buffer circuits in a one-to-one correspondence, wherein the plurality of first-type scan lines and the plurality of second-type scan lines may be electrically connected to a plurality of pixels across an introduction region adjacent to a plurality of pixels.

[0016] At least one of the multiple second-type scan lines can be positioned in the introduction region between the first first-type scan line of the multiple first-type scan lines and the second first-type scan line of the multiple first-type scan lines.

[0017] The display panel may also include data lines electrically connected to a plurality of pixels and power lines electrically connected to a plurality of pixels. Each of the plurality of pixels may include a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit. The pixel driving circuit may include a first transistor connected between the power line and the light-emitting element, a second transistor connected between the data line and the gate electrode of the first transistor, and a third transistor connected between the light-emitting element and the readout line.

[0018] The operation of the second transistor can be controlled by one of a plurality of first-type scan signals, and the operation of the third transistor can be controlled by one of a plurality of second-type scan signals.

[0019] The operation of the second transistor can be controlled by one of a plurality of second-type scan signals, and the operation of the third transistor can be controlled by one of a plurality of first-type scan signals.

[0020] According to an embodiment, the electronic device includes: a display panel having a display area and a non-display area adjacent to the display area; and a data driver electrically connected to the display panel. The display panel includes: a plurality of pixels arranged in the display area along a first direction; a data line electrically connected to the plurality of pixels and the data driver; a first type level disposed in the non-display area and outputting a plurality of first type scan signals to the plurality of pixels; and a second type level disposed in the non-display area and outputting a plurality of second type scan signals to the plurality of pixels, wherein the first type level and the second type level are spaced apart from each other in a second direction intersecting the first direction.

[0021] The first type level may include a plurality of first buffer circuits, wherein each of the plurality of first buffer circuits outputs a first type scan signal from a plurality of first type scan signals. The second type level may include a plurality of second buffer circuits, wherein each of the plurality of second buffer circuits outputs a second type scan signal from a plurality of second type scan signals. The plurality of first buffer circuits may be arranged along a first direction, and the plurality of second buffer circuits may be arranged along the first direction.

[0022] The display panel may further include: multiple carry clock lines disposed between multiple first buffer circuits and multiple second buffer circuits and extending in a first direction; multiple first type clock lines electrically connected to a first type stage; and multiple second type clock lines electrically connected to a second type stage, wherein the first type clock lines and the second type clock lines may be spaced apart from each other in a second direction, and the multiple carry clock lines may be disposed between the multiple first type clock lines and the multiple second type clock lines.

[0023] Multiple first-type clock lines, a first-type level, multiple carry clock lines, a second-type level, multiple second-type clock lines, and multiple pixels can be arranged sequentially along a second direction, and the display panel can also include voltage lines disposed between the multiple second-type clock lines and the multiple pixels, and the voltage lines extend along a first direction.

[0024] The display panel may further include: multiple signal lines electrically connected to a first type level and a second type level; a first connecting line extending along a second direction; and a second connecting line spaced apart from the first connecting line and extending along the second direction. The multiple signal lines may be disposed between multiple first buffer circuits and multiple second buffer circuits, and the first connecting line may be electrically connected to one of the multiple signal lines and the first type level, and the second connecting line may be electrically connected to the one of the multiple signal lines and the second type level. Attached Figure Description

[0025] The above and other objects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0026] Figure 1A This is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0027] Figure 1B This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0028] Figure 2 This is a plan view of an electronic device according to an embodiment of the present disclosure.

[0029] Figure 3 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0030] Figure 4 This is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0031] Figure 5 This is a block diagram illustrating some components of a display panel according to an embodiment of the present disclosure.

[0032] Figure 6A This is a view showing a scan driver according to an embodiment of the present disclosure.

[0033] Figure 6B This is an equivalent circuit diagram illustrating one stage according to an embodiment of the present disclosure.

[0034] Figure 7 This is a timing diagram illustrating the operation of a level in a first mode according to an embodiment of the present disclosure.

[0035] Figure 8It is a timing diagram of a plurality of clock signals used to describe the operation of a level in a second mode according to an embodiment of the present disclosure.

[0036] Figure 9 This is a view showing the activation state and brightness changes of a first type of scan signal and a second type of scan signal according to an embodiment of the present disclosure.

[0037] Figure 10 This is a view showing the activation state and brightness changes of a first type of scan signal and a second type of scan signal according to an embodiment of the present disclosure.

[0038] Figure 11 This is a plan view of a portion of a display panel according to an embodiment of the present disclosure.

[0039] Figure 12A This is a plan view showing a single signal line and multiple intersecting signal lines according to a comparative example of this disclosure.

[0040] Figure 12B This is a plan view illustrating one signal line and multiple cross signal lines according to an embodiment of the present disclosure.

[0041] Figure 12C This is a plan view illustrating signal lines according to an embodiment of the present disclosure.

[0042] Figure 13 This is a plan view showing some of the signal lines according to an embodiment of the present disclosure.

[0043] Figure 14 This is a plan view of a portion of a display panel according to an embodiment of the present disclosure.

[0044] Figure 15 This is a plan view of a portion of a display panel according to an embodiment of the present disclosure.

[0045] Figure 16 This is a plan view of a portion of a display panel according to an embodiment of the present disclosure.

[0046] Figure 17 This is a plan view of a portion of a display panel according to an embodiment of the present disclosure. Detailed Implementation

[0047] In the specification, the expressions "on" the first component (or area, layer, part, section, etc.) is "on" the second component, or "connected" or "combined" with the second component, indicate that the first component is directly on the second component, the first component is directly connected or combined with the second component, or that the third component is placed between the first component and the second component.

[0048] The same reference numerals denote the same components. Furthermore, in the drawings, for the sake of the effectiveness of the description of the technical content, the thickness, scale, and dimensions of the components are exaggerated. The term "and / or" includes one or more combinations of the related elements in each of them.

[0049] Although the terms “first,” “second,” etc., may be used to describe various components, these components should not be construed as being limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope and spirit of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. The articles “a,” “an,” and “the” are singular because they have a single indicator, but the use of the singular form in the specification should not preclude the existence of more than one indicator.

[0050] Furthermore, the terms "below," "under," "above," and "over" are used to describe the relational relationship of the components shown in the accompanying drawings. These terms are relative concepts and are described relative to the directions indicated in the drawings.

[0051] It will be understood that the terms “comprising,” “including,” “having,” etc., indicate the presence of the features, quantities, steps, operations, elements or components described in the specification, or combinations thereof, without excluding the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements or components, or combinations thereof.

[0052] The terms "component" and "unit" refer to software or hardware components that perform a specific function. For example, a hardware component may include a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). A software component may refer to executable code in addressable storage media and / or data used by the executable code. Therefore, a software component can be, for example, an object-oriented software component, a class component, and a task component, and may include processes, functions, attributes, programs, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, or variables.

[0053] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0054] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0055] Figure 1A This is a perspective view of an electronic device DD according to an embodiment of the present disclosure. Figure 1B This is a block diagram of an electronic device DD according to an embodiment of the present disclosure. Figure 2 This is a plan view of an electronic device DD according to an embodiment of the present disclosure.

[0056] Reference Figure 1A and Figure 1B The electronic device DD can be a device activated by an electrical signal. Besides large electronic devices such as televisions, monitors, or billboards, the electronic device DD can also be used in small to medium-sized electronic devices such as personal computers, laptops, personal digital terminals, car navigation units, game consoles, portable electronic devices, and cameras. Furthermore, these are presented only as examples. It should be noted that aspects of this disclosure are not limited to the disclosed types of electronic devices, and that this disclosure can be applied to other electronic devices as long as they do not depart from the concept of this disclosure. Figure 1A The electronic device DD shown in the image may be a monitor.

[0057] The electronic device DD outputs various information through the display module 140 in the operating system. When the processor 110 executes an application stored in the memory 120, the display module 140 provides application information to the user through the display panel DP. The processor 110 can be one or more processors that can execute method steps such as application execution individually, collectively, or partially collectively. For example, but without limitation, in the operation method, two processors can jointly execute a step, while a third processor executes a second step.

[0058] Processor 110 receives external input via input module 130 or sensor module 161 and executes the application corresponding to the external input. For example, when a user selects the camera icon displayed on the display panel DP, processor 110 receives user input via input sensor 161-2 and activates camera module 171. Processor 110 transmits image data corresponding to the captured image obtained by camera module 171 to display module 140. Display module 140 can display the image corresponding to the captured image via display panel DP.

[0059] As another example, when authentication of personal information is performed in display module 140, fingerprint sensor 161-1 obtains the input fingerprint information as input data. Processor 110 compares the input data obtained by fingerprint sensor 161-1 with the authentication data stored in memory 120 and executes the application based on the comparison result. Display module 140 can display the information executed according to the application logic via display panel DP.

[0060] As another example, when a user selects the music stream icon displayed in display module 140, processor 110 obtains user input via input sensor 161-2 and activates the music stream application stored in memory 120. When a music playback command is input to the music stream application, processor 110 activates sound output module 163 and provides the user with sound information corresponding to the music playback command.

[0061] The operation of the electronic device DD has been briefly described above. The construction of the electronic device DD will now be described in detail. Some of the components of the electronic device DD described later can be implemented as a single component, and a single component can be separated into two or more components.

[0062] Reference Figure 1B The electronic device DD can communicate with the external electronic device 102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to an embodiment, the electronic device DD may include a processor 110, a memory 120, an input module 130, a display module 140, a power module 150, an embedded module (or internal module) 160, and an external module 170. According to an embodiment, the electronic device DD may not include at least one of the above-described components, or it may include one or more other components. According to an embodiment, some of the above-described components (e.g., sensor module 161, antenna module 162, or audio output module 163) may be integrated into any other component (e.g., display module 140).

[0063] Processor 110 can execute software to control at least one component (e.g., a hardware or software component) of electronic device DD connected to processor 110, and can perform various data processing or operations. According to an embodiment, as at least part of data processing or operations, processor 110 can store instructions or data received from any other component (e.g., input module 130, sensor module 161, or communication module 173) in volatile memory 121, can process instructions or data stored in volatile memory 121, and can store processed data in non-volatile memory 122.

[0064] Processor 110 may include a main processor 111 and an auxiliary processor 112. Main processor 111 may include one or more of a central processing unit (CPU) 111-1 and an application processor (AP). Main processor 111 may also include one or more of a graphics processing unit (GPU) 111-2, a communication processor (CP), and an image signal processor (ISP). Main processor 111 may also include a neural processing unit (NPU) 111-3. Neural processing unit 111-3 may be a processor dedicated to processing artificial intelligence models, and the artificial intelligence models may be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural network may be one or a combination of two or more of the following: deep neural network (DNN), convolutional neural network (CNN), recurrent neural network (RNN), restricted Boltzmann machine (RBM), deep belief network (DBN), bidirectional recurrent deep neural network (BRDNN), deep Q network, but is not limited to the examples above. In addition to hardware architecture, the artificial intelligence model may also include software architecture. In this embodiment, the machine learning model may be a software architecture. At least two of the above processing units and processors can be implemented as a single component (e.g., a single chip), or each of the above processing units and processors can be implemented as a separate component (e.g., multiple chips).

[0065] The auxiliary processor 112 may include a controller 112-1. The controller 112-1 may include interface conversion circuitry and timing control circuitry. The controller 112-1 receives image signals from the main processor 111 and outputs image data obtained by converting the data format of the image signals into a format suitable for the interface specification with the display module 140. The controller 112-1 may output various types of control signals required to drive the display module 140.

[0066] The auxiliary processor 112 may also include a data conversion circuit 112-2, a gamma correction circuit 112-3, a rendering circuit 112-4, etc. The data conversion circuit 112-2 can receive image data from the controller 112-1. The data conversion circuit 112-2 can compensate the image data to display the image at the desired brightness according to the characteristics of the electronic device DD or user settings, or it can convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit 112-3 can convert the image data or gamma reference voltage so that the image displayed on the electronic device DD has the desired gamma characteristics. The rendering circuit 112-4 can receive image data from the controller 112-1 and can render the image data taking into account the pixel arrangement of the display panel DP applied to the electronic device DD. At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 can be integrated into any other component (e.g., the main processor 111 or the controller 112-1). At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 can be integrated into the data driver DDC, which will be described later.

[0067] Memory 120 may store various data used by at least one component of the electronic device DD (e.g., processor 110 or sensor module 161), as well as input or output data for instructions associated therewith. Memory 120 may include at least one of volatile memory 121 and non-volatile memory 122.

[0068] The input module 130 can receive instructions or data from outside the electronic device DD (e.g., from a user or external electronic device 102) that will be used by components of the electronic device DD (e.g., processor 110, sensor module 161, or sound output module 163).

[0069] Input module 130 may include a first input module 131 and a second input module 132, allowing a user to input instructions or data to the first input module 131 and an external electronic device 102 to input instructions or data to the second input module 132. The first input module 131 may include a microphone, mouse, keyboard, buttons (e.g., keypads), or pen (e.g., a passive or active pen). The second input module 132 may support a specified protocol enabling wired or wireless connection to the external electronic device 102. According to embodiments, the second input module 132 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital Card (SD) card interface, or an audio interface. The second input module 132 may include a connector capable of physically connecting to the external electronic device 102, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0070] Display module 140 provides information to the user visually. Display module 140 may include a display panel DP, a scan driver SDC, and a data driver DDC. Display module 140 may also include a window, a chassis, and a bracket for protecting the display panel DP.

[0071] The display panel DP can include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and there are no particular limitations on the type of display panel DP. The display panel DP can be rigid or flexible and can be rolled or folded. The display module 140 may also include a support, bracket, or heat dissipation component to support the display panel DP.

[0072] The scan driver SDC can be integrated into the display panel DP. For example, the scan driver SDC may include an amorphous silicon TFT gate drive circuit (ASG), a low-temperature polycrystalline silicon (LTPS) TFT gate drive circuit, or an oxide semiconductor TFT gate drive circuit (OSG) integrated into the display panel DP. The scan driver SDC receives control signals from the controller 112-1 and outputs scan signals to the display panel DP in response to the control signals. According to embodiments of this disclosure, the area or width occupied by the scan driver SDC can be designed to be reduced. Therefore, an electronic device DD with a reduced bezel area width can be provided.

[0073] The display panel DP may also include a transmitter driver. The transmitter driver outputs a light emission control signal to the display panel DP in response to a control signal received from the controller 112-1. The transmitter driver may be separate from the scan driver SDC, or it may be integrated into the scan driver SDC.

[0074] The data driver DDC receives a control signal from the controller 112-1, converts the image data into an analog voltage (e.g., a data voltage) in response to the control signal, and outputs the data voltage to the display panel DP.

[0075] The data driver DDC can be integrated into other components (e.g., controller 112-1). The functions of the interface conversion circuit and timing control circuit of the aforementioned controller 112-1 can be integrated into the data driver DDC. The data driver DDC can be referred to as a data driver or a data driver chip.

[0076] The display module 140 may also include a transmitter driver, a voltage generator, etc. The voltage generator can output various types of voltages required to drive the display panel DP.

[0077] Power module 150 supplies power to components of electronic device DD. Power module 150 may include a battery that is charged to a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 150 may include a power management integrated circuit (PMIC). The PMIC supplies optimized power for each of the modules described above and later. Power module 150 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple antenna radiators in the form of coils.

[0078] The electronic device DD may also include an embedded module 160 and an external module 170. The embedded module 160 may include a sensor module 161, an antenna module 162, and a sound output module 163. The external module 170 may include a camera module 171, an optical module 172, and a communication module 173.

[0079] The sensor module 161 can sense input from the user's body or pen in the first input module 131, and can generate an electrical signal or data value corresponding to the input. The sensor module 161 may include at least one of a fingerprint sensor 161-1, an input sensor 161-2, and a digitizer 161-3.

[0080] The fingerprint sensor 161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 161-1 may include at least one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0081] Input sensor 161-2 can generate data values ​​corresponding to the coordinate information of input from the user's body or a pen. Input sensor 161-2 generates capacitance changes caused by input as data values. Input sensor 161-2 can sense input from a passive pen or exchange data with an active pen.

[0082] Input sensor 161-2 can measure biometric signals such as blood pressure, water content, or body fat. For example, when a user touches a part of his / her body to the sensor layer or sensing panel and does not move it for a given period of time, input sensor 161-2 can detect biometric signals based on changes in the electric field caused by the body part and can output the information desired by the user to display module 140.

[0083] The digitizer 161-3 can generate data values ​​corresponding to the coordinate information of the pen input. The digitizer 161-3 generates the electromagnetic change caused by the input as a data value. The digitizer 161-3 can sense the input of a passive pen or exchange data with an active pen.

[0084] At least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 can be implemented as a sensor layer formed on the display panel DP by a continuous process. The fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 can be disposed above / on the display panel DP, and at least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 (e.g., the digitizer 161-3) can be disposed below / under the display panel DP.

[0085] At least two of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be integrally formed with a sensing panel using the same process. When they are integrally formed with a sensing panel, the sensing panel can be disposed between the display panel DP and a window disposed above / on the display panel DP. According to one embodiment, the sensing panel can be disposed on the window, and the position of the sensing panel is not particularly limited.

[0086] At least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 can be embedded in the display panel DP. That is, at least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 can be formed simultaneously by the process of forming elements (e.g., light-emitting devices and transistors) included in the display panel DP.

[0087] Additionally, sensor module 161 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device DD. Sensor module 161 may also include, for example, gesture sensors, gyroscope sensors, pressure sensors, magnetic sensors, accelerometers, grip sensors, proximity sensors, color sensors, infrared (IR) sensors, biometric sensors, temperature sensors, humidity sensors, or illuminance sensors.

[0088] Antenna module 162 may include one or more antennas to transmit or receive signals or power from an external source. According to an embodiment, communication module 173 may transmit or receive signals from external electronic device 102 via an antenna suitable for a communication method. The antenna pattern of antenna module 162 may be integrated with a component of display module 140 (e.g., display panel DP) or input sensor 161-2.

[0089] The sound output module 163 can be a device for outputting sound signals to the outside of the electronic device DD, and may include, for example, a speaker for general purposes such as multimedia playback or recording playback, and a receiver specifically for receiving telephone calls. According to embodiments, the receiver and speaker may be implemented as a whole or separately. The sound output pattern of the sound output module 163 may be integrated with the display module 140.

[0090] Camera module 171 can capture image data corresponding to still images or video images. According to one embodiment, camera module 171 may include one or more lenses, image sensors, or image signal processors. Camera module 171 may also include an infrared camera capable of measuring the presence or absence of a user, the user's position, and the user's line of sight.

[0091] The light module 172 can provide light. The light module 172 may include a light-emitting diode or a xenon lamp. The light module 172 can operate together with the camera module 171 or can operate independently.

[0092] Communication module 173 can establish a wired or wireless communication channel between electronic device DD and external electronic device 102, and can support communication execution through the established communication channel. Communication module 173 may include one or all of the following: a wireless communication module (such as a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) and a wired communication module (such as a local area network (LAN) communication module or a power line communication module). Communication module 173 can communicate with external electronic device 102 through short-range communication networks (such as Bluetooth, Wi-Fi Direct, or Infrared Data Association (IrDA)) or long-range communication networks (such as cellular networks, the Internet, or computer networks (e.g., LAN or WAN)). The various types of communication modules described above can be implemented using a single chip or separate chips.

[0093] The input module 130, sensor module 161, camera module 171, etc., can be used together with the processor 110 to control the operation of the display module 140.

[0094] Processor 110 outputs instructions or data to display module 140, sound output module 163, camera module 171, or optical module 172 based on input data received from input module 130. For example, processor 110 can generate image data corresponding to input data applied via a mouse or active pen, and can output the image data to display module 140. In an embodiment, processor 110 can generate instruction data corresponding to input data, and can output the instruction data to camera module 171 or optical module 172. When no input data is received from input module 130 during a given time period, processor 110 can switch the operating mode of electronic device DD to low-power mode or sleep mode, thereby reducing the power consumption of electronic device DD.

[0095] Processor 110 outputs instructions or data to display module 140, sound output module 163, camera module 171, or optical module 172 based on sensing data received from sensor module 161. For example, processor 110 can compare authentication data obtained by fingerprint sensor 161-1 with authentication data stored in memory 120, and then execute an application based on the comparison result. Processor 110 can execute instructions based on sensing data sensed by input sensor 161-2 or digitizer 161-3, or it can output image data corresponding to the sensing data to display module 140. When sensor module 161 includes a temperature sensor, processor 110 can receive temperature data associated with the measured temperature from sensor module 161, and can also perform brightness correction on image data based on the temperature data.

[0096] Processor 110 can receive measurement data from camera module 171 regarding the presence or absence of a user, the user's position, and the user's line of sight. Processor 110 can also perform brightness correction on image data based on the measurement data. For example, processor 110, which determines the presence or absence of a user based on input from camera module 171, can display image data whose brightness has been corrected by data conversion circuit 112-2 or gamma correction circuit 112-3.

[0097] Some of the components described above can be connected to each other via peripheral communication schemes (e.g., bus, general purpose input / output (GPIO), serial peripheral interface (SPI), mobile industrial processor interface (MIPI), or ultrapath interconnect (UPI) links) and can exchange signals (e.g., instructions or data). Processor 110 can communicate with display module 140 via a given interface. For example, one of the communication methods described above can be used, and this disclosure is not limited thereto.

[0098] According to the various embodiments disclosed in this publication, the electronic device DD can include various types of devices. The electronic device DD can include at least one of, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, and home appliances. The electronic device according to the disclosed embodiments is not limited to the electronic device DD described above.

[0099] Reference Figure 1A and Figure 2 Electronic devices (DD) may include display panels (DP), connecting films (COF), and circuit boards (PCB).

[0100] Display panel DP can be configured to substantially produce images. Display panel DP can be a light-emitting display panel, for example, an organic light-emitting display panel, an inorganic light-emitting display panel, an organic-inorganic light-emitting display panel, a quantum dot display panel, a micro-LED display panel, or a nano-LED display panel, but is not particularly limited thereto. Display panel DP can have a small to medium size of several inches or tens of inches or less. In embodiments, display panel DP can have a large size of several inches or more.

[0101] A display area DA and a non-display area NDA can be defined on a display panel DP. The display panel DP can display an image through the display area DA. For example, the display panel DP may include multiple pixels PX, and the pixels PX may be disposed in the display area DA. The display area DA may include a surface defined by a first direction DR1 and a second direction DR2. The display area DA can display an image on a third direction DR3 intersecting the first direction DR1 and the second direction DR2. The non-display area NDA may surround the display area DA.

[0102] The bezel area BA of the electronic device DD can cover at least a portion of the non-display area NDA of the display panel DP. The bezel area BA can cover the entire non-display area NDA or a portion of the non-display area NDA. When the area of ​​the non-display area NDA decreases, the area of ​​the bezel area BA can also decrease.

[0103] Multiple connection films (COFs) can be provided. A driver (e.g., a data driver (DDC) for driving the display panel (DP) can be mounted on each of the connection films (COFs). Multiple connection films (COFs) can be bonded to the non-display area (NDA) of the display panel (DP). For example, the connection films (COFs) can be attached to one side of the display panel (DP). In embodiments of this disclosure, the connection films (COFs) can be bonded to the pad (or "solder pad") area (PDA) of the display panel (DP). The pad area (PDA) can be defined within the non-display area (NDA) of the display panel (DP). The connection films (COFs) and the display panel (DP) can be bonded to each other via an anisotropic conductive film (ACF), but are not limited thereto.

[0104] Multiple circuit boards (PCBs) can be provided. Each of the PCBs can be electrically connected to the display panel (DP) via a corresponding portion of the connecting film COF. A chip (e.g., a processor 110 for controlling the operation of the display panel DP) can be mounted on the PCB.

[0105] although Figure 2 The diagram shows twelve connecting membrane COFs, but this disclosure is not limited thereto. Although Figure 2 Two circuit boards (PCBs) are shown, but this disclosure is not limited thereto. For example, the number of connecting films (COFs) and the number of circuit boards (PCBs) can vary depending on the resolution of the display panel (DP), the size of the display panel (DP), and the specifications of the data driver.

[0106] Figure 3 This is a block diagram of an electronic device DD according to an embodiment of the present disclosure.

[0107] Reference Figure 2 and Figure 3 The electronic device DD may include a display panel DP, a scan driver SDC, a data driver DDC, and a control circuit TC.

[0108] The display panel DP includes a display area DA where the image is displayed and a non-display area NDA located outside the display area DA. Multiple pixels PX can be located in the display area DA. A scan driver SDC used to drive the pixels PX can be located in the non-display area NDA.

[0109] The scan driver SDC can be formed directly on the substrate layer using photolithography. For example, the scan driver SDC can be formed together with the pixel driver circuit using the same process used to form the pixel PX.

[0110] The control circuit TC controls the operation of the scan driver SDC and the data driver DDC. The control circuit TC generates image data (RGB) by converting the data format of the input image signal to match the interface specification of the data driver DDC. The control circuit TC outputs the image data (RGB) and various control signals DCS and GCS. The control circuit TC can correspond to... Figure 1B The controller 112-1.

[0111] The scan driver SDC receives a first control signal GCS from the control circuit TC. The first control signal GCS may include a vertical start signal to initiate operation of the scan driver SDC, a clock signal to determine when to output a signal, etc. The scan driver SDC can output multiple scan signals to multiple scan lines SCL1 to SCLn and SSL1 to SSLn. "n" can be an integer greater than or equal to 2. The scan driver SDC may be referred to as a gate driver.

[0112] The data driver DDC receives the second control signal DCS and image data RGB from the control circuit TC. The data driver DDC converts the image data RGB into a data signal and outputs the data signal to multiple data lines DL1 to DLm. "m" can be an integer equal to or greater than 2. The data signal is an analog voltage corresponding to the grayscale value of the image data RGB. The data driver DDC can be configured as a driver chip and installed in... Figure 2 The connecting film COF shown can be mounted on the circuit board PCB, or on the non-display area NDA of the display panel DP.

[0113] The display panel DP may include multiple scan lines SCL1 to SCLn and SSL1 to SSLn, multiple data lines DL1 to DLm, multiple readout lines RL1 to RLm, and multiple pixels PX.

[0114] Scan lines SCL1 to SCLn and SSL1 to SSLn can be arranged along a first direction DR1, and each of the scan lines SCL1 to SCLn and SSL1 to SSLn can extend along a second direction DR2 that intersects the first direction DR1. Scan lines SCL1 to SCLn and SSL1 to SSLn can include first-type scan lines SCL1 to SCLn and second-type scan lines SSL1 to SSLn. The first-type scan lines SCL1 to SCLn can be referred to as first scan lines, write scan lines, or first gate lines, and the second-type scan lines SSL1 to SSLn can be referred to as second scan lines, initialization scan lines, sensing scan lines, or second gate lines.

[0115] Data lines DL1 to DLm can be arranged along the second direction DR2, and each of data lines DL1 to DLm can extend along the first direction DR1. Readout lines RL1 to RLm can be arranged along the second direction DR2, and each of readout lines RL1 to RLm can extend along the first direction DR1. Data lines DL1 to DLm and readout lines RL1 to RLm can cross and be insulated from scan lines SCL1 to SCLn and SSL1 to SSLn.

[0116] Each pixel PX can be connected to a corresponding first-type scan line and a corresponding second-type scan line among scan lines SCL1 to SCLn and SSL1 to SSLn, a corresponding data line among data lines DL1 to DLm, and a corresponding readout line among readout lines RL1 to RLm. For example, a pixel PX arranged in the first row can be connected to the first first-type scan line SCL1 and the first second-type scan line SSL1, and a pixel PX arranged in the nth row can be connected to the nth first-type scan line SCLn and the nth second-type scan line SSLn. A pixel PX arranged in the first column can be connected to the first data line DL1 and the first readout line RL1, and a pixel PX arranged in the mth column can be connected to the mth data line DLm and the mth readout line RLm. However, this is only an example, and the connection relationships between pixels PX and scan lines SCL1 to SCLn and SSL1 to SSLn, data lines DL1 to DLm, and readout lines RLm are not limited to this.

[0117] The display panel DP receives a first power voltage ELVDD and a second power voltage ELVSS. The first power voltage ELVDD can be supplied to the pixel PX. The display panel DP can also receive an initialization voltage Vint. The initialization voltage Vint can be supplied to the pixel PX.

[0118] Figure 4 This is an equivalent circuit diagram of pixel PXij according to an embodiment of the present disclosure.

[0119] exist Figure 4 The example illustrates multiple pixels PX (see [example]). Figure 3 The equivalent circuit diagram of one pixel PXij in the set of pixels PX. Since each of the multiple pixels PX has the same circuit structure, the description of the circuit structure of pixel PXij also applies to each of the remaining pixels PX. For pixel PXij, "i" can be an integer equal to or greater than 1 and equal to or less than "n", and "j" can be an integer equal to or greater than 1 and equal to or less than "m".

[0120] Reference Figure 4Pixel PXij includes a light-emitting element (ED) and a pixel driving circuit (PDC). Pixel PXij can be connected to the i-th scan line SCLi and SSLi among scan lines SCL1 to SCLn and SSL1 to SSLn, the j-th data line DLj among data lines DL1 to DLm, and the j-th readout line RLj among readout lines RL1 to RLm. The i-th scan line SCLi and SSLi can include the i-th first-type scan line SCLi and the i-th second-type scan line SSLi.

[0121] The pixel driving circuit PDC may include a first transistor TR1, a second transistor TR2, a third transistor TR3, and a capacitor Cst. The construction of the pixel driving circuit PDC according to this disclosure is not limited to... Figure 4 The embodiment shown. Figure 4 The pixel driver circuit PDC shown is merely an example, and its construction can be modified and implemented. For example, the pixel driver circuit PDC may also include at least one transistor and at least one capacitor.

[0122] In embodiments of this disclosure, each of the first transistor TR1, the second transistor TR2, and the third transistor TR3 is described as an N-type thin-film transistor. However, this disclosure is not limited thereto. For example, at least any one of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be a P-type thin-film transistor.

[0123] Furthermore, each of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be a transistor having an oxide semiconductor layer. However, this disclosure is not particularly limited thereto. For example, at least one of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer.

[0124] The first transistor TR1 can be electrically connected between the first power line PL1 and the light-emitting element ED. The first transistor TR1 may include a gate electrode connected to the first node N1, a first electrode electrically connected to the first power line PL1, and a second electrode connected to the light-emitting element ED. The light-emitting element ED and the first transistor TR1 can be electrically connected to each other at the second node N2. The first power voltage ELVDD can be provided to the pixel PXij through the first power line PL1.

[0125] The first transistor TR1 can control the amount of current flowing to the light-emitting element ED in response to the voltage of the first node N1. For example, the first transistor TR1 can be turned on when the voltage between the first node N1 and the second node N2 (i.e., the gate-source voltage) is higher than the threshold voltage.

[0126] The second transistor TR2 can be electrically connected between the j-th data line DLj and the first node N1. The second transistor TR2 may include a gate electrode connected to the i-th first type scan line SCLi, a first electrode connected to the j-th data line DLj, and a second electrode connected to the first node N1.

[0127] The second transistor TR2 can transmit the data voltage DS received from the j-th data line DLj to the first node N1 in response to the i-th first-type scan signal SCi provided to the i-th first-type scan line SCLi. For example, the second transistor TR2 can be turned on when the i-th first-type scan signal SCi is at a logic high level.

[0128] A third transistor TR3 may be electrically connected between the second node N2 and the j-th readout line RLj. The third transistor TR3 may include a gate electrode connected to the i-th second-type scan line SSLi, a first electrode connected to the j-th readout line RLj, and a second electrode connected to the second node N2. The third transistor TR3 may connect the second node N2 and the j-th readout line RLj in response to an i-th second-type scan signal SSi provided to the i-th second-type scan line SSLi. For example, the third transistor TR3 may be turned on when the i-th second-type scan signal SSi has a logic high level.

[0129] According to embodiments of this disclosure, during image display operation, the third transistor TR3 can transmit the initialization voltage Vint to the second node N2 in response to the i-th second type scan signal SSi. That is, when the third transistor TR3 is turned on, the second electrode of the first transistor TR1 can be reset to the initialization voltage Vint.

[0130] During sensing operation, the third transistor TR3 can transmit a sensing current corresponding to the voltage of the second node N2 to the j-th readout line RLj in response to the i-th second-type scan signal SSi. Control circuit TC (see reference) Figure 3 It can receive the sensed current to determine the threshold voltage or mobility of the first transistor TR1 and generate compensated image data RGB.

[0131] A capacitor Cst can be connected between the first node N1 and the second node N2. When the data voltage DS is supplied, the initialization voltage Vint can be supplied to the second node N2. In this case, the differential voltage between the data voltage DS and the initialization voltage Vint can be stored in the capacitor Cst. The voltage stored in the capacitor Cst can be used to determine whether the first transistor TR1 is turned on or off.

[0132] A light-emitting element (ED) can be connected between a second node N2 and a second electric field line PL2. A second electric field voltage ELVSS can be applied to the second electric field line PL2. The ED can include a first electrode (e.g., an anode), a second electrode (e.g., a cathode), and a light-emitting layer between the first and second electrodes. For example, the first electrode can be connected to the second node N2, and the second electrode can be connected to the second electric field line PL2. The ED can generate light with a specific brightness corresponding to the amount of current supplied from the first transistor TR1.

[0133] Figure 5 This is a block diagram illustrating some components of a display panel DP according to an embodiment of the present disclosure.

[0134] Reference Figure 5 The image shows a portion of the scan driver SDC and pixels PX. The scan driver SDC may include a first type scan driver SCD and a second type scan driver SSD. The first type scan driver SCD includes multiple first type classes SC-ST1, SC-ST2, and SC-ST3, and the second type scan driver SSD may include multiple second type classes SS-ST1, SS-ST2, and SS-ST3.

[0135] According to embodiments of this disclosure, first type classes SC-ST1, SC-ST2, and SC-ST3 can be arranged along a first direction DR1, and second type classes SS-ST1, SS-ST2, and SS-ST3 can also be arranged along the first direction DR1. Furthermore, the first type classes SC-ST1, SC-ST2, and SC-ST3, as well as the second type classes SS-ST1, SS-ST2, and SS-ST3, can be arranged to be spaced apart from each other on a second direction DR2 that intersects the first direction DR1.

[0136] According to embodiments of this disclosure, the first type levels SC-ST1, SC-ST2, and SC-ST3 and the second type levels SS-ST1, SS-ST2, and SS-ST3 can be arranged to be spaced apart from each other in a direction intersecting the arrangement direction of the pixel row PX-r. In this case, the lines for transmitting signals to the first type levels SC-ST1, SC-ST2, and SC-ST3 and the lines for transmitting signals to the second type levels SS-ST1, SS-ST2, and SS-ST3 can be divided into left and right regions (i.e., the left and right regions in the figures) on the second direction DR2. Therefore, it is easier to use designs that reduce the length of the lines used in the scan driver SDC or reduce the width of the scan driver SDC on the second direction DR2.

[0137] According to embodiments of this disclosure, first type levels SC-ST1, SC-ST2, and SC-ST3 can be electrically connected to multiple first type scan lines SCLs, respectively. Furthermore, second type levels SS-ST1, SS-ST2, and SS-ST3 can be electrically connected to multiple second type scan lines SSLs, respectively. For example, a first type level SC-ST1 can be connected to “Y” first type scan lines SCLs to output “Y” first type scan signals, and a second type level SS-ST1 can be connected to “Y” second type scan lines SSLs to output “Y” second type scan signals. “Y” can be an integer of 2 or greater.

[0138] Also refer to Figure 4 At least one of the first type stages SC-ST1, SC-ST2, and SC-ST3 can output a first type scan signal SCi to the gate electrode of the second transistor TR2, and at least one of the second type stages SS-ST1, SS-ST2, and SS-ST3 can output a second type scan signal SSi to the gate electrode of the third transistor TR3. In another embodiment of the invention, the functions of the first type stages SC-ST1, SC-ST2, and SC-ST3 and the second type stages SS-ST1, SS-ST2, and SS-ST3 can be reversed. In this case, at least one of the first type stages can output a first type scan signal to the gate electrode of the third transistor TR3, and at least one of the second type stages can output a second type scan signal to the gate electrode of the second transistor TR2.

[0139] exist Figure 5 The illustration shows, by way of example, a first type level SC-ST1 electrically connected to six first type scan lines SCLs and a second type level SS-ST1 electrically connected to six second type scan lines SSLs, but this disclosure is not particularly limited thereto. For example, two or more first type scan lines SCLs may be connected to a first type level SC-ST1, and two or more second type scan lines SSLs may be connected to a second type level SS-ST1.

[0140] According to embodiments of this disclosure, a plurality of pixels PX can be arranged in a first direction DR1 and a second direction DR2. Among the plurality of pixels PX, pixels PX-r in a row arranged in the second direction DR2 (hereinafter referred to as a pixel row) can be connected to a first type level SC-ST1 and a second type level SS-ST1. Furthermore, the pixels PX include pixels PXG1 in a “Y” row arranged in the first direction DR1 (hereinafter referred to as a first pixel group), and the first pixel group PXG1 can be connected to a first type level SC-ST1 and a second type level SS-ST1.

[0141] The first pixel group PXG1, comprising six rows of PX-r, can be connected to the first first type level SC-ST1 and the first second type level SS-ST1. The second pixel group PXG2, comprising the next six rows of PX-r, can be connected to the second first type level SC-ST2 and the second second type level SS-ST2. The third pixel group PXG3, comprising the next six rows of PX-r, can be connected to the third first type level SC-ST3 and the third second type level SS-ST3.

[0142] According to embodiments of this disclosure, a level (e.g., a first type level SC-ST1) can control the operation of a pixel group (e.g., a first pixel group PXG1) comprising two or more pixel rows PX-r. That is, the total number of levels can be less than the number of rows of pixels PX. Therefore, the amount of space required in the non-display area NDA (see...) can be reduced. Figure 3 This reduces the number of transistors, capacitors, and lines (e.g., clock lines) in the display panel. As a result, the display panel's display output (DP) can be reduced (see...). Figure 2 The non-display area NDA (see) Figure 3 The width of ).

[0143] Figure 6A This is a view showing a scan driver SDC according to an embodiment of the present disclosure. Figure 6B This is an equivalent circuit diagram showing a stage ST[N] according to an embodiment of the present disclosure.

[0144] exist Figure 6A The example illustrates three levels ST[N-1], ST[N], and ST[N+1]. “N” can be an integer equal to or greater than 2. The three levels ST[N-1], ST[N], and ST[N+1] can be the first type levels SC-ST1, SC-ST2, and SC-ST3 (see example). Figure 5 ) or second-class SS-ST1, SS-ST2 and SS-ST3 (see Figure 5 ).

[0145] exist Figure 6B An equivalent circuit diagram of a stage ST[N] is shown by way of example. Since the remaining stages ST[N-1] and ST[N+1] also include substantially the same construction, their repeated descriptions are omitted. The construction of a stage ST[N] according to this disclosure is not limited to... Figure 6B The embodiment shown. Figure 6B The stage ST[N] shown is merely an example, and the circuit construction of a stage ST[N] can be modified and implemented.

[0146] Reference Figure 6ALevels ST[N-1], ST[N], and ST[N+1] can be sequentially referred to as Level 1 ST[N-1], Level 2 ST[N], and Level 3 ST[N+1]. For clarity, Level 2 ST[N] can be referred to as the reference level or level, Level 1 ST[N-1] can be referred to as the first peripheral level, and Level 3 ST[N+1] can be referred to as the second peripheral level. In the following text, Level 2 ST[N] can be referred to as level.

[0147] Level ST[N] may include the first input terminal IN1, the second input terminal IN2, the third input terminal IN3, the fourth input terminal IN4, the fifth input terminal IN5 and the sixth input terminal IN6, the first clock terminal CIN1, the second clock terminal CIN2, the third clock terminal CIN3, the fourth clock terminal CIN4, the fifth clock terminal CIN5 and the sixth clock terminal CIN6, the first control terminal CINa, the second control terminal CINb, the first output terminal OUT1, the second output terminal OUT2, the third output terminal OUT3, the fourth output terminal OUT4, the fifth output terminal OUT5 and the sixth output terminal OUT6, and the carry output terminal COUT.

[0148] The first input terminal IN1 of stage ST[N] can receive the carry signal CR[N-1] output from the previous stage (e.g., the first stage ST[N-1]). When stage ST[N] is the first stage, the first input terminal IN1 can receive the start signal output from the dummy stage preceding the first stage.

[0149] The carry signal CR[N-1] can be referred to as the previous carry signal or the first carry signal, and will be referred to as the first carry signal CR[N-1] below. The first stage ST[N-1] and the stage ST[N] can be electrically connected to the first carry line CRL1, and the first carry line CRL1 can also be referred to as the first peripheral carry line. The first carry signal CR[N-1] generated at the first stage ST[N-1] can be transmitted to the stage ST[N] through the first carry line CRL1.

[0150] The second input terminal IN2 of stage ST[N] can receive the carry signal CR[N+1] output from the next stage (e.g., the third stage ST[N+1]). When stage ST[N] is the last stage, the second input terminal IN2 can receive the carry signal output from the dummy stage after the last stage.

[0151] The carry signal CR[N+1] can be referred to as the next carry signal or the third carry signal, and hereinafter referred to as the third carry signal CR[N+1]. The third stage ST[N+1] and the stage ST[N] can be electrically connected to the third carry line CRL3, and the third carry line CRL3 can be referred to as the second peripheral carry line. The third carry signal CR[N+1] generated in the third stage ST[N+1] can be transmitted to the stage ST[N] through the third carry line CRL3.

[0152] The third input terminal IN3 of stage ST[N] can be supplied with a first high voltage VDD1, and the fourth input terminal IN4 can be supplied with a second high voltage VDD2. The voltage level of the second high voltage VDD2 can be higher than the voltage level of the first high voltage VDD1, but this disclosure is not particularly limited thereto. For example, the first high voltage VDD1 can be 15V, and the second high voltage VDD2 can be 25V.

[0153] The fifth input terminal IN5 of stage ST[N] can receive a first low voltage VSS1, and the sixth input terminal IN6 can receive a second low voltage VSS2. The voltage level of the first low voltage VSS1 can be the same as or different from the voltage level of the second low voltage VSS2.

[0154] Stage ST[N] can receive the boost clock signal BCK through the first control terminal CINa, and can receive the carry clock signal CR_CK through the second control terminal CINb. Stage ST[N] can receive the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the fifth clock signal CK5, and the sixth clock signal CK6 through the first clock terminal CIN1, the second clock terminal CIN2, the third clock terminal CIN3, the fourth clock terminal CIN4, the fifth clock terminal CIN5, and the sixth clock terminal CIN6, respectively. In the embodiments of this disclosure, the first clock terminal CIN1, the second clock terminal CIN2, the third clock terminal CIN3, the fourth clock terminal CIN4, the fifth clock terminal CIN5, and the sixth clock terminal CIN6 of each of the first stage ST[N-1] and the third stage ST[N+1] can receive clock signals with an out-of-phase phase to the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the fifth clock signal CK5, and the sixth clock signal CK6, respectively.

[0155] The carry output terminal COUT of stage ST[N] can output a carry signal CR[N]. The carry signal CR[N] can be transmitted to the first stage ST[N-1] and the third stage ST[N+1]. The carry signal CR[N] can be referred to as the second carry signal, and hereinafter referred to as the second carry signal CR[N]. The first stage ST[N-1], stage ST[N], and third stage ST[N+1] can be electrically connected to the second carry line CRL2. The second carry signal CR[N] generated in stage ST[N] can be transmitted to the first stage ST[N-1] and the third stage ST[N+1] through the second carry line CRL2.

[0156] The first output terminal OUT1, the second output terminal OUT2, the third output terminal OUT3, the fourth output terminal OUT4, the fifth output terminal OUT5, and the sixth output terminal OUT6 of the stage ST[N] can respectively output the first scan signal SS1[N], the second scan signal SS2[N], the third scan signal SS3[N], the fourth scan signal SS4[N], the fifth scan signal SS5[N], and the sixth scan signal SS6[N]. The first scan signal SS1[N], the second scan signal SS2[N], the third scan signal SS3[N], the fourth scan signal SS4[N], the fifth scan signal SS5[N], and the sixth scan signal SS6[N] can be provided to pixels in six rows of, for example, the second pixel group PXG2.

[0157] The first scan signal SS1[N], the second scan signal SS2[N], the third scan signal SS3[N], the fourth scan signal SS4[N], the fifth scan signal SS5[N], and the sixth scan signal SS6[N] can be respectively passed through the first type of scan lines SCLs (see Figure 5 The first scan signal (or first type scan signal) provided by ) is used. In an embodiment, the first scan signal SS1[N], the second scan signal SS2[N], the third scan signal SS3[N], the fourth scan signal SS4[N], the fifth scan signal SS5[N], and the sixth scan signal SS6[N] can be provided by second type scan lines SSLs (see Figure 5 The second scan signal (or second type scan signal) provided.

[0158] Reference Figure 6B A level ST[N] may include a first node QC, a second node QB, a third node N-CQ, a fourth node NB, and multiple partition nodes Q-1 to Q-6. The first node QC may be called a Q node, the multiple partition nodes Q-1 to Q-6 may be called partition Q nodes, and the second node QB may be called a QB node.

[0159] In addition, a stage ST[N] may also include a first circuit S101, a second circuit S102, a third circuit S103, a fourth circuit S104, a fifth circuit S105, a sixth circuit S106, a seventh circuit S107, an eighth circuit S108, and a ninth circuit S109.

[0160] The first circuit S101 can control the voltage of the first node QC and can be referred to as the first node control circuit. The first circuit S101 may include a first transistor T11, a second transistor T12, a third transistor T13, and a fourth transistor T14.

[0161] The first transistor T11 and the second transistor T12 can be connected in series, and both transistors T11 and T12 can have a dual-gate structure. The first transistor T11 and the second transistor T12 can be connected between the first input terminal IN1 and the first node QC. Furthermore, both the gate electrode of the first transistor T11 and the gate electrode of the second transistor T12 can be connected to the first input terminal IN1. The fourth input terminal IN4 can be connected between the first transistor T11 and the second transistor T12. The first transistor T11 and the second transistor T12 are turned on in response to the gate on-state voltage (e.g., a logic high level) of the first carry signal CR[N-1], and the second transistor T12 can transfer a second high voltage VDD2 to the first node QC. The operation of transferring the second high voltage VDD2 to the first node QC can be referred to as a pre-charge operation or a first-stage boost operation. The third transistor T13 and the fourth transistor T14 can be connected in series, and both transistors T13 and T14 can have a dual-gate structure. The third transistor T13 and the fourth transistor T14 can be connected between the first node QC and the sixth input terminal IN6. Furthermore, the gate electrodes of the third transistor T13 and the fourth transistor T14 can be connected to the second input terminal IN2. The third transistor T13 and the fourth transistor T14 can transmit the second low voltage VSS2 to the first node QC in response to the gate on-state voltage (e.g., logic high level) of the third carry signal CR[N+1].

[0162] The second circuit S102 may include a first transistor T21 and a second transistor T22. The first transistor T21 and the second transistor T22 may be connected in series, and the first transistor T21 and the second transistor T22 may be connected between the first node QC and the sixth input terminal IN6. Furthermore, the gate electrode of the first transistor T21 and the gate electrode of the second transistor T22 may be connected to the second node QB. The first transistor T21 and the second transistor T22 may transmit a second low voltage VSS2 to the first node QC in response to the voltage at the second node QB. Therefore, the second circuit S102 may be referred to as a first node stabilization circuit.

[0163] The third circuit S103 may include a first transistor T31, a second transistor T32, a third transistor T33, a fourth transistor T34, and a fifth transistor T35.

[0164] The first transistor T31 can be connected between the second node QB and the third input terminal IN3. The second transistor T32 and the third transistor T33 can be connected in series with each other, and the gate electrodes of the second transistor T32 and the third transistor T33 can be connected to the third input terminal IN3. Furthermore, the second transistor T32 and the third transistor T33 can be connected between the third input terminal IN3 and the gate electrode of the first transistor T31.

[0165] The fourth transistor T34 can be connected between the gate electrode of the first transistor T31 and the fifth input terminal IN5, and the fifth transistor T35 can be connected between the second node QB and the sixth input terminal IN6. The gate electrodes of the fourth transistor T34 and the fifth transistor T35 can be connected to the first node QC.

[0166] The second transistor T32 and the third transistor T33, in response to the first high voltage VDD1, transfer the first high voltage VDD1 to the gate electrode of the first transistor T31. The operation of the fourth transistor T34 is controlled in response to the voltage of the first node QC. When the fourth transistor T34 is turned on, the first low voltage VSS1 can be transferred to the gate electrode of the first transistor T31.

[0167] The first transistor T31 can transfer a first high voltage VDD1 to the second node QB in response to the voltage at its gate electrode. The operation of the fifth transistor T35 is controlled in response to the voltage at the first node QC. When the fifth transistor T35 is turned on, a second low voltage VSS2 can be transferred to the second node QB.

[0168] The fourth circuit S104 may include a first transistor T41, a second transistor T42, and a capacitor C4.

[0169] The first transistor T41 can be connected between the first control terminal CINa and the fourth node NB. The gate electrode of the first transistor T41 can be connected to the first node QC. The operation of the first transistor T41 is controlled in response to the voltage of the first node QC. When the first transistor T41 is turned on, a logic high-level voltage can be provided to the fourth node NB.

[0170] The second transistor T42 can be connected between the fourth node NB and the sixth input terminal IN6. The gate electrode of the second transistor T42 can be connected to the second node QB. The operation of the second transistor T42 is controlled in response to the voltage of the second node QB. When the second transistor T42 is turned on, a second low voltage VSS2 can be provided to the fourth node NB.

[0171] Capacitor C4 is connected to the gate electrode of the first transistor T41 and the fourth node NB. Capacitor C4 can increase (boost) the voltage of the first node QC in response to an increase in the voltage of the fourth node NB; this can be referred to as a secondary boost operation.

[0172] The fifth circuit S105 may include a first transistor T51 and a second transistor T52.

[0173] The first transistor T51 can be connected between the second control terminal CINb and the carry output terminal COUT. The gate electrode of the first transistor T51 can be connected to the first node QC. The operation of the first transistor T51 is controlled in response to the voltage of the first node QC. When the first transistor T51 is turned on, a logic high level voltage of the second carry signal CR[N] can be provided to the carry output terminal COUT.

[0174] The second transistor T52 can be connected between the carry output terminal COUT and the sixth input terminal IN6. The gate electrode of the second transistor T52 can be connected to the second node QB. The operation of the second transistor T52 is controlled in response to the voltage of the second node QB. When the second transistor T52 is turned on, a second low voltage VSS2 can be provided to the carry output terminal COUT.

[0175] The sixth circuit S106 can control the voltage of the third node N-CQ and can be referred to as the third node control circuit. The sixth circuit S106 may include a first transistor T61, a second transistor T62, and a third transistor T63.

[0176] The first transistor T61 and the second transistor T62 can be connected in series, and both transistors T61 and T62 can have a dual-gate structure. The first transistor T61 and the second transistor T62 can be connected between the fourth input terminal IN4 and the third node N-CQ. Furthermore, the gate electrode of the first transistor T61 and the gate electrode of the second transistor T62 can be connected to the first input terminal IN1. The first transistor T61 and the second transistor T62 can transmit a second high voltage VDD2 to the third node N-CQ in response to the gate on-state voltage (e.g., a logic high level) of the first carry signal CR[N-1].

[0177] The third transistor T63 can be connected between the third node N-CQ and the third input terminal IN3. Furthermore, the gate electrode of the third transistor T63 can be connected to the second input terminal IN2. The third transistor T63 can transmit a first high voltage VDD1 to the third node N-CQ in response to the gate on-state voltage (e.g., a logic high level) of the third carry signal CR[N+1].

[0178] The seventh circuit S107 may include transistor T71. Transistor T71 may be connected between the third input terminal IN3 and the third node N-CQ. The gate electrode of transistor T71 may be connected to the fourth node NB. Transistor T71 may provide a first high voltage VDD1 to the third node N-CQ in response to the voltage of the fourth node NB.

[0179] The eighth circuit S108 may include a first transistor T81 and a second transistor T82.

[0180] The first transistor T81 and the second transistor T82 can be connected in series, and the first transistor T81 and the second transistor T82 can be connected between the third node N-CQ and the fifth input terminal IN5. Furthermore, the gate electrodes of both the first transistor T81 and the second transistor T82 can be connected to the second node QB. The first transistor T81 and the second transistor T82 can transmit a first low voltage VSS1 to the third node N-CQ in response to the voltage at the second node QB. Therefore, the eighth circuit S108 can be referred to as the third node stabilization circuit.

[0181] The ninth circuit S109 may include multiple output circuits S109s. In embodiments of this disclosure, since one stage ST[N] outputs six scan signals, the ninth circuit S109 may include six output circuits S109s. Figure 6B The example shows a total of two output circuits: the first output circuit and the last output circuit (e.g., the sixth output circuit).

[0182] Each of the output circuits S109s may include a first transistor T91, a second transistor T92, a third transistor T93, and a capacitor C9. The first output circuit S109s is described below, and the remaining output circuits S109s also include substantially the same construction, therefore their repeated description is omitted.

[0183] The first transistor T91 can be connected between the first clock terminal CIN1 and the first output terminal OUT1. The gate electrode of the first transistor T91 can be connected to the partition node Q-1. The second transistor T92 can be connected between the first node QC and the partition node Q-1. The gate electrode of the second transistor T92 can be connected to the third node N-CQ. The second transistor T92 can connect the first node QC and the partition node Q-1 in response to the voltage of the third node N-CQ, or it can disconnect the first node QC and the partition node Q-1.

[0184] The operation of the first transistor T91 is controlled in response to the voltage of the partition node Q-1. When the first transistor T91 is turned on, the logic high level voltage of the first scan signal SS1[N] can be output to the first output terminal OUT1.

[0185] According to embodiments of this disclosure, transistor T71 can be turned on in a timing sequence when the fourth node NB is boosted to transfer the first high voltage VDD1 to the third node N-CQ. During the timing sequence of the fourth node NB being boosted, the voltage of the first node QC can be higher than the first high voltage VDD1 of the third node N-CQ. Therefore, the second transistor T92 can be turned off. The second transistor T92 can separate the first node QC and the partition node Q-1 in response to the voltage of the third node N-CQ.

[0186] When signals are output to the first output terminal OUT1, the second output terminal OUT2 (not shown), the third output terminal OUT3 (not shown), the fourth output terminal OUT4 (not shown), the fifth output terminal OUT5 (not shown), and the sixth output terminal OUT6, the first node QC and the dividing node Q-1 can be electrically isolated from each other, and the dividing nodes Q-1 to Q-6 can also be electrically isolated from each other. Therefore, even if the voltage of the dividing node Q-1 is coupled and changed according to the signal output to the first output terminal OUT1, the influence on other nodes can be eliminated. For example, other nodes can be the first node QC and any of the dividing nodes Q-1 to Q-6 other than the dividing node Q-1. Therefore, horizontal line defects caused by differences in brightness relative to the line can be eliminated.

[0187] According to an embodiment of this disclosure, when the second low voltage VSS2 is transmitted to the first node QC in response to the gate turn-on voltage of the third carry signal CR[N+1], the voltage of the first node QC can be lower than the voltage of the third node N-CQ. In this case, the second transistor T92 is turned on to connect to the first node QC, and the partition node Q-1 can be discharged.

[0188] The third transistor T93 can be connected between the first output terminal OUT1 and the fifth input terminal IN5. The gate electrode of the third transistor T93 can be connected to the second node QB. The operation of the third transistor T93 is controlled in response to the voltage of the second node QB. When the third transistor T93 is turned on, a first low voltage VSS1 can be provided to the first output terminal OUT1.

[0189] Capacitor C9 is connected to partition node Q-1 and fourth node NB. Capacitor C9 can increase (boost) the voltage of partition node Q-1 in response to an increase in the voltage of fourth node NB. When the voltage of partition node Q-1 increases, a first scan signal SS1[N] with a high voltage can be output without distortion. Figure 7 This is a timing diagram used to describe the operation of the level in the first mode MD1 according to an embodiment of the present disclosure. Figure 8 It is a timing diagram of a plurality of clock signals used to describe the operation of a level in a second mode MD2 according to an embodiment of the present disclosure.

[0190] Reference Figure 1A , Figure 7 and Figure 8 The display panel DP can selectively operate in either a first mode MD1 or a second mode MD2. For example, the first mode MD1 can be a normal driving mode driven at a first frequency, and the second mode MD2 can be a high-frequency driving mode driven at a second frequency higher than the first frequency. For example, the first frequency can be 240Hz, and the second frequency can be 480Hz. However, the first and second frequencies described above are merely examples, and are not particularly limited to the examples above.

[0191] Reference Figure 7 The example illustrates the first carry signal CR[N-1], the second carry signal CR[N], the third carry signal CR[N+1], the boost clock signal BCK, the carry clock signal CR_CK, and the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the fifth clock signal CK5, and the sixth clock signal CK6 under the first mode MD1.

[0192] Reference Figure 8 The example illustrates the first carry signal CR[N-1], the second carry signal CR[N], the third carry signal CR[N+1], the boost clock signal BCKa, the carry clock signal CR_CKa, and the first clock signal CK1a, the second clock signal CK2a, the third clock signal CK3a, the fourth clock signal CK4a, the fifth clock signal CK5a, and the sixth clock signal CK6a in the second mode MD2.

[0193] Reference Figure 7 and Figure 8 In the first mode MD1, the period CY1 of the boost clock signal BCK can be longer than the period CY1a of the boost clock signal BCKa in the second mode MD2. For example, the period CY1 can be twice the period CY1a. Furthermore, the period CY2 of the carry clock signal CR_CK in the first mode MD1 can be longer than the period CY2a of the carry clock signal CR_CKa in the second mode MD2. For example, the period CY2 can be twice the period CY2a. In other words, in the second mode MD2, the clock period can be reduced.

[0194] According to embodiments of this disclosure, at least some of multiple scan lines can be driven (e.g., activated) simultaneously for low-power or high-speed driving. For example, two scan lines can be driven simultaneously, and the second mode MD2 can be referred to as a dual-line gate drive mode. In embodiments of this disclosure, the first mode MD1 can be a high-resolution mode, and the second mode MD2 can be a high scan rate mode.

[0195] In the first mode MD1, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the fifth clock signal CK5, and the sixth clock signal CK6 can have different phases. That is, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the fifth clock signal CK5, and the sixth clock signal CK6 can have waveforms shifted by a specific interval. Correspondingly, the first scan signal SS1, the second scan signal SS2, the third scan signal SS3, the fourth clock signal CK4, the fifth clock signal CK5, and the sixth scan signal SS6, which are output synchronously with the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the fifth clock signal CK5, and the sixth scan signal SS6, can also have different phases. The first scan signal SS1, the second scan signal SS2, the third scan signal SS3, the fourth scan signal SS4, the fifth scan signal SS5, and the sixth scan signal SS6 can also be referred to as the first mode scan signal.

[0196] The first scan signal SS1, the second scan signal SS2, the third scan signal SS3, the fourth scan signal SS4, the fifth scan signal SS5, and the sixth scan signal SS6 can each pass through the first type of scan lines SCLs (see...). Figure 5 The first scan signal (or first type scan signal) provided by the system. In an embodiment, the first scan signal SS1, the second scan signal SS2, the third scan signal SS3, the fourth scan signal SS4, the fifth scan signal SS5, and the sixth scan signal SS6 may be provided by second type scan lines SSLs (see...). Figure 5 The second scan signal (or second type scan signal) provided.

[0197] In the second mode MD2, some of the clock signals CK1a, CK2a, CK3a, CK4a, CK5a, and CK6a can have the same phase. For example, the waveforms of the first clock signal CK1a and the second clock signal CK2a can be identical. The third clock signal CK3a can have a waveform shifted by a specific time relative to the first clock signal CK1a, and the waveforms of the third clock signal CK3a and the fourth clock signal CK4a can be identical. Furthermore, the waveforms of the fifth clock signal CK5a and the sixth clock signal CK6a can be identical.

[0198] In the second mode MD2, some of the first scan signals SS1a, second scan signals SS2a, third scan signals SS3a, fourth clock signals CK4a, fifth clock signals CK5a, and sixth scan signals SS6a, which are output synchronously with the first clock signal CK1a, second clock signal CK2a, third clock signal CK3a, fourth clock signal CK4a, fifth clock signal CK5a, and sixth clock signal CK6a, can have the same waveform. For example, the first scan signal SS1a and the second scan signal SS2a can be superimposed on each other and can have substantially the same waveform. In this case, in the second mode MD2, the data voltage DS (see...) Figure 4 It can simultaneously provide pixels in one row that receive the first scan signal SS1a and pixels in another row that receive the second scan signal SS2a.

[0199] The third scan signal SS3a and the fourth scan signal SS4a can be superimposed on each other and have substantially the same waveform. The fifth scan signal SS5a and the sixth scan signal SS6a can be superimposed on each other and have substantially the same waveform. The first scan signal SS1a, the second scan signal SS2a, the third scan signal SS3a, the fourth scan signal SS4a, the fifth scan signal SS5a, and the sixth scan signal SS6a can also be referred to as the second mode scan signal.

[0200] The first scan signal SS1a, the second scan signal SS2a, the third scan signal SS3a, the fourth scan signal SS4a, the fifth scan signal SS5a, and the sixth scan signal SS6a can be respectively passed through the first type of scan lines SCLs (see...). Figure 5The first scan signal (or first type scan signal) provided by the system. In an embodiment, the first scan signal SS1a, the second scan signal SS2a, the third scan signal SS3a, the fourth scan signal SS4a, the fifth scan signal SS5a, and the sixth scan signal SS6a may be provided by the second type scan lines SSLs (see [link to documentation]). Figure 5 The second scan signal (or second type scan signal) provided.

[0201] Figure 9 This is a view showing the activation state and brightness changes of a first type scan signal SC and a second type scan signal SS according to an embodiment of the present disclosure. Figure 10 This is a view illustrating the activation state and brightness changes of a first type scan signal SCa and a second type scan signal SSa according to embodiments of the present disclosure. The first type scan signal SC and the first type scan signal SCa may be provided to... Figure 4 The signal of the first type scan line SCLi shown in the figure, the second type scan signal SS and the second type scan signal SSa can be provided to Figure 4 The signal of the second type scan line SSLi shown in the figure.

[0202] Reference Figure 1A , Figure 9 and Figure 10 The display panel DP can operate in a mode driven by a variable frame rate (hereinafter referred to as Mode 3, MD3). For example, the variable frame rate can be modified in various ways from 1Hz to 240Hz, but is not particularly limited thereto. Figure 9 The brightness of the first type scan signal SC, the second type scan signal SS, and the display panel DP are shown as an example when driven at 240Hz. Figure 10 The brightness of the first type scan signal SCa, the second type scan signal SSa, and the display panel DP are shown as an example when driven at 60Hz.

[0203] Reference Figure 9 and Figure 10 When driving the display panel DP at 240Hz, during a unit time TU, the first type scan signal SC may include four write cycle portions WP, and the second type scan signal SS may include four initialization cycle portions IP. Furthermore, when driving the display panel DP at 60Hz, the first type scan signal SCa may include one write cycle portion WPa, and the second type scan signal SSa may include four initialization cycle portions IP.

[0204] In the write cycle portion WP or WPa, the first type scan signal SC or SCa may have a waveform that repeatedly transitions between logic high and logic low levels, and in the remaining portion excluding the write cycle portion WP or WPa, the first type scan signal SC or SCa may have a logic low level. Furthermore, in the initialization cycle portion IP, the second type scan signal SS or SSa may have a waveform that repeatedly transitions between logic high and logic low levels.

[0205] Refer to together Figure 5 The multiple first-type stages SC-ST1, SC-ST2, and SC-ST3 of the first-type scan driver SCD that generate the first-type scan signal SC or SCa, and the multiple second-type stages SS-ST1, SS-ST2, and SS-ST3 of the second-type scan driver SSD that generate the second-type scan signal SS or SSa, can be separated from each other. Therefore, the operation of the first-type scan signal SC or SCa and the operation of the second-type scan signal SS or SSa can be separated from each other. As a result, within a unit time TU, the number of initialization cycle portions IP can be adjusted independently, regardless of the number of write cycle portions WP or WPa, which varies according to the operating frequency of the display panel DP. In this case, the difference in optical waveforms according to the operating frequency of the display panel DP can be reduced, and consequently, the difference in brightness according to the operating frequency of the display panel DP can be reduced. That is, the image display quality of the display panel DP can be improved.

[0206] Figure 7 , Figure 8 , Figure 9 and Figure 10 The driving modes described herein can be applied to the display panel DP in various combinations. For example, in embodiments of this disclosure, the display panel DP can operate under any of the first mode MD1, the second mode MD2, and the third mode MD3. The first mode MD1 may correspond to a mode driven at 240Hz in the third mode MD3. In embodiments of this disclosure, the display panel DP can operate under either the first mode MD1 or the third mode MD3. In this case, the first mode MD1 may be a general driving mode driven at a fixed frequency, and the third mode MD3 may be a variable driving mode driven at a variable frequency. In other embodiments of this disclosure, the display panel DP can operate under either the first mode MD1 or the second mode MD2. In embodiments of this disclosure, the display panel DP may operate only under the first mode MD1. In other embodiments of this disclosure, the display panel DP may operate only under the third mode MD3.

[0207] Figure 11 This is a plan view of a portion of a display panel DP according to an embodiment of the present disclosure.

[0208] Reference Figure 11 The display panel DP may include multiple pixels PX1, PX2, PX3, PX4, PX5 and PX6, a group level GST, multiple first type scan lines SCL1 to SCL6, multiple second type scan lines SSL1 to SSL6, multiple first type clock lines CKLT1, multiple second type clock lines CKLT2, multiple connection lines CLS1, CLS2, CLS31, CLS32, CLS41 and CLS42, multiple carry clock lines CRCKL, multiple signal lines SL and a second power line PL2.

[0209] Multiple pixels PX1, PX2, PX3, PX4, PX5, and PX6 can be disposed in the display area DA. Pixels PX1, PX2, PX3, PX4, PX5, and PX6 can be arranged along a first direction DR1. That is, pixels PX1, PX2, PX3, PX4, PX5, and PX6 can be arranged in different rows. Pixels PX1, PX2, PX3, PX4, PX5, and PX6 may include a first pixel PX1, a second pixel PX2, a third pixel PX3, a fourth pixel PX4, a fifth pixel PX5, and a sixth pixel PX6 arranged sequentially along the first direction DR1.

[0210] The first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 can receive scan signals provided from a group-level GST. For example, a group-level GST may include a first type level SC-ST and a second type level SS-ST, and the first type level SC-ST can provide first type scan signals to first type scan lines SCL1 to SCL6, and the second type level SS-ST can provide second type scan signals to second type scan lines SSL1 to SSL6.

[0211] The non-display area NDA can be divided into multiple regions. For example, the non-display area NDA may include a first non-display area NDA1, a second non-display area NDA2, a third non-display area NDA3, a fourth non-display area NDA4, a fifth non-display area NDA5, a sixth non-display area NDA6, and an introduction area INDA. The first non-display area NDA1, the second non-display area NDA2, the third non-display area NDA3, the fourth non-display area NDA4, the fifth non-display area NDA5, the sixth non-display area NDA6, and the introduction area INDA can be sequentially defined along the second direction DR2 in the direction facing the display area DA. That is, the first non-display area NDA1 can be closest to the edge of the display panel DP, and the introduction area INDA can be closest to the display area DA.

[0212] The second power line PL2 can be set in the first non-display area NDA1. The second power voltage ELVSS (see...) Figure 4 A second power line PL2 can be applied. The second power line PL2 can be electrically connected to pixel PXij (see...). Figure 4 ).

[0213] The first type clock line CKLT1 can be located in the second non-display area NDA2. Some of the first type clock lines CKLT1 can be the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the fifth clock signal CK5, and the sixth clock signal CK6 provided to the first type level SC-ST (see...). Figure 6A () line.

[0214] The first type of clock line CKLT1 may include a first clock line CLK1, a second clock line CLK2, a third clock line CLK3, a fourth clock line CLK4, a fifth clock line CLK5, and a sixth clock line CLK6. Each of the first clock lines CLK1, CLK2, CLK3, CLK4, CLK5, and CLK6 extends along a first direction DR1, and the first clock lines CLK1, CLK2, CLK3, CLK4, CLK5, and CLK6 may be arranged along a second direction DR2. The six clock lines in the first type of clock line CKLT1 arranged to the right of the sixth clock line CLK6 may be used to transmit clock signals to... Figure 11 The next set of levels of GST is shown as the first type level line.

[0215] The first type-level SC-ST can be located in the third non-display area NDA3. That is, since the first type-level SC-ST is set directly adjacent to the first type clock line CKLT1, the line design length in the circuit can be reduced or minimized. The first type-level SC-ST may include multiple first buffer circuits BC1 and first logic circuits LC1. The first buffer circuits BC1 can respectively correspond to... Figure 6B The six output circuits S109s shown are illustrated. The first logic circuit LC1 can correspond to... Figure 6B The diagram shows the remainder of a stage ST[N] excluding the six output circuits S109s. However, this is merely an example, and each of the first buffer circuits BC1 may include only the first transistor T91, and some of the components represented by the output circuits S109s may be omitted, or other components may be included in addition to those represented by the output circuits S109s.

[0216] According to an embodiment of this disclosure, a first buffer circuit BC1 can be disposed between the first logic circuit LC1 and the first type clock line CKLT1. This is because the first buffer circuit BC1 receives the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the fifth clock signal CK5, and the sixth clock signal CK6 (see...) from the first type clock line CKLT1. Figure 6A Therefore, the first type clock line CKLT1 can be set to be closest to the first buffer circuit BC1. Thus, the length of the multiple first clock connection lines CLS1 that connect the first type clock line CKLT1 to the first buffer circuit BC1 can be minimized.

[0217] According to embodiments of this disclosure, the first buffer circuit BC1 can be arranged sequentially along the first direction DR1. That is, the arrangement direction of the first buffer circuit BC1 can be the same as the arrangement direction of the first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6. In this case, the first buffer circuit BC1 and the first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 can be arranged to face each other in the second direction DR2. Therefore, the length of the first type scan lines SCL1 to SCL6, which are connected to the first buffer circuit BC1 in a one-to-one correspondence and extend toward the first pixel to the sixth pixel PX1, PX2, PX3, PX4, PX5, and PX6, can be minimized.

[0218] The carry clock line CRCKL and the signal line SL can be located in the fourth non-display area NDA4. In embodiments of this disclosure, the signal line SL can be spaced apart from the display area DA, and the carry clock line CRCKL is located between the signal line SL and the display area DA. That is, the distance between the first type level SC-ST and the signal line SL can be less than the distance between the first type level SC-ST and the carry clock line CRCKL.

[0219] The second type-level SS-ST can be located in the fifth non-display area NDA5. The second type clock line CKLT2 can be located in the sixth non-display area NDA6. That is, since the second type-level SS-ST is set directly adjacent to the second type clock line CKLT2, the line design length in the circuit can be reduced or minimized. The second type-level SS-ST can include multiple second buffer circuits BC2 and second logic circuits LC2. The second buffer circuit BC2 can respectively correspond to... Figure 6B The six output circuits S109s shown are illustrated. The second logic circuit LC2 can correspond to... Figure 6BThe remaining portion of a stage ST[N] shown here, excluding the six output circuits S109s.

[0220] According to embodiments of this disclosure, a second buffer circuit BC2 can be disposed between the second logic circuit LC2 and the second type clock line CKLT2. The first type stage SC-ST and the second type stage SS-ST can have a structure that is linearly symmetrical to each other with respect to an imaginary line extending along the first direction DR1. The second buffer circuit BC2 can receive the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the fifth clock signal CK5, and the sixth clock signal CK6 from the second type clock line CKLT2, and can therefore be positioned closest to the second type clock line CKLT2. Therefore, the length of the multiple second clock connection lines CLS2 connecting the second type clock line CKLT2 to the second buffer circuit BC2 can be minimized.

[0221] According to embodiments of this disclosure, the second buffer circuit BC2 can be arranged sequentially along the first direction DR1. That is, the arrangement direction of the second buffer circuit BC2 can be the same as the arrangement direction of the first pixel PX1, second pixel PX2, third pixel PX3, fourth pixel PX4, fifth pixel PX5, and sixth pixel PX6. In this case, the second buffer circuit BC2 and the first pixel PX1, second pixel PX2, third pixel PX3, fourth pixel PX4, fifth pixel PX5, and sixth pixel PX6 can be aligned facing each other in the second direction DR2. Therefore, the length of the second type of scan lines SSL1 to SSL6, which are connected to the second buffer circuit BC2 in a one-to-one correspondence and extend toward the first pixel PX1, second pixel PX2, third pixel PX3, fourth pixel PX4, fifth pixel PX5, and sixth pixel PX6, can be minimized.

[0222] According to embodiments of this disclosure, a first clock connection line CLS1 can be routed around a first logic circuit LC1. A second clock connection line CLS2 and second type scan lines SSL1 to SSL6 can be routed around a second logic circuit LC2. That is, there is no space occupied by the first clock connection line CLS1 in the area where the first logic circuit LC1 is located, and there is no space occupied by the second clock connection line CLS2 and the second type scan lines SSL1 to SSL6 in the area where the second logic circuit LC2 is located. Therefore, the space available for designing the first logic circuit LC1 and the second logic circuit LC2 can be further ensured. Therefore, designs that narrow the width of the first logic circuit LC1 and the second logic circuit LC2 in the second direction DR2 are easier to implement.

[0223] According to embodiments of this disclosure, first type scan lines SCL1 to SCL6 can extend from the first buffer circuit BC1 to be electrically connected across the introduction region INDA to the first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6, respectively. Second type scan lines SSL1 to SSL6 can extend from the second buffer circuit BC2 and can be electrically connected across the introduction region INDA to the first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6, respectively. The introduction region INDA is the region adjacent to the first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6, and can be defined between the sixth non-display region NDA6 and the display region DA.

[0224] According to embodiments of this disclosure, first type scan lines SCL1 to SCL6 can extend from the first buffer circuit BC1 to positions connected to the first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6, respectively. Second type scan lines SSL1 to SSL6 can extend from the second buffer circuit BC2 to positions connected to the first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6, respectively. For example, the first first type scan line SCL1 can extend from the first buffer circuit BC1 to a position connected to the first pixel PX1, the second first type scan line SCL2 can extend from the first buffer circuit BC1 to a position connected to the second pixel PX2, and so on. Similarly, for example, the first second type scan line SSL1 can extend from the second buffer circuit BC2 to a position connected to the first pixel PX1, the second second type scan line SSL2 can extend from the second buffer circuit BC2 to a position connected to the second pixel PX2, and so on. Therefore, the fan-out portion used to align the first type scan lines SCL1 to SCL6 and the second type scan lines SSL1 to SSL6 according to the arrangement of the first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 can be omitted. For example, the fan-out portion can refer to the portion in which a line extending along the first direction DR1 is provided. Therefore, the width of the non-display area NDA can be further reduced.

[0225] According to embodiments of this disclosure, the carry clock line CRCKL and the signal line SL can be disposed between the first type level SC-ST and the second type level SS-ST. At least some of the carry clock line CRCKL and the signal line SL can be electrically connected to both the first type level SC-ST and the second type level SS-ST. Figure 11The diagram shows a first connection line CLS41 and a second connection line CLS42 connected to one of the signal lines SL, and a first carry connection line CLS31 and a second carry connection line CLS32 connected to one of the carry clock lines CRCKL.

[0226] The first connecting line CLS41 can be electrically connected to a signal line SL and a first type level SC-ST, and can extend along the second direction DR2. The second connecting line CLS42 can be electrically connected to a signal line SL and a second type level SS-ST, and can extend along the second direction DR2. The first connecting line CLS41 and the second connecting line CLS42 can be spaced apart from each other in the second direction DR2.

[0227] The first carry connection line CLS31 can be electrically connected to a carry clock line CRCKL and a first type level SC-ST, and can extend along the second direction DR2. The second carry connection line CLS32 can be electrically connected to a carry clock line CRCKL and a second type level SS-ST, and can extend along the second direction DR2. The first carry connection line CLS31 and the second carry connection line CLS32 can be spaced apart from each other in the second direction DR2.

[0228] According to embodiments of this disclosure, since the carry clock line CRCKL and signal line SL are located between the first type level SC-ST and the second type level SS-ST, some of the connecting lines can be arranged to face each other in the second direction DR2. Therefore, the number of connecting lines arranged in the first direction DR1 can be reduced. Thus, design freedom is provided to reduce the width of lines extending in the first direction DR1 in the second direction DR2. Referring later... Figure 12A and Figure 12B Describe it in detail.

[0229] Furthermore, according to embodiments of this disclosure, the first type clock line CKLT1, the second type clock line CKLT2, the carry clock line CRCKL, and the signal line SL are arranged discontinuously. That is, the first type level SC-ST can be arranged between some of the first type clock lines CKLT1, CKLT2, CRCKL, and SL, and the second type level SS-ST can be arranged between some of the first type clock lines CKLT1, CKLT2, CRCKL, and SL, and the remainder. This reduces the number of crossing signal lines extending in the second direction DR2 that intersect a signal line extending in the first direction DR1. Therefore, design freedom is provided that can reduce the width of the line extending in the first direction DR1 in the second direction DR2, as will be discussed later. Figure 12A and Figure 12B Describe it in detail.

[0230] Figure 12A This is a plan view showing a single signal line SLL and multiple cross signal lines CLL according to a comparative example of this disclosure. Figure 12B This is a plan view showing a signal line SLLa and multiple cross signal lines CLLa according to an embodiment of the present disclosure.

[0231] Reference Figure 12A The diagram shows one signal line SLL and sixteen cross signal lines CLL. The signal line SLL can extend along a first direction DR1, and the cross signal lines CLL can overlap with the signal line SLL and can extend along a second direction DR2.

[0232] A signal line SLL may include a first layer line LL1 and multiple second layer patterns LL2 electrically connected to the first layer line LL1. The second layer patterns LL2 may be electrically connected to the first layer line LL1 via contact LCT. The second layer patterns LL2 may be disposed on the same layer as the crossover signal line CLL and may be electrically insulated from the crossover signal line CLL.

[0233] Multiple open LOPs and multiple slit LSLs can be defined within a single signal line SLL. Open LOPs can be provided to prevent coupling between the signal line SLL and the crossover signal line CLL. For example, an open LOP can be superimposed on a crossover signal line CLL. The portion where an open LOP is applied may act as a bottleneck and cause an increase in the resistance of a single signal line SLL. Therefore, as the number of open LOPs increases, the width of a single signal line SLL in the second direction DR2 may be increased to reduce resistance.

[0234] The slit LSL can be set in an area that does not overlap with the crossover signal line CLL. Figure 12A The diagram illustrates, as an example, two slit LSLs arranged on the second direction DR2. The slit LSLs can be configured to be placed in the manufacturing process of the display panel DP (see [reference]). Figure 1A In the process of curing the sealing member used in the manufacturing process, light is transmitted. Therefore, the slit LSL can be omitted from the signal line SLL included in the display panel DP, which has a structure that does not require a sealing member. Furthermore, the slit LSL can be omitted when the location of a signal line SLL is in an area that does not overlap with the sealing member.

[0235] Reference Figure 12B The diagram illustrates one signal line SLLa and six cross signal lines CLLa. The signal line SLLa can extend along a first direction DR1, and the cross signal lines CLLa can overlap with the signal line SLLa and extend along a second direction DR2. One signal line SLLa can be as shown above. Figure 11The description refers to any one of the following: Type 1 clock line CKLT1, Type 2 clock line CKLT2, carry clock line CRCKL, and signal line SL. The crossover signal line CLLa can be any of the lines described above. Figure 11 The first type of scan lines SCL1 to SCL6, the second type of scan lines SSL1 to SSL6, and at least some of the connecting lines CLS1, CLS2, CLS31, CLS32, CLS41, and CLS42 are described.

[0236] A signal line SLLa may include a first layer line LL1a and multiple second layer patterns LL2a electrically connected to the first layer line LL1a. The second layer patterns LL2a may be electrically connected to the first layer line LL1a via contact LTa. The second layer patterns LL2a may be disposed on the same layer as the cross signal line CLLa and may be electrically insulated from the cross signal line CLLa.

[0237] When the number of crossover signal lines CLLa stacked with signal line SLLa decreases, the number of openings LOPa set to prevent coupling can be reduced. In other words, as the number of bottleneck sections decreases, the width of a single signal line SLLa can be further reduced. For example, assuming the target resistance of signal lines SLLa is the same, Figure 12B The width SWT2 of the signal line SLLa superimposed with a relatively small number of cross signal lines CLLa in the second direction DR2 can be less than Figure 12A The width of the signal line SLL in the second direction DR2 is SWT1.

[0238] Figure 12C This is a plan view showing the signal line SLLb according to an embodiment of the present disclosure.

[0239] Reference Figure 12C A signal line SLLb may include a first layer line LL1b and a plurality of second layer patterns LL2b electrically connected to the first layer line LL1b. The second layer patterns LL2b may be electrically connected to the first layer line LL1b via contact LCTb.

[0240] Figure 12C The signal line SLLb shown can be set to be more than Figure 12B The signal line SLLa shown is close to the display area DA (see...) Figure 11 The signal line SLLb. For example, when Figure 12B The signal line SLLa shown is the first type clock line CKLT1 (see...) Figure 11 When one of the following is mentioned, Figure 12C The signal line SLLb shown can be the carry clock line CRCKL (see...) Figure 11One of them. The opening LOPb can be set in the signal line SLLb between the second layer patterns LL2b that are adjacent to each other on the first direction DR1.

[0241] In other words, because Figure 12C The signal line SLLb shown is configured to be spaced apart from the edge of the display panel DP, so the slit LSLa can be omitted (see...). Figure 12B In other words, the slit can be omitted from the signal line SLLb. Therefore, the resistance of the signal line SLLb can be further reduced, and the width SWT3 of the signal line SLLb in the second direction DR2 can be designed to be narrower.

[0242] Figure 13 This is a plan view showing some of the signal lines SL according to an embodiment of the present disclosure.

[0243] Reference Figure 13 The signal line SL is positioned between the first type level SC-ST and the second type level SS-ST. Therefore, within the signal line SL, the signal line SL-1, which is electrically connected to both the first type level SC-ST and the second type level SS-ST, can be connected to two connecting lines CLS41 and CLS42.

[0244] The two connecting lines CLS41 and CLS42 face each other in the second direction DR2 and can extend in opposite directions. Therefore, the number of connecting lines arranged in the first direction DR1 can be reduced. This provides design freedom by allowing for a reduction in the width of lines extending in the first direction DR1 in the second direction DR2. Furthermore, areas where no connecting lines are provided can be ensured as areas where other patterns or lines will be placed. In other words, design freedom can be further improved by ensuring the designable area.

[0245] Figure 14 This is a plan view of a portion of a display panel DPa according to an embodiment of the present disclosure. Figure 14 In the description, refer to Figure 11 The same reference numerals described are assigned to the same components, so their descriptions are omitted to avoid redundancy.

[0246] Above Figure 11 In this configuration, the voltage line SL-D can be placed together with the signal line SL in the fourth non-display area NDA4. That is to say, in... Figure 11 In this configuration, voltage line SL-D can be positioned between type 1 level SC-ST and type 2 level SS-ST. (Refer to...) Figure 14 At least some of the signal lines SL-Da among the signal lines SLa can be set in the sixth non-display area NDA6. Figure 14An example is shown where one of the signal lines SL-Da is located in the sixth non-display area NDA6. Hereinafter, a signal line SL-Da will be referred to as voltage line SL-Da.

[0247] The voltage line SL-Da can extend along the first direction DR1 and can be positioned between the second type clock line CKLT2 and the first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6. The voltage line SL-Da can have a specific voltage, for example, a constant voltage (or DC voltage). Therefore, the voltage line SL-Da can be used as a shielding line.

[0248] Due to the capacitance between the second type clock line CKLT2 and the circuit elements disposed in the display area DA, coupling between the second type clock line CKLT2 and the circuit elements may occur. According to embodiments of this disclosure, the voltage line SL-Da can receive... Figure 6B The second low voltage VSS2 is shown. That is, the voltage line SL-Da can be positioned between the second type clock line CKLT2 and the display area DA to act as a shielding layer. In other words, the voltage line SL-Da can prevent coupling between the second type clock line CKLT2 and circuit elements.

[0249] although Figure 14 As an example, a voltage line SL-Da is shown positioned between the second type clock line CKLT2 and the display area DA, but this disclosure is not particularly limited thereto. For example, at least some of the voltage lines SLa that are supplied with a specific voltage may be additionally positioned between the second type clock line CKLT2 and the display area DA.

[0250] Figure 15 This is a plan view of a portion of a display panel DPb according to an embodiment of the present disclosure. Figure 15 In the description, refer to Figure 14 The same reference numerals described are assigned to the same components, so their descriptions are omitted to avoid redundancy.

[0251] Reference Figure 15 The positions of the signal line SLb and the carry clock line CRCKLa, set in the fourth non-display area NDA4, can be related to... Figure 14 The positions of the signal line SL1 and the carry clock line CRCKL differ. For example, the carry clock line CRCKLa can be positioned between the first type level SC-ST and the signal line SL1, and the signal line SL1 can be positioned between the carry clock line CRCKLa and the second type level SS-ST.

[0252] In embodiments of this disclosure, at least some of the carry clock lines CRCKLa may also be positioned between a portion of signal line SLb and another portion of signal line SLb. That is, the arrangement order or arrangement of signal line SLb and carry clock line CRCKLa in the fourth non-display area NDA4 can be changed in various ways.

[0253] Figure 16 This is a plan view of a portion of a display panel DPc according to an embodiment of the present disclosure. Figure 16 In the description, refer to Figure 14 The same reference numerals described are assigned to the same components, so their descriptions are omitted to avoid redundancy.

[0254] Reference Figure 16 The second type clock line CKLT2 can be set in the second non-display area NDA2, and the second type level SS-ST can be set in the third non-display area NDA3. The carry clock line CRCKL and the signal line SLa can be set in the fourth non-display area NDA4. The first type level SC-ST can be set in the fifth non-display area NDA5. The first type clock line CKLT1 can be set in the sixth non-display area NDA6.

[0255] Figure 17 This is a plan view of a portion of a display panel DPd according to an embodiment of the present disclosure. Figure 17 In the description, refer to Figure 11 The same reference numerals described are assigned to the same components, so their descriptions are omitted to avoid redundancy.

[0256] Reference Figure 17 The first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 can receive a scan signal provided from a group level GSTA. A group level GSTA may include an integrated logic circuit LC-C that controls the operation of the first buffer circuit BC1 and the second buffer circuit BC2.

[0257] In embodiments of this disclosure, the integrated logic circuit LC-C can be disposed between the signal line SL and the carry clock line CRCKL. The first buffer circuit BC1 can be disposed between the first type clock line CKLT1 and the integrated logic circuit LC-C, and the second buffer circuit BC2 can be disposed between the integrated logic circuit LC-C and the second type clock line CKLT2.

[0258] The non-display area NDA can be divided into multiple regions. For example, the non-display area NDA may include a first non-display area NDA1, a second non-display area NDA2, a third non-display area NDA3a, a fourth non-display area NDA4a, a fifth non-display area NDA5a, a sixth non-display area NDA6a, a seventh non-display area NDA7, an eighth non-display area NDA8, and an introduction area INDA. The first non-display area NDA1, the second non-display area NDA2, the third non-display area NDA3a, the fourth non-display area NDA4a, the fifth non-display area NDA5a, the sixth non-display area NDA6a, the seventh non-display area NDA7, the eighth non-display area NDA8, and the introduction area INDA can be sequentially defined along the second direction DR2 in the direction facing the display area DA.

[0259] In embodiments of this disclosure, the integrated logic circuit LC-C may correspond to the remainder of a stage ST[N] excluding the six output circuits S109s. Figure 6B A stage ST[N] shown may also include six output circuits with a connection relationship similar to that of the six output circuits S109s. In this case, the first buffer circuit BC1 and the second buffer circuit BC2 may each correspond to twelve output circuits.

[0260] The second power line PL2 can be located in the first non-display area NDA1, the first type clock line CKLT1 can be located in the second non-display area NDA2, the first buffer circuit BC1 can be located in the third non-display area NDA3a, the signal line SL can be located in the fourth non-display area NDA4a, the integrated logic circuit LC-C can be located in the fifth non-display area NDA5a, the carry clock line CRCKL can be located in the sixth non-display area NDA6a, the second buffer circuit BC2 can be located in the seventh non-display area NDA7, and the second type clock line CKLT2 and voltage line SL-Da can be located in the eighth non-display area NDA8. The carry connection line CLS3 can be electrically connected to a carry clock line CRCKL and an integrated logic circuit LC-C, and can extend along the second direction DR2. The connection line CLS4 can be electrically connected to a signal line SL and an integrated logic circuit LC-C, and can extend along the second direction DR2.

[0261] According to the above embodiment, the first buffer circuit BC1, the second buffer circuit BC2, and pixels PX1, PX2, PX3, PX4, PX5, and PX6 can be arranged on the first direction DR1, and the first buffer circuit BC1, the second buffer circuit BC2, and pixels PX1, PX2, PX3, PX4, PX5, and PX6 can be aligned on the second direction DR2, which intersects the first direction DR1. In this case, the fan-out portions used to align the first type scan lines SCL1 to SCL6 connected to the first buffer circuit BC1 and the second type scan lines SSL1 to SSL6 connected to the second buffer circuit BC2 according to the arrangement order of pixels PX1, PX2, PX3, PX4, PX5, and PX6 can be omitted or reduced. As a result, the display panel DP (see...) can be reduced. Figure 2 The non-display area NDA (see) Figure 3 The width of ).

[0262] Furthermore, the first type clock line CKLT1 can be configured to be adjacent to the first buffer circuit BC1, and the second type clock line CKLT2 can be configured to be adjacent to the second buffer circuit BC2. Therefore, the design length of lines (e.g., the first clock connection line CLS1 and the second clock connection line CLS2) in the non-display area NDA can be reduced or minimized. Additionally, since the signal line SL and the carry clock line CRCKL are located between the first buffer circuit BC1 and the second buffer circuit BC2, the number of crossover signal lines CLLa that cross a signal line SLLa can be reduced (see...). Figure 12B The number of (SLLa) signals can be reduced. In this case, as the number of bottleneck portions designed to prevent the combination of cross signal lines CLLa with a single signal line SLLa is reduced, the width of a single signal line SLLa can be further reduced. Therefore, the display panel DP (see [link to relevant documentation]) can be reduced. Figure 2 The non-display area NDA (see) Figure 3 The width of ).

[0263] As described above, the display panel includes multiple levels disposed in a non-display area, and each level may include a first buffer circuit for outputting a first type of scan signal to multiple pixels and a second buffer circuit for outputting a second type of scan signal to multiple pixels. Each of the first buffer circuit, the second buffer circuit, and the pixels may be arranged in a first direction, and the first buffer circuit, the second buffer circuit, and the multiple pixels may be aligned in a second direction intersecting the first direction. In this case, the fan-out portions used for aligning the first type of scan lines connected to the first buffer circuit and the second type of scan lines connected to the second buffer circuit according to the pixel arrangement order may be omitted or reduced.

[0264] Furthermore, the first type of clock line can be configured to be adjacent to the first buffer circuit, and the second type of clock line can be configured to be adjacent to the second buffer circuit. Therefore, the line design length in the non-display area can be reduced or minimized. Additionally, the number of crossover signal lines intersecting with a signal line can be reduced. When the number of crossover signal lines overlapping with a signal line is reduced, the width of a signal line can be further reduced because the number of bottleneck portions designed to prevent the crossover signal lines from combining with a signal line can be reduced. Therefore, the width of the non-display area can be reduced.

[0265] Although embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications and substitutions can be made without departing from the scope and spirit of this disclosure as disclosed in the appended claims. Therefore, the technical scope of this disclosure should not be limited to what is described in the detailed description of the specification, but should be defined by the claims.

Claims

1. A display panel, the display panel comprising: Multiple pixels are arranged along a first direction; The first type level includes a plurality of first buffer circuits, which are configured to output a plurality of first type scan signals to the plurality of pixels respectively; The second type level includes a plurality of second buffer circuits, which are configured to output a plurality of second type scan signals to the plurality of pixels respectively; as well as Multiple carry clock lines are positioned between the first buffer circuit and the second buffer circuit, and extend in the first direction. The plurality of first buffer circuits are arranged along the first direction, and The plurality of second buffer circuits are arranged along the first direction.

2. The display panel according to claim 1, further comprising: Multiple Type 1 clock lines are electrically connected to the Type 1 level; as well as Multiple type II clock lines are electrically connected to the type II stage. The plurality of first-type clock lines and the plurality of second-type clock lines are spaced apart from each other in a second direction that intersects with the first direction, and the plurality of carry clock lines are disposed between the plurality of first-type clock lines and the plurality of second-type clock lines.

3. The display panel according to claim 2, wherein, The first type level is positioned between the plurality of first type clock lines and the plurality of carry clock lines, and The second type level is positioned between the plurality of second type clock lines and the plurality of carry clock lines.

4. The display panel according to claim 2, wherein, The first type level also includes a first logic circuit configured to control the operation of the plurality of first buffer circuits. The second type level further includes a second logic circuit configured to control the operation of the plurality of second buffer circuits. The plurality of first buffer circuits are disposed between the plurality of first type clock lines and the first logic circuit, and The plurality of second buffer circuits are disposed between the plurality of second type clock lines and the second logic circuit.

5. The display panel according to claim 2, wherein, The plurality of first-type clock lines, the first-type level, the plurality of carry clock lines, the second-type level, the plurality of second-type clock lines, and the plurality of pixels are arranged sequentially in the second direction.

6. The display panel according to claim 5, further comprising: Voltage lines are positioned between the plurality of second-type clock lines and the plurality of pixels. The voltage line extends along the first direction.

7. The display panel according to claim 5, further comprising: A voltage line is positioned between the first type level and the second type level. The voltage line extends along the first direction.

8. The display panel according to claim 1, further comprising: Multiple signal lines are electrically connected to the first type level and the second type level. The multiple signal lines are arranged between the multiple first buffer circuits and the multiple second buffer circuits.

9. The display panel according to claim 8, further comprising: The first connecting line extends in a second direction that intersects the first direction; as well as The second connecting line is spaced apart from the first connecting line along the second direction and extends along the second direction. The first connecting line is electrically connected to the first signal line and the first type level among the plurality of signal lines, and the second connecting line is electrically connected to the first signal line and the second type level among the plurality of signal lines.

10. The display panel according to claim 8, further comprising: An integrated logic circuit is disposed between the plurality of signal lines and the plurality of carry clock lines, and is configured to control the operation of the plurality of first buffer circuits and the plurality of second buffer circuits.

11. The display panel according to claim 1, further comprising: Multiple first-type scan lines are electrically connected to the multiple first-buffer circuits in a one-to-one correspondence. as well as Multiple second-type scan lines are electrically connected to the multiple second-buffer circuits in a one-to-one correspondence. The plurality of first-type scan lines and the plurality of second-type scan lines are electrically connected to the plurality of pixels across an introduction region adjacent to the plurality of pixels.

12. The display panel according to claim 11, wherein, At least one of the plurality of second-type scan lines is disposed in the introduction region between a first first-type scan line of the plurality of first-type scan lines and a second first-type scan line of the plurality of first-type scan lines.

13. The display panel according to claim 11, further comprising: Data cable, electrically connected to the plurality of pixels; as well as Power lines, electrically connected to the plurality of pixels, Each of the plurality of pixels includes a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit, and The pixel driving circuit includes: a first transistor connected between the power line and the light-emitting element; a second transistor connected between the data line and the gate electrode of the first transistor; and a third transistor connected between the light-emitting element and the readout line.

14. The display panel according to claim 13, wherein, The operation of the second transistor is controlled by one of the plurality of first-type scan signals, and The operation of the third transistor is controlled by one of the plurality of second-type scan signals.

15. The display panel according to claim 13, wherein, The operation of the second transistor is controlled by one of the plurality of second-type scan signals, and The operation of the third transistor is controlled by one of the plurality of first-type scan signals.

16. An electronic device, the electronic device comprising: The display panel has a display area and a non-display area adjacent to the display area; as well as The data driver is electrically connected to the display panel. The display panel includes: a plurality of pixels arranged along a first direction in the display area; a data line electrically connected to the plurality of pixels and the data driver; a first type level disposed in the non-display area and configured to output a plurality of first type scan signals to the plurality of pixels; and a second type level disposed in the non-display area and configured to output a plurality of second type scan signals to the plurality of pixels. The first type level and the second type level are spaced apart from each other in a second direction that intersects with the first direction.

17. The electronic device according to claim 16, wherein, The first type level includes a plurality of first buffer circuits, wherein each of the plurality of first buffer circuits is configured to output one of the plurality of first type scan signals as a first type scan signal. The second type level includes multiple second buffer circuits, wherein each of the multiple second buffer circuits is configured to output one of the multiple second type scan signals as a second type scan signal. The plurality of first buffer circuits are arranged along the first direction, and The plurality of second buffer circuits are arranged along the first direction.

18. The electronic device according to claim 17, wherein, The display panel also includes: Multiple carry clock lines are disposed between the multiple first buffer circuits and the multiple second buffer circuits, and extend in the first direction; Multiple type-1 clock lines are electrically connected to the type-1 stage; and Multiple second-type clock lines are electrically connected to the second-type stage, and The first type of clock line and the second type of clock line are spaced apart from each other in the second direction, and the multiple carry clock lines are disposed between the multiple first type of clock lines and the multiple second type of clock lines.

19. The electronic device according to claim 18, wherein, The plurality of first-type clock lines, the first-type level, the plurality of carry clock lines, the second-type level, the plurality of second-type clock lines, and the plurality of pixels are arranged sequentially along the second direction, and The display panel further includes voltage lines disposed between the plurality of second-type clock lines and the plurality of pixels, and the voltage lines extend along the first direction.

20. The electronic device according to claim 17, wherein, The display panel further includes: multiple signal lines electrically connected to the first type level and the second type level; a first connecting line extending along the second direction; and a second connecting line spaced apart from the first connecting line in the second direction and extending along the second direction. The plurality of signal lines are disposed between the plurality of first buffer circuits and the plurality of second buffer circuits, and The first connecting line is electrically connected to a first signal line among the plurality of signal lines and the first type level, and the second connecting line is electrically connected to the first signal line among the plurality of signal lines and the second type level.

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