Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device.The display panel comprises a substrate, a plurality of first grid signal lines and a plurality of first standby signal lines, the first grid signal lines and the first standby signal lines are located on the substrate, and the first grid signal lines extend in the first direction and are arranged in the second direction; the multiple first standby signal lines extend in the second direction and are arranged in the first direction, the gate drive circuit is connected with the first gate signal lines through the first standby signal lines, the first gate signal lines are connected with the pixel circuits, and at least part of the first standby signal lines are located in the display area. According to the technical scheme provided by the embodiment, the gate drive circuit is moved to the non-arc-angle area from the arc-angle area, and the connecting line between the gate drive circuit and the pixel circuit is moved into the display area for connection, so that the gate control signal output by the gate drive circuit is transmitted to the pixel circuit, the arc-angle area is not provided with a winding any more, and the display effect is improved. Therefore, the screen-to-body ratio of the non-display area can be effectively reduced, and the design of a narrow frame is realized.

Description

Display panel and display device Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] As display technology continues to mature, users' demands for display quality are increasing. A key challenge facing current products is how to minimize bezel size as much as possible to improve the overall display performance of the screen. Summary of the Invention

[0003] This invention provides a display panel and a display device to reduce the bezel of the display panel.

[0004] According to one aspect of the present invention, a display panel is provided, including a gate driving circuit and a pixel circuit. The display panel is provided with a display area and a non-display area at least partially surrounding the display area. The non-display area includes a curved corner area and a non-curved corner area. The gate driving circuit is located in the non-curved corner area, and the pixel circuit is located in the display area. The display panel further includes: a substrate; a plurality of first gate signal lines and a plurality of first spare signal lines located on the substrate. The plurality of first gate signal lines extend along a first direction and are arranged along a second direction. The plurality of first spare signal lines extend along the second direction and are arranged along the first direction. The gate driving circuit is connected to the first gate signal lines via the first spare signal lines. The first gate signal lines are connected to the pixel circuit. The first spare signal lines are at least partially located in the display area. The first direction and the second direction intersect.

[0005] Optionally, the first gate signal line and the first spare signal line are disposed on different layers; optionally, the display panel further includes multiple conductive layers stacked on the substrate, the multiple conductive layers including a first conductive layer and a fourth conductive layer, the fourth conductive layer being located on the side of the first conductive layer away from the substrate, the first gate signal line being located on the first conductive layer, and the first spare signal line being located on the fourth conductive layer; optionally, the display panel further includes an active layer, the active layer being located between the substrate and the first conductive layer, the pixel circuit including a driving transistor, a first transistor, and a second transistor, the overlapping position of the first gate signal line and the active layer respectively forming the gate of the first transistor and the gate of the second transistor, the first electrode of the driving transistor being connected to the second electrode of the first transistor through the active layer, the second electrode of the driving transistor being connected to the first electrode of the second transistor through the active layer, and the second electrode of the second transistor being connected to the light-emitting element; optionally, the first transistor and the second transistor are used to control the driving transistor to drive the light-emitting element to emit light.

[0006] Optionally, the gate driving circuit is used to output a light emission control signal, and the first gate signal line is used to transmit the light emission control signal to the gate of the first transistor and the gate of the second transistor.

[0007] Optionally, the multilayer conductive layer further includes a first connecting line, through which the first spare signal line is connected to the first gate signal line; optionally, the first connecting line is disposed on a different layer from the first spare signal line and the first gate signal line; optionally, the multilayer conductive layer further includes a third conductive layer, which is located between the first conductive layer and the fourth conductive layer, and the first connecting line is located on the third conductive layer; optionally, the first spare signal line is connected to one end of the first connecting line through a first type of via, and the first gate signal line is connected to the other end of the first connecting line through a second type of via.

[0008] Optionally, the pixel circuit further includes a third transistor, and the display panel further includes multiple first data lines, multiple second spare signal lines, and multiple third spare signal lines. The multiple first data lines extend along the second direction and are arranged along the first direction, the multiple second spare signal lines extend along the second direction and are arranged along the first direction, and the multiple third spare signal lines extend along the first direction and are arranged along the second direction; wherein, both the second spare signal lines and the third spare signal lines are at least partially located in the display area; the second spare signal lines are connected to the first data lines through the third spare signal lines, the first data lines are connected to the first electrode of the third transistor through a second connecting line, and the second electrode of the third transistor is connected to the first electrode of the driving transistor through the active layer; optionally, the multilayer conductive layer further includes a third conductive layer, the third conductive layer is located between the first conductive layer and the fourth conductive layer, and the second connecting line is located on the third conductive layer. The first data line is connected to one end of the third backup signal line via a first type of via, and one end of the first data line is connected to the other end of the third backup signal line via the first type of via. The first electrode of the third transistor is connected to one end of the second connection line via a second type of via, and the other end of the second connection line is connected to the other end of the first data line via the first type of via. Optionally, the first data line and the second backup signal line are disposed on the same layer, and the second backup signal line and the third backup signal line are disposed on different layers. Optionally, the first data line and the second backup signal line are located on the fourth conductive layer, and the third backup signal line is located on the third conductive layer. Optionally, the display panel further includes multiple second data lines, the second data lines are located on the side of the first data line near the display area, the multiple second data lines extend along the second direction and are arranged along the first direction, and one second data line is connected to a column of pixel circuits.

[0009] Optionally, the first spare signal line and the second spare signal line are located in different columns of the pixel circuit area, and in the same column of the pixel circuit, the display panel includes the first spare signal line or the second spare signal line; Optionally, the orthographic projection of the first spare signal line on the substrate does not overlap with the orthographic projection of the second spare signal line on the substrate; Optionally, the first spare signal line is located in the Nth column of the pixel circuit area, and the second spare signal line is located in the N+1th column of the pixel circuit area, where N is an integer greater than or equal to 1.

[0010] Optionally, the display panel further includes a first mesh structure, the first mesh structure including a first sub-signal line, a fourth spare signal line, and a third connecting line, wherein multiple first sub-signal lines extend along a first direction and are arranged along a second direction, and multiple fourth spare signal lines extend along the second direction and are arranged along the first direction, and the first sub-signal lines are connected to the fourth spare signal lines through the third connecting line; optionally, the first sub-signal line is connected to one end of the third connecting line through a second type of via, and the fourth spare signal line is connected to the other end of the third connecting line through a first type of via; optionally, the first sub-signal line and the fourth spare signal line are different The multilayer conductive layer is configured such that the third connecting line and the first sub-signal line are disposed on different layers; optionally, the multilayer conductive layer further includes a second conductive layer, which is located between the first conductive layer and the third conductive layer, the first sub-signal line is located on the second conductive layer, the fourth spare signal line is located on the fourth conductive layer, and the third connecting line is located on the third conductive layer; optionally, the display panel further includes a second gate signal line, a fourth connecting line, and a fifth connecting line, and the pixel circuit further includes a fourth transistor, wherein the second gate signal line overlaps with the active layer to form the gate of the fourth transistor, and the first electrode of the fourth transistor is connected to the first sub-signal line through the fourth connecting line. The second terminal of the fourth transistor is connected to the gate of the driving transistor via a fifth connection line; optionally, the first terminal of the fourth transistor is connected to one end of the fourth connection line via a second type of via, the first sub-signal line is connected to the other end of the fourth connection line via a second type of via, the second terminal of the fourth transistor is connected to one end of the fifth connection line via a second type of via, and the gate of the driving transistor is connected to the other end of the fifth connection line via a second type of via; optionally, the first mesh structure is used to transmit the first initialization voltage, and the fourth transistor is used to transmit the first initialization voltage to the gate of the driving transistor; optionally, the... The second gate signal line is located in the first conductive layer, and the fifth connection line is located in the third conductive layer; optionally, the first spare signal line, the second spare signal line, and the fourth spare signal line are located in different columns of the pixel circuit area, and in the same column of the pixel circuit, the display panel includes one of the first spare signal line, the second spare signal line, or the fourth spare signal line; optionally, the first spare signal line is located in the Nth column of the pixel circuit area, the second spare signal line is located in the N+1th column of the pixel circuit area, and the fourth spare signal line is located in the N+2th column of the pixel circuit area, where N is an integer greater than or equal to 1.

[0011] Optionally, the display panel further includes a second mesh structure, the second mesh structure including a second sub-signal line, a fifth spare line, and a sixth connecting line, wherein multiple second sub-signal lines extend along the first direction and are arranged along the second direction, multiple fifth spare signal lines extend along the second direction and are arranged along the first direction, and the second sub-signal lines are connected to the fifth spare signal lines through the sixth connecting line; optionally, the second sub-signal lines are connected to one end of the sixth connecting line through a second type of via, and the fifth spare signal lines are connected to the other end of the sixth connecting line through a first type of via; optionally, the second sub-signal lines... The first and second backup signal lines are disposed on different layers, and the sixth connecting line is disposed on a different layer from the second sub-signal line. Optionally, the second sub-signal line is located on the second conductive layer, the fifth backup signal line is located on the fourth conductive layer, and the sixth connecting line is located on the third conductive layer. Optionally, the pixel circuit further includes a fifth transistor, and the gate of the fifth transistor is formed at the intersection of the second gate signal line and the active layer. The first electrode of the fifth transistor is connected to one end of the sixth connecting line through a second type of via, and the second electrode of the fifth transistor is connected to the first electrode of the light-emitting element. Optionally, the orthogonal projection of the fifth backup signal line on the substrate at least partially covers the orthogonal projection of the sixth connecting line on the substrate. Optionally, the second mesh structure is used to transmit a second initialization voltage, and the fifth transistor is used to transmit the second initialization voltage to the first electrode of the light-emitting element. Optionally, the first backup signal line, the second backup signal line, the fourth backup signal line, and the fifth backup signal line are respectively located in different columns of the pixel circuit area. In the same column of the pixel circuit, the display panel includes one of the first backup signal line, the second backup signal line, the fourth backup signal line, or the fifth backup signal line. Optionally, The first spare signal line is located in the area where the pixel circuit is located in the Nth column, the second spare signal line is located in the area where the pixel circuit is located in the (N+1)th column, the fourth spare signal line is located in the area where the pixel circuit is located in the (N+2)th column, and the fifth spare signal line is located in the area where the pixel circuit is located in the (N+3)th column, where N is an integer greater than or equal to 1; Optionally, the trace breaks of the first spare signal line, the second spare signal line, the third spare signal line, the fourth spare signal line and / or the fifth spare signal line at the location of the first type of via are arranged in a "V" shape, a " / " shape, a "\" shape or a "W" shape within the display area.

[0012] Optionally, the display panel further includes a third gate signal line, and the pixel circuit further includes a sixth transistor. The third gate signal line overlaps with the active layer to form the gate of the third transistor and the gate of the sixth transistor, respectively. The orthographic projection of the third gate signal line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the second sub-signal line on the substrate. The second sub-signal line includes a first main body extending along the first direction, a first branch extending along the second direction, and a second branch extending along the second direction. The orthographic projection of the first branch on the substrate does not overlap with the orthographic projection of the second branch on the substrate. The orthographic projection of the first branch on the substrate does not overlap with the orthographic projection of the third gate signal line on the substrate; the orthographic projection of the second branch on the substrate does not overlap with the orthographic projection of the third gate signal line on the substrate; in the first direction, the orthographic projection of the first branch on the substrate is located between the orthographic projection of the connection hole between the first data line and the second connection line on the substrate and the orthographic projection of the connection hole between the second electrode of the fourth transistor and the fifth connection line on the substrate; optionally, the orthographic projection of the first branch on the substrate, the orthographic projection of the connection hole between the first data line and the second connection line on the substrate, and the orthographic projection of the connection hole between the second electrode of the fourth transistor and the fifth connection line on the substrate... The orthographic projections of the first branch portion on the substrate do not overlap; optionally, the orthographic projection of the first branch portion on the substrate, the orthographic projection of the connection hole between the first data line and the second connection line on the substrate, and the orthographic projection of the connection hole between the second electrode of the fourth transistor and the fifth connection line on the substrate do not overlap; optionally, the third gate signal line includes a second main body portion extending along the first direction and a third branch portion extending along the second direction, the second main body portion overlapping with the active layer respectively forming the gate of the third transistor and the first gate of the sixth transistor, the third branch portion overlapping with the active layer forming the second gate of the sixth transistor, and the dual gate node of the sixth transistor is located in the active layer; Optionally, the orthographic projection of the second branch on the substrate covers at least a portion of the orthographic projection of the dual-gate node of the sixth transistor on the substrate; Optionally, the orthographic projection of the second branch on the substrate covers at least a portion of the orthographic projection of the dual-gate node of the sixth transistor on the substrate; Optionally, the display panel further includes a third mesh structure, the third mesh structure including a first power line and a second power line, a plurality of first power lines extending along a first direction and arranged along a second direction, a plurality of second power lines extending along a second direction and arranged along a first direction, the first power line and the second power line being disposed in different layers, and the first power line being connected to the second power line through a first type of via;Optionally, the first power line includes a plurality of connection units arranged sequentially along the first direction. Each connection unit includes a first connection portion extending along the first direction, and a second connection portion and a third connection portion extending along the second direction. Within the same connection unit, the first connection portion is connected to the second connection portion, the second connection portion is connected to the second power line through a first type of via, and the third connection portion is connected to the first connection portion. Optionally, the first connection portion, the second connection portion, and the third connection portion are an integral structure. Optionally, in two adjacent connection units, the third connection portion in the preceding connection unit and the first connection portion in the following connection unit are connected as an integral structure. Optionally, the third connection portion is located within the... The orthographic projection on the substrate covers at least a portion of the orthographic projection of the first spare signal line on the substrate; the orthographic projection of the first spare signal line on the substrate is separate from the orthographic projection of the gate of the driving transistor on the substrate, and the orthographic projection of the third connection portion on the substrate simultaneously covers at least a portion of the orthographic projection of the first spare signal line on the substrate and at least a portion of the orthographic projection of the gate of the driving transistor on the substrate; optionally, the pixel circuit further includes a storage capacitor, the first plate of the storage capacitor is located on the first conductive layer, the second plate of the storage capacitor is located on the second conductive layer, the second conductive layer is located between the first conductive layer and the fourth conductive layer, and the first connection portion is connected to the second plate of the storage capacitor through a second type of via.

[0013] According to another aspect of the present invention, a display device is provided, which includes a display panel provided in any embodiment of the present invention.

[0014] The technical solution provided in this embodiment moves the gate driving circuit from the arc corner area to the non-arc corner area, and moves the connection line between the gate driving circuit and the pixel circuit to the inside of the display area for connection. The first spare signal line is connected to the first gate signal line, so that the gate control signal output by the gate driving circuit can be transmitted to the pixel circuit. This eliminates the need for winding in the arc corner area, thereby effectively reducing the screen ratio of the non-display area and achieving a narrow bezel design.

[0015] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 is a planar structural schematic diagram of a display panel provided in an embodiment of the present invention; Figure 2 is a partially enlarged structural schematic diagram of a display panel provided in an embodiment of the present invention; Figure 3 is a layout structural schematic diagram of a display panel provided in an embodiment of the present invention; Figure 4 is a cross-sectional structural schematic diagram of a display panel provided in an embodiment of the present invention; Figure 5 is a structural schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 6 is a planar structural schematic diagram of another display panel provided in an embodiment of the present invention; Figure 7 is a layout structural schematic diagram of another display panel provided in an embodiment of the present invention; Figure 8 is a cross-sectional structural schematic diagram of another display panel provided in an embodiment of the present invention; Figure 9 is a layout structural schematic diagram of another display panel provided in an embodiment of the present invention; Figure 10 is a layout structural schematic diagram of another display panel provided in an embodiment of the present invention; Figure 11 is a layout structural schematic diagram of another display panel provided in an embodiment of the present invention. Figure 12 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention; Figure 13 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention; Figure 14 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention; Figure 15 is a schematic diagram of the cross-sectional structure of another display panel provided in an embodiment of the present invention; Figure 16 is a schematic diagram of the cross-sectional structure of another display panel provided in an embodiment of the present invention; Figure 17 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention; Figure 18 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention; Figure 19 is a schematic diagram of the structure of a connection unit provided in an embodiment of the present invention; Figure 20 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention; Figure 21 is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] Figure 1 is a schematic diagram of the planar structure of a display panel provided in an embodiment of the present invention, and Figure 2 is a partially enlarged schematic diagram of the display panel provided in an embodiment of the present invention, specifically the enlarged structure within the dotted circle in the display panel shown in Figure 1. Referring to Figures 1 and 2, the display panel provided in this embodiment includes a gate driving circuit 100 and a pixel circuit 200. The display panel is provided with a display area AA and a non-display area NA that is at least partially surrounding the display area AA. The non-display area NA includes a corner area and a non-corner area (e.g., an upper corner area A and an upper non-corner area B). The gate driving circuit 100 is located in the non-corner area, and the pixel circuit 200 is located in the display area AA. The pixel circuits 200 can be arrayed within the display area AA to drive the light-emitting elements to emit light; the gate driving circuit 100 provides gate driving signals to the pixel circuits 200.

[0021] The display panel further includes: a substrate (not shown in the figure); a plurality of first gate signal lines GL1 and a plurality of first spare signal lines 11 located on the substrate, the plurality of first gate signal lines GL1 extending along a first direction X and arranged along a second direction Y, the plurality of first spare signal lines 11 extending along the second direction Y and arranged along the first direction X, the gate driving circuit 100 being connected to the first gate signal lines GL1 via the first spare signal lines 11, the first gate signal lines GL1 being connected to the pixel circuit 200, and the first spare signal lines 11 being at least partially located in the display area AA; wherein the first direction X and the second direction Y intersect.

[0022] In related technologies, the gate driving circuit 100 is disposed in the arc corner region, such as the upper arc corner region A. The gate driving circuit 100 is connected to the pixel circuit 200 in the display area AA through a winding located in the arc corner region. The winding is connected to the pixel circuit 200 through the first gate signal line GL1.

[0023] The technical solution provided in this embodiment moves the gate driving circuit 100 from the arc corner area to the non-arc corner area, and moves the connection line between the gate driving circuit 100 and the pixel circuit 200 to the inside of the display area AA for connection. The first spare signal line 11 is connected to the first gate signal line GL1, so that the gate control signal output by the gate driving circuit 100 is transmitted to the pixel circuit 200. This eliminates the need for winding in the arc corner area, thereby effectively reducing the screen ratio of the non-display area NA and achieving a narrow bezel design.

[0024] It should be understood that each first gate signal line GL1 is connected to a row of pixel circuits 200, and each first spare signal line 11 is connected to a first gate signal line GL1, so that the gate drive circuit 100 outputs gate control signals to each row of pixel circuits 200 row by row.

[0025] Figure 3 is a schematic diagram of the layout structure of a display panel provided in an embodiment of the present invention, and Figure 4 is a schematic diagram of the cross-sectional structure of a display panel provided in an embodiment of the present invention. Specifically, Figure 4 is the cross-sectional structure of the display panel shown in Figure 3 along the cutting line AA'. Based on the above embodiment, referring to Figures 3 and 4, since the first gate signal line GL1 and the first spare signal line 11 have different extension directions and intersect, the first gate signal line GL1 and the first spare signal line 11 are arranged in different layers to achieve a one-to-one connection.

[0026] Specifically, the display panel also includes multiple conductive layers stacked on the substrate 20. The multiple conductive layers include a first conductive layer M1 and a fourth conductive layer M4. The fourth conductive layer M4 is located on the side of the first conductive layer M1 away from the substrate 30. The first gate signal line GL1 is located on the first conductive layer M1, and the first spare signal line 11 is located on the fourth conductive layer M4.

[0027] The multilayer conductive layer also includes a first connection line 31, and the first spare signal line 11 is connected to the first gate signal line GL1 through the first connection line 31.

[0028] The multiple conductive layers are isolated from each other by insulating layers. For example, a first insulating layer 21 is disposed between the first conductive layer M1 and the active layer 10, a second insulating layer 22 is disposed between the first conductive layer M1 and the second active layer M2, a third insulating layer 23 is disposed between the second conductive layer M2 and the third conductive layer M3, a fourth insulating layer 24 is disposed between the third conductive layer M3 and the fourth conductive layer M4, and a fifth insulating layer 25 is disposed on the side of the fourth conductive layer M4 away from the substrate 20. Here, the Z direction is the thickness direction of the display panel.

[0029] Optionally, the first connecting line 31 is disposed on a different layer from the first spare signal line 11 and the first gate signal line GL1. The multilayer conductive layer further includes a third conductive layer M3, which is located between the first conductive layer M1 and the fourth conductive layer M4. The first connecting line 31 is located on the third conductive layer M3. The first spare signal line 11 is connected to one end of the first connecting line 31 through a first type via K1, and the first gate signal line GL1 is connected to the other end of the first connecting line 31 through a second type via K2. That is, the first gate signal line GL1 and the first spare signal line 11 are bridged by the first connecting line 31. The gate drive signal output by the gate drive circuit 100 is transmitted to the first spare signal line 11 extending along the second direction Y, then switched through the first type via K1 to the first connecting line 31 located in the third conductive layer M3, and then switched through the second type via K2 to the first gate signal line GL1 extending along the first direction X. Here, the first type of via K1 can be an organic via, and the second type of via K2 can be an inorganic via. The membrane structure penetrated by the first type of via K1 and the second type of via K2 is different.

[0030] Figure 5 is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. In conjunction with Figures 3, 4 and 5, the display panel further includes an active layer 10, which is located between the substrate 20 and the first conductive layer M1. The pixel circuit 200 includes a driving transistor T0, a first transistor T1 and a second transistor T2. The first gate signal line GL1 overlaps with the active layer 10 to form the gate of the first transistor T1 and the gate of the second transistor T2, respectively. The first electrode of the driving transistor T0 is connected to the second electrode of the first transistor T1 through the active layer 10, and the second electrode of the driving transistor T0 is connected to the first electrode of the second transistor T2 through the active layer 10. The second electrode of the second transistor T2 is connected to a light-emitting element (not shown in the figure).

[0031] Among them, the first transistor T1 and the second transistor T2 are light-emitting control transistors, which can be used to control the driving transistor T0 to drive the light-emitting element to emit light. The gate driving circuit 100 is used to output the light-emitting control signal EM. The first gate signal line GL1 is used to transmit the light-emitting control signal EM to the gate of the first transistor T1 and the gate of the second transistor T2.

[0032] The technical solution provided by the embodiments of the present invention can avoid winding in the arc corner area by setting the light emission control signal EM in the display area AA for routing, thereby reducing the screen ratio in the arc corner area and realizing a narrow bezel design.

[0033] Optionally, the arc corner area includes an upper arc corner area A and a lower arc corner area. The above embodiments are to reduce the screen ratio of the upper arc corner area A. Of course, the ratio of the lower arc corner area can also be reduced. Typically, the lower arc corner area is used to arrange the fan-out routing of data cables.

[0034] Referring again to Figure 5, the pixel circuit 200 also includes a third transistor T3, which is connected to the data line and used to write the data voltage Vdata transmitted on the data line to the driving transistor T0. Similarly, the fan-out routing of the data line can be set inside the display area AA. By simultaneously reducing the screen ratio of the lower arc corner area A and the lower arc corner area, the bezel size can be further reduced, thereby achieving a narrow bezel design.

[0035] Figure 6 is a schematic diagram of another planar structure of a display panel provided in an embodiment of the present invention. Referring to Figure 6, the display panel further includes multiple first data lines DL1, multiple second spare signal lines 12, and multiple third spare signal lines 13. The multiple first data lines DL1 extend along the second direction Y and are arranged along the first direction X. The multiple second spare signal lines 12 extend along the second direction Y and are arranged along the first direction X. The multiple third spare signal lines 13 extend along the first direction X and are arranged along the second direction Y. The second spare signal lines 12 and the third spare signal lines 13 are at least partially located in the display area AA.

[0036] The second backup signal line 12 is connected to the first data line DL1 through the third backup signal line 13. The first data line DL1 is connected to the first terminal of the third transistor T3. The second terminal of the third transistor T3 is connected to the first terminal of the driving transistor T0 through the active layer 10.

[0037] Not all data lines need to be connected via the second spare signal line 12 and the third spare signal line 13. Only the first data line DL, located at the edge of the display area AA, needs to be moved inside the display area AA for routing. The data line DL, located at the center of the display area AA, does not pass through the lower arc corner area C and does not require a spare signal line for connection. For example, the display panel also includes a second data line DL2, located on the side of the first data line DL1 closest to the display area AA. Multiple second data lines DL2 extend along the second direction Y and are arranged along the first direction X. One second data line DL2 is connected to a column of pixel circuits 200. That is, the second data line DL2 does not require a spare signal line for connection.

[0038] The technical solution provided in this embodiment reduces the number of traces in the lower arc corner area C by moving the original fan-out traces of the data line located in the lower arc corner area C to the display area AA for wiring, and using the second spare signal line 12 and the third spare signal line 12 for wiring to connect to the first data line DL1. This reduces the number of traces in the lower arc corner area C, thereby reducing the screen ratio of the lower arc corner area C, which is beneficial for narrow bezel design.

[0039] Figure 7 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention, and Figure 8 is a schematic diagram of the cross-sectional structure of another display panel provided in an embodiment of the present invention. Specifically, Figure 8 shows the cross-sectional structure of the display panel shown in Figure 7 along the cutting line BB'. In Figure 7, the structure of two (column) pixel circuits 200 arranged along the first direction X is shown, and the left and right pixel circuits 200 are divided by the center line MIL. Referring to Figures 7 and 8, based on the above embodiments, the multilayer conductive layer further includes a second connecting line 32, and the first data line DL1 is connected to the first electrode of the third transistor T3 through the second connecting line 32.

[0040] Specifically, the second backup signal line 12 is connected to one end of the third backup signal line 13 through a first type via K1, one end of the first data line DL1 is connected to the other end of the third backup signal line 13 through a first type via K1, the first electrode of the third transistor T3 is connected to one end of the second connection line 32 through a second type via K2, and the other end of the second connection line 32 is connected to the other end of the first data line DL1 through a first type via K1.

[0041] The first data line DL1 and the second spare signal line 12 are disposed on the same layer, while the second spare signal line 12 and the third spare signal line 13 are disposed on different layers. For example, the first data line DL1 and the second spare signal line 12 are located on the fourth conductive layer M4, and the third spare signal line 13 is located on the third conductive layer M3. The data voltage Vdata is transmitted to the second spare signal line 12, then switched to the third spare signal line 13 via the first type via K1, then switched to the first data line DL1 via the first type via K1, and finally transmitted to the pixel circuit 200 of the corresponding column via the first data line DL1.

[0042] Optionally, in this embodiment, the first backup signal line 11 and the second backup signal line 12 are located in the areas of pixel circuits 200 in different columns. In the same column of pixel circuits 200, the display panel includes the first backup signal line 11 or the second backup signal line 12.

[0043] Specifically, within the same column of pixel circuits 200, the display panel only includes either the first spare signal line 11 or the second spare signal line 12. The first spare signal line 11 and the second spare signal line 12 will not coexist in the same pixel circuit 200. This arrangement has two advantages: firstly, it reduces the density of signal lines, lowers the possibility of mutual interference between lines, and thus improves the accuracy and stability of signal transmission. Secondly, each column of pixel circuits 200 only requires adding one spare signal line to the existing layout structure. Depending on the requirements of different transmitted signals, different connection lines can be used to rationally utilize the layout space of the display panel. For example, the first spare signal line 11 and the first gate signal line GL1 can be connected via the first connection line 31, allowing the gate drive signal output by the gate drive circuit 100 to be connected to the first gate signal line GL1 within the display area AA; similarly, the first data line DL1 and the second spare signal line 12 can be connected via the third spare signal line 13 and the second connection line 32, allowing the data voltage Vdata to be connected to the first data line DL1 within the display area AA.

[0044] Optionally, the first spare signal line 11 is located in the area where the Nth column pixel circuit 200 is located, and the second spare signal line 12 is located in the area where the (N+1)th column pixel circuit 200 is located, where N is an integer greater than or equal to 1.

[0045] Optionally, the orthographic projection of the first spare signal line 11 onto the substrate 20 does not overlap with the orthographic projection of the second spare signal line 12 onto the substrate 20. In pixel circuits 200 of different columns, the first spare signal line 11 and the second spare signal line 12 are positioned in the same location in the corresponding column of pixel circuit 200, which helps to ensure the consistency of the layout structure of each pixel circuit 200.

[0046] Figure 9 is a schematic diagram of another display panel layout structure provided by an embodiment of the present invention. Referring to Figure 9, based on the above embodiments, the display panel may optionally include a first mesh structure. The first mesh structure includes a first sub-signal line 41, a fourth spare signal line 14 and a third connecting line 33. Multiple first sub-signal lines 41 extend along a first direction X and are arranged along a second direction Y. Multiple fourth spare signal lines 14 extend along the second direction Y and are arranged along the first direction X. The first sub-signal lines 41 are connected to the fourth spare signal lines 14 through the third connecting line 33.

[0047] The first sub-signal line 41 is connected to one end of the third connecting line 33 through a second type via K2, and the fourth spare signal line 14 is connected to the other end of the third connecting line 33 through a first type via K1.

[0048] The technical solution provided in this embodiment, by forming the first sub-signal line 41, the fourth spare signal line 14 and the third connecting line 33 of the first mesh structure, can reduce the impedance of the first mesh structure, thereby reducing the difference in the signal transmitted by the first mesh structure signal line at different positions on the display panel, and thus improving the brightness uniformity of the display panel and improving the display quality.

[0049] Figure 10 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention, specifically a schematic diagram of the structure of the third conductive layer M3; Figure 11 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention, specifically a schematic diagram of the structure of the active layer 10, the first conductive layer M1, the second conductive layer M2 and the third conductive layer M3; Figure 12 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention, specifically a schematic diagram of the structure of the fourth conductive layer M4; Figure 13 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention, specifically a schematic diagram of the structure of the second conductive layer M2, the third conductive layer M3 and the fourth conductive layer M4; Figure 14 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention; Figure 15 is a schematic diagram of the cross-sectional structure of another display panel provided in an embodiment of the present invention, wherein Figure 15 is specifically a cross-sectional structure obtained along the cutting line CC' of the display panel shown in Figure 14. Referring to Figures 10 to 15, based on the above embodiments, optionally, the first sub-signal line 41 and the fourth spare signal line 14 are arranged in different layers, and the third connecting line 33 is arranged in different layers from the first sub-signal line 41. The multilayer conductive layer also includes a second conductive layer M2, which is located between the first conductive layer M1 and the third conductive layer M3. The first sub-signal line 41 is located in the second conductive layer M2, the fourth spare signal line 14 is located in the fourth conductive layer M4, and the third connecting line 33 is located in the third conductive layer M3.

[0050] Referring again to Figures 5, 10 to 15, the display panel further includes a second gate signal line GL2, a fourth connection line 34 and a fifth connection line 35. The pixel circuit 200 also includes a fourth transistor T4. The second gate signal line GL2 overlaps with the active layer 10 to form the gate of the fourth transistor T4. The first electrode of the fourth transistor T4 is connected to the first sub-signal line 41 through the fourth connection line 34, and the second electrode of the fourth transistor T4 is connected to the gate of the driving transistor T0 through the fifth connection line 35.

[0051] Specifically, the first electrode of the fourth transistor T4 is connected to one end of the fourth connection line 34 through the second type via K2, the first sub-signal line 41 is connected to the other end of the fourth connection line 34 through the second type via K2, the second electrode of the fourth transistor T4 is connected to one end of the fifth connection line 35 through the second type via K2, and the gate of the driving transistor T0 is connected to the other end of the fifth connection line T5 through the second type via K2.

[0052] Optionally, the first mesh structure is used to transmit the first initialization voltage Vrefn1, and the fourth transistor T4 is used to transmit the first initialization voltage Vrefn1 to the gate of the driving transistor T0 to initialize the gate of the driving transistor T0. The second gate signal line GL2 is located in the first conductive layer M1, the fifth connection line 35 is located in the third conductive layer M3, and both the third connection line 33 and the fourth connection line 34 are located in the third conductive layer M3.

[0053] Optionally, the fourth transistor M4 can be a single-gate transistor or a horizontal dual-gate transistor. Of course, in other embodiments, the first terminal of the fourth transistor T4 can also be connected to the fourth spare signal line 14.

[0054] Optionally, the orthographic projection of the third backup signal line 13 on the substrate 20 may partially overlap with the orthographic projection of the first sub-signal line 41 on the substrate 20.

[0055] Referring again to Figures 9, 10 to 15, the display panel also includes a second mesh structure. The second mesh structure includes a second sub-signal line 42, a fifth spare line 15, and a sixth connecting line 36. Multiple second sub-signal lines 42 extend along the first direction X and are arranged along the second direction Y. Multiple fifth spare signal lines 15 extend along the second direction Y and are arranged along the first direction X. The second sub-signal lines 42 are connected to the fifth spare signal lines 15 through the sixth connecting line 36.

[0056] The technical solution provided in this embodiment, by forming the second sub-signal line 42, the fifth spare line 15 and the sixth connecting line 36 of the second mesh structure, can reduce the impedance of the second mesh structure, thereby reducing the difference in the signal transmitted by the second mesh structure signal line at different positions on the display panel, and thus improving the brightness uniformity of the display panel and improving the display quality.

[0057] Figure 16 is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention. Specifically, it is the cross-sectional structure obtained along the cutting line DD' of the display panel shown in Figure 14. Referring to Figures 14 to 16, the second sub-signal line 42 and the fifth spare signal line 15 are disposed on different layers, and the sixth connecting line 36 is disposed on a different layer from the second sub-signal line 42. For example, the second sub-signal line 42 is located in the second conductive layer M2, the fifth spare signal line 15 is located in the fourth conductive layer M4, and the sixth connecting line 36 is located in the third conductive layer M2.

[0058] In this embodiment, the second sub-signal line 42 is connected to one end of the sixth connecting line 36 through a second type via K2, and the fifth spare signal line 15 is connected to the other end of the sixth connecting line 36 through a first type via K1. That is, the connection between the fifth spare signal line 15 and the second sub-signal line 42 on the upper and lower layers is achieved through the sixth connecting line 36 located on the third conductive layer M3.

[0059] Optionally, the orthographic projection of the fifth spare signal line 15 on the substrate 20 at least partially covers the orthographic projection of the sixth connection line 36 on the substrate 20. By stacking the fifth spare signal line 15 and the sixth connection line 36, it is beneficial to reduce the area occupied by the layout, optimize the layout space, and thus improve the layout utilization.

[0060] Based on the above embodiment, and referring to Figure 5, the pixel circuit 200 further includes a fifth transistor T5. The gate of the fifth transistor T5 is formed at the intersection of the second gate signal line GL2 and the active layer 10. The first terminal of the fifth transistor T5 is connected to one end of the sixth connection line 36 through a second type via K2, and the second terminal of the fifth transistor T5 is connected to the first terminal of the light-emitting element. The second mesh structure is used to transmit the second initialization voltage Vrefn2, and the fifth transistor T5 is used to transmit the second initialization voltage Vrefn2 to the first terminal of the light-emitting element to initialize the first terminal of the light-emitting element.

[0061] Figure 17 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention. Specifically, it is a partially enlarged schematic diagram of the display panel shown in Figure 14. Referring to Figures 14-17, the display panel also includes a third gate signal line GL3, and the pixel circuit 200 also includes a sixth transistor T6. The third gate signal line GL3 and the active layer 20 overlap to form the gate of the third transistor T3 and the gate of the sixth transistor T6, respectively. The orthogonal projection of the third gate signal line GL3 on the substrate 20 is located between the orthogonal projection of the gate of the driving transistor T0 on the substrate 20 and the orthogonal projection of the second sub-signal line 42 on the substrate 20.

[0062] The second sub-signal line 42 includes a first main body portion 421 extending along the first direction X, a first branch portion 422 extending along the second direction Y, and a second branch portion 423 extending along the second direction Y. The orthographic projection of the first branch portion 422 on the substrate 20 does not overlap with the orthographic projection of the second branch portion 423 on the substrate 20, and the orthographic projection of the first branch portion 422 on the substrate 20 does not overlap with the orthographic projection of the third gate signal line GL3 on the substrate 20, and the orthographic projection of the second branch portion 423 on the substrate 20 does not overlap with the orthographic projection of the third gate signal line GL3 on the substrate 20.

[0063] In this embodiment, the orthographic projection of the first branch 422 on the substrate 20 does not overlap with the orthographic projection of the connection hole between the first data line DL1 and the second connection line 32 on the substrate 20, nor with the orthographic projection of the connection hole between the second electrode of the fourth transistor T4 and the fifth connection line 35 on the substrate 20. In the first direction X, the orthographic projection of the first branch 422 on the substrate 20 is located between the orthographic projections of the connection hole between the first data line DL1 and the second connection line 32 and the connection hole between the second electrode of the fourth transistor T4 and the fifth connection line 35 on the substrate 20, thus shielding the data voltage Vdata and the gate signal of the driving transistor T0, which is beneficial for improving signal reliability and stability.

[0064] Optionally, the orthographic projection of the first branch 422 onto the substrate 20 at least partially covers the orthographic projection of the second electrode of the fourth transistor T4 onto the substrate 20, so as to prevent the signal transmitted by the fourth transistor T4 from being interfered with by other signals.

[0065] Referring again to Figure 17, the sixth transistor T6 is used to compensate for the threshold voltage of the driving transistor T0. The sixth transistor T6 can be a horizontal dual-gate transistor. The third gate signal line GL3 includes a second main body GL3-1 extending along the first direction X and a third branch GL3-2 extending along the second direction Y. The second main body GL3-1 overlaps with the active layer 10 to form the gate of the third transistor T3 and the first gate of the sixth transistor T6, respectively. The third branch GL3-2 overlaps with the active layer 10 to form the second gate of the sixth transistor T6. The dual-gate node of the sixth transistor T6 is located in the active layer 10. The orthographic projection of the second branch 423 onto the substrate 20 covers at least a portion of the orthographic projection of the dual-gate node of the sixth transistor T6 onto the substrate 20, which helps to improve the potential stability of the dual-gate node of the sixth transistor T6.

[0066] Optionally, the first gate signal line GL1 can be used to transmit the light emission control signal EM, the second gate signal line GL2 can be used to transmit the second scan signal SP2, and the third gate signal line GL3 can be used to transmit the first scan signal SP1.

[0067] Figure 18 is a schematic diagram of another display panel layout structure provided by an embodiment of the present invention. Referring to Figure 18, based on the above embodiments, the display panel may optionally further include a third mesh structure. The third mesh structure includes first power lines 51 and second power lines 52. Multiple first power lines 51 extend along a first direction X and are arranged along a second direction Y. Multiple second power lines 52 extend along the second direction Y and are arranged along the first direction X. The first power lines 51 and second power lines 52 are disposed in different layers. The first power lines 51 are connected to the second power lines 52 through a first type of via K1. The third mesh structure can be used to transmit power supply voltage, such as transmitting the first power supply voltage VDD shown in Figure 5.

[0068] The technical solution provided in this embodiment can reduce the impedance of the third mesh structure by forming the first power line 51 and the second power line 52 of the third mesh structure, thereby reducing the difference in the signal transmitted by the signal line of the third mesh structure at different positions on the display panel, and thus improving the brightness uniformity of the display panel and improving the display quality.

[0069] In this embodiment, the first, second, and third mesh structures are mutually insulated. Furthermore, without adding additional film layers, these three mutually insulated mesh structures can be achieved based on the existing film layer structure, significantly improving film layer utilization and reducing manufacturing costs. Since the signal lines corresponding to the first initialization voltage Vrefn1, the second initialization voltage Vrefn2, and the first power supply voltage VDD are all mesh structures, the differences in the initialization levels of the gates of the driving transistors T0 and the first electrodes of the light-emitting elements D1 in each pixel circuit 200 of the display panel can be reduced, as can the differences in the first power supply voltage VDD at different locations on the display panel. This improves the brightness uniformity of the display panel and enhances display quality.

[0070] It should be understood that a second power line 52 is provided in the area where each column of pixel circuits 200 is located.

[0071] Figure 19 is a schematic diagram of a connection unit provided in an embodiment of the present invention. Optionally, referring to Figures 18 and 19, the first power line 51 includes a plurality of connection units arranged sequentially along a first direction. The connection unit includes a first connection portion 501 extending along the first direction X, and a second connection portion 502 and a third connection portion 503 extending along the second direction Y. In the same connection unit, the first connection portion 501 is connected to the second connection portion 502. The second connection portion 502 is connected to the second power line 52 through a first type via K1. The third connection portion 503 is connected to the first connection portion 501.

[0072] The second connection portion 502 can be connected upwards to the second power line 52 along the second direction Y, and / or downwards to the second power line 52. That is, along the second direction Y, within the layout space of the same pixel circuit 200, the connection node between the second connection portion 502 and the second power line 52 can be located above the gate of the driving transistor T0 or below the gate of the driving transistor T0.

[0073] Optionally, the first connecting part 501, the second connecting part 502 and the third connecting part 503 are integral structures. In two adjacent connecting units, the third connecting part 503 in the first connecting unit and the first connecting part 501 in the second connecting unit are connected to form an integral structure.

[0074] Figure 20 is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention. Referring to Figures 19 and 20, the orthographic projection of the third connection portion 503 on the substrate 20 covers at least part of the orthographic projection of the first spare signal line 11 on the substrate 20, so as to use the third connection portion 503 to shield the signal transmitted on the first spare signal line 11 and improve the stability of the signal transmitted on the first spare signal line 11.

[0075] Specifically, the orthographic projection of the first backup signal line 11 on the substrate 20 is separate from the orthographic projection of the gate of the driving transistor T0 on the substrate 20, and the orthographic projection of the third connection portion 503 on the substrate 20 simultaneously covers at least a portion of the orthographic projection of the first backup signal line 11 on the substrate 20 and at least a portion of the orthographic projection of the gate of the driving transistor T0 on the substrate 20.

[0076] Optionally, the orthographic projection of the third connection portion 503 on the substrate 20 similarly covers at least a portion of the orthographic projections of the second spare signal line 12, the fourth spare signal line 14, and the fifth spare signal line 15 on the substrate 20, thus having the same shielding effect.

[0077] Optionally, the pixel circuit 200 further includes a storage capacitor Cst, with its first plate located on the first conductive layer M1 and its second plate located on the second conductive layer M2. The first connection portion 501 is connected to the second plate of the storage capacitor Cst through a second type via K2. The gate of the driving transistor T0 is reused as the first plate of the storage capacitor Cst.

[0078] Optionally, the orthographic projection of the second plate of the storage capacitor Cst onto the substrate 20 covers a portion of the orthographic projection of the gate of the driving transistor T0 onto the substrate 20. The area where the second plate of the storage capacitor Cst overlaps with the gate of the driving transistor T0 is the effective area of ​​the storage capacitor Cst.

[0079] Referring again to Figures 9 and 20, the first backup signal line 11, the second backup signal line 12, and the fourth backup signal line 14 are located in different columns of pixel circuits 200. Within the same column of pixel circuits 200, the display panel includes one of the first backup signal line 11, the second backup signal line 12, or the fourth backup signal line 14. For example, the first backup signal line 11 is located in the Nth column of pixel circuits 200, the second backup signal line 12 is located in the (N+1)th column of pixel circuits 200, and the fourth backup signal line 14 is located in the (N+2)th column of pixel circuits 200, where N is an integer greater than or equal to 1.

[0080] Furthermore, the first backup signal line 11, the second backup signal line 12, the fourth backup signal line 14, and the fifth backup signal line 15 are located in the areas of different columns of pixel circuits 200. Within the same column of pixel circuits 200, the display panel includes one of the first backup signal line 11, the second backup signal line 12, the fourth backup signal line 14, or the fifth backup signal line 15. For example, the first backup signal line 11 is located in the area of ​​the Nth column of pixel circuits 200, the second backup signal line 12 is located in the area of ​​the (N+1)th column of pixel circuits 200, the fourth backup signal line 14 is located in the area of ​​the (N+2)th column of pixel circuits 200, and the fifth backup signal line 15 is located in the area of ​​the (N+3)th column of pixel circuits 200, where N is an integer greater than or equal to 1.

[0081] In other words, the four columns of pixel circuits 200 containing the first backup signal line 11, the second backup signal line 12, the fourth backup signal line 14, and the fifth backup signal line 15 are repeated as a group. The first backup signal line 11, the second backup signal line 12, the fourth backup signal line 14, and the fifth backup signal line 15 can be arranged sequentially or arbitrarily, and the specific arrangement can be flexibly set according to the actual layout requirements.

[0082] Optionally, in this embodiment, the trace breaks of the first spare signal line 11, the second spare signal line 12, the third spare signal line 13, the fourth spare signal line 14, and / or the fifth spare signal line 15 at the location of the first type via K1 are presented in a "V" shape, a " / " shape, a "\" shape, or a "W" shape within the display area AA, which is beneficial for optimizing the layout design. Here, a trace break refers to the break created at the location of the first type via K1 when the spare signal line connects to the lower layer's connecting line or signal line, in order to reduce the length of the signal line and thus reduce line impedance. As shown in Figure 2, the break at the first spare signal line 11 is generally in a "\" shape, and as shown in Figure 6, the break at the third spare signal line 13 is generally in a " / " shape.

[0083] Optionally, the trace break can be shielded by an upper conductive layer to block interference signals, which can effectively reduce the risk of display defects such as slanted bright lines and mura, thereby improving display quality.

[0084] This invention also provides a display device, which includes the display panel provided in any embodiment of this invention. Therefore, this display device also possesses the beneficial effects described in any of the above embodiments. The display panel can be a flexible display panel or a rigid display panel. Figure 21 is a schematic diagram of the structure of a display device provided in an embodiment of this invention. In this embodiment, the display device 500 can be a mobile phone or any electronic product with display function, including but not limited to the following categories: display panels in products such as televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, and touch interactive terminals. This invention does not impose any special limitations on these categories.

[0085] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0086] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, The display panel includes a gate driving circuit and a pixel circuit. It has a display area and a non-display area at least partially surrounding the display area. The non-display area includes a curved corner area and a non-curved corner area. The gate driving circuit is located in the non-curved corner area, and the pixel circuit is located in the display area. The display panel further includes a substrate; a plurality of first gate signal lines and a plurality of first spare signal lines located on the substrate. The plurality of first gate signal lines extend along a first direction and are arranged along a second direction. The plurality of first spare signal lines extend along the second direction and are arranged along the first direction. The gate driving circuit is connected to the first gate signal lines via the first spare signal lines. The first gate signal lines are connected to the pixel circuit. At least a portion of the first spare signal lines are located in the display area. The first direction and the second direction intersect.

2. The display panel according to claim 1, characterized in that, The first gate signal line and the first spare signal line are disposed on different layers; preferably, the display panel further includes a multilayer conductive layer stacked on the substrate, the multilayer conductive layer including a first conductive layer and a fourth conductive layer, the fourth conductive layer being located on the side of the first conductive layer away from the substrate, the first gate signal line being located on the first conductive layer, and the first spare signal line being located on the fourth conductive layer; preferably, the display panel further includes an active layer, the active layer being located between the substrate and the first conductive layer, the pixel circuit including a driving transistor, a first transistor and a second transistor, the overlapping position of the first gate signal line and the active layer respectively forming the gate of the first transistor and the gate of the second transistor, the first electrode of the driving transistor being connected to the second electrode of the first transistor through the active layer, the second electrode of the driving transistor being connected to the first electrode of the second transistor through the active layer, and the second electrode of the second transistor being connected to the light-emitting element; preferably, the first transistor and the second transistor are used to control the driving transistor to drive the light-emitting element to emit light; preferably, the gate driving circuit is used to output a light-emitting control signal, and the first gate signal line is used to transmit the light-emitting control signal to the gate of the first transistor and the gate of the second transistor.

3. The display panel according to claim 2, characterized in that, The multilayer conductive layer further includes a first connecting line, through which the first spare signal line is connected to the first gate signal line; preferably, the first connecting line is disposed on a different layer from the first spare signal line and the first gate signal line; preferably, the multilayer conductive layer further includes a third conductive layer, which is located between the first conductive layer and the fourth conductive layer, and the first connecting line is located on the third conductive layer; preferably, the first spare signal line is connected to one end of the first connecting line through a first type of via, and the first gate signal line is connected to the other end of the first connecting line through a second type of via.

4. The display panel according to claim 2, characterized in that, The pixel circuit further includes a third transistor, and the display panel further includes multiple first data lines, multiple second spare signal lines, and multiple third spare signal lines. The multiple first data lines extend along the second direction and are arranged along the first direction; the multiple second spare signal lines extend along the second direction and are arranged along the first direction; and the multiple third spare signal lines extend along the first direction and are arranged along the second direction. The second spare signal lines and the third spare signal lines are at least partially located in the display area. The second spare signal lines are connected to the first data lines via the third spare signal lines. The first data lines are connected to the first electrode of the third transistor via a second connecting line. The second electrode of the third transistor is connected to the first electrode of the driving transistor via the active layer. Preferably, the multilayer conductive layer further includes a third conductive layer, which is located between the first conductive layer and the fourth conductive layer, and the second connecting line is located on the third conductive layer. The second backup signal line is connected to one end of the third backup signal line through a first type of via, and one end of the first data line is connected to the other end of the third backup signal line through the first type of via. The first electrode of the third transistor is connected to one end of the second connecting line through a second type of via, and the other end of the second connecting line is connected to the other end of the first data line through the first type of via. Preferably, the first data line and the second backup signal line are disposed on the same layer, and the second backup signal line and the third backup signal line are disposed on different layers. Preferably, the first data line and the second backup signal line are located on the fourth conductive layer, and the third backup signal line is located on the third conductive layer. Preferably, the display panel further includes multiple second data lines, the second data lines are located on the side of the first data line near the display area, the multiple second data lines extend along the second direction and are arranged along the first direction, and one second data line is connected to a column of pixel circuits.

5. The display panel according to claim 4, characterized in that, The first spare signal line and the second spare signal line are located in different columns of the pixel circuit area. In the same column of the pixel circuit, the display panel includes either the first spare signal line or the second spare signal line. Preferably, the orthographic projection of the first spare signal line on the substrate does not overlap with the orthographic projection of the second spare signal line on the substrate. Preferably, the first spare signal line is located in the Nth column of the pixel circuit area, and the second spare signal line is located in the (N+1)th column of the pixel circuit area, where N is an integer greater than or equal to 1.

6. The display panel according to claim 4, characterized in that, The display panel further includes a first mesh structure, which includes a first sub-signal line, a fourth spare signal line, and a third connecting line. Multiple first sub-signal lines extend along a first direction and are arranged along a second direction, and multiple fourth spare signal lines extend along the second direction and are arranged along the first direction. The first sub-signal lines are connected to the fourth spare signal lines via the third connecting line. Preferably, the first sub-signal lines are connected to one end of the third connecting line via a second type of via, and the fourth spare signal lines are connected to the other end of the third connecting line via a first type of via. Preferably, the first sub-signal lines and the fourth spare signal lines are disposed on different layers. The third connecting line is disposed on a different layer from the first sub-signal line; preferably, the multilayer conductive layer further includes a second conductive layer, which is located between the first conductive layer and the third conductive layer, the first sub-signal line is located on the second conductive layer, the fourth spare signal line is located on the fourth conductive layer, and the third connecting line is located on the third conductive layer; preferably, the display panel further includes a second gate signal line, a fourth connecting line, and a fifth connecting line, and the pixel circuit further includes a fourth transistor, the gate of the fourth transistor is formed at the intersection of the second gate signal line and the active layer, and the first electrode of the fourth transistor is connected to the first sub-signal line through the fourth connecting line. The second terminal of the fourth transistor is connected to the gate of the driving transistor via a fifth connection line; preferably, the first terminal of the fourth transistor is connected to one end of the fourth connection line via a second type of via, the first sub-signal line is connected to the other end of the fourth connection line via a second type of via, the second terminal of the fourth transistor is connected to one end of the fifth connection line via a second type of via, and the gate of the driving transistor is connected to the other end of the fifth connection line via a second type of via; preferably, the first mesh structure is used to transmit the first initialization voltage, and the fourth transistor is used to transmit the first initialization voltage to the gate of the driving transistor; preferably, the The second gate signal line is located in the first conductive layer, and the fifth connection line is located in the third conductive layer; preferably, the first spare signal line, the second spare signal line, and the fourth spare signal line are located in different columns of the pixel circuit area, and in the same column of the pixel circuit, the display panel includes one of the first spare signal line, the second spare signal line, or the fourth spare signal line; preferably, the first spare signal line is located in the Nth column of the pixel circuit area, the second spare signal line is located in the N+1th column of the pixel circuit area, and the fourth spare signal line is located in the N+2th column of the pixel circuit area, where N is an integer greater than or equal to 1.

7. The display panel according to claim 6, characterized in that, The display panel further includes a second mesh structure, which includes a second sub-signal line, a fifth spare line, and a sixth connecting line. Multiple second sub-signal lines extend along the first direction and are arranged along the second direction. Multiple fifth spare signal lines extend along the second direction and are arranged along the first direction. The second sub-signal lines are connected to the fifth spare signal lines via the sixth connecting line. Preferably, the second sub-signal lines are connected to one end of the sixth connecting line via a second type of via, and the fifth spare signal lines are connected to the other end of the sixth connecting line via a first type of via. Preferably, the second sub-signal lines and the fifth spare signal lines are disposed on different layers, and the sixth connecting line is disposed on a different layer from the second sub-signal lines. Preferably, the second sub-signal lines are located on the second conductive layer, the fifth spare signal lines are located on the fourth conductive layer, and the sixth connecting line is located on the third conductive layer. Preferably, the pixel circuit further includes a fifth transistor, and the gate of the fifth transistor is formed at the intersection of the second gate signal line and the active layer. The first electrode of the fifth transistor is connected to one end of the sixth connecting line via a second type of via, and the second electrode of the fifth transistor is connected to the first electrode of the light-emitting element. Preferably, the fifth spare signal line is connected to the second connecting line via a second type of via. The orthographic projection on the substrate at least partially covers the orthographic projection of the sixth connecting line on the substrate; preferably, the second mesh structure is used to transmit the second initialization voltage, and the fifth transistor is used to transmit the second initialization voltage to the first electrode of the light-emitting element; preferably, the first spare signal line, the second spare signal line, the fourth spare signal line, and the fifth spare signal line are respectively located in the areas where the pixel circuits are located in different columns, and in the same column of the pixel circuits, the display panel includes one of the first spare signal line, the second spare signal line, the fourth spare signal line, or the fifth spare signal line; preferably, the... The first spare signal line is located in the area where the pixel circuit is located in the Nth column, the second spare signal line is located in the area where the pixel circuit is located in the (N+1)th column, the fourth spare signal line is located in the area where the pixel circuit is located in the (N+2)th column, and the fifth spare signal line is located in the area where the pixel circuit is located in the (N+3)th column, where N is an integer greater than or equal to 1; preferably, the trace breaks of the first spare signal line, the second spare signal line, the third spare signal line, the fourth spare signal line and / or the fifth spare signal line at the location of the first type of via present an overall "V" shape, " / " shape, "\" shape or "W" shape within the display area.

8. The display panel according to claim 7, characterized in that, The display panel further includes a third gate signal line, and the pixel circuit further includes a sixth transistor. The third gate signal line overlaps with the active layer to form the gate of the third transistor and the gate of the sixth transistor, respectively. The orthographic projection of the third gate signal line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the second sub-signal line on the substrate. The second sub-signal line includes a first main body extending along the first direction, a first branch extending along the second direction, and a second branch extending along the second direction. The orthographic projection of the first branch on the substrate does not overlap with the orthographic projection of the second branch on the substrate, and the orthographic projection of the first branch on the substrate does not overlap with the orthographic projection of the third gate signal line on the substrate. Preferably, in the first direction, the orthographic projection of the first branch on the substrate is located between the orthographic projection of the connection hole of the first data line and the second connection line on the substrate and the second electrode of the fourth transistor and the fifth... The connection holes of the connecting lines are between the orthographic projections on the substrate; preferably, the orthographic projection of the first branch portion on the substrate does not overlap with the orthographic projections of the connection holes of the first data line and the second connecting line on the substrate, nor with the orthographic projections of the connection holes of the second electrode of the fourth transistor and the fifth connecting line on the substrate; preferably, the orthographic projection of the first branch portion on the substrate at least partially covers the orthographic projection of the second electrode of the fourth transistor on the substrate; preferably, the third gate signal line includes a second main body portion extending along the first direction and a third branch portion extending along the second direction, the second main body portion overlapping with the active layer respectively forming the gate of the third transistor and the first gate of the sixth transistor, the third branch portion overlapping with the active layer forming the second gate of the sixth transistor, and the dual-gate node of the sixth transistor is located on the active layer; preferably, the orthographic projection of the second branch portion on the substrate covers at least part of the orthographic projection of the dual-gate node of the sixth transistor on the substrate; preferably, the sixth transistor is used to compensate for the threshold voltage of the driving transistor.

9. The display panel according to claim 2, characterized in that, The display panel further includes a third mesh structure, which includes a first power line and a second power line. Multiple first power lines extend along a first direction and are arranged along a second direction, and multiple second power lines extend along the second direction and are arranged along the first direction. The first power lines and second power lines are disposed in different layers, and the first power lines are connected to the second power lines through a first type of via. Preferably, the first power line includes multiple connecting units arranged sequentially along the first direction. Each connecting unit includes a first connecting portion extending along the first direction, and a second connecting portion and a third connecting portion extending along the second direction. Within the same connecting unit, the first connecting portion is connected to the second connecting portion, the second connecting portion is connected to the second power line through the first type of via, and the third connecting portion is connected to the first connecting portion. Preferably, the first connecting portion, the second connecting portion, and the third connecting portion are an integral structure. Preferably, in the phase... In two adjacent connection units, the third connection portion in the preceding connection unit and the first connection portion in the following connection unit are connected as a single structure; preferably, the orthographic projection of the third connection portion on the substrate covers at least a portion of the orthographic projection of the first spare signal line on the substrate; preferably, the orthographic projection of the first spare signal line on the substrate is separate from the orthographic projection of the gate of the driving transistor on the substrate, and the orthographic projection of the third connection portion on the substrate simultaneously covers at least a portion of the orthographic projection of the first spare signal line on the substrate and at least a portion of the orthographic projection of the gate of the driving transistor on the substrate; preferably, the pixel circuit further includes a storage capacitor, the first electrode of the storage capacitor is located on the first conductive layer, the second electrode of the storage capacitor is located on the second conductive layer, the second conductive layer is located between the first conductive layer and the fourth conductive layer, and the first connection portion is connected to the second electrode of the storage capacitor through a second type of via.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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