Display panel, driving method thereof and display device

Abstract

The embodiment of the invention provides a display panel, a driving method thereof and a display device. The display panel comprises a plurality of pixel units, a plurality of pairs of grid lines and a plurality of data lines, the display area comprises a display sub-area, the display sub-area meets at least one of three items, the first item comprises a first target sub-pixel pair and a second target sub-pixel pair which are respectively arranged in two adjacent rows of sub-pixels and are coupled with a first target data line, and the second target sub-pixel pair and the second target sub-pixel pair are respectively arranged in two adjacent rows of sub-pixels and are coupled with a second target data line. The second sub-pixel in the first target sub-pixel pair is coupled with the corresponding grid line between the two adjacent rows of sub-pixels, the third sub-pixel in the second target sub-pixel pair is coupled with the corresponding grid line between the two adjacent rows of sub-pixels, and the first target data line is located between the second sub-pixel and the third sub-pixel. According to the invention, the pre-charging effect can be improved, the brightness difference between adjacent pixel columns is reduced, and the poor vertical lines are improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. Background Technology

[0002] With the continuous advancement of flat panel display technology, liquid crystal displays (LCDs) have been successfully applied to display devices such as flat panels, televisions, and computers. Each liquid crystal pixel on an LCD is driven by a thin-film transistor integrated on it, enabling high-speed, high-brightness, and high-contrast display of information.

[0003] Figure 1 This is a planar schematic diagram of a liquid crystal display. (For example...) Figure 1 As shown, the liquid crystal display (LCD) includes multiple sub-pixels P arranged in an array, with every three sub-pixels R, G, and B forming a pixel unit. The LCD also includes multiple gate lines (Gate) and multiple data lines (Data), with the thin-film transistors (TFTs) of each sub-pixel connected to their corresponding gate lines and data lines. The display further includes a gate driving module and a data driving module; the gate lines are connected to the gate driving module, and the data lines are connected to the data driving module. The gate driving module provides gate signals to the TFTs via the gate lines, and the data driving module provides data signals to the TFTs via the data lines.

[0004] With the development of LCD technology and the increase in demand, high-frequency TDDI (Touch and Display Driver Integration) dual-grid display products have emerged. In related technologies, TDDI products are prone to vertical stripe defects when displaying sky blue images, affecting the display effect. Summary of the Invention

[0005] This disclosure provides a display panel and its driving method, as well as a display device, to solve or alleviate one or more technical problems in the prior art.

[0006] As a first aspect of the present disclosure, a display panel is provided, including a display area, the display area comprising:

[0007] Multiple pixel units arranged in an array, each pixel unit including a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged along a first direction;

[0008] Multiple pairs of gate lines extending along the first direction correspond one-to-one with multiple rows of sub-pixels. Each pair of gate lines includes an odd number of gate lines and an even number of gate lines. The odd number of gate lines and the even number of gate lines are located on opposite sides of the corresponding row of sub-pixels. The odd number of gate lines are coupled to a portion of the sub-pixels in the corresponding row of sub-pixels, and the even number of gate lines are coupled to another portion of the sub-pixels in the corresponding row of sub-pixels.

[0009] Multiple data lines are arranged along the first direction, with two columns of sub-pixels between two adjacent data lines. Each row of sub-pixels is divided into multiple sub-pixel pairs by the multiple data lines. Along the arrangement direction of the multiple rows of sub-pixels, the data lines are alternately coupled to the sub-pixel pairs located on both sides.

[0010] The display area includes at least one display sub-area, and the display sub-area satisfies at least one of the following:

[0011] In two adjacent rows of sub-pixels, a first target sub-pixel pair and a second target sub-pixel pair coupled to the first target data line are respectively set. The second sub-pixel in the first target sub-pixel pair is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. The third sub-pixel in the second target sub-pixel pair is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. The first target data line is located between the second sub-pixel and the third sub-pixel.

[0012] In two adjacent rows of sub-pixels, a third target sub-pixel pair and a fourth target sub-pixel pair coupled to a second target data line are respectively set. The third target sub-pixel pair includes a second sub-pixel and a third sub-pixel. The fourth target sub-pixel pair includes a first sub-pixel and a non-first sub-pixel. One sub-pixel in the third target sub-pixel pair is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. The non-first sub-pixel in the fourth target sub-pixel pair is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. The third target sub-pixel pair is configured to be refreshed before the fourth target sub-pixel pair. The second target data line is located between the first sub-pixel and the second sub-pixel or between the third sub-pixel and the first sub-pixel.

[0013] A fifth target sub-pixel pair and a sixth target sub-pixel pair, coupled to a second target data line, are respectively set in two adjacent rows of sub-pixels. The fifth target sub-pixel pair includes a first sub-pixel and a non-first sub-pixel, and the sixth target sub-pixel pair includes a second sub-pixel and a third sub-pixel. The first sub-pixel in the fifth target sub-pixel pair is coupled to the corresponding gate line between the two adjacent rows of sub-pixels, and one sub-pixel in the sixth target sub-pixel pair is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. The fifth target sub-pixel pair is configured to be refreshed before the sixth target sub-pixel pair. The second target data line is located between the first sub-pixel and the second sub-pixel or between the third sub-pixel and the first sub-pixel.

[0014] In some embodiments, the second target data line is located between the first sub-pixel and the second sub-pixel, the non-first sub-pixel in the fourth target sub-pixel pair is the third sub-pixel, the third target sub-pixel pair is located in the upper sub-pixel of the two adjacent rows of sub-pixels, the fourth target sub-pixel pair is located in the lower sub-pixel of the two adjacent rows of sub-pixels, the fourth target sub-pixel pair is located on the first side of the second target data line, and the third target sub-pixel pair is located on the second side of the second target data line.

[0015] In some embodiments, the second target data line is located between the third sub-pixel and the first sub-pixel, the non-first sub-pixel in the fourth target sub-pixel pair is the second sub-pixel, the third target sub-pixel pair is located in the upper sub-pixel of the two adjacent rows of sub-pixels, the fourth target sub-pixel pair is located in the lower sub-pixel of the two adjacent rows of sub-pixels, the third target sub-pixel pair is located on the first side of the second target data line, and the fourth target sub-pixel pair is located on the second side of the second target data line.

[0016] In some embodiments, the second target data line is located between the first sub-pixel and the second sub-pixel, the non-first sub-pixel in the fifth target sub-pixel pair is the third sub-pixel, the fifth target sub-pixel pair is located in the upper sub-pixel of the two adjacent rows of sub-pixels, the sixth target sub-pixel pair is located in the lower sub-pixel of the two adjacent rows of sub-pixels, the fifth target sub-pixel pair is located on the first side of the second target data line, and the sixth target sub-pixel pair is located on the second side of the second target data line.

[0017] In some embodiments, the second target data line is located between the third sub-pixel and the first sub-pixel, the non-first sub-pixel in the fifth target sub-pixel pair is the second sub-pixel, the fifth target sub-pixel pair is located in the upper sub-pixel of the two adjacent rows of sub-pixels, the sixth target sub-pixel pair is located in the lower sub-pixel of the two adjacent rows of sub-pixels, the sixth target sub-pixel pair is located on the first side of the second target data line, and the fifth target sub-pixel pair is located on the second side of the second target data line.

[0018] In some embodiments, a display sub-region is provided with four rows and six columns of sub-pixels, and the display area includes multiple display sub-regions.

[0019] In some embodiments, a display sub-region is provided with two adjacent rows of sub-pixels, wherein the second, third, and fifth columns of sub-pixels in the upper row are coupled to the corresponding even-numbered grid lines, and the second, third, and fifth columns of sub-pixels in the lower row are coupled to the corresponding odd-numbered grid lines.

[0020] The subpixel pairs in the up row subpixel are coupled to the data line on its second side, and the subpixel pairs in the down row subpixel are coupled to the data line on its first side.

[0021] In some embodiments, a display sub-region is provided with two adjacent rows of sub-pixels, wherein the first column of sub-pixels, the fourth column of sub-pixels and the sixth column of sub-pixels in the upper row are coupled to the corresponding even-numbered grid lines, and the second column of sub-pixels, the third column of sub-pixels and the fifth column of sub-pixels in the lower row are coupled to the corresponding odd-numbered grid lines.

[0022] The subpixel pairs in the up row subpixel are coupled to the data line on its first side, and the subpixel pairs in the down row subpixel are coupled to the data line on its second side.

[0023] In some embodiments, a display sub-region is provided with two adjacent rows of sub-pixels, wherein the first column of sub-pixels, the fourth column of sub-pixels and the sixth column of sub-pixels in the upper row are coupled to the corresponding even-numbered gate lines, and the first column of sub-pixels, the fourth column of sub-pixels and the sixth column of sub-pixels in the lower row are coupled to the corresponding odd-numbered gate lines.

[0024] The subpixel pairs in the up row subpixel are coupled to the data line on its second side, and the subpixel pairs in the down row subpixel are coupled to the data line on its first side.

[0025] In some embodiments, one of the second and third sub-pixels is a green sub-pixel and the other is a blue sub-pixel.

[0026] In some embodiments, odd-numbered gate lines are coupled to one sub-pixel in each sub-pixel pair in the corresponding row, and even-numbered gate lines are coupled to the other sub-pixel in each sub-pixel pair in the corresponding row.

[0027] In some embodiments, the display panel further includes touch signal lines extending along a second direction and located between two adjacent columns of sub-pixels defined by two adjacent data lines, the second direction intersecting the first direction.

[0028] In some embodiments, a common electrode signal is applied to the touch signal line during the display of frames on the display panel, and a touch signal is applied to the touch signal line between two frames on the display panel.

[0029] In some embodiments, multiple gate lines arranged along a second direction are configured to provide gate signals sequentially, with the gate signals of each two adjacent gate lines overlapping, and the second direction intersecting with the first direction.

[0030] In some embodiments, the gate signal includes a pre-charge phase and a lighting phase, and in two adjacent gate lines, the lighting phase of the gate signal of the preceding gate line and the pre-charge phase of the gate signal of the following gate line at least partially overlap.

[0031] As a second aspect of the present disclosure, a driving method for a display panel is provided, applied to a display panel according to any of the present disclosure, the method comprising:

[0032] A gate signal is sequentially provided to multiple gate lines arranged along the second direction, wherein the gate signals of each two adjacent gate lines overlap, and the second direction is perpendicular to the first direction;

[0033] Based on the gate signal, data signals are provided to each data line, causing the second and third sub-pixels to be lit.

[0034] As a third aspect of the present disclosure, a display device is provided, including a display panel according to any one of the present disclosures.

[0035] The technical solution disclosed herein, by setting both the first target sub-pixel pair and the second target sub-pixel pair to be coupled to the first target data line, with the second sub-pixel in the first target sub-pixel pair coupled to the corresponding even-numbered grid line and the third sub-pixel in the second target sub-pixel pair coupled to the corresponding odd-numbered grid line, avoids the situation where the pre-charge effect of the second and third sub-pixels in the first column of pixels is poor when the display panel displays an image composed of the second and third sub-pixels. At least the pre-charge effect of the third sub-pixel in the second target sub-pixel pair is better. Thus, when each sub-pixel in the first column of pixels is lit, the overall brightness of the corresponding column of pixels is improved, the brightness difference between the current column of pixels and the adjacent column of pixels is reduced, and the vertical stripe defects are improved.

[0036] The technical solution disclosed herein, by adopting the second solution, can improve the overall brightness of the darker pixel column, and by adopting the third solution, can reduce the overall brightness of the brighter pixel column, further reducing the brightness difference between adjacent pixel columns and improving the vertical stripe defects.

[0037] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0038] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0039] Figure 1 This is a planar schematic diagram of a liquid crystal display;

[0040] Figure 2 This is a partial planar schematic diagram of a display panel in a related technology;

[0041] Figure 3 for Figure 2 The diagram shows the driving timing used in the display panel.

[0042] Figure 4 for Figure 2 The display panel shown uses Figure 3 The diagram shows the display effect of the driving timing.

[0043] Figure 5 This is a partial plan view of the display panel in one embodiment of the present disclosure;

[0044] Figure 6 This is a schematic diagram of a driving timing diagram used in the display panel of an embodiment of the present disclosure;

[0045] Figure 7 for Figure 5 The display panel shown uses Figure 6 The diagram shows the display effect of the driving timing. Detailed Implementation

[0046] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure, and different embodiments can be combined arbitrarily without conflict. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0047] Figure 2 This is a partial planar schematic diagram of a display panel in a related technology. For example... Figure 2 As shown, the display panel adopts a Dual Gate pixel architecture design. The display panel includes a display area, which comprises multiple pixel units arranged in an array. Figure 2 A two-row, two-column pixel unit is shown, each pixel unit comprising three sub-pixels P arranged along a first direction X. Each pixel unit may include three sub-pixels, R, G, and B.

[0048] The display area also includes multiple pairs of gate lines extending along the first direction X, each pair corresponding to a row of sub-pixels. Each pair of gate lines includes an odd-numbered gate line and an even-numbered gate line, located on opposite sides of the corresponding row of sub-pixels. The odd-numbered gate line is coupled to a portion of the sub-pixels in the corresponding row, while the even-numbered gate line is coupled to another portion of the sub-pixels in the corresponding row. The display area also includes multiple data lines arranged along the first direction X, with two columns of sub-pixels between adjacent data lines.

[0049] The display panel also includes multiple thin-film transistors (TFTs), each corresponding to a sub-pixel. The gate of the TFT is connected to the gate line, the source of the TFT is connected to the data line, and the drain of the TFT is connected to the pixel electrode of the sub-pixel.

[0050] For example, in Figure 2In the diagram, the first row of sub-pixels corresponds to the odd-numbered gate line Gate1 and the even-numbered gate line Gate2, which are located above and below the first row of sub-pixels, respectively. The odd-numbered gate line Gate1 is coupled to the first, fourth, and sixth columns of sub-pixels in the first row, while the even-numbered gate line Gate2 is coupled to the second, third, and fifth columns of sub-pixels in the first row.

[0051] The second row of subpixels corresponds to the odd-numbered gate line Gate3 and the even-numbered gate line Gate4, which are located above and below the second row of subpixels, respectively. The odd-numbered gate line Gate3 is coupled to the first, fourth, and sixth columns of subpixels in the second row, while the even-numbered gate line Gate4 is coupled to the second, third, and fifth columns of subpixels in the second row.

[0052] exist Figure 2 In the first row of subpixels, the first and second column subpixels are coupled to data line Data1, the third and fourth column subpixels are coupled to data line Data2, and the fifth and sixth column subpixels are coupled to data line Data3; in the second row of subpixels, the first and second column subpixels are coupled to data line Data2, the third and fourth column subpixels are coupled to data line Data3, and the fifth and sixth column subpixels are coupled to data line Data4.

[0053] like Figure 2 As shown, for data line Data2, in the first row of sub-pixels, data line Data2 is coupled to the third and fourth columns of sub-pixels to its right. In the second row of sub-pixels, data line Data2 is coupled to the first and second columns of sub-pixels to its left. This arrangement is called a 2-dot Z-inversion pixel structure. In the 2-dot Z-inversion pixel structure, data line Data is coupled to the two right sub-pixels in the upper row and to the two left sub-pixels in the lower row. Subsequent data lines Data follow the same pattern, forming a Z-shaped trend.

[0054] It should be noted that in the 2dot Z-inversion pixel structure, for two adjacent rows of sub-pixels, the data line Data can be coupled to the two left sub-pixels in the upper row and to the two right sub-pixels in the lower row.

[0055] Figure 2 The pixel structure shown can constitute a sub-region of the display area, and one sub-region constitutes one cycle. Figure 2 In this embodiment, the display sub-region comprises two rows and six columns of sub-pixels. The pixel structure of the display sub-region is as follows: Figure 2The illustrated dual-gate pixel arrangement represents one cycle, and the display area can include multiple display sub-regions arranged in an array. Figure 2 In this embodiment, the three sub-pixels in the pixel unit can be R, G, and B respectively along the first direction X.

[0056] It should be noted that, Figure 2 The three sub-pixels R, G, and B in the accompanying figures are arranged from left to right, but this does not imply a limitation on their arrangement. Those skilled in the art should understand that the arrangement of the three sub-pixels R, G, and B is not limited to the arrangement shown in the figures, and can be set as needed. For ease of explanation, the three sub-pixels R, G, and B in the accompanying figures are arranged from left to right.

[0057] In this article, the coupling between a sub-pixel and the data line (Data) should be understood as the coupling of the source of the thin-film transistor corresponding to the sub-pixel to the data line (Data), and the data line (Data) provides a data signal to the sub-pixel during the display process; the coupling between a sub-pixel and the gate line (Gate) should be understood as the coupling of the gate of the thin-film transistor corresponding to the sub-pixel to the gate line (Gate), and the gate line (Gate) provides a gate signal to the sub-pixel during the display process.

[0058] Figure 3 for Figure 2 The diagram shown illustrates the driving timing of the display panel. Figure 4 for Figure 2 The display panel shown uses Figure 3 The diagram shows the display effect of the driving timing. It should be noted that... Figure 3 And below Figure 6 In the data signal waveform diagram, "0" represents a low-level signal, and "1" represents a high-level signal. These "0" and "1" should not be interpreted as specific data signal voltage values. In practice, the specific voltage value of the data signal can be determined according to actual needs. For example, "V1" can represent a low-level voltage, corresponding to data 0, or it can be understood that when the data signal voltage value is V1, the corresponding sub-pixel is off. Similarly, "V2" can represent a high-level voltage, corresponding to data 1, or it can be understood that when the data signal voltage value is V2, the corresponding sub-pixel is lit.

[0059] Figures 2-4In the related technologies shown, the gate lines are driven by a gate driver circuit (GOA), eliminating the need for a gate driver module such as a gate COF (Chip On Film). The data lines are driven by a data COF. Doubling the number of gate lines halves the number of data signals, thus halving the data COF, reducing costs and enhancing market competitiveness. Currently, product requirements include 90Hz and 120Hz. Taking a certain product as an example, due to the doubled number of gate lines, the charging time for 1H is 4.0μs at 90Hz and 3.8μs at 120Hz. The shorter the charging time, the more difficult the charging becomes.

[0060] In the single-gate case, the gate's on-time is 1 hour. When the gate is on, data is written to the sub-pixel, meaning the sub-pixel is charged and illuminated. Therefore, the sub-pixel illumination stage is 1 hour. To meet the charging requirements of Dual Gate products, a precharge method can be used. For example... Figure 2 The gate's activation time is 3H, and correspondingly, the sub-pixel's charging time is 3H. The first two H times are the pre-charging stage, and the last H time is the lighting stage.

[0061] Taking Gate 1 as an example, the two H's marked "0H" in Gate 1 represent the pre-charge stage, and the one H' marked "1H" represents the illumination stage, during which data is written to the sub-pixels. Taking Gate 2 as an example, the two H's marked "0H" and "1H" in Gate 2 represent the pre-charge stage, and the one H' marked "2H" represents the illumination stage. Similarly, the one H' marked "3H" represents the illumination stage of Gate 3; the one H' marked "4H" represents the illumination stage of Gate 4; the one H' marked "5H" represents the illumination stage of Gate 5; the one H' marked "6H" represents the illumination stage of Gate 6; the one H' marked "7H" represents the illumination stage of Gate 7; and the one H' marked "8H" represents the illumination stage of Gate 8.

[0062] Before the illumination phase where data is written to each sub-pixel, the gate corresponding to two time intervals (H) is open, writing the data from the previous two rows to the corresponding sub-pixel. For example, in illumination phase 1H corresponding to gate 1, gate 2 is also open, and the sub-pixel corresponding to gate 2 is pre-charged with the data from the sub-pixel corresponding to gate 1; in illumination phase 2H corresponding to gate 2, gate 3 is also open, and the sub-pixel corresponding to gate 3 is pre-charged with the data from the sub-pixel corresponding to gate 2, and so on. Therefore, the sub-pixel is pre-charged with the data from the previous row before the illumination phase. It should be noted that the gate has two pre-charging times (H), and the pre-charged data is usually the data from the previously written row.

[0063] like Figure 3 As shown, V2 is at a high level and V1 is at a low level. When displaying a blue-green mixed color image, sub-pixels G and B are lit, while sub-pixel R is turned off.

[0064] like Figure 4 The display sub-region comprises two rows and two columns of pixels. The display process of the blue-green image in the display sub-region is as follows: (Reference) Figure 3 The data signal written by data line Data1 (same as data line Data4) is 0 (R off) 1 (G on) 1 (B on) 1 (G on) in a cycle; the data signal written by data line Data2 (same as data line Data5) is 0 (R off) 1 (B on) 0 (R off) 1 (G on) in a cycle; the data signal written by data line Data3 (same as data line Data6) is 1 (blue on) 1 (green on) 0 (R off) 1 (blue on) in a cycle.

[0065] Within one cycle, for data line Data1, taking the first row of G sub-green pixels in the first column of pixels opened by gate line Gate2 as an example, the data written to the R sub-pixel by the previous row gate line Gate1 is 0. Gate line Gate2 pre-charges the G sub-pixel with 0 data during the pre-charge phase. Therefore, the pre-charge effect of the G sub-pixel is poor, marked as "-". Similarly, for data line Data2, taking the second row of G sub-pixels in the first column of pixels opened by gate line Gate4 as an example, the data written to the R sub-pixel by the previous row Gate3 is 0. Gate line Gate4 pre-charges the G sub-pixel with 0 data during the pre-charge phase. Therefore, the pre-charge effect of the G sub-pixel is poor, marked as "-". And so on, the pre-charge effect of the G sub-pixels in the first column of pixels is always "-".

[0066] For data line Data3, taking the first row of G sub-pixels in the second column of pixels opened by gate line Gate2 as an example, the data written to the B sub-pixel by the previous gate line Gate1 is 1. Gate line Gate2 pre-charges the G sub-pixel with data of 1 during the pre-charge phase. Therefore, the G sub-pixel pre-charge effect is good, marked with "+". Similarly, for data line Data4, taking the second row of G sub-pixels in the second column of pixels opened by gate line Gate4 as an example, the data written to the B sub-pixel by the previous gate line Gate3 is 1. Gate line Gate4 pre-charges the G sub-pixel with data of 1 during the pre-charge phase. Therefore, the G sub-pixel pre-charge effect is good, marked with "+". And so on, the pre-charge effect of the G sub-pixels in the second column of pixels is "+".

[0067] Following the same method, the pre-charge effect of the B sub-pixels in the first column is always "-", while the pre-charge effect of the B sub-pixels in the second column is always "+". A column of R, G, and B pixels constitutes a pixel column, and within one cycle, there are two columns of pixels. When superimposed, from a display perspective, one column of pixels has a poorer pre-charge effect, resulting in lower brightness when lit, while the other column has a better pre-charge effect, resulting in higher brightness when lit. This effect continues periodically in subsequent pixels. The human eye is particularly sensitive to the G sub-pixels, causing the entire display panel to appear as alternating columns of darkness and light, resulting in vertical stripes when displaying sky blue (blue-green) images.

[0068] It should be noted that, in Figure 4 In the diagram, "-" represents subpixel pre-charge data 0, which has a poor pre-charge effect, while "+" represents subpixel pre-charge data 1, which has a better pre-charge effect.

[0069] To address the issue of vertical lines appearing on a display screen, this disclosure provides a display panel.

[0070] Figure 5 This is a partial planar schematic diagram of the display panel according to an embodiment of this disclosure. Figure 5 As shown, the display panel includes a display area, which includes multiple pixel units arranged in an array, as well as multiple pairs of gate lines and multiple data lines. Each pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged along a first direction X. Thus, the display area is provided with multiple sub-pixels arranged in an array. A column of pixel units constitutes a pixel column. Figure 5 In the image, the first sub-pixel, the second sub-pixel, and the third sub-pixel are R, G, and B, respectively.

[0071] Multiple pairs of gate lines extend along a first direction X, each pair corresponding one-to-one with a row of sub-pixels. Each pair of gate lines includes an odd-numbered gate line and an even-numbered gate line. The odd-numbered and even-numbered gate lines are located on opposite sides of the corresponding row of sub-pixels. The odd-numbered gate line is coupled to a portion of the sub-pixels in the corresponding row, and the even-numbered gate line is coupled to another portion of the sub-pixels in the corresponding row.

[0072] For example, in Figure 5 In the first row of sub-pixels, odd-numbered gate lines (Gate1) and even-numbered gate lines (Gate2) correspond to the first row of sub-pixels, with Gate1 and Gate2 located above and below the first row of sub-pixels, respectively. Odd-numbered gate lines (Gate3) and even-numbered gate lines (Gate4) correspond to the second row of sub-pixels, with Gate3 and Gate4 located above and below the second row of sub-pixels, respectively.

[0073] In the exemplary figures of this disclosure, odd-numbered gate lines are located above the corresponding row of sub-pixels, and even-numbered gate lines are located below the corresponding row of sub-pixels. For a display panel, in a frame, the refresh order of multiple rows of sub-pixels is from top to bottom; that is, in a pair of gate lines, the gate signal of the odd-numbered gate line is earlier than the gate signal of the even-numbered gate line.

[0074] Multiple data lines (Data) are arranged along a first direction X. Each data line Data can extend along a second direction Y, which intersects with the first direction X. Two columns of sub-pixels are positioned between adjacent data lines Data. Each row of sub-pixels is divided into multiple sub-pixel pairs by the multiple data lines Data, and each sub-pixel pair includes two sub-pixels. Along the arrangement direction of the multiple rows of sub-pixels, that is, along the second direction Y, the data lines Data are alternately coupled to the sub-pixel pairs located on both sides. It should be understood that the coupling of the data lines Data to the sub-pixel pairs should be interpreted as the data lines Data being coupled to each sub-pixel within the sub-pixel pair.

[0075] For example, in Figure 5 In the middle, along the second direction Y, data line Data2 is coupled to subpixel pair SP10 in the first row of subpixels, subpixel pair SP1 in the second row of subpixels, subpixel pair SP2 in the third row of subpixels, and subpixel pair SP11 in the fourth row of subpixels. This method can be called a 2-dot Z-inversion pixel architecture, and thus, the display panel of this disclosure adopts a 2-dot Z-inversion pixel architecture.

[0076] The display area may include at least one display sub-region, and the display sub-region may satisfy the first requirement. In the first requirement, a first target sub-pixel pair SP1 and a second target sub-pixel pair SP2, coupled to a first target data line MD1, are respectively provided in two adjacent rows of sub-pixels. The second sub-pixel G in the first target sub-pixel pair SP1 is coupled to the corresponding gate line Gate between the two adjacent rows of sub-pixels, and the third sub-pixel B in the second target sub-pixel pair SP2 is coupled to the corresponding gate line Gate between the two adjacent rows of sub-pixels. The first target data line MD1 is located between the second sub-pixel G and the third sub-pixel B.

[0077] Since the display panel of this disclosure adopts a 2-dot Z-inversion pixel architecture, the first target sub-pixel pair SP1 and the second target sub-pixel pair SP2 are located on opposite sides of the first target data line MD1, and each sub-pixel in the first target sub-pixel pair SP1 is coupled to the first target data line MD1, and each sub-pixel in the second target sub-pixel pair SP2 is coupled to the first target data line MD1.

[0078] exist Figure 5 In the display sub-region SA1, data line Data2 is a first target data line MD1. In the adjacent second and third rows of sub-pixels, first target sub-pixel pairs SP1 and SP2 are respectively set. Each sub-pixel in the first target sub-pixel pair SP1 is coupled to data line Data2, and each sub-pixel in the second target sub-pixel pair SP2 is coupled to data line Data2. The second sub-pixel G in the first target sub-pixel pair SP1 is coupled to the corresponding even-numbered gate line Gate4, and the third sub-pixel B in the second target sub-pixel pair SP2 is coupled to the corresponding odd-numbered gate line Gate5. Both even-numbered gate lines Gate4 and odd-numbered gate lines Gate5 are located between the second and third row sub-pixels.

[0079] Taking R, G, and B as the first, second, and third sub-pixels respectively, in related technologies, vertical stripes appear when the display panel displays a sky-blue image. For the display panel of this embodiment, when using related technologies, the pre-filling effect of the G and B sub-pixel columns in the first column of pixel units is poor. (Refer to...) Figure 4 When the light is on, the brightness is low. The G and B sub-pixel columns in the second column of pixel units have better pre-charge effects and are brighter when the light is on. As a result, the image is formed with alternating dark and bright columns, which is a defective vertical stripe.

[0080] In this embodiment, the first target data line MD1 is located between the second sub-pixel G and the third sub-pixel B. Both the first target sub-pixel pair SP1 and the second target sub-pixel pair SP2 are coupled to the first target data line MD1. The second sub-pixel G in the first target sub-pixel pair SP1 is coupled to the corresponding even-numbered gate line Gate4, and the third sub-pixel B in the second target sub-pixel pair SP2 is coupled to the corresponding odd-numbered gate line Gate5. Since the even-numbered gate line Gate4 and the odd-numbered gate line Gate5 are two adjacent gate lines, the second sub-pixel G in the first target sub-pixel pair SP1 and the third sub-pixel B in the second target sub-pixel pair SP2 are sequentially and adjacently illuminated. For example, during the illumination phase, even-numbered gate line Gate4 illuminates the second sub-pixel G in the first target sub-pixel pair SP1. At this time, odd-numbered gate line Gate5 pre-charges the third sub-pixel B in the second target sub-pixel pair SP2 with a high level. The pre-charging effect of the third sub-pixel B in the second target sub-pixel pair SP2 is better. Therefore, when odd-numbered gate line Gate5 illuminates the third sub-pixel B in the second target sub-pixel pair SP2 during the illumination phase, the brightness of the third sub-pixel B in the second target sub-pixel pair SP2 is higher.

[0081] Therefore, the technical solution of this disclosure, by setting the first target sub-pixel pair SP1 and the second target sub-pixel pair SP2 to be coupled to the first target data line MD1, the second sub-pixel G in the first target sub-pixel pair SP1 to be coupled to the corresponding even-numbered gate line Gate4, and the third sub-pixel B in the second target sub-pixel pair SP2 to be coupled to the corresponding odd-numbered gate line Gate5, since the even-numbered gate line Gate4 and the odd-numbered gate line Gate5 are two adjacent gate lines, when the display panel displays an image composed of the second sub-pixel and the third sub-pixel, the pre-charging effect of the second sub-pixel and the third sub-pixel in the first column of pixels is avoided, at least the pre-charging effect of the third sub-pixel B in the second target sub-pixel pair is better. Thus, when each G sub-pixel and B sub-pixel in the first column of pixels is lit, the overall brightness of the corresponding column of pixels is improved, the brightness difference between the current column of pixels and the adjacent column of pixels is reduced, and the vertical stripe defects are improved.

[0082] In another embodiment, the display sub-region can satisfy the second requirement. In the second requirement, a third target sub-pixel pair SP3 and a fourth target sub-pixel pair SP4, coupled to the second target data line MD2, are respectively provided in two adjacent rows of sub-pixels. The third target sub-pixel pair SP3 includes a second sub-pixel G and a third sub-pixel B, and the fourth target sub-pixel pair SP4 includes a first sub-pixel R and a non-first sub-pixel. One sub-pixel in the third target sub-pixel pair SP3 is coupled to the corresponding gate line between the two adjacent rows of sub-pixels, and the non-first sub-pixel in the fourth target sub-pixel pair SP4 is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. The third target sub-pixel pair SP3 is configured to be refreshed before the fourth target sub-pixel pair SP4. The second target data line MD2 is located between the first sub-pixel and the second sub-pixel or between the third sub-pixel and the first sub-pixel.

[0083] exist Figure 5 In the display sub-region SA1, data line Data3 is a second target data line MD2. Third target sub-pixel pairs SP3 and SP4 are respectively set in the adjacent third and fourth rows of sub-pixels. The second sub-pixel G and the third sub-pixel B in the third target sub-pixel pair SP3 are both coupled to data line Data3. The third sub-pixel B and the first sub-pixel R in the fourth target sub-pixel pair SP4 are both coupled to data line Data3. One sub-pixel in the third target sub-pixel pair SP3, for example, the third sub-pixel B, is coupled to the even-numbered gate line Gate6. The third sub-pixel B (i.e., not the first sub-pixel) in the fourth target sub-pixel pair is coupled to the odd-numbered gate line Gate7. Both the even-numbered gate line Gate6 and the odd-numbered gate line Gate7 are located between the third and fourth rows of sub-pixels. The third target sub-pixel pair SP3 is configured to be refreshed before the fourth target sub-pixel pair SP4, thus, the gate signal of the even-numbered gate line Gate6 is earlier than the gate signal of the odd-numbered gate line Gate7.

[0084] Since even-numbered gate 6 and odd-numbered gate 7 are two adjacent gates, the third sub-pixel B in the third target sub-pixel and the third sub-pixel B in the fourth target sub-pixel are lit sequentially and adjacently. For example, when even-numbered gate 6 lights up the third sub-pixel B in the third target sub-pixel during the lighting phase, odd-numbered gate 7 pre-charges the third sub-pixel B in SP4 with a high level. The pre-charging effect of the third sub-pixel B in the fourth target sub-pixel is better. Therefore, when odd-numbered gate 7 lights up the third sub-pixel B in SP3 during the lighting phase, the brightness of the third sub-pixel B in the fourth target sub-pixel is higher. From the above analysis, it can be seen that the pre-charging effect of the B sub-pixel in the fourth row of the first column of pixels is improved.

[0085] It should be noted that the second target data line MD2 is located between the first sub-pixel R and the second sub-pixel G. Therefore, the third sub-pixel B in the third target sub-pixel is located in the second column of pixels, and the third sub-pixel B in the fourth target sub-pixel is located in the first column of pixels. In other words, the third sub-pixel B in the third target sub-pixel pair SP3 and the third sub-pixel B in the fourth target sub-pixel pair SP4 are located in two adjacent pixel columns.

[0086] exist Figure 5 In this diagram, data line Data4 is also a second target data line MD2. In the adjacent second and third rows of sub-pixels, third target sub-pixel pairs SP3 and SP4 are respectively set. The second sub-pixel G in the third target sub-pixel pair SP3 is coupled to the even-numbered gate line Gate4, and the second sub-pixel G in the fourth target sub-pixel pair is coupled to the odd-numbered gate line Gate5. Both the even-numbered gate line Gate4 and the odd-numbered gate line Gate5 are located between the second and third rows of sub-pixels. Since the even-numbered gate line Gate4 and the odd-numbered gate line Gate5 are two adjacent gate lines, the second sub-pixel G in the third target sub-pixel pair SP3 and the second sub-pixel G in the fourth target sub-pixel pair SP4 are lit sequentially and adjacently. For example, during the illumination phase, even-numbered gate line Gate4 illuminates the second sub-pixel G in the third target sub-pixel. At this time, odd-numbered gate line Gate5 provides a high-level pre-charge signal for the second sub-pixel G in SP4 from the fourth target sub-pixel. The pre-charge effect of the fourth target sub-pixel on the second sub-pixel G in SP4 is better. Therefore, when odd-numbered gate line Gate5 illuminates the second sub-pixel G in SP4 from the fourth target sub-pixel during the illumination phase, the brightness of the second sub-pixel G in SP4 from the fourth target sub-pixel is higher. Figure 5 In the image, the second sub-pixel G in the third target sub-pixel pair SP3 is located in the second pixel column, and the second sub-pixel G in the fourth target sub-pixel pair SP4 is located in the third pixel column. In other words, the second sub-pixel G in the third target sub-pixel pair SP3 and the second sub-pixel G in the fourth target sub-pixel pair SP4 are located in two adjacent pixel columns. Based on the above analysis, it can be seen that the pre-filling effect of the G sub-pixel in the third row of the third column is improved.

[0087] The above analysis shows that by adopting the second scheme, the pre-fill effect of at least one sub-pixel in an adjacent column of pixels can be improved, so that the pre-fill effect of at least one sub-pixel changes from "-" to "+". Thus, during the lighting stage, the brightness of at least one sub-pixel in an adjacent column of pixels with lower brightness can be increased, thereby increasing the overall brightness of the pixel column. This can reduce the brightness difference between two adjacent pixel columns and improve the vertical stripe defects.

[0088] It should be noted that, Figure 5The image shows a display sub-region SA1. It should be understood that the display sub-region is not limited to, for example, SA1. Figure 5 As indicated, sub-regions that repeat periodically within the display area can be divided into a single display sub-region. Figure 5 In the diagram, data line Data3 and its corresponding third target sub-pixel pair SP3 and fourth target sub-pixel pair SP4 are located in display sub-region SA1. Data line Data4 and its corresponding third target sub-pixel pair SP3 and fourth target sub-pixel pair SP4 can be located in a display sub-region with a different partitioning method. Alternatively, since the fourth target sub-pixel pair SP4 corresponding to data line Data4 is a periodic repetition of sub-pixel pair SP8 in the display sub-region, the third target sub-pixel pair SP3 and the fourth target sub-pixel pair SP4 corresponding to data line Data4 can be considered as being located in display sub-region SA1.

[0089] In another embodiment, the display sub-region can satisfy the third item. In the third item, a fifth target sub-pixel pair SP5 and a sixth target sub-pixel pair SP6 coupled to the second target data line MD2 are respectively provided in two adjacent rows of sub-pixels. The fifth target sub-pixel pair SP5 includes a first sub-pixel R and a non-first sub-pixel. The sixth target sub-pixel pair SP6 includes a second sub-pixel G and a third sub-pixel B. The first sub-pixel R in the fifth target sub-pixel pair SP5 is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. One sub-pixel in the sixth target sub-pixel pair SP6 is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. The fifth target sub-pixel pair SP5 is configured to be refreshed before the sixth target sub-pixel pair SP6. The second target data line MD2 is located between the first sub-pixel R and the second sub-pixel G or between the third sub-pixel B and the first sub-pixel R.

[0090] exist Figure 5 In this configuration, data line Data3 is a second target data line MD2. In the adjacent fourth and fifth rows of sub-pixels, there are fifth target sub-pixel pairs SP5 and SP6, respectively. Each sub-pixel in both SP5 and SP6 is coupled to data line Data3. The first sub-pixel R in SP5 is coupled to even-numbered gate line Gate8, and the third sub-pixel B in SP6 is coupled to odd-numbered gate line Gate9. Both even-numbered and odd-numbered gate lines Gate8 and Gate9 are located between the fourth and fifth rows of sub-pixels. SP5 is configured to be refreshed before SP6, thus the gate signal of even-numbered gate line Gate8 is earlier than the gate signal of odd-numbered gate line Gate9.

[0091] Since even-numbered gate 8 and odd-numbered gate 9 are two adjacent gates, the first sub-pixel R in the fifth target sub-pixel pair SP5 and the third sub-pixel B in the sixth target sub-pixel pair SP6 are lit sequentially and adjacently. For example, since the display panel displays an image composed of the second sub-pixel G and the third sub-pixel B, even-numbered gate 8 will not light up the first sub-pixel R during the lighting phase. That is, the signal charged to the first sub-pixel R during the lighting phase is a low-level signal. At this time, the pre-charge signal for the third sub-pixel B in the sixth target sub-pixel pair SP6 is low-level for odd-numbered gate 9. The pre-charge effect of the third sub-pixel B in the sixth target sub-pixel pair SP6 is poor. Therefore, when odd-numbered gate 9 lights up the third sub-pixel B in the sixth target sub-pixel pair SP6 during the lighting phase, the brightness of the third sub-pixel B in the sixth target sub-pixel pair SP6 is weak. It should be noted that... Figure 5 In the sixth target sub-pixel pair SP6, the third sub-pixel B is coupled to the odd-numbered gate line Gate9, and the second sub-pixel G is coupled to the even-numbered gate line Gate10; in other embodiments, the second sub-pixel G in the sixth target sub-pixel pair SP6 may be coupled to the odd-numbered gate line Gate9, while the third sub-pixel B is coupled to the even-numbered gate line Gate10.

[0092] exist Figure 5 In this diagram, data line Data4 is another second target data line MD2. A fifth target sub-pixel pair SP5 and a sixth target sub-pixel pair SP6 are respectively set in the adjacent third and fourth rows of sub-pixels. The first sub-pixel R in the fifth target sub-pixel pair SP5 is coupled to the even-numbered gate line Gate6. One sub-pixel in the sixth target sub-pixel pair SP6, such as the second sub-pixel G, is coupled to the odd-numbered gate line Gate7. Both the even-numbered gate line Gate6 and the odd-numbered gate line Gate7 are located between the third and fourth rows of sub-pixels. The fifth target sub-pixel pair SP5 is configured to be refreshed before the sixth target sub-pixel pair SP6, thus the gate signal of the even-numbered gate line Gate6 is earlier than the gate signal of the odd-numbered gate line Gate7. Based on the above analysis, the pre-charge effect of the second sub-pixel G in the sixth target sub-pixel pair SP6 is poor. When the odd-numbered gate line Gate7 illuminates the second sub-pixel G in the sixth target sub-pixel pair SP6 during the illumination phase, the brightness of the second sub-pixel G in the sixth target sub-pixel pair SP6 is low.

[0093] It should be noted that since the sixth target sub-pixel pair SP6 corresponding to data line Data3 is a periodic repetition of sub-pixel pair SP9 in display sub-region SA1, the sixth target sub-pixel pair SP6 corresponding to data line Data3 can be considered as being located in display sub-region SA1. Similarly, since the fifth target sub-pixel pair SP5 corresponding to data line Data4 is a periodic repetition of sub-pixel pair SP8 in display sub-region SA1, the fifth target sub-pixel pair SP5 corresponding to data line Data4 can be considered as being located in display sub-region SA1.

[0094] In related technologies, refer to Figure 4 The pre-filling effect of R and G in the second column of pixels is good, and is "+".

[0095] In this embodiment of the disclosure, by setting the first sub-pixel R in the fifth target sub-pixel pair SP5 to be coupled to the corresponding gate line Gate between the two adjacent rows of sub-pixels, and setting the first sub-pixel in the sixth target sub-pixel pair SP6 to be coupled to the corresponding gate line Gate between the two adjacent rows of sub-pixels, the fifth target sub-pixel pair SP5 is configured to be refreshed before the sixth target sub-pixel pair SP6, so that the pre-charge effect of at least one sub-pixel in the second column of pixels changes from "+" to "0", reducing the brightness of at least one sub-pixel in the second column of pixels when lit, thereby reducing the overall brightness of the second column of pixels, which can reduce the brightness difference between the second column of pixels and the adjacent column of pixels and improve the vertical stripe defects.

[0096] The technical solution disclosed herein can improve the pre-filling effect of sub-pixels, thereby increasing the brightness of pixel columns with lower brightness and decreasing the brightness of pixel columns with higher brightness, reducing the brightness difference between adjacent pixel columns, and improving vertical stripe defects.

[0097] In one embodiment, the second target data line MD2 is located between the first sub-pixel R and the second sub-pixel G. The non-first sub-pixel in the fourth target sub-pixel pair SP4 is the third sub-pixel B. The third target sub-pixel pair SP3 is located in the upper row of sub-pixels in two adjacent rows, and the fourth target sub-pixel pair SP4 is located in the lower row of sub-pixels in two adjacent rows. The fourth target sub-pixel pair SP4 is located on the first side of the second target data line MD2, and the third target sub-pixel pair SP3 is located on the second side of the second target data line MD2. For example, in... Figure 5 In the diagram, data line Data3 is the second target data line MD2. The third target sub-pixel is located in the third row of sub-pixels and is to the right of data line Data3. The fourth target sub-pixel is located in the fourth row of sub-pixels and is to the left of data line Data3.

[0098] In this article, "first side" can refer to the left side, and "second side" can refer to the right side.

[0099] In two adjacent rows of subpixels, the upper row subpixels are refreshed before the lower row subpixels. For example, in a frame, the display panel refreshes from top to bottom, the upper row subpixels are the top row of subpixels in two adjacent rows, and the lower row subpixels are the bottom row of subpixels in two adjacent rows.

[0100] In one embodiment, the second target data line MD2 is located between the third sub-pixel B and the first sub-pixel R, the non-first sub-pixel in the fourth target sub-pixel pair SP4 is the second sub-pixel G, the third target sub-pixel pair SP3 is located in the upper row of sub-pixels in two adjacent rows, the fourth target sub-pixel pair SP4 is located in the lower row of sub-pixels in two adjacent rows, the third target sub-pixel pair SP3 is located on the first side of the second target data line MD2, and the fourth target sub-pixel pair SP4 is located on the second side of the second target data line MD2. For example, in Figure 5 In the diagram, data line Data4 is the second target data line MD2. The third target sub-pixel pair SP3 is located in the second row of sub-pixels and is to the left of data line Data4. The fourth target sub-pixel pair SP4 is located in the third row of sub-pixels and is to the right of data line Data4. The non-second sub-pixel G is located within the fourth target sub-pixel pair SP4.

[0101] In one embodiment, the second target data line MD2 is located between the first sub-pixel R and the second sub-pixel G, the non-first sub-pixel in the fifth target sub-pixel pair SP5 is the third sub-pixel B, the fifth target sub-pixel pair SP5 is located in the upper row of sub-pixels in two adjacent rows, the sixth target sub-pixel pair SP6 is located in the lower row of sub-pixels in two adjacent rows, the fifth target sub-pixel pair SP5 is located on the first side of the second target data line MD2, and the sixth target sub-pixel pair SP6 is located on the second side of the second target data line MD2. For example, in Figure 5 In the diagram, data line Data3 can be the second target data line MD2. The fifth target sub-pixel pair SP5 is located in the fourth row of sub-pixels and is to the left of data line Data3. The sixth target sub-pixel pair SP6 is located in the fifth row of sub-pixels and is to the right of data line Data3. The non-first sub-pixel in the fifth target sub-pixel pair SP5 is the third sub-pixel B.

[0102] In one embodiment, the second target data line MD2 is located between the third sub-pixel B and the first sub-pixel R, the non-first sub-pixel in the fifth target sub-pixel pair SP5 is the second sub-pixel G, the fifth target sub-pixel pair SP5 is located in the upper row of sub-pixels in two adjacent rows, the sixth target sub-pixel pair SP6 is located in the lower row of sub-pixels in two adjacent rows, the sixth target sub-pixel pair SP6 is located on the first side of the second target data line MD2, and the fifth target sub-pixel pair SP5 is located on the second side of the second target data line MD2. For example, in Figure 5 In the diagram, data line Data4 can be the second target data line MD2. The fifth target sub-pixel pair SP5 is located in the third row of sub-pixels and is to the right of data line Data4. The sixth target sub-pixel pair SP6 is located in the fourth row of sub-pixels and is to the left of data line Data4. The non-first sub-pixel in the fifth target sub-pixel pair SP5 is the second sub-pixel G.

[0103] like Figure 5 As shown, a display sub-region can be configured with four rows and six columns of subpixels. The display sub-region can be a repeating area of ​​the display area, and it can repeat periodically within the display area. For example, the display area may include multiple display sub-regions. Multiple display sub-regions can be arranged in an array.

[0104] For example, a sub-region is provided with two adjacent rows of sub-pixels, such as Figure 5 The second and third rows of sub-pixels. Among them, the second, third, and fifth columns of sub-pixels in the upper row (i.e., the second row of sub-pixels) are all coupled to the corresponding even-numbered gate line Gate4, and the second, third, and fifth columns of sub-pixels in the lower row (i.e., the third row of sub-pixels) are all coupled to the corresponding odd-numbered gate line Gate5.

[0105] The subpixel pairs in the upper row (i.e., the second row of subpixels) are coupled to the data line Data located on its second side (i.e., the right side), and the subpixel pairs in the lower row (i.e., the third row of subpixels) are coupled to the data line Data located on its first side (i.e., the left side).

[0106] In another example, a sub-region is set with two adjacent rows of sub-pixels, for example, Figure 5 The third and fourth rows of sub-pixels. Among them, the first, fourth, and sixth columns of sub-pixels in the upper row (i.e., the third row of sub-pixels) are coupled to the corresponding even-numbered gate line Gate6, and the second, third, and fifth columns of sub-pixels in the lower row (i.e., the fourth row of sub-pixels) are coupled to the corresponding odd-numbered gate line Gate7.

[0107] The subpixel pairs in the upper row (i.e., the third row of subpixels) are coupled to the data line Data located on its first side (i.e., the left side), and the subpixel pairs in the lower row (i.e., the fourth row of subpixels) are coupled to the data line Data located on its second side (i.e., the right side).

[0108] In another example, a sub-region is set with two adjacent rows of sub-pixels, for example... Figure 5The fourth and fifth rows of sub-pixels are the same as the first row of sub-pixels. Among them, the first, fourth, and sixth columns of sub-pixels in the upper row (i.e., the fourth row of sub-pixels) are coupled to the corresponding even-numbered gate line Gate8, and the first, fourth, and sixth columns of sub-pixels in the lower row (i.e., the fifth row of sub-pixels) are coupled to the corresponding odd-numbered gate line Gate9.

[0109] The subpixel pairs in the upper row (i.e., the fourth row of subpixels) are coupled to the data line Data located on its second side (i.e., the right side), and the subpixel pairs in the lower row (i.e., the fifth row of subpixels) are coupled to the data line Data located on its first side (i.e., the left side).

[0110] exist Figure 5 In this embodiment, the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are R, G, and B, respectively. In other embodiments, one of the second and third sub-pixels is a green sub-pixel G, and the other is a blue sub-pixel B. For example, the second sub-pixel is G and the third sub-pixel is B, or the second sub-pixel is B and the third sub-pixel is G.

[0111] A row of subpixels corresponds to a pair of gates. Some subpixels in a row are coupled to odd-numbered gates, while others are coupled to even-numbered gates. For example, an odd-numbered gate can be coupled to one subpixel in each subpixel pair in the corresponding row, and an even-numbered gate can be coupled to the other subpixel in each subpixel pair in the corresponding row.

[0112] For example, in Figure 5 In the second row of sub-pixels, the second, third, and fifth column sub-pixels are coupled to the corresponding even-numbered gate line Gate4, and the first, fourth, and sixth column sub-pixels are coupled to the corresponding odd-numbered gate line Gate3.

[0113] In this way, odd-numbered gate lines and even-numbered gate lines drive the corresponding sub-pixels in a row of sub-pixels in turn, thus achieving dual-gate driving.

[0114] Figure 6 This is a schematic diagram of a driving timing diagram used in the display panel according to an embodiment of this disclosure. Figure 7 for Figure 5 The display panel shown uses Figure 6 The diagram illustrates the display effect of the driving timing. In one embodiment, as shown... Figure 6 and Figure 7As shown, multiple gate lines arranged along the second direction Y are configured to provide gate signals sequentially. That is, in every two adjacent gate lines, the gate signal of the preceding gate line is earlier than the gate signal of the following gate line. The gate signals of every two adjacent gate lines overlap. The second direction Y intersects with the first direction X. In this disclosure, the first direction X is the extension direction of a row of sub-pixels, and the second direction Y is the extension direction of a column of sub-pixels. The second direction Y is perpendicular to the first direction X.

[0115] like Figure 6 Eight gate lines provide gate signals sequentially, and there is an overlap of two H signals between each pair of adjacent gate lines.

[0116] The gate signal may include a pre-charge phase and an illumination phase. In two adjacent gate lines, the illumination phase of the gate signal of the preceding gate line at least partially overlaps with the pre-charge phase of the gate signal of the following gate line. For example, the illumination phase of the gate signal of the preceding gate line overlaps with a portion of the pre-charge phase of the gate signal of the following gate line. For instance, in the signal of gate line 2, the phase marked 2H is the illumination phase, and the phases marked 0H and 1H are the pre-charge phases, which partially overlap with the signal of the preceding gate line 1. Figure 6 In the diagram, the lighting stages of gate lines Gate1, Gate2, Gate3, Gate4, Gate5, Gate6, Gate7, and Gate8 are 1H, 2H, 3H, 4H, 5H, 6H, 7H, and 8H, respectively.

[0117] This disclosure also provides a driving method for a display panel, applied to the display panel of this disclosure. The driving method may include: sequentially providing gate signals to a plurality of gate lines arranged along a second direction Y, wherein the gate signals of each pair of adjacent gate lines overlap, and the second direction Y is perpendicular to the first direction X; and providing data signals to each data line Data according to the gate signals, so that the second sub-pixel and the third sub-pixel are lit.

[0118] The following is combined Figure 6 and Figure 7 The driving process of the display panel according to embodiments of this disclosure is described in detail. Taking R, G, and B as the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively, as an example, the display panel displays a sky-blue image, i.e., a GB mixed color image. Therefore, sub-pixels G and B are lit during their corresponding lighting phases, while sub-pixel R is turned off. Figure 6In the diagram, V2 is high and recorded as 1, and V1 is low and recorded as 0. Taking one cycle as an example, the data signal written by data line Data1 (same as data line Data4) is a cycle of 01111011, the data signal written by data line Data2 is a cycle of 01011010, and the data signal written by data line Data3 is a cycle of 11011110.

[0119] Within one cycle, taking the example of gate line Gate4 opening the second row of sub-pixels G in the first column of pixels, where data line Data2 provides the data signal, and the previous row's odd-numbered gate line Gate3 writes data 0 to sub-pixel R during the illumination phase, then gate line Gate4 pre-charges sub-pixel G with data 0 during the pre-charge phase. The pre-charge effect is poor and is marked as "-". Similarly, taking the example of gate line Gate5 opening the third row of sub-pixels B in the first column of pixels, where data line Data2 provides the data signal, and the previous row's gate line Gate4 writes data 1 to sub-pixel G during the illumination phase, then gate line Gate5 pre-charges sub-pixel B with data 1 during the pre-charge phase. The pre-charge effect is good and is marked as "+". And so on, the pre-charge effect of sub-pixels G in the first column of pixels is -, -, +, - in sequence.

[0120] Taking the example of gate line 4 opening the second row of sub-pixels G in the second column of pixels, where data line Data4 provides the data signal, and the previous row of gate line Gate3 writes data 1 to sub-pixel B during the illumination phase, then gate line Gate4 precharges sub-pixel G with data 1 during the precharge phase, resulting in a good precharge effect, marked as "+". Similarly, taking the example of gate line Gate5 opening the third row of sub-pixels G in the second column of pixels, where data line Data3 provides the data signal, and the previous row of gate line Gate4 writes data 1 to sub-pixel B during the illumination phase, then gate line Gate5 precharges sub-pixel G with data 1 during the precharge phase, resulting in a good precharge effect, marked as "+". Similarly, taking the example of gate line Gate7 opening the fourth row of sub-pixels G in the second column of pixels, where data line Data3 provides the data signal, and the previous row of gate line Gate6 writes data 0 to sub-pixel R during the illumination phase, then gate line Gate7 precharges sub-pixel G with data 0 during the precharge phase, resulting in a poor precharge effect, marked as "-". Similarly, the pre-charge effects of sub-pixels G in the second column of pixels are +, +, +, and - in sequence.

[0121] Similarly, it can be deduced that the pre-fill effect of sub-pixel B in the first column of pixels is -, -, +, +, and the pre-fill effect of sub-pixel B in the second column of pixels is -, +, +, +, +.

[0122] Compared to related technologies, the pre-charging effect of sub-pixels in the first column of pixels is poor during the pre-charging stage, resulting in a "-" value. Therefore, the overall brightness is low during the illumination stage. This embodiment improves the pre-charging effect of at least some sub-pixels in the first column of pixels, thereby increasing the brightness of some sub-pixels during the illumination stage. This enhances the overall brightness of the first column of pixels and reduces the brightness difference between adjacent columns of pixels.

[0123] Compared to related technologies, the pre-charge effect of the sub-pixels in the second column of pixels is better, showing a "+" sign, resulting in higher overall brightness during the illumination phase. This embodiment of the present disclosure reduces the pre-charge effect of at least some sub-pixels in the second column of pixels, thereby reducing the brightness of some sub-pixels during the illumination phase, which can reduce the overall brightness of the second column of pixels and decrease the brightness difference between adjacent columns of pixels.

[0124] Therefore, by adopting the technical solution of this disclosure, when displaying a mixed image composed of a second sub-pixel G and a third sub-pixel B, the brightness of the darker pixel column can be increased, the brightness of the brighter pixel column can be decreased, the brightness difference between adjacent pixel columns can be reduced, the vertical stripe defects can be improved, and the display effect can be enhanced.

[0125] In one embodiment, such as Figure 5 and Figure 7 As shown, the display panel may also include touch signal lines that extend along a second direction Y. The touch signal lines are located between two adjacent columns of sub-pixels defined by two adjacent data lines (Data). Thus, the data lines (Data) and touch signal lines can be arranged alternately.

[0126] The touch signal line is given a common electrode signal during the display of frames on the display panel, and a touch signal is given between two frames. Thus, the touch signal line can be used as a common electrode signal line to realize TDDI products.

[0127] This disclosure also provides a display device, including the display panel in any embodiment of this disclosure.

[0128] For example, the display device can be a liquid crystal display device. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0129] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0130] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0131] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0132] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0133] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0134] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure. Different parts of different embodiments can be combined with each other without conflict, and these should all be covered within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, Includes a display area, the display area including: Multiple pixel units arranged in an array, wherein the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged along a first direction; Multiple pairs of gate lines extending along the first direction correspond one-to-one with multiple rows of sub-pixels. Each pair of gate lines includes an odd number of gate lines and an even number of gate lines. The odd number of gate lines and the even number of gate lines are located on opposite sides of the corresponding row of sub-pixels. The odd number of gate lines are coupled to a portion of the sub-pixels in the corresponding row of sub-pixels, and the even number of gate lines are coupled to another portion of the sub-pixels in the corresponding row of sub-pixels. Multiple data lines are arranged along the first direction, with two columns of sub-pixels between two adjacent data lines. Each row of sub-pixels is divided into multiple sub-pixel pairs by the multiple data lines. Along the arrangement direction of the multiple rows of sub-pixels, the data lines are alternately coupled to the sub-pixel pairs located on both sides. The display area includes at least one display sub-area, and the display sub-area satisfies at least one of the following: In two adjacent rows of sub-pixels, a first target sub-pixel pair and a second target sub-pixel pair coupled to a first target data line are respectively provided. The second sub-pixel in the first target sub-pixel pair is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. The third sub-pixel in the second target sub-pixel pair is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. The first target data line is located between the second sub-pixel and the third sub-pixel. A third target sub-pixel pair and a fourth target sub-pixel pair, coupled to a second target data line, are respectively provided in two adjacent rows of sub-pixels. The third target sub-pixel pair includes a second sub-pixel and a third sub-pixel. The fourth target sub-pixel pair includes a first sub-pixel and a non-first sub-pixel. One sub-pixel in the third target sub-pixel pair is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. The non-first sub-pixel in the fourth target sub-pixel pair is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. The third target sub-pixel pair is configured to be refreshed before the fourth target sub-pixel pair. The second target data line is located between the first sub-pixel and the second sub-pixel or between the third sub-pixel and the first sub-pixel. A fifth target sub-pixel pair and a sixth target sub-pixel pair, coupled to a second target data line, are respectively provided in two adjacent rows of sub-pixels. The fifth target sub-pixel pair includes a first sub-pixel and a non-first sub-pixel. The sixth target sub-pixel pair includes a second sub-pixel and a third sub-pixel. The first sub-pixel in the fifth target sub-pixel pair is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. One sub-pixel in the sixth target sub-pixel pair is coupled to the corresponding gate line between the two adjacent rows of sub-pixels. The fifth target sub-pixel pair is configured to be refreshed before the sixth target sub-pixel pair. The second target data line is located between the first sub-pixel and the second sub-pixel or between the third sub-pixel and the first sub-pixel.

2. The display panel according to claim 1, characterized in that, The second target data line is located between the first sub-pixel and the second sub-pixel. The non-first sub-pixel in the fourth target sub-pixel pair is the third sub-pixel. The third target sub-pixel pair is located in the upper sub-pixel of the two adjacent rows of sub-pixels. The fourth target sub-pixel pair is located in the lower sub-pixel of the two adjacent rows of sub-pixels. The fourth target sub-pixel pair is located on the first side of the second target data line. The third target sub-pixel pair is located on the second side of the second target data line.

3. The display panel according to claim 1, characterized in that, The second target data line is located between the third sub-pixel and the first sub-pixel. The non-first sub-pixel in the fourth target sub-pixel pair is the second sub-pixel. The third target sub-pixel pair is located in the upper sub-pixel of the two adjacent rows of sub-pixels. The fourth target sub-pixel pair is located in the lower sub-pixel of the two adjacent rows of sub-pixels. The third target sub-pixel pair is located on the first side of the second target data line. The fourth target sub-pixel pair is located on the second side of the second target data line.

4. The display panel according to claim 1, characterized in that, The second target data line is located between the first sub-pixel and the second sub-pixel. The non-first sub-pixel in the fifth target sub-pixel pair is the third sub-pixel. The fifth target sub-pixel pair is located in the upper sub-pixel of the two adjacent rows of sub-pixels. The sixth target sub-pixel pair is located in the lower sub-pixel of the two adjacent rows of sub-pixels. The fifth target sub-pixel pair is located on the first side of the second target data line, and the sixth target sub-pixel pair is located on the second side of the second target data line.

5. The display panel according to claim 1, characterized in that, The second target data line is located between the third sub-pixel and the first sub-pixel. The non-first sub-pixel in the fifth target sub-pixel pair is the second sub-pixel. The fifth target sub-pixel pair is located in the upper sub-pixel of the two adjacent rows of sub-pixels. The sixth target sub-pixel pair is located in the lower sub-pixel of the two adjacent rows of sub-pixels. The sixth target sub-pixel pair is located on the first side of the second target data line, and the fifth target sub-pixel pair is located on the second side of the second target data line.

6. The display panel according to any one of claims 1-5, characterized in that, The display sub-region is provided with four rows and six columns of sub-pixels, and the display area includes multiple display sub-regions.

7. The display panel according to claim 6, characterized in that, The display sub-region is provided with two adjacent rows of sub-pixels, wherein the second, third and fifth columns of sub-pixels in the upper row are coupled to the corresponding even-numbered grid lines, and the second, third and fifth columns of sub-pixels in the lower row are coupled to the corresponding odd-numbered grid lines. The sub-pixel pairs in the up-row sub-pixel are coupled to the data line located on its second side, and the sub-pixel pairs in the down-row sub-pixel are coupled to the data line located on its first side.

8. The display panel according to claim 6, characterized in that, The display sub-region is provided with two adjacent rows of sub-pixels, wherein the first column of sub-pixels, the fourth column of sub-pixels and the sixth column of sub-pixels in the upper row are coupled to the corresponding even-numbered grid lines, and the second column of sub-pixels, the third column of sub-pixels and the fifth column of sub-pixels in the lower row are coupled to the corresponding odd-numbered grid lines. The sub-pixel pairs in the up-row sub-pixel are coupled to the data line located on its first side, and the sub-pixel pairs in the down-row sub-pixel are coupled to the data line located on its second side.

9. The display panel according to claim 6, characterized in that, The display sub-region is provided with two adjacent rows of sub-pixels, wherein the first column of sub-pixels, the fourth column of sub-pixels and the sixth column of sub-pixels in the upper row are coupled to the corresponding even-numbered grid lines, and the first column of sub-pixels, the fourth column of sub-pixels and the sixth column of sub-pixels in the lower row are coupled to the corresponding odd-numbered grid lines. The sub-pixel pairs in the up-row sub-pixel are coupled to the data line located on its second side, and the sub-pixel pairs in the down-row sub-pixel are coupled to the data line located on its first side.

10. The display panel according to claim 1, characterized in that, One of the second sub-pixel and the third sub-pixel is a green sub-pixel, and the other is a blue sub-pixel.

11. The display panel according to claim 1, characterized in that, The odd-numbered gate lines are coupled to one sub-pixel in each sub-pixel pair in the corresponding row, and the even-numbered gate lines are coupled to the other sub-pixel in each sub-pixel pair in the corresponding row.

12. The display panel according to claim 1, characterized in that, The display panel also includes a touch signal line extending along a second direction, located between two adjacent columns of sub-pixels defined by two adjacent data lines, the second direction intersecting the first direction.

13. The display panel according to claim 12, characterized in that, The touch signal line is given a common electrode signal during the display of frames on the display panel, and the touch signal line is given a touch signal between two frames on the display panel.

14. The display panel according to claim 1, characterized in that, Multiple gate lines arranged along the second direction are configured to provide gate signals sequentially, with the gate signals of each two adjacent gate lines overlapping, and the second direction intersecting the first direction.

15. The display panel according to claim 14, characterized in that, The gate signal includes a pre-charge stage and an illumination stage. In two adjacent gate lines, the illumination stage of the gate signal of the preceding gate line and the pre-charge stage of the gate signal of the following gate line overlap at least partially.

16. A driving method for a display panel, characterized in that, Applied to the display panel of any one of claims 1-15, the method comprises: A gate signal is sequentially provided to multiple gate lines arranged along the second direction, wherein the gate signals of each two adjacent gate lines overlap, and the second direction is perpendicular to the first direction; According to the gate signal, data signals are provided to each of the data lines, so that the second sub-pixel and the third sub-pixel are lit.

17. A display device, characterized in that, The display panel includes any one of claims 1-15.

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