Breakdown mitigation for programmable resistive memory elements

Abstract

Techniques for reducing the threshold voltage of a threshold switching selector in a programmable resistive memory cell. When a control circuit applies a voltage across a programmable resistance memory cell in order to reduce a threshold voltage of a threshold switching selector in the programmable resistance memory cell, the programmable resistance memory cell is configured to switch the voltage across the programmable resistance memory cell. A memory system applies a first control signal to the circuit to establish a first resistance of a transistor in series with the programmable resistive memory cell, the word line, and the bit line. The memory system applies a second control signal to the circuit to establish a second resistance of the circuit in series with the programmable resistive memory cell, the word line, and the bit line to read a selected programmable resistive memory. The second resistance is lower than the first resistance.

Description

Background Technology

[0001] Memory is widely used in a variety of electronic devices such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery). Non-volatile memory can be made non-volatile, at least for a finite time, by adding a battery back to the power source outside the memory chip.

[0002] Memory cells can reside in a crosspoint memory array. In a memory array with a crosspoint-type architecture, one set of conductive lines extends across the surface of the substrate, and another set of conductive lines is formed above this set and extends in a direction orthogonal to the initial layer. The memory cell is located at the crosspoint junction of these two sets of conductive lines. Crosspoint memory arrays are sometimes called crossbar memory arrays.

[0003] Programmable resistive memory cells are formed from materials with programmable resistance. In a binary approach, a programmable resistive memory cell can be programmed into one of two resistance states: a high resistance state (HRS) and a low resistance state (LRS). In some methods, more than two resistance states can be used. One type of programmable resistive memory cell is a magnetoresistive random access memory (MRAM) cell. MRAM cells use magnetization to represent the stored data, in contrast to some other memory technologies that use electron charge (DRAM) or voltage (SRAM) to store data. Data bits are written to the MRAM cell by changing the magnetization direction of magnetic elements (“free layers”) within the MRAM cell, and bits are read by measuring the resistance of the MRAM cell, which changes with the magnetization direction. However, crosspoint memory arrays can have other types of memory cells. For example, crosspoint memory arrays can have memory cells using other technologies such as ReRAM, PCM (phase-change memory), or FeRAM.

[0004] In a crosspoint memory array, each memory cell may contain a threshold switching selector connected in series with a material having a programmable resistor. The threshold switching selector has a high resistance in the off or non-conducting state until it is biased to a voltage above its threshold voltage (Vt) or a current above its threshold current (It), and until the bias voltage of the threshold switching selector drops below Vhold (“Voffset”) or below the holding current Ihold. After exceeding Vt and exceeding Vhold across the threshold switching selector, the threshold switching selector (in the on or conducting state) has a significantly lower resistance. The threshold switching selector remains on until the current of the threshold switching selector drops below the holding current Ihold, or the voltage drops below the holding voltage Vhold. When this occurs, the threshold switching selector returns to the off (higher) resistance state. To read a memory cell, the threshold switching selector is activated by turning it on before determining the resistance state of the memory cell. An example of a threshold switching selector is a bidirectional threshold switch (OTS). Other examples of threshold switching selectors include, but are not limited to, volatile conductive bridges (VCBs), metal-insulator-metal (MIMs), or other materials that provide a highly nonlinear dependence of current on the selected voltage. Attached Figure Description

[0005] Elements with the same number represent common parts in different figures.

[0006] Figure 1 This is a block diagram of one implementation of a non-volatile memory system connected to a host computer.

[0007] Figure 2 This is a block diagram of one implementation scheme for a memory die.

[0008] Figure 3 It is a block diagram of one embodiment of an integrated memory assembly that includes control dies and memory structure dies.

[0009] Figure 4A An implementation of a memory array forming a cross-point architecture is depicted in oblique view.

[0010] Figure 4B and Figure 4C They were presented respectively Figure 4A Side and top views of the intersection structure.

[0011] Figure 4D An implementation of a portion of a secondary memory array forming a cross-point architecture is depicted in oblique view.

[0012] Figure 5An embodiment of the structure of an MRAM memory cell (here, for example, a selected cell driven by a current source for reading or writing) is illustrated.

[0013] Figure 6A and Figure 6B An implementation scheme for incorporating a threshold switching selector into an MRAM memory array with a crosspoint architecture is illustrated.

[0014] Figure 7A An implementation scheme for a memory array with a cross-point architecture accessed using a forced voltage method is described.

[0015] Figure 7B An implementation scheme for a memory array with a cross-point architecture using a current-force method is described.

[0016] Figure 8 This is a schematic diagram illustrating a resistor along a path that provides voltage across a programmable resistive memory cell.

[0017] Figure 9 This is a diagram illustrating the bounce events of the first trigger operation and the normal read operation.

[0018] Figure 10 An example of a rebound current that can be generated in response to the switching of a threshold selector is shown.

[0019] Figure 11 This is a diagram illustrating one embodiment of a circuit that provides voltage across a programmable resistive memory cell to reduce the threshold voltage of a threshold switching selector.

[0020] Figure 12 This is a schematic diagram of one embodiment of a programmable resistive memory cell 401 that includes word lines, bit lines, and several transistors connected in series.

[0021] Figure 13 This is a schematic diagram of one implementation of a programmable resistive memory cell that includes a word line, a bit line, and several transistors connected in series.

[0022] Figure 14 This is a flowchart of an implementation of a process to mitigate damage to programmable resistive memory cells while reducing the threshold voltage of the threshold switching selector for the memory cells.

[0023] Figure 15 This is a flowchart of an implementation of a process that mitigates damage to programmable resistive memory cells during the formation process while simultaneously reducing the threshold voltage of the threshold switching selector for the memory cells.

[0024] Figure 16This is a flowchart of an implementation of a process that mitigates damage to programmable resistive memory cells while reducing the threshold voltage of the threshold switching selector of the memory cells during the formation process of providing a formation voltage using a current-force method. Detailed Implementation

[0025] Techniques for reducing the threshold voltage of a threshold switching selector in a programmable resistive memory cell are disclosed. Turning on the threshold switching selector can cause a rebound current. Specifically, after the threshold switching selector is turned on, the voltage across the memory cell drops rapidly from Vth to Vhold (or Voffset), resulting in a rebound current. This rebound current can flow through the programmable resistive memory element, potentially damaging it. Furthermore, the voltage across the programmable resistive memory element can undergo rapid and large changes, which can also potentially damage it. The techniques discussed herein mitigate damage to the programmable resistive memory element during operation that reduces the threshold voltage of the threshold switching selector.

[0026] An embodiment of the memory system includes circuitry configured to connect to a selected programmable resistive memory cell in a crosspoint array and apply a voltage across the selected programmable resistive memory cell. The circuitry includes a transistor configured to be connected in series with the selected programmable resistive memory cell, a selected word line, and a selected position line in the crosspoint array. When the circuitry is controlled to apply a voltage across the selected programmable resistive memory cell to reduce the threshold voltage of a threshold switching selector in the programmable resistive memory cell, the memory system applies a first control signal to the circuitry to establish a first resistance of the transistor connected in series with the selected programmable resistive memory cell, the selected word line, and the selected position line. The memory system applies a second control signal to the circuitry to establish a second resistance of the circuitry connected in series with the selected programmable resistive memory cell, the selected word line, and the selected position line to sense the selected programmable resistive memory. The first resistance is higher than the second resistance. When the threshold switching selector is on, the higher second resistance of the transistor results in a larger voltage across the transistor, thereby reducing the voltage across the programmable resistive memory element and mitigating damage to the programmable resistive memory element. The lower first resistance used in sensing operation allows for better sensing of the state of the programmable resistive memory element. The first and second control signals can be decoder address signals with different values. Therefore, a transistor with adjusted resistance can reside in the decoder circuit, which can be used to select memory cells.

[0027] In the implementation, the threshold voltage reduction operation is the first activation operation. When the threshold switching selector is first turned on during the lifetime of the memory device, the threshold voltage (Vth) is substantially higher than the threshold voltage during normal operations such as reading or writing. The voltage required to turn on the selector during initial use (referred to as the first activation voltage) is substantially higher than the target voltage range required to turn on the selector during normal operation. This is due to a transformation that occurs in the threshold switching selector during a process called “seasoning” or “forming,” which reduces the Vth of the threshold switching selector. Typically, the threshold voltage of the threshold switching selector decreases over several cycles, which can be referred to as the forming operation. The state of the selector can be transformed from an initial amorphous state with an initial threshold voltage (referred to herein as the first activation voltage Vff) to an operating state with an operating threshold voltage (Vop) lower than the initial threshold voltage. This transformation results in a permanent reduction in the threshold voltage of the selector. This transformation leads to a structural change, which may be due to thermal effects on the selector material.

[0028] In the implementation, the threshold voltage reduction operation occurs during the cold start operation. After the initial formation operation has been performed, if the threshold switching selector remains inactive for a considerable period, the threshold voltage of the threshold switching selector may drift higher. As used herein, the term "cold start operation" refers to the operation of reducing the threshold voltage of the threshold switching selector after the threshold voltage has drifted higher. Therefore, the cold start operation can be performed after the initial formation operation has established its threshold voltage at the operating threshold voltage (Vop) of the threshold switching selector. As used herein, the term "cold start operation" does not sense the state of the memory cells.

[0029] In this implementation, the Vth of the threshold switching selector in the crossbar array is gradually reduced over several formation cycles. Gradually reducing the Vth of the threshold switching selector can be termed "partially forming" the threshold switching selector because the Vth of the threshold switching selector is only fully formed after several formation cycles. In this implementation, the memory cell selected to form its threshold switching selector has a formation voltage applied across that cell. The formation voltage can be gradually reduced during the formation operation. In this implementation, as the formation voltage gradually decreases, the resistance of the circuitry connected in series with the memory cell (as well as the word lines and bit lines) gradually decreases.

[0030] As described above, the resistance of the circuitry connected in series with the memory cell (as well as the word line and bit line) is lower during the sensing of the memory cell than during the first excitation, formation, or cold start operation. A technique for sensing programmable resistive memory cells has emerged in global reference reads. Global reference reads are sometimes called midpoint reads or midpoint reference reads. Global reference reads can use a reference voltage between a lower resistance state (LRS) and a higher resistance state (HRS). Here, LRS and HRS refer to the voltages that appear across the cell in response to a read current. For example, the midpoint reference can be a reference voltage between two voltages corresponding to sensing a cell with either LRS or HRS. In forced current methods, the state of the memory cell is determined based on whether the sensed voltage Vsense is higher or lower than the midpoint reference voltage VREF.

[0031] Another technique for sensing programmable resistive memory cells appears in what is commonly known as destructive self-reference read (SRR). In SRR, the reference is generated based on sensing the cell itself rather than using a midpoint reference independent of the cell state. In destructive SRR, the state of the memory cell can be altered (e.g., destroyed) by a write operation of the SRR. One SRR technique includes a first read (read 1), followed by a destructive write to a known state (e.g., a high-resistance state HRS) and a second read (read 2). The results of the two reads are compared to determine the original state of the cell. One technique for the first read is to apply a read current through the memory cell, causing the voltage across the cell to have a magnitude representing the resistance of the memory cell. The voltage is stored and can be adjusted (e.g., increased or decreased by 150mV) for comparison with a voltage sample from the second read. The voltage adjustment can be approximately half the signal difference across the MRAM for each state. For example, if the MRAM low resistance state (LRS) is 25 Kohm, the high resistance state is 50 Kohm, and the read current is 15 μA, the difference from the state change is 375 mV, so an adjustment of approximately 182.5 mV can be made from the read 1 storage voltage of the SRR. The determination of the original state of the memory cell depends on the difference between the first adjusted read voltage and the second read voltage. For example, if the first sampling voltage from read 1 of the SRR is increased and written to the HRS, then with the cell initially in the HRS, the second sampling voltage from read 2 should be approximately the same as read 1 and therefore lower than the first read voltage after the increase. However, if the cell is initially in the LRS, the second sampling voltage from read 2 should be higher than the increased voltage from read 1 due to the higher read 2 voltage resulting from writing the bit from the low resistance LRS to the HRS.

[0032] In implementations, the memory system is used in conjunction with programmable resistive memory cells residing in a crosspoint memory array. In a memory array with a crosspoint-type architecture, one set of conductive lines extends across the surface of a substrate, and another set of conductive lines is formed above this set, extending above the substrate in a direction perpendicular to the first set. The memory cell is located at the crosspoint junction of these two sets of conductive lines. Crosspoint memory arrays are sometimes referred to as crossbar memory arrays. In implementations, each memory cell has a magnetoresistive memory element connected in series with an OTS, which may be referred to as an MRAM memory cell. However, crosspoint memory arrays may have other types of memory cells. For example, crosspoint memory arrays may have memory cells using other technologies such as ReRAM, PCM (phase-change memory), FeRAM, etc. Furthermore, the threshold switching selector does not need to be an OTS and can be a pair of diodes with an anode-to-cathode connection.

[0033] In some embodiments, the programmable resistive memory cell has magnetoresistive random access memory (MRAM) elements. As used herein, the magnetization direction is the direction in which the magnetic moment is oriented relative to a reference direction set by another element of the MRAM (“reference layer”). In some embodiments, low resistance is referred to as parallel or P-state or LRS, and high resistance is referred to as anti-parallel or AP-state or HRS. The MRAM can use a spin-shift torque effect to change the magnetization direction from P-state to AP-state and vice versa, which typically requires bipolar (bidirectional write) operations for writing. However, the SRR of the programmable resistive memory cell disclosed herein is not limited to memory cells having MRAM elements or OTS elements.

[0034] Figure 1 This is a block diagram of one embodiment of a non-volatile memory system (or more simply, a "memory system") 100 connected to a host system 120. The memory system 100 implements the techniques presented herein for reading programmable resistive memory cells with threshold-switching selectors. In this embodiment, the memory cell has a programmable resistive memory element (e.g., an MRAM element) connected in series with a threshold-switching selector such as an OTS. Many types of memory systems can be used with the techniques presented herein. Example memory systems include dual in-line memory modules (DIMMs), solid-state drives ("SSDs"), memory cards, and embedded memory devices; however, other types of memory systems may also be used.

[0035] Figure 1The memory system 100 includes a memory controller 102, a memory 104 for storing data, and a local memory 140 (e.g., MRAM, ReRAM, DRAM). The local memory 140 may be non-volatile and retain data after power loss. Alternatively, the local memory 140 may be volatile and data retention after power loss is not expected. In one embodiment, the local memory 140 is MRAM. In another embodiment, the local memory MRAM does not need to retain data after power loss. However, the local memory MRAM may retain data after power loss. In one embodiment, the memory controller 102 and / or the local memory controller 164 provide access to programmable resistive memory cells in the local memory 140. For example, the memory controller 102 may provide access to a cross-point array of MRAM cells in the local memory 140. In another embodiment, the memory controller 102 or interface 126, or both, are removed, and the memory packages are directly connected to the host 120 via a bus such as DDRn. Alternatively, they are connected to a host memory management unit (MMU). In another example, memory controller 102 or its components are moved onto memory 104 to allow memory 104 to be directly connected to the host, such as by providing parity bits, ECC, and wear leveling on memory 104 along with a DDRn interface to / from host 120 or the MMU. As used throughout this document, the term "memory system" is not limited to memory system 100. For example, local memory 140 or a combination of local memory 140 and local memory controller 164 can be considered a memory system. Similarly, host memory 124 or a combination of host processor 122 and host memory 124 can be considered a memory system.

[0036] Figure 1The components of the depicted memory system 100 are electrical circuits. The memory controller 102 includes a host interface 152, a processor 156, an ECC engine 158, a memory interface 160, a local memory controller 164, refresh logic 172, and a wear leveler 174. The host interface 152 connects to and communicates with a host 120. The host interface 152 also connects to a network on-chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains or use non-clock asynchronous logic. NOC technology applies networking theory and methods to on-chip communication, resulting in significant improvements over conventional bus and crossbar interconnects. Compared to other designs, NOC improves the scalability of the system-on-chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Because all links in the NOC can operate simultaneously on different data packets, a high level of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to increase, the NOC offers enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 may be replaced by a bus. Connected to and communicating with the NOC 154 are the processor 156, ECC engine 158, memory interface 160, local memory controller 164, refresh logic 172, and wear leveler 174. The local memory controller 164 is used to operate and communicate with the local high-speed memory 140 (e.g., MRAM). In other embodiments, the local high-speed memory 140 may be DRAM, SRAM, or another type of volatile memory.

[0037] ECC engine 158 performs error correction services. For example, ECC engine 158 performs data encoding and decoding on or off-memory parity bits, which are part of a codeword used to correct errors in data retrieved from memory 140 or 104. In one embodiment, ECC engine 158 is a software-programmable electrical circuit. For example, ECC engine 158 may be a programmable processor. In other embodiments, ECC engine 158 is a custom-designed dedicated hardware circuit without any software. In one embodiment, the functionality of ECC engine 158 is implemented by processor 156. In one embodiment, local memory 140 has an ECC engine with or without a wear leveling engine. In one embodiment, memory 104 has an ECC engine with or without a wear leveling engine.

[0038] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes including wear leveling. A separate wear leveler 174 is depicted, but wear leveler 174 can be implemented by processor 156. Additionally, refresh logic 172 is depicted, but refresh can also be implemented by processor 156. In one embodiment, processor 156 is firmware-programmed. In other embodiments, processor 156 is a custom-designed dedicated hardware circuit without any software. Processor 156 may also implement a translation module as software / firmware processing or dedicated hardware circuitry. In many systems, non-volatile memory is internally addressed to the memory system using physical addresses associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This allows the host to assign data to consecutive logical addresses while the memory system is free to store data in the locations of one or more memory dies as desired. To implement this system, memory controller 102 (e.g., a translation module) performs address translation between logical addresses used by the host and physical addresses used by the memory dies. One example implementation is maintaining a table that identifies the current translation between logical addresses and physical addresses (i.e., the L2P table mentioned above). Entries in the L2P table may include identifiers for logical addresses and their corresponding physical addresses. Although logical address-to-physical address tables (or L2P tables) include the word "table," they do not need to be tables in the literal sense. Instead, logical address-to-physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of the storage system is so large that local memory 140 cannot hold all the L2P tables. In such cases, the entire set of L2P tables is stored in memory 104, and a subset of the L2P tables is cached (the L2P cache) in local memory 140.

[0039] Memory interface 160 communicates with storage device 104. In one embodiment, storage device 104 includes programmable resistive memory cells in a crosspoint array. In another embodiment, storage device 104 includes NAND memory cells. In one embodiment, the memory interface provides a mode-switching interface. Other interfaces may also be used. In some example implementations, memory interface 160 (or another part of controller 102) implements a scheduler and buffer for sending data to and receiving data from one or more memory dies.

[0040] In one embodiment, local memory 140 has an ECC engine. Local memory 140 can be used to assist in performing other functions, such as wear leveling. Further details of on-chip memory maintenance are described in U.S. Patent 10,545,692, entitled "Memory Maintenance Operations During Refresh Window," and U.S. Patent 10,885,991, entitled "Data Rewrite During Refresh Window," the entire contents of which are incorporated herein by reference. In one embodiment, local memory 140 is synchronous. In another embodiment, local memory 140 is asynchronous.

[0041] In one embodiment, storage device 104 includes multiple memory packages. Each memory package includes one or more memory dies. Therefore, memory controller 102 is connected to one or more memory dies. In one embodiment, the memory package may include various types of memory, such as storage class memory (SCM) based on programmable resistor random access memory (such as ReRAM, MRAM, FeRAM, or RRAM) or phase-change memory (PCM). In one embodiment, memory controller 102 provides access to memory cells in a cross-point array within storage device 104.

[0042] Memory controller 102 communicates with host 120 via interface 152 implementing protocols such as Compute Fast Link (CXL). Alternatively, such a controller may be omitted, and the memory package may be placed directly on, for example, the host bus, DDRn, or CXL. To work with memory system 100, host system 120 includes host processor 122, host memory 124, and interface 126 connected along bus 128. Host memory 124 is the host's physical memory and may be DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or another type of memory device. In an embodiment, host memory 124 includes a cross-point array of programmable resistive memory cells, wherein each memory cell includes a programmable resistive memory element and a threshold switching selector connected in series with the programmable resistive memory element.

[0043] The host 120 is located outside and spaced apart from the memory system 100. In one embodiment, the memory system 100 is embedded within the host 120. The host memory 124 may be referred to herein as the memory system. The combination of the host processor 122 and the host memory 124 may be referred to herein as the memory system. In an embodiment, such host memory may be a cross-point memory using MRAM.

[0044] Figure 2 This is a block diagram illustrating an example of a memory die 292 that can implement the techniques described herein. In one embodiment, the memory die 292 is included in local memory 140, and in another embodiment, the memory die 292 is included in storage device 104. In one embodiment, the memory die 292 is included in host memory 124. The memory die 292 includes a memory structure 202, which may include any memory cells described below. The memory structure 202 may include one or more memory arrays. The array terminal lines of the memory structure 202 include various layers of word lines organized into rows and various layers of bit lines organized into columns. However, other orientations may also be implemented, including, for example, a diagonal pattern to save space. The memory die 292 includes row control circuitry 220, the output of which 208 is connected to a corresponding word line of the memory structure 202. Row control circuitry 220 receives a set of M row address signals and one or more various control signals from system control logic circuitry 260, and typically includes circuitry such as row decoder 222, row driver 224, and block select circuitry 226 for both read and write operations. Row control circuitry 220 may also include read / write circuitry. In one embodiment, row control circuitry 220 has sense amplifiers 228, each containing circuitry for sensing the condition (e.g., voltage) of word lines in memory structure 202. In another embodiment, the condition or bit state of a memory cell in the cross-point array is directly determined by sensing the word line voltage and comparing the voltage of the accessed memory cell with a reference voltage using the sense amplifiers. Alternatively, the determination can be made less directly by first accessing the memory cell and storing the read voltage generated by forcing a read current through the cell and adjusting it up or down by 150mV (or half the voltage difference generated by changing the bit state), then writing the cell to the AP state, and accessing the memory cell again with the read current and comparing the resulting voltage with, for example, the stored voltage adjusted by 150mV (or half the voltage difference generated by two different bit states). The memory die 292 also includes column decoder and control circuitry 210, whose input / output 206 is connected to the corresponding bit lines of the memory structure 202. Although only a single block for the memory structure 202 is shown, the memory die may include arrays or “tiles” that can be accessed individually. The column control circuitry 210 receives a set of N column address signals and one or more various control signals from the system control logic 260, and typically includes circuitry such as column decoder 212, column decoder and driver 214, block selection circuitry 216, read / write circuitry, and I / O multiplexers.

[0045] System control logic 260 receives data and commands from the host system and provides output data and status to the host system. In other embodiments, system control logic 260 receives data and commands from a separate controller circuit and provides output data to that controller circuit, which communicates with the host system. Such a controller system may implement interfaces such as DDR, DIMM, CXL, PCIe, etc. In another embodiment, those data and commands are transferred and received directly from the memory package to the host without a separate controller, and any required controller is located within each die or within a die added to the multi-chip memory package. In some embodiments, system control logic 260 may include a state machine 262 that provides die-level control over memory operations. In one embodiment, state machine 262 is programmable by software. In other embodiments, state machine 262 does not use software and is implemented entirely in hardware (e.g., electrical circuitry). In another embodiment, state machine 262 is replaced by a microcontroller or microprocessor. System control logic 260 may also include a power control module 264 that controls the power, current source current, and voltage supplied to each row and column of memory structure 202 during memory operation, and may include charge pump and regulator circuitry for generating regulated voltages, as well as on / off control for word line bit line selection of memory cells. In some embodiments, power control 264 includes one or more current sources. The current sources can be used to provide read and / or write currents. System control logic 260 includes a storage device 266 that can be used to store parameters for operating memory structure 202. System control logic 260 also includes refresh logic 272 and wear leveling logic 274. Such system control logic can be executed by command from host 120 or memory controller 102. Refresh logic 272 can load on-chip stored row and column addresses (pointers) that can be incremented after a refresh. Only such address bits can be selected (to refresh the OTS). Alternatively, such addresses can be read, corrected via ECC engine 269, and then stored in a "spare" location that is also being incremented (so all codewords are periodically read, corrected, and relocated throughout the chip under the control of wear leveling logic 274) to achieve wear leveling, thus using each bit more evenly across the chip. This type of operation may be more directly controlled by the host with an external controller (such as a PCIe, CXL, or DDRn controller located separately from the memory chip or on the memory die).

[0046] Commands and data are transferred between memory controller 102 and memory die 292 via memory controller interface 268 (also referred to as the "communication interface"). Such an interface can be, for example, PCIe, CXL, or DDRn. Memory controller interface 268 is an electrical interface for communicating with memory controller 102. Examples of memory controller interface 268 also include a switching mode interface. Other I / O interfaces may also be used. For example, memory controller interface 268 may implement a switching mode interface connected to the switching mode interface of memory interface 228 / 258 of memory controller 102. In one embodiment, memory controller interface 268 includes a set of input and / or output (I / O) pins connected to controller 102. In another embodiment, the interface is a JEDEC standard DDRn or LPDDRn (such as DDR5 or LPDDR5), or a subset thereof with smaller page size and / or more relaxed timing.

[0047] The system control logic 260 in the controller located on the memory die within the memory package may include an error correction code (ECC) engine 269. The ECC engine 269 may be referred to as an on-die ECC engine because it resides on the same semiconductor die as the memory cells. That is, the on-die ECC engine 269 can be used to encode the data and parity bits to be stored in the memory structure 202 and to decode and correct errors in the decoded data. The encoded data may be referred to herein as a codeword or ECC codeword. The ECC engine 269 can be used to execute decoding algorithms and perform error correction. Therefore, the ECC engine 269 can decode ECC codewords. In this embodiment, the ECC engine 269 is able to decode data more quickly through direct decoding without iteration. Having the ECC engine 269 on the same die as the memory cells allows for faster decoding. ECC Engine 269 can use a wide variety of decoding algorithms, including but not limited to Reed Solomon, Bose-Chaudhuri-Hocquenghem (BCH), and Low-Density Parity Check (LDPC).

[0048] In some embodiments, all elements of memory die 292 (including system control logic 260) may be formed as part of a single die. In other embodiments, some or all of the system control logic 260 may be formed on different dies; for example, on an external controller chip.

[0049] In one embodiment, memory structure 202 includes a three-dimensional memory array of non-volatile or volatile memory cells, in which multiple memory levels are formed over a single substrate such as a wafer. The memory structure may include any type of non-volatile or volatile memory, formed monolithically in one or more physical levels of memory cells having an effective area disposed over a silicon substrate or silicon-on-insulator (or other type) substrate. In another embodiment, memory structure 202 includes a two-dimensional memory array of non-volatile memory cells.

[0050] The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. For the purposes of the recently claimed embodiments presented herein, no specific non-volatile memory technology is required. Other examples of suitable technologies for the memory cells of memory structure 202 include ReRAM (Resistive Random Access Memory), magnetoresistive memory (e.g., MRAM, spin-orbit MRAM, spin-track MRAM), FeRAM, phase-change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0051] An example of a ReRAM or MRAM crosspoint memory includes a programmable resistor switching element connected in series with an OTS selector arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word lines and bit lines). In another embodiment of the crosspoint, a PCM is connected in series with the OTS selector. In yet another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell. The conductive bridge memory element can be used as a state-changing element based on the physical relocation of ions within a solid electrolyte. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a solid electrolyte film between the two electrodes. As temperature increases, ion mobility also increases, resulting in a decrease in the programming threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element may have a wide range of programming thresholds that vary with temperature.

[0052] Magnetoresistive random access memory (MRAM) uses magnetic storage elements to store data. This element is formed of two ferromagnetic layers, each of which can remain magnetized, separated by a thin insulating layer. For field-controlled MRAM, one of the layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed by applying an external field to store memory. Other types of MRAM cells are possible. Memory devices can be constructed from a grid of MRAM cells or built as SOT magnetoresistive memories. MRAM-based memory implementations will be discussed in more detail below.

[0053] Phase-change memory (PCM) utilizes the unique behavior of chalcogenides. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve a non-thermal phase transition by simply changing the coordination state of germanium atoms with a laser pulse (or a light pulse from another source). The memory cell is programmed by a current pulse that alters the coordination of the PCM material or switches it between an amorphous and crystalline state. Note that the use of "pulse" in this document does not require a square pulse, but includes (continuous or discontinuous) vibrations or bursts of sound, current, voltage, light, or other waves. The current forced for writing can, for example, be rapidly driven to a peak and then linearly sloped down at an edge rate of, for example, 500 ns. This peak current force can be limited by partition voltage compliance, which varies depending on the location of the memory cell along the word line or bit line. In an embodiment, the phase-change memory cell has a phase-change memory element connected in series with a threshold switching selector such as an OTS.

[0054] Those skilled in the art will recognize that the techniques described herein are not limited to a single particular memory structure, memory construction, or material composition, but encompass many related memory structures as described herein and as understood by those skilled in the art.

[0055] Can Figure 2The components are grouped into two parts: memory structure 202 and peripheral circuitry, including all other components. A key characteristic of the memory circuitry is its capacity, which can be increased by increasing the area allocated to memory structure 202 for the memory die 292; however, this reduces the area available for peripheral circuitry or increases chip area-related costs. This can impose very strict limitations on these peripheral components. For example, the need to fit sense amplifier circuitry within the available area can significantly limit the sense amplifier design architecture. Regarding system control logic 260, the reduced area availability can limit the available functionality that can be implemented on-chip. Therefore, the fundamental trade-off when designing memory die 292 is the amount of area dedicated to memory structure 202 versus the amount dedicated to peripheral circuitry. Such trade-offs can result in a larger IR drop due to the use of a larger xy memory array between the driving word lines and bit lines, which can be further benefited by using voltage limits and partitioning voltage compliance along the word lines and bit lines by memory cell location.

[0056] Another area where the memory structure 202 and peripheral circuitry are often inconsistent is the processing involved in forming these regions, as these regions typically involve different processing techniques and trade-offs in using different techniques on a single die. For example, components such as sense amplifier circuitry, charge pumps, logic elements in state machines, and other peripheral circuitry in system control logic 260 often employ PMOS devices. In some cases, the memory structure will be based on CMOS devices. The processing operations used to fabricate CMOS dies will differ in many ways from those optimized for NMOS-only technology.

[0057] To mitigate these limitations, the implementation scheme described below can... Figure 2 The components are separated onto individually formed dies, which are then bonded together. Figure 3An integrated memory assembly 270 is depicted having a memory structure die 280 and a control die 290. A memory structure 202 is formed on the memory structure die 280, and some or all of the peripheral circuitry elements (including one or more control circuitry elements) are formed on the control die 290. For example, the memory structure die 280 may be formed only of memory elements, such as an array of memory cells from MRAM, PCM, ReRAM, or other memory types. Some or all of the peripheral circuitry (even including elements such as decoders, current sources, and sense amplifiers) may then be moved to the control die. This allows each semiconductor die in the semiconductor assembly to be individually optimized according to its technology. This frees up more space for peripheral elements, which can now incorporate additional capabilities that would otherwise be difficult to incorporate due to the margin of the same die used to maintain the memory cell array. The two dies can then be joined together in a bonded multi-die integrated memory assembly, where an array on one die is connected to peripheral elements on the other die. Although the following will focus on an integrated memory assembly with one memory die and one control die, other implementations may use additional dies, such as, for example, two memory dies and one control die.

[0058] as Figure 2 The memory die 292 is the same. Figure 3 The memory structure die 280 includes a memory structure 202, which may include an array or "tile" with multiple individually accessible arrays. System control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 290. In some embodiments, all or a portion of the column control circuitry 210 and all or a portion of the row control circuitry 220 are located on the memory structure die 280. In some embodiments, some circuitry in the system control logic 260 is located on the memory structure die 280.

[0059] Figure 3A column control circuit 210 on a control die 290 is shown coupled to a memory structure 202 on a memory structure die 280 via an electrical path 293. For example, electrical path 293 may provide electrical connections between the column decoder 212, column driver circuitry 214, and block select device 216 and the bit lines of the memory structure 202. The electrical path may extend from the column control circuitry 210 in the control die 290 through pads on the control die 290 that bond to corresponding pads on the memory structure die 280, which are connected to the bit lines of the memory structure 202. Each bit line of the memory structure 202 may have a corresponding electrical path in electrical path 293, including a pair of bonded pads connected to the column control circuitry 210. Similarly, a row control circuitry 220, including a row decoder 222, a row driver 224, a block select device 226, and a sense amplifier 228, is coupled to the memory structure 202 via electrical path 294. Each electrical path in electrical path 294 may, for example, correspond to a word line. Additional electrical paths can also be provided between the control die 290 and the memory structure die 280.

[0060] For the purposes of this document, the phrase "control circuitry" may include one or more of the following: memory controller 102, local memory controller 164, processor 156, system control logic 260, column control circuitry 210, row control circuitry 220, host processor 122, microcontroller, state machine, and / or other control circuitry or other analog circuitry for controlling non-volatile memory. Control circuitry may consist of hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of control circuitry. Control circuitry may include processors, FPGAs, ASICs, integrated circuits, or other types of circuitry. Such control circuitry may include drivers, such as direct drives to a fixed voltage, such as a power supply, via a connection of nodes through fully conducting transistors (gate to power supply). Such control circuitry may include current source drivers.

[0061] For the purposes of this document, the term “device” may include, but is not limited to, one or more of the following: memory system 100, local memory 140, local memory controller 164 and / or a combination of memory controller 102 and local memory 140, storage device 104, memory die 292, integrated memory assembly 270 and / or control die 290.

[0062] The following discussion will be conducted in the context of intersection architecture. Figure 2 and Figure 3The memory structure 202. In the crosspoint architecture, a first set of conductive lines or wires (such as word lines) extends in a first direction relative to the underlying substrate, and a second set of conductive lines or wires (such as bit lines) extends in a second direction relative to the underlying substrate. Memory cells are located at the intersections of word lines and bit lines. These memory cells at the intersections can be formed according to any of several techniques including those described above. The following discussion will focus primarily on an implementation based on a crosspoint architecture using MRAM memory cells, each MRAM memory cell being connected in series with a threshold switching selector such as a bidirectional threshold switch (OTS) to include selectable memory bits. However, the implementation is not limited to providing current to a crosspoint architecture with MRAM cells, each MRAM cell having a magnetic memory element in a series OTS selector. For example, the crosspoint memory array may have memory cells of other technologies such as ReRAM, PCM (phase-change memory), or FeRAM.

[0063] Figure 4A An embodiment of a portion of a memory array 402 forming a cross-point architecture is depicted in oblique view. Figure 4A The memory array 402 is used for Figure 2 or Figure 3 One example of a specific implementation of memory structure 202 is that memory die 292 or memory structure die 280 may include multiple such memory arrays 402. Memory array 402 may be contained in local memory 140 or host memory 124. Bit lines BL1 to BL5 are arranged in a first direction relative to the underlying substrate (not shown) of the die (represented as extending into the page), and word lines WL1 to WL5 are arranged in a second direction perpendicular to the first direction or along a diagonal to provide intersections for interconnecting memory cells between WL and BL. Figure 4A This is an example of a horizontal crossover structure, where both word lines WL1 to WL5 and BL1 to BL5 extend in a horizontal direction relative to the substrate, and memory cells (two of which are indicated at 401) are oriented such that the current through the memory cells (such as in I...) cell (as shown below) extends vertically. In memory arrays with additional layers of memory cells (such as those described below) Figure 4D (As discussed), there may be corresponding additional layers for bit lines and word lines. For example, a pattern might start from the bottom layer: WL, memory cell, BL, memory cell, WL, WL, memory cell, BL, memory cell, WL.

[0064] like Figure 4AAs depicted, memory array 402 includes a plurality of memory cells 401. Memory cells 401 may include rewritable memory elements, such as those implemented using ReRAM, MRAM, PCM, or other materials with programmable resistors. Memory cells 401 may be referred to herein as programmable resistive memory cells. One type of programmable resistive memory cell is called an MRAM cell, which is a memory cell comprising MRAM memory elements. Memory cells 401 may also include threshold switching selectors as additional series elements within memory cells 401, such as those implemented using bidirectional threshold switches (OTS), volatile conductive bridges (VCB), metal-insulator-metal (MIM), or other materials that provide a highly nonlinear dependence of current or resistance on a changing selection voltage. The following discussion will focus on memory cells composed of MRAM memory elements combined in series with bidirectional threshold switching elements, but many of the discussions can be applied more generally. The current in a memory cell of a first memory level is shown as shown by arrow I. cell The current is indicated to flow upwards, but it can flow in any direction to read or write the state of a memory cell bit, as discussed in more detail below.

[0065] Figure 4B and Figure 4C They were presented respectively Figure 4A Side and top views of the intersection structure. Figure 4B The side view shows a bottom wire or word line WL1 and a top wire or bit line BL1 to BL2. n At the intersection of each top and bottom wire is an MRAM memory cell 401, but PCM, ReRAM, FeRAM, or other technologies can be used as memory elements. Figure 4C This example illustrates M bottom conductors WL1 to WL. M and N top conductors BL1 to BL NA top view of the intersection structure. In a binary implementation, the MRAM cell at each intersection can be programmed into one of two resistance states: a high-resistance state and a low-resistance state. Further details regarding implementations of the MRAM memory cell design and its read techniques are given below. In some implementations, these sets of wires are arranged continuously as “tiles,” and such tiles can be paired adjacently in the word line (WL) direction and orthogonally in the bit line direction to create a module. Such a module can consist of 2×2 tiles to form a combination of four tiles, where the WL drivers between the tiles are “center-driven” between the tiles, with the WL extending continuously above the transistor drivers at approximately the center of the line. Similarly, BL drivers can be located between a pair of tiles to be center-driven in the BL direction, whereby the transistor drivers and their area are shared between the pair of tiles. Copper vias or other types of low-resistance vias can decode the WL or BL and connect transistor drivers / selection devices to the WL or BL. In addition to the memory elements in the memory cells between the WL and BL, cascaded selection elements, such as OTS, may also be included.

[0066] Figure 4A The cross-point array illustrates an implementation with a single layer of word lines and bit lines, where the MRAM or other memory technology for the memory cells is located at the intersection of two sets of conductive lines. To increase the storage density of the memory die, multiple layers of such memory cells and conductive lines can be formed. Figure 4D The example shows two layers.

[0067] Figure 4D An implementation of a portion of a secondary memory array forming a cross-point architecture is depicted in oblique view. For example... Figure 4A middle, Figure 4D The first layer 418 of the memory cell 401 of the memory array 403 is shown, which is connected to the word line WL mentioned above. 1,1 To WL 1,4 At the intersection of the first layer of bit lines BL1 to BL5. Memory array 403 may be included in Figure 2 or Figure 3 In the memory structure 202, the second layer 420 of the memory cells is formed above bit lines BL1 to BL5 and between these bit lines and word lines WL 2,1 To WL 2,4 The second set is between them. In fact, the BL is shared. Alternatively, the second layer could include another BL level above the shown BL and below the second level of the WL. Although Figure 4D Two layers 418 and 420 of the memory cell are shown, but the structure can extend upwards in a similar pattern through additional alternating layers of word lines and bit lines. According to the embodiment, Figure 4DThe word lines and bit lines of the array can be biased for read or program operations, such that current in each layer flows from the word line layer to the bit line layer or in the opposite direction. These two layers can be configured to have current flowing in the same direction in each layer for a given operation, or to have current flowing in opposite directions by driver selection in the positive or negative direction. Memory cells can be placed in the same orientation within the first and second layers, allowing reads or writes to be performed layer by layer using current in opposite directions. Alternatively, when placed between BL and WL in the second layer, the memory cells are placed in an inverted or flipped orientation (thus allowing current to be used in the same direction as for reads or writes in the memory cells within the first layer). It will be apparent to those skilled in the art that these two layers can be extended to three or more layers.

[0068] The use of a crosspoint architecture enables arrays with a small footprint, and several such arrays can be formed on a single die. The memory cell formed at each crosspoint can be a resistive memory cell, where data values ​​are encoded as different resistance levels, such as two levels in the case of MRAM, or two or more levels for other memory element technologies such as PCM. Depending on the implementation, the memory cell can be binary-valued, having a low-resistance state or a high-resistance state, or it can be a multi-level cell (MLC) with an additional resistance between the low-resistance and high-resistance states. The crosspoint arrays described herein can... Figure 2 Memory die 292, Figure 1 Local memory 140 and / or Figure 1 It is used in the host memory 124, or in any other configuration where additional memory is useful. Resistive memory cells can be formed according to many of the technologies mentioned above, such as ReRAM, PCM, FeRAM, or MRAM. The following discussion is presented primarily in the context of memory arrays using a crosspoint architecture (with MRAM memory cells that are binary-valued), but much of the discussion is more generally applicable to other memory elements in memory cells within a crosspoint array or other configurations that will be obvious to those skilled in the art.

[0069] Figure 5 The structure of an implementation of an MRAM cell is illustrated. An MRAM cell can be used as, for example... Figures 4A to 4DThe programmable resistive memory cell 401 is described above. The MRAM cell includes a bottom electrode 501, spacers 512, a threshold switching selector 502, spacers 514, a pair of magnetic layers (reference layer 503 and free layer 507) separated by a separating or tunneling layer of magnesium oxide (MgO) 505 (in this example), and a top electrode 511 separated from the free layer 507 by spacers 509. Spacers 509 may consist of an MgO capping layer in contact with the free layer 507. Spacers 509 may also include additional metal layers. In another embodiment, the positions of the reference layer 503 and the free layer 507 are interchanged, with the reference layer 503 on top of the MgO 505 and the free layer 507 below the MgO 505. In another embodiment, the threshold switching selector 502 is located between the free layer 507 and the top electrode 511.

[0070] In some embodiments, the bottom electrode 501 is a word line and the top electrode 511 is a bit line. In other embodiments, the bottom electrode 501 is a bit line and the top electrode 511 is a word line. The state of the memory cell is based on the relative orientation of the magnetization of the reference layer 503 and the free layer 507: if the two layers are magnetized in the same direction, the memory cell will be in a parallel (P) low resistance state (LRS); and if they have opposite orientations, the memory cell will be in an antiparallel (AP) high resistance state (HRS). MLC embodiments may include additional intermediate states. The orientation of the reference layer 503 is fixed, and... Figure 5 In the example, it is oriented upwards. Reference layer 503 is also called a pinning layer or anchoring layer. Reference layer 503 may consist of multiple ferromagnetic layers antiferromagnetically coupled in a structure commonly referred to as a synthetic antiferromagnet or simply SAF.

[0071] Data is written to MRAM memory cells by programming free layer 507 to have the same or opposite orientation as reference layer 503. An array of MRAM memory cells can be placed in an initial or erased state by setting all MRAM memory cells to a low-resistance state (where all free layers of that MRAM memory cell have the same magnetic field orientation as its reference layer). Each memory cell is then selectively programmed (also called “written”) by reversing the magnetic field to be opposite to that of reference layer 503, thus placing free layer 507 of each memory cell in a high-resistance state. Reference layer 503 is formed such that it maintains its orientation when free layer 507 is programmed. Reference layer 503 can have a more complex design, including synthetic antiferromagnetic layers and additional reference layers. For simplicity, these additional layers are omitted in the figures and discussion, and only the fixed magnetic layer primarily responsible for tunneling magnetoresistance in the cells is considered.

[0072] The threshold switching selector 502 (in the off or non-conducting state) has a high resistance until it is biased to a voltage higher than its threshold voltage or a current higher than its threshold current, and until the bias voltage of the threshold switching selector drops below Vhold (also known as "Voffset") or below Ihold current. After exceeding Vt and exceeding Vhold across the selector, the selector (in the on or conducting state) has a low resistance. The threshold switching selector remains on until the current of the selector drops below the holding current Ihold, or the voltage drops below the holding voltage Vhold. When this occurs, the threshold switching selector returns to the off (higher) resistance state. Therefore, to program a memory cell at a crossover point, a voltage or current sufficient to turn on the associated threshold switching selector and set or reset the memory cell is applied; and to read a memory cell, the threshold switching selector is activated in a similar manner by turning it on before determining the resistance state of the memory cell. One set of examples of threshold switching selectors is the bidirectional threshold switching material of a bidirectional threshold switch (OTS). Example threshold switching materials include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, GeSe, GeTe6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te, with each element having an atomic percentage ranging from a few percent to greater than 90 percent. In an embodiment, the threshold switching selector is a two-terminal device. The threshold switching selector 502 may also include an additional conductive layer at its interface with the reference layer 503. For example, a spacer 514 is depicted between the switching selector 502 and the reference layer 503. The spacer layer 514 at the interface with the reference layer 503 may be a single conductive layer or may consist of multiple conductive layers. The threshold switching selector 502 may also include an additional conductive layer at its interface with the bottom electrode 501. For example, a spacer 512 is depicted between the switching selector 502 and the reference layer 503. The spacer layer 512 at the interface with the bottom electrode 501 can be a single conductive layer or composed of multiple conductive layers. Examples of conductive layers adjacent to the OTS include carbon, carbon nitride, carbon silicide, tungsten carbide, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, etc. The threshold voltage switch has a threshold voltage (Vth) above which the resistance of the device essentially changes from insulating or quasi-insulating to conductive.

[0073] In this implementation, a current-force method is used to access the MRAM cell. The current-force method can be used to read or write the MRAM cell. In this implementation, a current-force method is used to lower the threshold voltage of the threshold switching selector in the programmable resistive memory cell. In the current-force method, the access current (e.g., I0) is used to access the MRAM cell. read I write I drive The current driver is driven through the bottom electrode 501. The current will be provided by a transistor- or resistor-based current source. In one embodiment, the current driver may be part of a row driver circuit (e.g., array driver 224) where the address of electrode 501 is selected. Alternatively, however, the current driver may be part of a column driver circuit (e.g., driver circuit 214) where the address of electrode 501 is selected. The voltage (e.g., V) will be... select ) is provided to the top electrode 511. In this document, the term "read current" (I) is used... read ) and "write current" (I write This will be used in conjunction with the access current driven through the MRAM cell (or other programmable resistive cell). The write current changes the state of the MRAM cell. As an example, a write current of approximately 30 μA for 50 ns can be used for a critical dimension (CD) of approximately 20 nanometers and a resistance (RA) of 10 Ωμm. 2 The MRAM cell is read from the P state to the AP state. If the applied time is limited (e.g., <20 ns), the read current can be approximately half the write current. A write current flowing through the MRAM cell in one direction will cause an MRAM cell in the AP state to become the P state. A write current flowing through the MRAM cell in another direction (e.g., in the read direction) will cause an MRAM cell in the P state to become the AP state. Generally, the read current is preferably set low enough and the read duration is set short enough so that the MRAM cell state does not change from P to AP or from AP to P during the read operation. Typically, the write current required to switch the MRAM state from P to AP is greater in absolute value than the write current required to switch the MRAM state from AP to P, thus providing a margin for state change before correctly sensing the bit state. When using a single value, the current value can be adjusted accordingly by the write direction or the current used from P to AP.

[0074] In some implementations, the read current may be applied in the P2AP direction or alternatively in the AP2P direction. In some implementations, the MRAM cell is read by performing an SRR (Self-Reference Read). In one implementation, the SRR has a first read (read 1 in the P2AP direction), a first write (write 1 to the AP state), and a second read (read 2 in the P2AP direction). The cell's original state can then be restored by a second write (write_back to the P state for bits initially in the P state). Alternatively, in another implementation, both the SRR read current and the destructive write current are reversed; for example, when addressing the second layer using a memory cell with the same orientation as in the first layer.

[0075] In the implementation, the voltage level of the memory cell resulting from read 1 in the P2AP direction is sensed and stored, for example, on a capacitor; or converted to digital bits by an analog-to-digital converter and stored in memory, such as in SRAM, until used in read 2. The state stored on the capacitor can be adjusted by forcibly applying a voltage to one terminal of the capacitor connected to the storage capacitor, for example, adjusting by a positive or negative 150mV. Alternatively, the level of digital storage can be adjusted by digitally adding or subtracting 150mV from the stored bit. The 150mV can be adjusted based on typical bit resistance. For example, if the resistance state of the low bit is 25K ohms and the high resistance is 50K ohms, the difference is 25K ohms. For example, if the read current is 15μA, the voltage difference between the states is 25K ohms × 15μA = 375mV, making the selection of 150mV acceptable, but perhaps 187.5mV might be more preferable.

[0076] Although the read in the P2AP direction and the destructive write to the AP state (write back to the P state after the SRR) have been described above, in an alternative implementation, the first SRR has a first read (read 1 in the AP2P direction), a destructive write to the P state (write 1), and a second read in the AP2P direction (read 2).

[0077] In one embodiment, an MRAM cell is read by applying, for example, approximately 0V to the top electrode 511 by turning on a transistor connected between the top electrode 511 and a power supply, while simultaneously driving a current of, for example, 15 microamperes (μA) through the bottom electrode 501. This read current can flow from the bottom electrode 501 to the top electrode 511. Note that the read can be read 1 or read 2 in the P2AP direction. P2AP refers to the current flow in the direction in which bits can be written from P to AP or from AP to AP. In some embodiments, a bipolar write operation is used to write data to the MRAM cell. In one embodiment, an MRAM cell is written from the AP state to the P state by applying, for example, 3V to the top electrode 511, while simultaneously driving a write current of, for example, -30μA through the bottom electrode 501. This write current flows from the top electrode 511 to the bottom electrode 501. In one embodiment, an MRAM cell is written from the P state to the AP state by applying, for example, 0V to the top electrode 511, while simultaneously driving a current of, for example, 30μA through the bottom electrode 501. The write current will flow from electrode 501 to electrode 511.

[0078] As Figure 5 An alternative to the method described above is to apply a selection voltage to the bottom electrode 501, wherein an access current is applied through the top electrode 511. In one such embodiment, an MRAM cell is read by applying, for example, 3V to the bottom electrode 501 while driving, for example, a read current of -15μA through the top electrode 511. This read current can flow from the bottom electrode 501 to the top electrode 511.

[0079] In one embodiment, an MRAM cell is written from the AP state to the P state by applying, for example, -3V to the bottom electrode 501 while driving, for example, a write current of 30μA through the top electrode 511. Electron current flows from the bottom electrode 501 to the top electrode 511. In another embodiment, an MRAM cell is written from the P state to the AP state by applying, for example, 0V to the bottom electrode 501 while driving, for example, a current of -30μA through the top electrode 511. Electron current flows from the top electrode 511 to the bottom electrode 501. The direction of the current polarity used to switch the magnetization of a bit to the P or AP state can vary based on the reference layer design and the position of the reference layer relative to the free layer.

[0080] Some biasing techniques can generate a voltage across unselected memory cells in an array, which can induce "leakage" current in these cells. While this wasted power can be mitigated to some extent by designing memory cells to have relatively high resistance levels for both high-resistance and low-resistance states when an address in the WL or BL is not selected, this overhead leakage still results in increased current consumption and power consumption, as well as additional design constraints on the memory cell and array design due to a lack of read and write margins. One way to address this unwanted current leakage is to place the selector element in series with each MRAM or other resistive (e.g., ReRAM, PCM) memory cell. For example, the select transistor can be connected in series with... Figures 4A to 4D Each resistive memory cell element is placed in series, such that memory cell 401 is now a combination of a selection transistor and a programmable resistor. This type of architecture may be referred to as 1T1R. However, using a selection transistor requires the introduction of additional control lines and cell area to enable the corresponding transistor of the selected memory cell. Additionally, the transistor will typically not scale in the same way as the write current of the resistive memory element, making the use of transistor-based selectors a limiting factor, for example, in terms of cost reduction, as the size of the memory array becomes smaller. An alternative method for selecting the transistor is to use a threshold-switching selector (e.g., threshold-switching selector 502) connected in series with a programmable resistive element. A two-terminal threshold-switching selector enables the corresponding selection transistor of the selected memory cell without the aforementioned additional control lines and additional cell area. In some embodiments, the memory system performs a read as disclosed herein to read a memory cell having a two-terminal threshold-switching selector connected in series with a programmable resistive memory element.

[0081] Figure 6A and Figure 6B An implementation scheme for incorporating a threshold switching selector into an MRAM memory array with a crosspoint architecture is illustrated. Figure 6A and Figure 6B The example shows two MRAM cells (layer 1 cell, layer 2 cell) in a two-layer crosspoint array, such as Figure 4D As shown, but in a side view. Figure 6A As depicted, maintaining the same orientation of the MRAM layers in layer 1 and layer 2 cells allows for identical manufacturing processes for each layer. The 6B features inverted memory cells, which allows the drive circuitry to operate identically; for example, BL goes low to enable P2AP reads for each layer. Figure 6A and Figure 6BThe lower first conductive line of word line 1 600, the upper first conductive line of word line 2 620, and the middle second conductive line of bit line 610 are shown. In these figures, for ease of presentation, all these lines are shown as extending from left to right across the page, but in the array of intersections, they will be as follows: Figure 4D A more precise representation, as shown in the oblique view, is that word lines or first conductive lines or wires extend in a direction parallel to the surface of the underlying substrate, and bit lines or second conductive lines or wires extend in a second direction parallel to the surface of the substrate, which is largely orthogonal to the first direction. MRAM memory cells are also represented in a simplified form, showing only the reference layer, free layer, and intermediate tunnel barrier; however, in actual implementations, the aforementioned [details omitted] will typically be included. Figure 5 Additional structures described.

[0082] An MRAM element 602, comprising a free layer 601, a tunnel barrier 603, and a reference layer 605, is formed above a threshold switching selector 609. This series combination of the MRAM element 602 and the threshold switching selector 609 forms a layer 1 cell between bit line 610 and word line 1 600. When the threshold switching selector 609 is turned on, the series combination of the MRAM element 602 and the threshold switching selector 609 operates largely as described above. However, initially, it is necessary to apply a threshold voltage V higher than that of the threshold switching selector 609. th The voltage is used to turn on the threshold switching selector 609, and then the bias current or voltage needs to be maintained high enough above the holding current or holding voltage of the threshold switching selector 609 so that the threshold switching selector remains on during subsequent read or write operations.

[0083] On the second layer, an MRAM element 612, comprising a free layer 611, a tunnel barrier 613, and a reference layer 615, is formed above a threshold switching selector 619. The MRAM element 612, in series with the threshold switching selector 619, forms a layer 2 cell between bit line 610 and word line 2 620. The layer 2 cell operates as a layer 1 cell, but the lower conductor now corresponds to bit line 610, and the upper conductor is now the word line (word line 2 620). Additional mating layers may similarly share another bit line between them, the other bit line being of the pattern WL1, BL1, WL2; WL3, BL2, WL4; or having a separate bit line in a pattern such as WL1, BL1, WL2, BL2, etc. Alternatively, a separate bit line in a pattern such as WL1, BL1, BL2, WL2.

[0084] exist Figure 6AIn one embodiment, the threshold switching selector 609 / 619 is formed below the MRAM element 602 / 612; however, in another embodiment, the threshold switching selector may be formed above one or two layers of MRAM elements. The MRAM memory cell is oriented. Figure 6A In this configuration, MRAM elements 602 and 612 have the same orientation, with free layers 601 / 611 (relative to a substrate not shown) above reference layers 605 / 615. Forming layers with the same structure between conductive lines has several advantages, particularly regarding processing, since each of the two layers, as well as subsequent layers in embodiments with more layers, can be formed according to the same processing sequence.

[0085] Figure 6B Examples similar to Figure 6A Alternative implementation schemes for the layout, besides reversing the positions of the reference layer and the free layer in layer 2 unit, include, more specifically, arrangements between word line 1 650 and bit line 660, such as... Figure 6A In the middle, layer unit 1 includes an MRAM element having a free layer 651 formed above a tunnel barrier 653, which in turn is formed above a reference layer 655, wherein the MRAM element 652 is formed above a threshold switching selector 659. Figure 6B The second layer of the implementation also has an MRAM element 662, which is formed above the threshold switching selector 669, between bit line 660 and word line 2 670, but relative to... Figure 6A MRAM element 662 is inverted, such that reference layer 661 is now formed above tunnel barrier 663 and free layer 665 is now located below tunnel barrier 663. Alternatively, the configuration of MRAM element 662 can be used in layer 1 cells, and the configuration of MRAM cell 652 can be used in layer 2 cells.

[0086] although Figure 6B Implementation schemes require different processing sequences to form layers, but may have advantages in some implementation schemes. In particular, the orientation of the MRAM structure can make... Figure 6BThe implementation is attractive because when writing or reading in the same direction (relative to the reference layer and free layer), the bit lines will be biased identically for both the lower and upper layers, and the two word lines will be biased identically. For example, if both layer 1 memory cells and layer 2 memory cells are sensed in the P2AP direction (relative to the reference layer and free layer), bit line layer 660 will be biased as in the P2AP direction, with bit line 660 biased at a low voltage level (e.g., 0V) for both the upper and lower cells, while word line 1 650 and word line 2 670 are biased at a higher voltage level. Similarly, regarding writing, for writing to a high-resistance AP state, bit line 660 is biased at a low voltage level (e.g., 0V) for both the upper and lower cells, while word line 1 650 and word line 2 670 are biased at a higher voltage level.

[0087] Reading or writing data to an MRAM memory cell involves passing current through the memory cell. In an embodiment where a threshold switching selector is placed in series with an MRAM element, the threshold switching selector can be turned on by applying a sufficient voltage across the series combination of the threshold switching selector and the MRAM element and applying current through the series combination before current can pass through the MRAM element.

[0088] Figure 7A An implementation of a memory array 700 with a cross-point architecture is depicted. The memory array 700 may be contained within... Figure 2 or Figure 3 In the memory structure 202, array 700 has a set of first conductive lines 706a to 706h and a set of second conductive lines 708a to 708d. In one embodiment, the set of first conductive lines 706a to 706h is a word line, and the set of second conductive lines 708a to 708d is a bit line. For ease of discussion, the set of first conductive lines 706a to 706h may be referred to as a word line, and the set of second conductive lines 708a to 708d may be referred to as a bit line. However, the set of first conductive lines 706a to 706h can be a bit line, and the set of second conductive lines 708a to 708d can be a word line.

[0089] The memory array 700 has a plurality of programmable resistive memory cells 401. Each memory cell 401 is connected between a first conductive line in the first conductive line 706 and a second conductive line in the second conductive line 708 (e.g., at the intersection of the first conductive line in the first conductive line 706 and the second conductive line in the second conductive line 708). Each memory cell has a programmable resistive memory element 702 connected in series with a threshold switching selector 502. In one embodiment, the programmable resistive memory element includes a magnetoresistive random access memory (MRAM) element. The threshold switching selector 502 is configured to become conductive with a lower resistance in response to an applied voltage level exceeding a threshold voltage of the threshold switching selector 502, and to remain conductive with a lower resistance until the current through the switching selector 502 decreases below the selector holding current Ihold. The threshold switching selector 502 may be a two-terminal device. In an embodiment, the threshold switching selector 502 includes an OTS.

[0090] A technique for reducing the threshold voltage of a threshold switching selector 502 while simultaneously tuning a series resistor to mitigate damage to a programmable resistive memory element 702 is disclosed. The reduction of the threshold voltage of the threshold switching selector 502 may include, but is not limited to, a first excitation operation, a formation operation, or a cold start operation. For discussion purposes, a memory cell 401a is selected to reduce the threshold voltage of the threshold switching selector 502. The selected memory cell 401a is located at the intersection of a selected word line 706g and a selected bit line 708b. A selected memory cell refers to a memory cell selected for memory operations such as first excitation, formation, cold start, read, or write. The selected memory cell is connected between the selected word line and the selected bit line. In an embodiment, to reduce the threshold voltage of the threshold switching selector 502 in the selected memory cell 401, a selection voltage such as proximity to ground is provided to the selected bit line (e.g., bit line 708b), and a threshold voltage reduction voltage (Vs) is applied to the selected word line (e.g., word line 706g). A selected word line refers to a word line connected to at least one selected memory cell. Alternatively, a memory cell can be selected by applying a voltage (Vs) to the select positioning line and a selection voltage to the select word line simultaneously. The threshold voltage reduction voltage (Vs) may include, but is not limited to, a first activation voltage, a formation (also known as aging) voltage, or a voltage used for cold start operation.

[0091] In one method, word lines not connected to selected memory cells can be driven by a voltage approximately half the value of Vs. For example... Figure 7AThe word lines 706a, 706b, 706c, 706d, 706e, 706f, and 706h each have a voltage applied to them called a half-select voltage (Vs / 2). The half-select voltage (Vs / 2) has a value approximately half that of the threshold voltage reduction voltage (Vs).

[0092] In one approach, bit lines not connected to selected memory cells can be driven by a voltage approximately half the value of Vs. For example... Figure 7A As depicted, bit lines 708a, 708c, and 708d each have a voltage applied to them called a half-select voltage (Vs / 2). As mentioned above, the half-select voltage (Vs / 2) has a value approximately half that of Vs.

[0093] Some memory cells connected to the selected word line are referred to herein as half-selected memory cells. The voltage across a half-selected memory cell is approximately half the voltage across the selected memory cell. Each half-selected memory cell 401b connected to the selected word line has a Vs applied to the selected word line and a Vs / 2 applied to its corresponding bit line. Therefore, each half-selected memory cell 401b has a Vs / 2 applied across it.

[0094] Some of the memory cells connected to the select line are referred to herein as semi-selected memory cells. The voltage across these semi-selected memory cells is approximately half the voltage across the selected memory cells. Each semi-selected memory cell 401c connected to the select line has 0V applied to the select line and Vs / 2 applied to its corresponding word line. Therefore, each semi-selected memory cell 401c has Vs / 2 applied across its memory cell.

[0095] Other memory cells were not selected at all, meaning they had approximately 0V across their terminals. Figure 7A The text indicates several completely unselected memory cells 401d. In this example, each completely unselected memory cell 401d has a Vs / 2 applied to its word line and a Vs / 2 applied to its bit line. Even if the threshold voltage of the threshold switching selector 502 is slightly below the target Vth range, the threshold switching selector 502 for the completely unselected memory cell 401d will not be turned on.

[0096] exist Figure 7A In one example, there are more word lines than word lines in the cross-point array. In another embodiment, there are more bit lines than word lines in the cross-point array. In yet another embodiment, the number of bit lines in the cross-point array equals the number of word lines. Figure 7AIn the example, the number of word lines in the cross-point array is twice the number of bit lines; however, different ratios can be used. This allows for different tile sizes. For example, a tile can have 1024 BLs × 2048 WLs, which can be configured into a module with 2048 × 4096 cells by center-driving the WLs and BLs between four tiles. In one implementation, a set of memory cells is read, for example, by selecting a memory cell in each of several tiles. In some implementations, more than one memory cell from a tile can be selected for reading.

[0097] In one embodiment, the memory system applies a threshold voltage reduction voltage (Vs) to gradually reduce the threshold voltage of the threshold switching selector 502 over several formation cycles. For at least some of the formation cycles, the magnitude of the voltage Vs is reduced. In another embodiment, as the voltage Vs decreases, the memory system gradually reduces the resistance of one or more transistors connected in series with the selected memory cell.

[0098] In some implementations, voltage-force techniques are used to access memory cells in a crosspoint memory array. In other implementations, current-force methods are used to access memory cells in a crosspoint memory array. Figure 7B An implementation of a memory array 700 with a cross-point architecture using a current-force method is depicted. The memory array 700 and memory cells are similar to... Figure 7A A memory array and memory cell. To select memory cell 401a, a selection voltage (V) close to ground is applied. select_BL ) is provided to the selected bit line (e.g., bit line 708b), and the access current (I) is provided. access An access current is driven (or forcibly applied) to a selected word line (e.g., word line 706g). The access current charges the voltage on the selected word line 706g. There are limitations on how high the voltage on the selected word line 706g can reach (e.g., compliance voltage). In one embodiment, it is assumed that an IL is applied to the selected word line at a compliance voltage sufficient relative to the BL voltage. access Then V select_BL The value is sufficient to activate the threshold switching selector 502 in the selected memory cell. For example, V select_BL It can be approximately 0V. On the other hand, V unsel_BL The value is such that the threshold switching selector 502 in the unselected memory cell will not be turned on. For example, if the positive power supply is 3.3V, then V unsel_BL It can be approximately 1.65V. After the OTS is turned on, the drive access current (I) accessThe access current flows through at least a portion of the selected word line 706g. This access current can also flow through the selected memory cell 401a and into a portion of the select positioning line 708b after the OTS is turned on. Such a selected WL can be driven high at 15μA for reading or high at 30μA for writing, for example, by a current source having a compliant voltage of, for example, 3.3V. For writing with the opposite polarity, for example, -30μA is forced onto the selected word line, and the select positioning line is brought close to 3.3V.

[0099] Unselected word lines and bit lines are referred to as unselected word lines or unselected bit lines, respectively. In one embodiment, a word line or bit line can be deselected by forcing it to an unselected voltage (such as Vmid, e.g., 1.65V) at approximately half the drive compliance voltage; for example, the drive compliance voltage is 3.3V. The unselected voltage (Vmid) unsel_BL This is provided to unselected bit lines (e.g., bit lines 708a, 708c, 708d). An unselected voltage, such as Vmid, is provided to unselected word lines (e.g., word lines 706a, 706b, 706c, 706d, 706e, 706f, and 706h). access Selected word lines (and selected position lines) can flow in any direction. In one implementation, no current is forced through unselected word lines except for leakage (e.g., 706a, 706b, 706c, 706d, 706e, 706f, and 706h).

[0100] Figure 8This is a schematic diagram illustrating a resistor along a path that provides voltage across programmable resistive memory cell 401. Path 800 includes programmable resistive memory cell 401, bit lines, word lines, and several transistors. The transistors may include transistors in circuitry commonly referred to as drivers and / or decoders. For example, transistors may reside in row drivers, row decoders, column drivers, and / or column decoders. Thus, transistors may include decoder transistors, including but not limited to global word line decoder transistors, local word line decoder transistors, global bit line decoder transistors, and / or local bit line decoder transistors. Path 800 therefore includes a series resistance of programmable resistive memory cell 401, bit line and word line resistors 802, and transistor resistor 804. A voltage (V) is applied across the series combination of programmable resistive memory cell 401, bit lines, word lines, and transistors. This voltage V can be used to lower the threshold voltage of threshold switching selector 502 in memory cell 401. This voltage should have a sufficient magnitude to turn on threshold switching selector 502. The voltage across programmable resistive memory element 702 is referred to as V_Memory Element. The voltage across the threshold switching selector 502 is called V_Threshold SwitchingSelector. The voltage across the combination of the bit line and word line is called V_BL / WL. The voltage across the transistor is called V_Transistors. In an implementation, when the threshold voltage of the threshold switching selector 502 is lowered, the resistance of the transistor is increased, thereby increasing V_Transistors and decreasing V_Memory Element. Decreasing V_Memory Element when a voltage is applied to lower the threshold voltage of the threshold switching selector 502 mitigates potential damage to the programmable resistive memory element 702.

[0101] Before threshold switching selector 502 is turned on, its resistance may be much larger than that of other components in the path, causing most of the voltage to appear across threshold switching selector 502. When threshold switching selector 502 is turned on, its resistance drops significantly. As an example, for the purposes of discussion, the resistance of threshold switching selector 502 may be approximately 1 GΩ when it is off and approximately 100 kΩ when it is on. The resistance of programmable resistor memory element 702 may be approximately 70 kΩ when in AP state. BL / WL resistor 802 is typically very small relative to cell resistor 401. For example, BL / WL resistor 802 may be in the range of 5 kΩ to 15 kΩ, but this may vary depending on the location of the memory cell in the array. Transistor resistor 804 may also be quite low relative to cell resistance. For example, transistor resistor 804 may be in the range of 1 kΩ to 10 kΩ. As will be explained in more detail below, when the threshold voltage of the threshold switching selector decreases, the transistor resistor 804 can be increased to avoid damage to the programmable resistor memory element 702.

[0102] When the threshold switching selector 502 is turned on, its resistance drops significantly, which can lead to rebound current. Rebound current can potentially damage the programmable resistive memory element 702. In an embodiment, the transistor resistor 804 is tuned to mitigate potential damage to the programmable resistive memory element 702 due to rebound current. In an embodiment, the memory system increases the resistance of at least one transistor to significantly increase transistor resistance 804, which mitigates potential damage to the programmable resistive memory element 702 due to rebound current. For example, transistor resistance 804 can be increased to approximately 200 kΩ, but this is only one example.

[0103] Figure 9These are diagrams illustrating the bounce events of the first trigger operation and the normal read operation. Plot 910 shows the bounce event for the first trigger operation. Plot 920 shows the bounce event for the normal read operation. Each plot 910, 920 shows the relationship between current and voltage across the threshold switching selector (note that the current is on a logarithmic scale). Plot 910 shows the threshold switching selector 502 turned on at the "first trigger" voltage Vff. After the threshold switching selector 502 is turned on, the voltage across it drops rapidly to a voltage called Voffset. As an example, Voffset can be approximately 1.8V. The current can rise sharply when the threshold switching selector 502 is turned on. Plot 920 shows the threshold switching selector 502 turned on at the "normal operation threshold" voltage Vop. After the threshold switching selector 502 is turned on, the voltage across it drops rapidly to Voffset. Similarly, the current can rise sharply when the threshold switching selector 502 is turned on.

[0104] Figure 10 An example of rebound current in response to the switching on of threshold selector 502 is shown. Plot 1000 shows the current versus time. The current is very low before threshold selector 502 is switched on at t1. At t1, threshold selector 502 is switched on, resulting in a large current spike. The current decays to a stable level (I_stable) over a period of time, which can depend on the RC time constant of the circuitry in the path where the memory cell resides.

[0105] As noted, potential damage to the programmable resistive memory element 702 can be mitigated by tuning the resistance of the transistor in the path providing the voltage across memory cell 401. The following examples will be used to illustrate this. First, an example of a resistor without a tuned transistor will be discussed, followed by an example of a resistor with a tuned transistor. Return to Reference Figure 8The voltage V can be 4V. After the threshold switching selector 502 is turned on, the voltage (Voffset) across the threshold switching selector can be 1.8V, leaving approximately 2.2V across other components in path 800. Assuming the resistance of memory element 702 is 70kΩ, the BL / WL resistance is 5kΩ, and the transistor resistance is 2kΩ, then V_Memory Element is approximately 2V, V_BL / WL is approximately 0.14V, and V_Transistors is approximately 0.06V. However, assuming the transistor resistance is increased to approximately 200kΩ, then V_Memory Element is approximately 0.56V, V_BL / WL is approximately 0.04V, and V_Transistors is approximately 1.6V. Therefore, increasing the transistor resistance reduces the voltage across programmable resistive memory element 702 from approximately 2V to approximately 0.56V, which essentially reduces the stress on programmable resistive memory element 702, thereby mitigating damage to programmable resistive memory element 702.

[0106] Figure 11 This is a diagram illustrating one embodiment of a circuit that provides voltage across programmable resistive memory cell 401 to reduce the threshold voltage of threshold switching selector 502. This circuit can be used for operations including, but not limited to, first excitation, formation, and / or cold start. Figure 11A path including a first CMOS driver 1102, a first conductive line 1106, a programmable resistive memory cell 401, a second conductive line 1108, and a second CMOS driver 1104 is shown. The memory cell 401 resides in a cross-point memory array. Either the first conductive line 1106 or the second conductive line 1108 can be a word line, while the other conductive line is a bit line. The first CMOS driver 1102 includes a first decoder circuit 1132, which may include one or more transistors. The first CMOS driver 1102 may include transistors other than the one or more transistors in the first decoder circuit 1132. The first CMOS driver 1102 selects and drives the first conductive line 1106. The first CMOS driver 1102 may drive current or voltage to the first conductive line 1106. The second CMOS driver 1104 includes a second decoder circuit 1134, which may include one or more transistors. The second CMOS driver 1104 may include transistors other than the one or more transistors in the second decoder circuit 1134. The second CMOS driver 1104 selects and drives the second conductive line 1108. The second CMOS driver 1104 can drive current or voltage to the second conductor 1108. Voltage V1 can be higher or lower than voltage V2. A resistance control signal is provided to the first CMOS driver 1102 to control the resistance of the first CMOS driver 1102. In one embodiment, the resistance control signal is a voltage applied to the control gate of a transistor in the first CMOS driver 1102. In another embodiment, the resistance control signal is a voltage applied to the control gate of a transistor in the decoder circuit 1132. The magnitude of the voltage controls the resistance of the transistor. In one embodiment, the magnitude of the resistance control signal is sufficient to turn on the transistor, allowing it to transmit signals (e.g., current, voltage), select lines in the array, etc. In one embodiment, the transistor is a decoder transistor that selects the first conductor from other similar conductors. For example, the decoder transistor could be a local word line decoder transistor that selects word lines in the array. As another example, the decoder transistor could be a local bit line decoder transistor that selects bit lines in the array. However, it is not required that the transistor be a local word line (or local bit line) decoder transistor.

[0107] Figure 12This is a schematic diagram of one embodiment of a path including a programmable resistive memory cell 401 connected in series with word lines, bit lines, and several transistors. The path includes a current source 1202, word line decoder transistors (T3P, T1P), a word line (WL), memory cell 401, a bit line (BL), and bit line decoder transistors (T1N, T3N). In one embodiment, the word line decoder transistors (T3P, T1P) reside in decoder circuit 1132, and in one embodiment, the bit line decoder transistors (T1N, T3N) reside in decoder circuit 1134. Alternatively, in one embodiment, the word line decoder transistors (T3P, T1P) reside in decoder circuit 1134, while in one embodiment, the bit line decoder transistors (T1N, T3N) reside in decoder circuit 1132. The path has a positive power supply Vp, such as approximately 3.3V. The current source 1202 is connected to the power supply (Vp) and supplies a drive current I_Drive that can be used to charge the word lines. The maximum possible voltage achievable on the word line is Vp minus the voltage appearing across current source 1202 and transistors T1, T3P, and T1N. The resistance of one or more of the transistors can be tuned to mitigate potential damage to memory element 702 during operation that lowers the threshold voltage of threshold switching selector 502. In an embodiment, the magnitude of the control gate voltage to one or more of T3P, T1P, T1N, and / or T3N is used to control the resistance of the corresponding transistors T3P, T1P, T1N, and / or T3N to mitigate potential damage to memory element 702. During this operation, all transistors in the path are turned on to select memory cell 401 and provide the target voltage across memory cell 401.

[0108] Current can be enabled by pulling Read* low to turn on transistor T1. The output of T1 (as node VXSP) also drives the non-inverting input (+) of differential sense amplifier 1206. Differential sense amplifier 1206 can be used to sense the resistance of memory cell 401, but sensing of memory cell 401 is not required for threshold voltage reduction operations such as first excitation, formation, or cold start. A reference voltage (Vref) is provided to the inverting input (-) of differential sense amplifier 1206. For global reference reads, Vref is the global reference voltage. For SRR, Vref is derived from previous sensing operations, for example, by increasing the voltage from read 1 by 150mV.

[0109] P-channel transistor T3P acts as a global WL decoder, which can be selected when the gate of T3P is low (such as when driven by the decoder address signal SVXP*). P-channel transistor T1P acts as a local WL decoder, which can be selected when the gate of T1P is low (such as when driven by the decoder address signal RDEC*). P-channel transistor T3P can act as a driver for the selected WL. The decoder address signal is SVXP*, which is active low in this example, such that when SVXP* is low, T3P will be turned on and Tx will be turned off. However, when SVXP* is high, T3P will be turned off and Tx will be turned on, thus providing Vmid to the word line. The decoder address signal is RDEC*, which is active low in this example, such that when RDEC* is low, T1P will be turned on. In an implementation, the magnitude of the decoder address signal SVXP* is used to control the resistance of T3P to mitigate potential damage to memory element 702. The value of the decoder address signal SVXP* can be set to an appropriate level to turn on T3P (with Tx off and T1P on) to select the word line (WL). Alternatively, the value of the decoder address signal RDEC* can be used to control the resistance of T1P to mitigate potential damage to memory element 702. The value of the decoder address signal RDEC* will be set to an appropriate level to select the word line WL, while simultaneously establishing the required resistance in T1P.

[0110] Memory cell 401 is connected between WL and BL. The memory cell (or bit) has a threshold switching selector 502 and a memory element 702. The selected WL can be one of N WLs in an array. The BL can be one of M BLs in an array. Memory cell 401 can reside at the intersection of WL and BL on a chip having one or more arrays. An N-channel transistor T1N can act as a local decoder driver to BL. BL can be selected when the gate of T1N is high (e.g., when driven by the decoder address signal T1N_S). An N-channel transistor T3N can act as a global decoder, which is selected when the gate of T3N is high (e.g., when driven by the decoder address signal T3N_S). The output of T3N is VYS. The driver (YEN) is located between VYS and a negative (i.e., negative relative to Vp) power supply (GND).

[0111] In one implementation, the magnitude of the decoder address signal T1N_S is used to control the resistance of T1N to mitigate potential damage to memory element 702. The magnitude of the decoder address signal T1N_S can be at an appropriate level to turn on T1N (where T3N is also turned on) to select the bit line (BL). Alternatively, the magnitude of the decoder address signal T3N_S is used to control the resistance of T3N to mitigate potential damage to memory element 702. The magnitude of the decoder address signal T3N_S will be at an appropriate level to select the bit line BL, while simultaneously establishing the required resistance in T3N.

[0112] In one implementation, the path operates as follows. Nodes VXSP, Selected WL, Selected BL, and VYS can be transistors pre-charged to Vmid during the standby phase. The desired WL line (one of N WL lines) can be selected by disconnecting the precharge and applying a low voltage (the gate voltage is called the decoder address signal) to the gates of transistors T3P and T1P. The BL line can be selected by disconnecting the precharge and applying a high voltage (the gate voltage is called the decoder address signal) to the gates of transistors T1N and T3N. The gate of transistor YEN can be pulled high to connect node VYS to GND. I_drive can then be turned on and connected to VXSP by pulling the gate of T1 low (e.g., Read* goes low). Thus, by YEN going H, the active driver of BL can quickly pull BL to GND upon turn-on. The selected WL and VXSP rise to Vp via I_drive.

[0113] Threshold switching selector 502 is turned on when the voltage across it reaches its current threshold voltage. During the first activation operation, this will be for Vff (see...). Figure 9 During the formation operation, the threshold voltage of the threshold switching selector 502 can be any value between Vop and Vff (see [link]). Figure 9 When threshold switching selector 502 is turned on, the voltage across threshold switching selector 502 drops to Voffset (see [link]). Figure 9 When the threshold switching selector 502 is turned on, a rebound current is generated due to the drop in voltage on the word line. Furthermore, when the voltage across the threshold switching selector 502 drops, the voltage across the memory element 702 may rise significantly. However, by establishing that the resistance of one or more of T3P, T1P, T1N, and / or T3N is higher than the nominal resistance (the resistance used when sensing the memory cell 401 with the sense amplifier 1206), a significant voltage will appear across transistors T3P, T1P, T1N, and / or T3N after the threshold switching selector 502 is turned on, thereby reducing the voltage across the memory element 702.

[0114] Figure 13 This is a schematic diagram of one embodiment of a programmable resistive memory cell 401 connected in series with word lines, bit lines, and several transistors. The read path includes a current source 1302, word line decoder transistors (T6N, T4N), a word line (WL), memory cell 401, a bit line (BL), and bit line decoder transistors (T4P, T6P). In one embodiment, the word line decoder transistors (T6N, T4N) reside in decoder circuit 1132, and in one embodiment, the bit line decoder transistors (T4P, T6P) reside in decoder circuit 1134. Alternatively, in one embodiment, the word line decoder transistors (T6N, T4N) reside in decoder circuit 1134, while in one embodiment, the bit line decoder transistors (T4P, T6P) reside in decoder circuit 1132. The read path has a positive power supply, such as approximately 3.3V, connected to transistor YEP. Current source 1302 is grounded and supplies I_Drive to the memory cell (current flows from the bit line to the word line when threshold switching selector 502 is on). Current can be enabled by pulling Read* low to turn on transistor T1. The output of T1 (as node VXSN) also drives the non-inverting input (+) of differential sense amplifier 1206. A reference voltage (Vref) is provided to the inverting input (-) of differential sense amplifier 1206. For global reference reads, Vref is the global reference voltage. For SRR, Vref is derived from previous sensing operations, for example, by increasing the voltage from read 1 by 150mV.

[0115] The N-channel transistor T6N acts as a global WL decoder, which can be selected when its gate is high (e.g., when driven by the decoder address signal SVXN). The N-channel transistor T4N acts as a local WL decoder, which can be selected when its gate is high (e.g., when driven by the decoder address signal RDEC). The N-channel transistor T6N can also act as a driver for the selected WL. The decoder address signal is SVXN, which is active high in this example, such that when SVXN is high, T6N will be turned on and T5 will be turned off. However, when SVXN is low, T6N will be turned off and T5 will be turned on, thus providing Vmid to the word line. The decoder address signal is RDEC, which is active high in this example, such that when RDEC is high, T4N will be turned on.

[0116] Memory cell 401 is similar to a combination Figure 12The described unit. BL can be selected when the gate of T4P is low (such as when driven by the decoder address signal T4P_S*). The P-channel transistor T6P can act as a global bitline decoder, which is selected when the gate of T6P is low (such as when driven by the decoder address signal T6P_S*). The output of T6P is VYS. The driver (YEP) is located between VYS and the positive supply (Vp), which can be approximately 3.3V. The operation of this path is similar to that of a combination. Figure 12 The described path. Therefore, a detailed description will be omitted.

[0117] Figure 13 The resistance of one or more transistors in the transistor path can be tuned to mitigate potential damage to memory element 702 during operation that lowers the threshold voltage of threshold switching selector 502. In an embodiment, the magnitude of the control gate voltage to one or more of T6N, T4N, T4P, and / or T6P is used to control the resistance of the corresponding transistors T6N, T4N, T4P, and / or T6P to mitigate potential damage to memory element 702. During this operation, all transistors in the path are turned on to select memory cell 401 and provide the target voltage across memory cell 401.

[0118] In one implementation, the magnitude of the decoder address signal SVXN is used to control the resistance of T6N to mitigate potential damage to memory element 702. The magnitude of the decoder address signal SVXN can be set to an appropriate level such that T6N is turned on (with T5 off and T4N on) to select the word line (WL). Alternatively, the magnitude of the decoder address signal RDEC is used to control the resistance of T4N to mitigate potential damage to memory element 702. The magnitude of the decoder address signal RDEC will be set to an appropriate level to select the word line WL while simultaneously establishing a target resistance in T4N.

[0119] In one implementation, the value of the decoder address signal T4P_S* is used to control the resistance of T4P to mitigate potential damage to memory element 702. The value of the decoder address signal T4P_S* can be at an appropriate level to turn on T4P (where T6P is also turned on) to select the bit line (BL). Alternatively, the value of the decoder address signal T6P_S* is used to control the resistance of T6P to mitigate potential damage to memory element 702. The value of the decoder address signal T6P_S* will be at an appropriate level to select the bit line BL, while simultaneously establishing a target resistance in T6P.

[0120] Figure 14This is a flowchart of one embodiment of a process 1400 for mitigating damage to the programmable resistive memory cell 401 while reducing the threshold voltage of the threshold switching selector 502 in the memory cell 401. Step 1402 includes: establishing the resistance of one or more transistors connected in series with the memory cell 401 as a first resistance for reducing the threshold voltage of the threshold switching selector 502 in the programmable resistive memory cell 401.

[0121] Step 1404 includes: applying a voltage across the programmable resistor memory cell 401 using a transistor located in the first resistor to reduce the threshold voltage of the threshold switching selector 502 in the programmable resistor memory cell 401.

[0122] Step 1406 is to determine whether to perform a further reduction of the threshold voltage of the threshold switching selector 502. In one embodiment, steps 1402 and 1404 are performed in a cold start operation, wherein no further reduction of the threshold voltage of the threshold switching selector 502 is required after the first cycle. In one embodiment, steps 1402 and 1404 are performed in a first activation operation, wherein no further reduction of the threshold voltage of the threshold switching selector 502 is required after the first cycle. However, steps 1402 and 1404 may be performed in a formation operation, wherein steps 1402 and 1404 may be repeated several times. When repeating steps 1402 and 1404, one option is to gradually use a lower resistance of the transistor as the voltage applied across memory cell 401 decreases. The execution of steps 1402 and 1404 may end when the threshold voltage of the threshold switching selector 502 has been reduced to the desired level (e.g., Vop).

[0123] A dashed line exists between steps 1406 and 1408 to indicate that a considerable amount of time may pass between steps 1406 and 1408. For example, if steps 1402 and 1404 are used for the first excitation and / or formation, a considerable amount of time may pass between steps 1406 and 1408. However, if steps 1402 and 1404 are used for a cold start operation, step 1408 can be performed without requiring a considerable amount of time.

[0124] Step 1408 includes: establishing the resistance of one or more transistors connected in series with memory cell 401 as a second resistance for sensing programmable resistive memory cell 401. The second resistance is lower than the first resistance.

[0125] Step 1410 includes: applying a voltage across the programmable resistive memory cell 401 using a transistor located in the second resistor to sense the programmable resistive memory cell 401. Step 1410 may include: using a sensing amplifier (e.g., sensing amplifier 1206) to sense the memory cell 401. In one embodiment, sensing amplifier 1206 is used to sense the voltage at node VXSP (see [link to relevant documentation]). Figure 12 and Figure 13 ).

[0126] Figure 15 This is a flowchart of one embodiment of process 1500, which mitigates damage to programmable resistive memory cell 401 during the formation process while simultaneously reducing the threshold voltage of the threshold switching selector of memory cell 401. Memory cell 401 may reside in a crosspoint array. Process 1500 provides further details of an embodiment of process 1400. Process 1500 can be used to reduce the threshold voltage of a bidirectional threshold switch (OTS). Other types of threshold switching selectors can have their threshold voltage reduced by performing process 1500. Programmable resistive memory cell 401 has a programmable resistive memory element 702 connected in series with threshold switching selector 502. Examples of programmable resistive memory elements include, but are not limited to, MRAM, ReRAM, PCM (phase-change memory), and FeRAM. Reference will be made when discussing process 1500. Figure 7A The crossbar array 700 in the middle.

[0127] Step 1502 includes setting an initial value for the formation voltage. A formation voltage is applied across the selected memory cells(s) to be formed. In an embodiment, the initial value of the formation voltage is greater than the maximum expected initial threshold voltage (e.g., Vff) of the threshold switching selector 502. An example of the initial value of the formation voltage is approximately 4.2V, but this value may vary depending on the characteristics of the threshold switching selector 502. Step 1504 includes setting an initial value for the control gate voltage of the decoder transistor for a maximum resistance. This maximum resistance refers to the highest resistance used in process 1500, at which the decoder transistor will be turned on, making it available for selecting a word line or a bit line. In an embodiment, the decoder transistor is a "global decoder transistor." In an embodiment, the decoder transistor is a "local decoder transistor." However, the decoder transistor is not limited to being a global or local decoder transistor. In an embodiment, the control gate voltage is a decoder address signal.

[0128] Process 1500 will be described using an example of a memory cell 401 in a single-selection crosspoint array. For ease of explanation, steps 1506 to 1512 are described in a specific order. Steps 1506 to 1512 may occur in a different order and / or some of these steps may be performed simultaneously. Step 1506 includes: grounding the selected bit line. For example, applying 0V to bit line 708b. Step 1508 includes: applying a half-select voltage Vs / 2 to the half-selected word lines. For example, applying Vs / 2 to word lines 706a, 706b, 706c, 706d, 706e, 706f, and 706h. Step 1510 includes: applying a half-select voltage Vs / 2 to the half-selected bit lines. For example, applying Vs / 2 to bit lines 708a, 708c, and 708d. Step 1512 includes: applying a forming voltage to the selected word lines. In one embodiment, Figure 7A Vs in the equation is the formation voltage. For example, Vs is applied to word line 706g. Step 1512 also includes applying a voltage to the control gate of the decoder transistor to establish a target resistance in the decoder transistor. An example range for the duration of the formation voltage is 10 nanoseconds (ns) to 100 ns. However, the duration of the formation voltage may be longer or shorter than this example range. In an embodiment, the formation voltage is applied to one end of a selected memory cell, wherein the other end of the selected memory cell is grounded.

[0129] Step 1514 includes determining whether to perform additional forming on the cell. In step 1514, the memory system may test the threshold voltage of the memory cell to determine whether the threshold voltage has reached a target level. When testing the Vt of the memory cell, the resistance of the decoder transistor may be established at a lower resistance than that used in step 1512. For example, the resistance of the decoder transistor may be established at a nominal level used during sensing during a read operation. An example range for the target level is between 2V and 3V, but the target level may be lower or higher than this range. It is not required to test the threshold voltage for each iteration. Instead, the memory system may apply a forming voltage several times between each threshold voltage test.

[0130] Step 1516 may optionally reduce the formation voltage. In one embodiment, the memory system applies a formation voltage of the current magnitude to the selected memory cell a predetermined number of times. The memory system may change the polarity of the formation signal in a subsequent application. For example, in one iteration of steps 1508 to 1512, the formation voltage may result in a positive voltage from the word line to the bit line, and in another iteration of steps 1508 to 1512, the formation voltage may result in a negative voltage from the word line to the bit line. Step 1516 may include reducing the magnitude of the formation voltage. As an example, the magnitude of the formation voltage may be reduced by 100mV. The magnitude of the half-select voltage is also reduced accordingly, such that the half-select voltage is maintained at Vs / 2.

[0131] Step 1518 includes: optionally changing the magnitude of the control gate voltage of the decoder transistor to reduce the resistance of the decoder transistor. In an embodiment, the resistance of the decoder transistor is reduced in response to reducing the magnitude of the forming voltage. After step 1518, the memory system again executes steps 1508 to 1512.

[0132] Figure 16 This is a flowchart of one embodiment of process 1600, which mitigates damage to programmable resistive memory cell 401 while reducing the threshold voltage of the threshold switching selector of memory cell 401 during the formation process using a current-force method to provide the formation voltage. Process 1600 provides further details of an embodiment of process 1400. Process 1600 can be used to reduce the threshold voltage of a bidirectional threshold switch (OTS). Other types of threshold switching selectors can have their threshold voltage reduced by performing process 1600. Programmable resistive memory cell 401 has a programmable resistive memory element 702 connected in series with threshold switching selector 502. Examples of programmable resistive memory elements include, but are not limited to, MRAM, ReRAM, PCM (phase-change memory), and FeRAM. Reference will be made when discussing process 1500. Figure 7B The crossbar array 700 in the middle.

[0133] Step 1602 includes setting an initial value for a voltage limit of the formed voltage, which is caused by a current applied to the selected word line. In an embodiment, the initial value of the formed voltage is greater than the maximum expected initial Vth of the threshold switching selector 502. An example of the initial voltage limit of the formed voltage is approximately 4.2V, but this value may vary depending on the characteristics of the threshold switching selector 502.

[0134] Step 1604 involves setting an initial value for the control gate voltage of the decoder transistor for the highest resistance. This highest resistance refers to the highest resistance used in process 1600, at which the decoder transistor will be turned on, making it available for selecting a word line or bit line. In some embodiments, the decoder transistor is a "global decoder transistor." In other embodiments, the decoder transistor is a "local decoder transistor." However, the decoder transistor is not limited to being a global or local decoder transistor. In some embodiments, the control gate voltage is a decoder address signal.

[0135] Process 1600 will be described using an example of selecting one memory cell 401 in a crossbar array. For ease of explanation, steps 1606 through 1612 are described in a specific order. Steps 1606 through 1612 may occur in a different order and / or some of these steps may be performed simultaneously. Step 1606 includes: grounding the selected bit line. For example, applying 0V to bit line 708b. Step 1608 includes: applying a half-select voltage Vs / 2 to the half-selected word lines. For example, applying Vs / 2 to word lines 706a, 706b, 706c, 706d, 706e, 706f, and 706h. Step 1610 includes: applying a half-select voltage Vs / 2 to the half-selected bit lines. For example, applying Vs / 2 to bit lines 708a, 708c, and 708d. Step 1612 includes: driving (forcing) current to the selected word line. For example, current is driven to word line 706g. Step 1612 further includes: applying a voltage to the control gate of the decoder transistor to establish a target resistance in the decoder transistor.

[0136] Step 1614 includes determining whether to perform additional forming on the cell. In step 1614, the memory system may test the threshold voltage of the memory cell to determine whether the threshold voltage has reached a target level. When testing the Vt of the memory cell, the resistor of the decoder transistor may be set to a lower resistance than the resistor used in step 1512. An example range for the target level is between 2V and 3V, but the target level may be lower or higher than this range. It is not required to test the threshold voltage in every iteration.

[0137] Step 1616 is optionally to reduce the voltage limit. The memory system can change the polarity of the current in the next application. For example, one iteration of steps 1608 to 1612 can result in a positive voltage from the word line to the bit line, and another iteration of steps 1608 to 1612 can result in a negative voltage from the word line to the bit line. Step 1616 may include reducing the voltage limit by an amount. As an example, the voltage limit may be reduced by 100mV. The half-select voltage is also reduced accordingly, such that the half-select voltage is maintained at Vs / 2.

[0138] Step 1618 includes: optionally changing the magnitude of the control gate voltage of the decoder transistor to reduce the resistance of the decoder transistor. In an embodiment, the resistance of the decoder transistor is reduced in response to a reduction in the voltage limit. After step 1618, the memory system again executes steps 1608 to 1612.

[0139] In view of the foregoing, it can be seen that, according to an embodiment, an apparatus includes a circuit configured to be connected to a selected programmable resistive memory cell in a crosspoint array and to apply a voltage across the selected programmable resistive memory cell. The circuit includes a plurality of transistors configured to be connected in series with the selected programmable resistive memory cell, a selected word line, and a selected position line in the crosspoint array. The apparatus includes one or more control circuits in communication with the circuit. The one or more control circuits are configured to apply a first control signal to the circuit to establish a first resistance of the plurality of transistors connected in series with the selected programmable resistive memory cell, the selected word line, and the selected position line when controlling the circuit to apply a voltage across the selected programmable resistive memory cell to reduce the threshold voltage of a threshold switching selector in the selected programmable resistive memory cell. The one or more control circuits are configured to apply a second control signal to the circuit to establish a second resistance of the circuit connected in series with the selected programmable resistive memory cell, the selected word line, and the selected position line to sense the selected programmable resistive memory. The second resistance is lower than the first resistance.

[0140] In another embodiment of the device, the first control signal and the second control signal are decoder address signals with different values.

[0141] In another embodiment of the device, the one or more control circuits are configured to apply the first control signal to the control gate of the decoder transistor in the circuit during a threshold voltage reduction operation of the threshold switching selector to select the selected word line or the selected position line to reduce the threshold voltage of the threshold switching selector in the programmable resistive memory cell. Furthermore, the one or more control circuits are configured to apply the second control signal to the control gate of the decoder transistor in the circuit during a read operation to select the selected word line or the selected position line to sense the selected programmable resistive memory cell.

[0142] In another embodiment of the device, the one or more control circuits are configured to apply a series of voltages across the selected programmable resistive memory cell to gradually reduce the threshold voltage of the threshold switching selector in the programmable resistive memory cell, including using the series of voltages to gradually reduce the resistance of the plurality of transistors connected in series with the selected programmable resistive memory cell, the selected word line and the selected position line.

[0143] In another embodiment of the device, the one or more control circuits are configured to apply the first control signal to the circuits during the first excitation operation to establish the first resistance of the plurality of transistors.

[0144] In another embodiment of the device, the one or more control circuits are configured to apply the first control signal to the circuit during the forming operation to establish the first resistance of the plurality of transistors.

[0145] In another embodiment of the device, the one or more control circuits are configured to apply the first control signal to the circuit during a cold start operation to establish the first resistance of the plurality of transistors.

[0146] In another embodiment of the device, the threshold switching selector includes a bidirectional threshold switch (OTS).

[0147] In another embodiment of the device, the programmable resistive memory element in the programmable resistive memory cell includes a magnetoresistive random access memory (MRAM) element.

[0148] One embodiment includes a method for operating a memory having an array of crosspoints. The method includes: during a threshold voltage reduction operation of a threshold switching selector for a selected programmable resistive memory cell connected to a first selected conductive line in the crosspoint array, providing a first decoder address signal having a first magnitude to the control gate of a transistor in decoder circuitry, when the transistor has a first resistance, to charge the voltage on the first selected conductive line in the decoder circuitry. The method also includes: during a read operation of the selected programmable resistive memory cell connected to the first selected conductive line in the crosspoint array, providing a second decoder address signal having a second magnitude to the control gate of the transistor in the decoder circuitry, when the transistor has a second resistance, to charge the voltage on the first selected conductive line in the decoder circuitry. The second resistance is lower than the first resistance.

[0149] An embodiment includes a memory system comprising a crossbar array including multiple first conductive lines, multiple second conductive lines, and multiple programmable resistive memory cells. Each programmable resistive memory cell has a threshold switching selector connected in series with a programmable resistive memory element. Each programmable resistive memory cell is located at the intersection between one of the first conductive lines and one of the second conductive lines. The memory system includes decoder circuitry including a transistor with a control gate. The memory system includes one or more control circuits communicating with the crossbar array and the decoder circuitry. The one or more control circuits are configured to apply a first voltage to the control gate of the transistor to give the transistor a first resistance during the formation operation of a threshold switching selector in a selected programmable resistive memory cell connected to a selected first conductive line in the crossbar array, while the transistor supplies a first current to the selected first conductive line to charge the voltage on the selected first conductive line. The one or more control circuits are configured to apply a second voltage to the control gate of the transistor to give the transistor a second resistance during a read operation of the selected programmable resistive memory cell connected to the selected first conductive line in the crossbar array, while the transistor supplies a second current to the selected first conductive line to charge the voltage on the selected first conductive line. The second resistance is less than the first resistance.

[0150] For the purposes of this document, references to “implementation scheme,” “one implementation scheme,” “some implementation schemes,” or “another implementation scheme” in the specification may be used to describe different implementation schemes or the same implementation scheme.

[0151] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when a component is referred to as being connected to or coupled to another component, the component may be directly connected to that other component or indirectly connected to it via an intermediate component. When a component is referred to as being directly connected to another component, there is no intermediate component between the component and the other component. If two devices are directly or indirectly connected, the two devices are "in communication," allowing electronic signals to be transmitted between the two devices.

[0152] For the purposes of this document, the term "based on" may be understood as "at least partially based on".

[0153] For the purposes of this document, the use of numerical terms such as “first” object, “second” object, and “third” object without additional context may not imply an order of objects, but may be used for identification purposes to distinguish different objects.

[0154] The terms “top” and “bottom”, “upper” and “lower”, and “vertical” and “horizontal” as used herein, and their various forms, are by way of example and for illustrative purposes only, and are therefore not intended to limit the description of the technique, as the referenced items may be interchanged in position and orientation. Furthermore, as used herein, the terms “substantially” and / or “about” mean that a specified size or parameter may vary within acceptable tolerances for a given application.

[0155] The foregoing detailed description has been presented for illustrative and descriptive purposes. It is not intended to be exhaustive or limiting to the exact forms disclosed. Many modifications and variations are possible in accordance with the foregoing teachings. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to fully utilize the technology in various embodiments and with various modifications suitable for the specific intended use. The scope is intended to be defined by the claims appended herein.

Claims

1. An apparatus, the apparatus comprising: A circuit configured to be connected to a selected programmable resistive memory cell in a crosspoint array and to apply a voltage across the selected programmable resistive memory cell, the circuit including a plurality of transistors configured to be connected in series with the selected programmable resistive memory cell, a selected word line, and a selected position line in the crosspoint array; and One or more control circuits, the one or more control circuits communicating with the circuit, the one or more control circuits being configured to: When the circuit is controlled to apply a voltage across the selected programmable resistive memory cell in order to reduce the threshold voltage of the threshold switching selector in the selected programmable resistive memory cell, a first control signal is applied to the circuit to establish a first resistance of the plurality of transistors connected in series with the selected programmable resistive memory cell, the selected word line and the selected position line; as well as A second control signal is applied to the circuit to establish a second resistance of the circuit connected in series with the selected programmable resistive memory cell, the selected word line, and the selected position line in order to sense the selected programmable resistive memory, the second resistance being lower than the first resistance.

2. The apparatus according to claim 1, wherein the first control signal and the second control signal are decoder address signals with different values.

3. The apparatus of claim 1, wherein the one or more control circuits are configured to: In the threshold voltage reduction operation of the threshold switching selector, the first control signal is applied to the control gate of the decoder transistor in the circuit to select the selected word line or the selected position line to reduce the threshold voltage of the threshold switching selector in the programmable resistive memory cell; and During a read operation, the second control signal is applied to the control gate of the decoder transistor in the circuit to select the selected word line or the selected position line to sense the selected programmable resistive memory cell.

4. The apparatus of claim 1, wherein the one or more control circuits are configured to: Applying a series of voltages across the selected programmable resistive memory cell to gradually reduce the threshold voltage of the threshold switching selector in the programmable resistive memory cell includes using the series of voltages to gradually reduce the resistance of the plurality of transistors connected in series with the selected programmable resistive memory cell, the selected word line, and the selected position line.

5. The apparatus of claim 1, wherein the one or more control circuits are configured to apply the first control signal to the circuits during a first excitation operation to establish the first resistance of the plurality of transistors.

6. The apparatus of claim 1, wherein the one or more control circuits are configured to apply the first control signal to the circuits during a forming operation to establish the first resistance of the plurality of transistors.

7. The apparatus of claim 1, wherein the one or more control circuits are configured to apply the first control signal to the circuits during a cold start operation to establish the first resistance of the plurality of transistors.

8. The apparatus of claim 1, wherein the threshold switching selector comprises a bidirectional threshold switch (OTS).

9. The apparatus of claim 1, wherein the programmable resistive memory element in the programmable resistive memory cell comprises a magnetoresistive random access memory (MRAM) element.

10. A method for operating a memory having an array of crosspoints, the method comprising: During the threshold voltage reduction operation of the threshold switching selector of the selected programmable resistor memory cell connected to the first selected conductor in the crosspoint array, when the transistor in the decoder circuit has a first resistance, a first decoder address signal with a first magnitude is provided to the control gate of the transistor to cause the decoder circuit to charge the voltage on the first selected conductor. as well as During a read operation of the selected programmable resistor memory cell connected to the first selected conductive line in the crosspoint array, when the transistor in the decoder circuit has a second resistance, a second decoder address signal with a second magnitude is provided to the control gate of the transistor to charge the voltage on the first selected conductive line, wherein the second resistance is lower than the first resistance.

11. The method according to claim 10, further comprising: During the threshold voltage reduction operation, a series of formation voltages are applied to the selected programmable resistive memory cell, including: when the transistor has a resistance that gradually decreases with the series of formation voltages, applying the series of voltages to the control gate of the transistor in the decoder circuit to charge the decoder circuit to the voltage on the first selected conductive line.

12. The method of claim 10, wherein the threshold voltage reduction operation is a first excitation operation.

13. The method of claim 10, wherein the threshold voltage reduction operation is a forming operation.

14. The method of claim 10, wherein the threshold voltage reduction operation is a cold start operation.

15. A memory system, the memory system comprising: A crossbar array, comprising multiple first conductive lines, multiple second conductive lines, and multiple programmable resistor memory units, each programmable resistor memory unit having a threshold switching selector connected in series with a programmable resistor memory element, and each programmable resistor memory unit being located at the intersection point between one of the first conductive lines and one of the second conductive lines; A decoder circuit, the decoder circuit including a transistor having a control gate; and One or more control circuits, which communicate with the crossbar array and the decoder circuit, are configured to: During the formation operation of a threshold switching selector in a selected programmable resistor memory cell connected to a selected first conductive line in the crossbar array, a first voltage is applied to the control gate of the transistor to give the transistor a first resistance while the transistor supplies a first current to the selected first conductive line to charge the voltage on the selected first conductive line; as well as During a read operation of a selected programmable resistive memory cell connected to a selected first conductive line in the crossbar array, while the transistor supplies a second current to the selected first conductive line to charge the voltage on the selected first conductive line, a second voltage is applied to the control gate of the transistor to give the transistor a second resistance, wherein the second resistance is less than the first resistance.

16. The memory system according to claim 15, wherein: The forming operation includes a series of progressively decreasing forming voltages applied across the selected programmable resistive memory cell to progressively reduce the threshold voltage of the threshold switching selector within the selected programmable resistive memory cell; and The one or more control circuits are configured to change the magnitude of the first voltage applied to the transistor during the formation operation to gradually reduce the resistance of the transistor as the series of formation voltages decrease.

17. The memory system according to claim 15, wherein: The first voltage and the second voltage are decoder address signals with different values.

18. The memory system according to claim 17, wherein: The decoder circuit is a local word line decoder or a local word line decoder configured to select the selected first conductor in response to the decoder address signal.

19. The memory system of claim 15, wherein the threshold switching selector comprises a bidirectional threshold switch (OTS).

20. The memory system of claim 15, wherein the programmable resistive memory element comprises a magnetoresistive random access memory (MRAM) element.

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