A laser driving system with light waveform feedback

Abstract

The application belongs to the technical field of laser driver, and relates to a laser driver system with optical waveform feedback. The system comprises a driving circuit, an optical feedback circuit and a control system; the driving circuit is a multi-phase staggered parallel BUCK circuit, which is used for providing a large-current and low-ripple driving pulse current for the laser; the optical feedback circuit comprises a photoelectric detector, a transimpedance amplifier and a full-differential amplifier, which are used for collecting a laser signal output by the laser and converting the laser signal into an electric feedback signal; the control system comprises an FPGA, a high-speed ADC and an upper computer; the FPGA comprises a waveform processing unit, a DDS module, a digital integrator and a SerDes module; the FPGA realizes high-fidelity driving of the laser waveform and stable control of the output power through double-loop control. The application adopts the waveform feedback technology, realizes high-fidelity driving of the laser output waveform, and can still maintain the stability of the output power after the waveform is adjusted.

Description

Technical Field

[0001] This invention belongs to the field of laser driving technology and relates to a laser driving system with optical waveform feedback. Background Technology

[0002] Semiconductor lasers, with their advantages of high brightness, high monochromaticity, strong directionality, and good coherence, have received widespread attention. In lasers, the driver power supply plays a crucial role in the output performance. Laser diodes (LDs) are extremely sensitive to electrostatic discharge, excessive current, and excessively high peak current; even small instantaneous bias voltage fluctuations can lead to large current fluctuations, disrupting stability and even damaging the LD. Semiconductor lasers require a driver power supply that provides power in the form of a current source, with the output current being a rectangular pulse waveform. The rise and fall edges should be as steep as possible, with no overshoot or overshoot when the pulse current rises to its rated value, and a smooth, stable pulse discharge without overshoot. Even a small overshoot can cause fatal damage to the semiconductor laser; therefore, good current stability is a fundamental requirement for pulse power supplies. Because semiconductor lasers are physically very similar to diodes, the semiconductor laser can only enter its operating region and emit laser light when the driver output voltage exceeds the threshold voltage.

[0003] Currently, most pulsed drive power supplies employ a linear drive topology. The power transistors operate in the linear region, and the output current is controlled by adjusting the transistor voltage. However, in linear drive circuits, the power transistors operate in the linear region for extended periods, leading to increased transistor resistance and power loss. Furthermore, much of this power loss is converted into heat, increasing the power supply's heatsink volume. This not only reduces the power supply's drive efficiency but may also damage the power transistors. Therefore, there is an urgent need for a pulsed power drive technology that can achieve ideal waveform driving and enable high-efficiency, low-ripple, and high-power laser driving. Summary of the Invention

[0004] The purpose of this invention is to solve the problems in the prior art and provide a pulse power drive technology that can achieve ideal waveform driving.

[0005] To achieve the above objectives, the present invention provides a laser driving system with optical waveform feedback, including a driving circuit, an optical feedback circuit, and a control system;

[0006] The driving circuit is a multi-phase interleaved parallel BUCK circuit, used to provide the laser with a high-current, low-ripple driving pulse current;

[0007] The optical feedback circuit includes a photodetector, a transimpedance amplifier, and a fully differential amplifier, used to acquire the laser signal output by the laser and convert it into an electrical feedback signal.

[0008] The control system is connected to the drive circuit and the optical feedback circuit respectively, and includes an FPGA, a high-speed ADC, and a host computer; wherein the FPGA includes a waveform processing unit, a DDS module, a digital integrator, and a SerDes module; the high-speed ADC There are two systems: one for synchronously sampling the output current signal of the drive circuit and the other for synchronously sampling the electrical feedback signal output by the optical feedback circuit, and the sampled data is transmitted to the FPGA. The FPGA adopts dual closed-loop control, including inner loop control and outer loop control. The control logic is as follows: the outer loop control divides the sampled electrical feedback signal into two paths. One path is input to the waveform processing unit to generate an ideal waveform, and then the DDS module generates a current reference waveform. The other path calculates the laser waveform area through a digital integrator to obtain the average power of the laser output and inputs it into the DDS module. The DDS module compares the average power of the laser output with the actual required output power to obtain a multiple n. The DDS module multiplies the generated current reference waveform by n to obtain the final current reference value, which is the actual required output current value. The inner loop control samples the waveform of the drive circuit output current in one switching cycle and inputs it together with the current reference value into the PID algorithm to generate the duty cycle value of the next switching cycle. The SerDes module generates PWM to control the output current of the switching transistor in the drive circuit.

[0009] Furthermore, the multi-phase interleaved parallel BUCK circuit is a synchronous buck BUCK topology circuit. Each phase circuit includes two switching transistors, one sampling resistor, and one power inductor. Multiple BUCK circuits are connected in an interleaved parallel manner, and the branch current is the total current divided by the number of phases.

[0010] Furthermore, the waveform processing unit performs wavelet denoising on the input electrical feedback signal to extract waveform features; using a pre-trained deep Q-network model, it acquires and outputs ideal waveform data based on the waveform features and the current load and driving conditions, while simultaneously outputting frequency control words and phase control words.

[0011] Furthermore, the DDS module uses the ideal waveform data, frequency control word and phase control word output by the waveform processing unit to generate a current reference waveform.

[0012] Furthermore, the bandwidth rate of the inner loop control is determined by the switching frequency; the bandwidth rate of the outer loop control is controlled by the repetition frequency.

[0013] This invention employs waveform feedback technology, adjusting the drive signal by the laser output waveform to achieve high-fidelity drive of the laser output waveform, and maintaining stable output laser power even after waveform changes. This invention also utilizes multi-phase interleaved parallel technology to achieve low-ripple, high-power current waveform output, reducing waveform distortion. Attached Figure Description

[0014] Figure 1 Design diagram of a multi-channel interleaved parallel BUCK circuit;

[0015] Figure 2 This is the circuit design diagram for the optical feedback circuit;

[0016] Figure 3 This is the internal logic diagram of the control system;

[0017] Figure 4 This is a schematic diagram illustrating the training of the DQN model;

[0018] Figure 5 This is the control logic block diagram for dual closed-loop control.

[0019] Figure 6 This is a schematic diagram of the ideal waveform of the output current;

[0020] Figure 7 The waveform of the output current without waveform adjustment is shown.

[0021] Figure 8 The waveform of the output current after waveform adjustment according to the present invention is shown.

[0022] Figure 9 This is a schematic diagram illustrating the stability of the output laser power of the system of the present invention. Detailed Implementation

[0023] The technology will be further described below with reference to the accompanying drawings and specific embodiments to help understand the content of the present invention.

[0024] The present invention provides a laser driving system with optical waveform feedback, comprising a driving circuit, an optical feedback circuit, and a control system.

[0025] To achieve high-fidelity laser waveform driving, higher requirements are placed on the flatness, rise time, and ripple of the topology circuit. In this invention, a multi-phase interleaved parallel BUCK circuit is used as the topology circuit. This circuit is a synchronous buck BUCK topology circuit, such as... Figure 1 As shown, multiple BUCK circuits are connected together in an interleaved parallel configuration. Each independent branch contains a switching transistor, an energy storage inductor, and a current-limiting resistor, forming the core energy storage / voltage regulation unit of the BUCK topology.

[0026] The control system outputs control signals for the switching transistors of each phase inductor. The control signals for the upper switching transistors Q1, Q3, Q5, ..., Q2m-1 have the same duty cycle, and the phase delay between each phase is 360° / m. Q2, Q4, Q6, ..., Q2m are the lower switching transistors, and their control signals are opposite to those of the upper switching transistors. A reasonable dead time is set according to the switching transistor parameters. R1, R2, R3, ..., Rm are branch resistors, and L1, L2, L3, ..., Lm are power inductors. Taking the first phase circuit as an example, this branch consists of Q1, Q2, R1, and L1. Q1 is the main switching transistor, and Q2 is the freewheeling switching transistor. The waveforms of Q2 and Q1 are complementary. When Q1 is on, Q1, R1, and L1 form a closed loop, and the current in inductor L1 increases linearly; conversely, if Q1 is off, the current in inductor L1 decreases. The structure and principle of other branches are the same as those of the first phase circuit. If the current of the m-th phase branch is to be adjusted, it can be adjusted by adjusting the duty cycle of the Q2m-1 switching transistor.

[0027] When the circuit operates in steady state, its output is stable, and the switching time of each phase is fixed. Taking a single-phase circuit as an example, assuming the system input voltage is Vin and the total output current is Iout in one cycle, the average current on the inductor of the single-phase circuit is Iavg = Iout / m. Phases 1 to m each form independent "input-energy storage-output" paths, ultimately converging at a common output terminal. The common output terminal is connected in series with the total sampling resistor Rs and the output filter capacitor Cout to complete the output current sampling and voltage ripple suppression, forming a stable output current Iout.

[0028] When high-current applications are required, each path only needs to handle the branch current equal to the total current divided by the number of phases, effectively reducing the performance requirements for individual components. Simultaneously, the phase delay within each BUCK path results in a total current ripple smaller than the branch current ripple. Therefore, using interleaved parallel BUCKs as a pulsed power circuit reduces the power requirements of power devices and minimizes current ripple, making it suitable as a driver for pulsed lasers.

[0029] like Figure 2As shown, the optical feedback circuit consists of a photodetector (PD), a first-stage operational amplifier circuit, and a second-stage operational amplifier circuit. The PD operates in zero-bias mode (photovoltaic mode), with its anode grounded and its cathode connected to the non-inverting input of the operational amplifier, converting the incident laser signal into a weak current signal. The first-stage operational amplifier circuit includes a transimpedance amplifier (TIA), which forms a current-to-voltage (IV) converter amplifier. Its non-inverting input is connected to the cathode of the PD to acquire the photocurrent signal; its inverting input is connected to the output through a feedback network. The feedback network consists of a resistor R1 and a capacitor C1 connected in parallel, achieving current-to-voltage conversion while introducing a low-pass filter to suppress high-frequency noise. The second-stage operational amplifier circuit includes a fully differential amplifier (FDA), forming a non-inverting proportional amplifier, further amplifying the output voltage of the first-stage amplifier. Its input receives the output signal of the first-stage operational amplifier circuit through a resistor R3. The non-inverting input is connected to the junction of resistors R3 and R4, with the lower end of R4 grounded, forming a voltage divider input. The feedback network consists of resistor R2 connected between the output and the inverting input, creating negative voltage feedback to stabilize the amplification factor. The optical feedback circuit converts the acquired laser light into an electrical signal via a PD, then into a voltage signal via a transgroup amplifier (TIA), and finally amplifies it via a fully differential amplifier (FDA) before entering the high-speed ADC.

[0030] The photodiode selected is the LSSPD-U3.2 silicon photodiode from Beijing Minguang Optoelectronics. This photodiode can detect a maximum power of 25mW and a wavelength range of 200-1100nm. The transimpedance amplifier used is the MAX40660, which features extremely low offset voltage and low noise, making it well-suited for laser measurements. The reverse voltage in the transimpedance amplifier is set to -2.5V, and a 50kΩ transimpedance value is chosen. The fully differential amplifier selected is the LTC6253, which features a 320MHz gain-bandwidth product and extremely low quiescent current, making it suitable for front-end signal processing in high-speed ADCs.

[0031] like Figure 3 As shown, the control system consists of an FPGA, two high-speed ADCs, and a host computer. The FPGA includes a waveform processing unit, a DDS module, a digital integrator, and a SerDes module. The FPGA communicates with the host computer via a serial port. The host computer interacts with the FPGA, handling functions such as power supply initialization, parameter setting, and control and monitoring of the laser drive's waveform parameters, output power, and repetition frequency.

[0032] The waveform processing unit extracts features from the sampled laser waveform data (i.e., the electrical feedback signal output by the optical feedback circuit) and eliminates high-frequency noise interference caused by EMI through wavelet transform, obtaining relatively pure optical waveform feature data. The FPGA employs a parallel architecture, allowing for parallel computation of multiple data points through a multi-layer pipeline. DB4 (Daubechies 4th order wavelet) is used as the wavelet transform function. While removing noise interference, DB4 offers faster computation speed, enabling wavelet denoising of the waveform within a single pulse frequency. Taking a waveform with a 250μs pulse width as an example, with a switching frequency of 1MHz, a sampling rate of 2MHz is sufficient to reconstruct the optical waveform signal. Therefore, the ADC has a total of 500 sampling points in one pulse output. By performing wavelet transform on these 500 sampling points and utilizing the pipelined design within the FPGA, wavelet transform can be performed on all data within 10ms, and the waveform can be reconstructed.

[0033] Taking a trapezoidal wave as an example of an ideal driving waveform, the obtained laser waveform feedback signal generally changes due to electrical parameters and the hysteresis of the control system. Furthermore, the load during descent differs from that during ascent, resulting in completely different ascent and descent slopes. Additionally, the inner-loop control of the control system, using PID control, may also generate overshoot and oscillations. To address this issue, waveform generation is performed using different types of reference waveform data, generating datasets from different driving conditions, load conditions, ideal waveforms, and actual waveform data collected. The obtained datasets are trained using a Deep Q-Network (DQN) model to find ideal waveform data under different load and driving conditions. The trained DQN model is then deployed in an FPGA. The DQN model takes the driving conditions, load conditions, and sampled waveform features (after wavelet transform processing) as inputs, and outputs waveform data, frequency control words, and phase control words. Thus, by adjusting the sampled laser waveform data under different driving and load conditions, the most ideal waveform is obtained.

[0034] The core of the waveform processing unit is the DQN model, which is trained as follows: Figure 4 As shown, the rise time, fall time, and overshoot of the sampled laser waveform data are used as waveform feature values. After denoising the acquired waveform data, the rise slope, fall slope, and overshoot value of the measured waveform data are calculated. The driving voltage and load at this time are used as input parameters for reinforcement learning, and the waveform data type, frequency control word, and phase control word of the DDS module are used as output parameters for calculation. The trained DQN model is deployed inside the FPGA. In this way, by analyzing and processing the acquired waveform data, the model input can be obtained, and the desired ideal waveform can be output, thus achieving high-fidelity waveform driving.

[0035] The waveform data, frequency control word, and phase control word generated by the DQN model, along with the actual required output power (set by the user), are input into the DDS module. The DDS module then generates a current reference waveform. Since the current reference waveform is adjusted by the DQN model, this adjustment may cause power changes. Therefore, the final output waveform data needs to be multiplied by an amplification factor, n. This multiplication factor is determined by the actual required output power and the average power of the laser output. Power stability is controlled by multiplying the waveform.

[0036] A digital integrator is used to calculate the average power of the laser output. Because the current signal of the photodetector (PD) is related to the laser power, the average power of the laser output can be calculated by integrating the electrical feedback signal after laser sampling using a digital integrator.

[0037] The FPGA in the control system employs dual closed-loop control, such as... Figure 5 As shown, the control system includes inner-loop control and outer-loop control. The inner-loop control controls the output current, while the outer-loop control controls the shape and power of the output laser. The inner-loop control uses the output current Iout of the drive circuit and the current reference value Iref as the loop input signals, where Iref is the actual required current value. The outer-loop control uses the electrical feedback signal output from the optical feedback circuit and the actual required output power Pref as the loop inputs.

[0038] The outer loop control splits the sampled electrical feedback signal into two paths. One path enters the waveform processing unit, where it undergoes wavelet transform processing and then uses the DQN model to generate an ideal waveform, which is then used by the DDS module to generate a current reference waveform. The other path calculates the laser waveform area through a digital integrator to obtain the average laser output power Pavg, which is then input into the DDS module. The DDS module compares the input average power Pavg with the actual required output power Pref to obtain a multiple n between the two. The DDS module multiplies the generated current reference waveform by n to obtain the final current reference value (i.e., the actual required output current value). This value is also the current reference value Iref in the inner loop control, which can generate the required power output while maintaining the waveform shape.

[0039] The inner loop control samples the waveform of the drive circuit output current Iout during one switching cycle and inputs it along with the current reference value Iref into the PID algorithm to generate the duty cycle value for the next switching cycle. The SerDes module generates PWM to control the switching transistors (Q1, Q2, ..., Qm) in the drive circuit, thereby controlling the output current Iout of the drive circuit. This process is repeated cyclically.

[0040] The inner loop bandwidth rate of the system is determined by the switching frequency, while the outer loop bandwidth rate is controlled by the repetition frequency. The bandwidth rate controlled by the inner loop is much greater than that of the outer loop. Only after the previous pulse cycle has ended can complete laser waveform data and output power be sampled, and these data are processed and compared to affect the waveform output in the next pulse cycle.

[0041] To generate a higher resolution PWM wave, a SerDes module is selected. SerDes (SERializer / DESerializer) is a core physical layer (PHY) module for modern high-speed communication (Gbps level). This system uses a PWM wave with a maximum resolution of 1ns. To achieve this, the FPGA output frequency needs to reach 1GHz. However, the FPGA's internal frequency can only reach a maximum of 625MHz, so it cannot directly generate the required 1GHz signal through internal PLL frequency division. Therefore, this system uses SerDes primitives to generate the 1GHz signal. The system uses 125MHz as the main clock frequency and 8 bits of parallel data as the input to the SerDes module. Since the SerDes module also requires a fast data clock for output, this clock is set to 500MHz in this system. The SerDes module then processes these 8 bits of parallel data and generates a 1GHz signal based on the data.

[0042] To verify the performance of the system of this invention, an experimental prototype was built for testing. A switching power supply with a supply voltage of 24V was used to power the entire system. A laser diode (HD-N107-3-D12-0003, Huaguang Optoelectronics) was used as the load of the system to test the power supply driving performance. Figure 6 This is a schematic diagram of the ideal output current waveform. The current output waveform at a repetition frequency of 100Hz was tested. Figure 7 The output current waveform without waveform adjustment shows that the rise time of the output waveform is slow and there is oscillation in the output. Furthermore, due to the pulse width limitation, the current drops rapidly to 0 during the fall. Figure 8 The output current waveform, after adjustment by the waveform processing unit, is relatively symmetrical and flat, without oscillation. The stability of the output optical power was then tested. Figure 9 As shown, the output power is relatively stable.

Claims

1. A laser driving system with optical waveform feedback, characterized in that, Includes drive circuits, optical feedback circuits, and control systems; The driving circuit is a multi-phase interleaved parallel BUCK circuit, used to provide the laser with a high-current, low-ripple driving pulse current; The optical feedback circuit includes a photodetector, a transimpedance amplifier, and a fully differential amplifier, used to acquire the laser signal output by the laser and convert it into an electrical feedback signal. The control system is connected to the drive circuit and the optical feedback circuit, and includes an FPGA, a high-speed ADC, and a host computer. The FPGA includes a waveform processing unit, a DDS module, a digital integrator, and a SerDes module. Two high-speed ADCs are used to synchronously sample the output current signal of the drive circuit and the electrical feedback signal output by the optical feedback circuit, respectively, and transmit the sampled data to the FPGA. The FPGA employs dual closed-loop control, including inner-loop control and outer-loop control. The control logic is as follows: the outer-loop control divides the sampled electrical feedback signal into two paths. One path is input to the waveform processing unit to generate an ideal waveform, and then the DDS module generates a current reference waveform. The other path calculates the laser waveform area through the digital integrator to obtain the average laser output power, which is then input to the DDS module. The DDS module compares the average laser output power with the actual required output power to obtain a multiple n. The DDS module multiplies the generated current reference waveform by n to obtain the final current reference value, i.e., the actual required output current value. Inner-loop control involves sampling the waveform of the drive circuit's output current during a switching cycle and inputting it along with a current reference value into the PID algorithm to generate the duty cycle value for the next switching cycle. This duty cycle value is then generated by the SerDes module to produce PWM, which controls the output current of the switching transistor in the drive circuit.

2. The laser driving system with optical waveform feedback according to claim 1, characterized in that, The multiphase interleaved parallel BUCK circuit is a synchronous buck BUCK topology circuit. Each phase circuit includes two switching transistors, one sampling resistor and one power inductor. Multiple BUCK circuits are connected in an interleaved parallel manner, and the branch current is the total current divided by the number of phases.

3. The laser driving system with optical waveform feedback according to claim 1, characterized in that, The waveform processing unit performs wavelet denoising on the input electrical feedback signal to extract waveform features; using a pre-trained deep Q-network model, it acquires and outputs ideal waveform data based on the waveform features and current load and driving conditions, while simultaneously outputting frequency control words and phase control words.

4. The laser driving system with optical waveform feedback according to claim 3, characterized in that, The DDS module uses the ideal waveform data, frequency control word and phase control word output by the waveform processing unit to generate a current reference waveform.

5. The laser driving system with optical waveform feedback according to claim 1, characterized in that, The bandwidth rate of the inner loop control is determined by the switching frequency; the bandwidth rate of the outer loop control is controlled by the repetition frequency.

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