Auxiliary resonant commutated pole inverter unit and method

Abstract

The application provides an auxiliary resonant converter pole inverter unit and method, which can be applied to the field of power electronic converters. The auxiliary resonant converter pole inverter unit comprises: a configuration configured to control the second main switch tube and the second auxiliary switch tube to be turned on, and the first main switch tube and the first auxiliary switch tube to be turned off in a first time period, so as to turn on a path passing through the second split capacitor, the turn-on channel of the second auxiliary switch tube, the parasitic diode of the first auxiliary switch tube, the resonant inductor, the turn-on channel of the second main switch tube, and returning to the second split capacitor, and a path passing through the positive electrode of the output voltage, the first split capacitor, the turn-on channel of the second auxiliary switch tube, the parasitic diode of the first auxiliary switch tube, the turn-on channel of the second main switch tube, and the negative electrode of the output voltage. By controlling the second auxiliary switch tube to be turned on when the second main switch tube maintains a turn-on state, the voltage deviation generated by the first split capacitor and the second split capacitor in operation is compensated, and the reliability is improved.

Description

Technical Field

[0001] This application relates to the field of power electronic converter technology, specifically to an auxiliary resonant commutator inverter unit and method. Background Technology

[0002] In the field of power electronic converters, high efficiency, high power density, and reliability have become the goals pursued. Soft-switching technology, as one way to achieve these goals, can reduce switching losses or improve electromagnetic interference (EMI), enabling the converter to operate at higher frequencies, thereby reducing the size and weight of passive components. The Auxiliary Resonant Commutated Pole Inverter (ARCPI), as a soft-switching implementation, has attracted widespread attention due to its ability to achieve zero-voltage turn-on of the main switch and zero-current turn-off of the auxiliary switch, as well as its good compatibility with Pulse Width Modulation (PWM).

[0003] Among related technologies, the reliability of auxiliary resonant commutator inverter units is relatively low. Summary of the Invention

[0004] In view of the above problems, this application provides an auxiliary resonant commutator inverter unit and method.

[0005] According to one aspect of the embodiments of this application, an auxiliary resonant commutator inverter unit is provided, comprising: a first auxiliary switch transistor; a resonant inductor, the first end of which is electrically connected to the first electrode of the first auxiliary switch transistor; a filter inductor, the first end of which is electrically connected to the positive electrode of the power supply voltage, and the second end of which is electrically connected to the second end of the resonant inductor; a first main switch transistor, the second electrode of which is electrically connected to the second end of the resonant inductor and the second end of the filter inductor; a second main switch transistor, the first electrode of which is electrically connected to the second end of the resonant inductor, the second end of the filter inductor, and the second electrode of the first main switch transistor, and the second electrode of which is electrically connected to the negative electrode of the power supply voltage; a first split capacitor, the first end of which is electrically connected to the first electrode of the first main switch transistor and the positive electrode of the output voltage; a second auxiliary switch transistor, the first electrode of which is electrically connected to the second end of the first split capacitor, and the second electrode of which is electrically connected to the second electrode of the first auxiliary switch transistor; and a second split capacitor. The first terminal of the second split capacitor is electrically connected to the second terminal of the first split capacitor and the first electrode of the second auxiliary switch. The second terminal of the second split capacitor is electrically connected to the second electrode of the second main switch, the negative electrode of the power supply voltage, and the negative electrode of the output voltage. A control module is also included, with its first control terminal electrically connected to the control electrode of the second main switch, its second control terminal electrically connected to the control electrode of the first auxiliary switch, and its third control terminal electrically connected to the control electrode of the second auxiliary switch. The module is configured to control the second main switch and the second auxiliary switch to be turned on and the first auxiliary switch to be turned off during a first time period. This allows for the conduction of a path through the second split capacitor, the conduction channel of the second auxiliary switch, the parasitic diode of the first auxiliary switch, the resonant inductor, and the conduction channel of the second main switch, returning to the second split capacitor, and a path through the positive electrode of the output voltage to the first split capacitor, the conduction channel of the second auxiliary switch, the parasitic diode of the first auxiliary switch, the conduction channel of the second main switch, and the negative electrode of the output voltage.

[0006] According to another aspect of the embodiments of this application, an auxiliary resonant commutator inverter method is provided, applied to the above-mentioned auxiliary resonant commutator inverter unit. The auxiliary resonant commutator inverter method includes: controlling the second main switch and the second auxiliary switch to be turned on and the first auxiliary switch to be turned off during a first time period, so as to conduct a path through the second split capacitor, the conduction channel of the second auxiliary switch, the parasitic diode of the first auxiliary switch, the resonant inductor, the conduction channel of the second main switch, and back to the second split capacitor, and a path through the positive terminal of the output voltage to the first split capacitor, the conduction channel of the second auxiliary switch, the parasitic diode of the first auxiliary switch, the conduction channel of the second main switch, and the negative terminal of the output voltage.

[0007] According to an embodiment of this application, by controlling the second auxiliary switch to be on while the second main switch is in a state of being on, the voltage deviation generated by the first and second split capacitors during the operation of the auxiliary resonant commutator inverter unit is compensated. This reduces the potential change at the neutral point during the operation of the auxiliary resonant commutator inverter unit, achieving a voltage equalization state between the voltages across the first and second split capacitors in the auxiliary resonant commutator inverter unit's operating mode. This improves the stability of the voltages across the first and second split capacitors, thereby enhancing the reliability of the auxiliary resonant commutator inverter unit. Attached Figure Description

[0008] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments of this application with reference to the accompanying drawings.

[0009] Figure 1A A schematic diagram of an auxiliary resonant commutator inverter unit according to an embodiment of this application is shown.

[0010] Figure 1B A schematic diagram of the current flow of the device during a first time period according to an embodiment of this application is shown.

[0011] Figure 1C A schematic diagram of a first conduction path during a first time period according to an embodiment of this application is shown.

[0012] Figure 1D A schematic diagram of a second conduction path during a first time period according to an embodiment of this application is shown.

[0013] Figure 1E A schematic diagram of the current flow of the device during a second time period according to an embodiment of this application is shown.

[0014] Figure 1F A schematic diagram of the first conduction path during the second time period according to an embodiment of this application is shown.

[0015] Figure 1G A schematic diagram of a second conduction path during a second time period according to an embodiment of this application is shown.

[0016] Figure 1H A schematic diagram of the current flow direction of the device during a third time period according to an embodiment of this application is shown.

[0017] Figure 1I A schematic diagram of the first conduction path during the third time period according to an embodiment of this application is shown.

[0018] Figure 1J A schematic diagram of the second conduction path during the third time period according to an embodiment of this application is shown.

[0019] Figure 1K A schematic diagram of the current flow direction of the device during the fourth time period according to an embodiment of this application is shown.

[0020] Figure 1L A schematic diagram of the first conduction path in the fourth time period according to an embodiment of this application is shown.

[0021] Figure 1M A schematic diagram of the second conduction path in the fourth time period according to an embodiment of this application is shown.

[0022] Figure 2 A schematic diagram of the working waveform of an auxiliary resonant commutator inverter unit according to an embodiment of this application is shown.

[0023] Figure 3 A schematic diagram of another auxiliary resonant commutator inverter unit according to an embodiment of this application is shown.

[0024] Figure 4 A schematic diagram of the control module according to an embodiment of this application is shown.

[0025] Figure 5 The simulation waveform of an auxiliary resonant commutator inverter unit according to an embodiment of this application is shown.

[0026] Figure 6 A schematic diagram showing the experimental results of an auxiliary resonant commutator inverter unit according to an embodiment of this application is provided.

[0027] Figure 7 A schematic diagram of the operational experimental results of another auxiliary resonant commutator inverter unit according to an embodiment of this application is shown.

[0028] Figure 8 An embodiment according to this application is shown. Figure 7 A magnified schematic diagram of the experimental results of the auxiliary resonant commutator inverter unit. Detailed Implementation

[0029] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0031] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0032] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0033] Zero-voltage switching (ZVS) can include zero-voltage turn-on (or zero-voltage conduction) and zero-voltage turn-off. Zero-current switching (ZCS) can include zero-current turn-on (zero-current conduction) and zero-current turn-off. In related technologies, auxiliary resonant commutator inverter units suffer from the dependence of the resonant process on the load current, DC-side capacitor voltage equalization issues, or complexity of control strategies, which limit their application.

[0034] To address this, this application proposes an auxiliary resonant commutator inverter unit. This unit integrates the entire soft-switching topology into a compact soft-switching implementation unit and employs an advanced logic device combination strategy to construct a logic control unit that intelligently and flexibly recognizes soft-switching conditions and whether the capacitors are operating under equal voltage conditions. This effectively solves the problems of control accuracy and capacitor voltage imbalance in DC-DC (Direct Current-Direct Current) operation. This application requires no additional components and offers high cost-effectiveness and reliability in practical applications.

[0035] Figure 1A A schematic diagram of an auxiliary resonant commutator inverter unit according to an embodiment of this application is shown.

[0036] like Figure 1A As shown, the auxiliary resonant commutator inverter unit may include a first main switch S. m1 Second main switch Sm2 First auxiliary switch S a1 Second auxiliary switch S a2 Resonant inductor L r Filter inductor L F The first split capacitor C1 and the second split capacitor C2.

[0037] Resonant inductor L r The first terminal can be connected to the first auxiliary switch S a1 The first electrode is electrically connected to the resonant inductor L. r The second terminal can be connected to the filter inductor L F The second terminal is electrically connected. Filter inductor L F The first terminal can be connected to the power supply voltage V. in The positive terminal is connected. The first auxiliary switch transistor S... a1 The second electrode can be connected to the second auxiliary switch S. a2 The second electrode is electrically connected. The second auxiliary switch S... a2 The first terminal can be electrically connected to the second terminal of the first split capacitor C1 and the first terminal of the second split capacitor C2.

[0038] First main switch transistor S m1 The first terminal can be connected to the first terminal of the first split capacitor C1 and the output voltage V. out The positive terminal is connected. The first main switch transistor S... m1 The second pole can be connected to the resonant inductor L r The second terminal, filter inductor L F The second terminal and the second main switch S m2 The first electrode is electrically connected. The second main switch transistor S... m2 The second pole can be connected to the power supply voltage V. in The negative terminal, the second terminal of the second split capacitor C2, and the output voltage V out The negative terminal is electrically connected.

[0039] The first control terminal of the control module can be connected to the second main switch S. m2 The control terminal is electrically connected to the control electrode. The second control terminal of the control module can be connected to the first auxiliary switch S. a1 The control electrode is electrically connected. The third control terminal of the control module can be connected to the second auxiliary switch S. a2 The control electrode is electrically connected. The output of the control module is a digital PWM waveform, which needs to be converted into a drive signal by the control electrode drive unit and transmitted to the control electrode of the switching transistor. For simplicity, the output terminal of the control module (e.g., the first control terminal, the second control terminal, or the third control terminal) and the switching transistor (e.g., the second main switching transistor S) are referred to as the control electrode. m2 First auxiliary switch S a1 Second auxiliary switch S a2The control electrode is electrically connected.

[0040] First main switch transistor S m1 Second main switch S m2 First auxiliary switch S a1 Second auxiliary switch S a2 It can be a power switching transistor. Power switching transistors can include metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), or wide-bandgap power semiconductor devices. Wide-bandgap power semiconductor devices can include those represented by silicon carbide (SiC) and gallium nitride (GaN). The first main switch S... m1 Second main switch S m2 First auxiliary switch S a1 Second auxiliary switch S a2 Each can have its own parasitic diode.

[0041] The control module can control the second main switch S in the first time period. m2 Second auxiliary switch S a2 On, and the first auxiliary switch S a1 Turn off to enable the first conduction path, i.e., via the second split capacitor C2 and the second auxiliary switch S. a2 The conduction channel, the first auxiliary switch S a1 Parasitic diode, resonant inductor L r Second main switch S m2 The conduction channel is opened, and the path returns to the second split capacitor C2. Additionally, a second conduction path can be opened, i.e., via the output voltage V. out The positive terminal flows to the first split capacitor C1 and the second auxiliary switch S. a2 The conduction channel, the first auxiliary switch S a1 Parasitic diode and second main switch S m2 The conduction channel and output voltage V out The path to the negative terminal. Furthermore, it should be noted that the conduction paths described in the embodiments of this application are intended to illustrate the conduction status of important devices. The devices included in the conduction path do not necessarily form a loop; the conduction path may be a circuit branch. For example, the devices through which current flows in the first time period also involve the power supply voltage V. in Filter inductor L F Output voltage regulator capacitor C F and output load resistance R FTo facilitate understanding, the following will be combined with... Figure 1B , Figure 1C and Figure 1D Explain the current flow direction and conduction path of the device in the first time period. Figure 1B A schematic diagram of the current flow of the device during a first time period according to an embodiment of this application is shown. Figure 1C A schematic diagram of a first conduction path during a first time period according to an embodiment of this application is shown. Figure 1D A schematic diagram of a second conduction path during a first time period according to an embodiment of this application is shown. Figure 1B , Figure 1C and Figure 1D As shown, Figure 1B The red arrows indicate the direction of current flow in the device, the red lines indicate the devices through which current flows, and the black lines indicate that no current flows. Figure 1C and Figure 1D The above-mentioned conduction path is highlighted, the red arrows indicate the direction of current flow in the devices, and the red lines indicate the devices through which current flows along the above-mentioned conduction path. It should be noted that... Figure 1B The devices indicated by the red arrows and red lines also include power supply voltages V not covered in the aforementioned conduction paths. in Filter inductor L F Output voltage regulator capacitor C F and output load resistance R F . Figure 1D The devices indicated by the red arrows and red lines also include the resonant inductor L, which is not covered in the second conduction path described above. r and output voltage regulator capacitor C F Furthermore, regarding the output voltage regulator capacitor C shown in the attached diagram... F and output load resistance R F For further explanation, please refer to the corresponding section below. For ease of understanding, the following section combines... Figure 2 Please provide an explanation. Figure 2 A schematic diagram of the working waveform of an auxiliary resonant commutator inverter unit according to an embodiment of this application is shown.

[0042] like Figure 2 As shown, t i Let represent time i. i can be an integer greater than or equal to 1 and less than or equal to 9. i ∈ {1, 2, ..., 8, 9}. The time interval can be the duration between two times. The first time interval can be t6~t7. The second time interval can be t1~t2. The third time interval can be t7~t8. The fourth time interval can be t2~t4. The fifth time interval can be t5~t6. The sixth time interval can be t1~t5. sm1 For the flow through the first main switch transistor S m1 The instantaneous current. sm2 For the flow through the second main switch Sm2 The instantaneous current. r For the flow through the resonant inductor L r The instantaneous current. V out This is the output voltage of the auxiliary resonant commutator inverter unit. PWM_IN is the external input. F For the flow through the filter inductor L F The current, I F This is a constant value. The working waveforms for the first, second, third, fourth, fifth, and sixth time periods are described below.

[0043] like Figure 2 As shown, during the sixth time period (t1~t5), the second split capacitor C2 is in a charging state, while the first split capacitor C1 is in a discharging state. If there are no other switching modes, after the cumulative effect of multiple cycles, the voltage between the first and second terminals of the second split capacitor C2 (i.e., the voltage across the two terminals of the second split capacitor C2) will gradually rise to the output voltage V of the auxiliary resonant commutation inverter unit. out The voltage between the first and second terminals of the first split capacitor C1 (i.e., the voltage across the first split capacitor C1) drops to 0. Therefore, if left uncontrolled, after several cycles, an imbalance will occur between the first split capacitor C1 and the second split capacitor C2, with the voltage across the second split capacitor C2 being higher than the voltage across the first split capacitor C1. This, in turn, causes the first auxiliary switch S to... a1 Second auxiliary switch S a2 Failure. During the fifth time period (t5~t6), the instantaneous current flowing through the resonant inductor is 0. The voltages across the first split capacitor C1 and the second split capacitor C2 do not change, but the voltage across the second split capacitor C2 is in a stable voltage imbalance state where the voltage across the first split capacitor C1 is higher than the voltage across the second split capacitor C2. To address this, this embodiment adds an operating mode from t6 to t8 to compensate for the voltage deviation caused by the operation of the first split capacitor C1 and the second split capacitor C2.

[0044] At t6, the external input PWM_IN requires a second main switch S. m2 When shut down, the control module can continue to maintain the second main switch S. m2 To enable conduction, a second auxiliary switch S is required. a2 On, and the first auxiliary switch S a1 Off, resonant inductor L r A negative voltage is generated at both ends (i.e., with the resonant inductance L in the second time period). r (The voltage is opposite to the voltage). In this case, the first split capacitor C1 is in a charging state, the second split capacitor C2 is in a discharging state, and the current flows through the resonant inductor L. r instantaneous current ir The current rises linearly to t7, reaching a negative peak.

[0045] As one implementation method, the resonant inductance L in the first time period r The absolute value of the negative current peak satisfies the following formula (1).

[0046] (1)

[0047] in, The resonant inductance L represents the value of the first time interval. r The absolute value of the negative current peak value. This represents the output voltage of the auxiliary resonant commutator inverter unit during the first time period. Represents the resonant inductance L r The inductance. t6 represents the sixth time point. t7 represents the seventh time point.

[0048] According to an embodiment of this application, by controlling the second auxiliary switch to be on while the second main switch is in a state of being on, the voltage deviation generated by the first and second split capacitors during the operation of the auxiliary resonant commutator inverter unit is compensated. This reduces the potential change at the neutral point during the operation of the auxiliary resonant commutator inverter unit, achieving a voltage equalization state between the voltages across the first and second split capacitors in the auxiliary resonant commutator inverter unit's operating mode. This improves the stability of the voltages across the first and second split capacitors, thereby enhancing the reliability of the auxiliary resonant commutator inverter unit.

[0049] As one implementation method, such as Figure 1A As shown, the control module can control the first auxiliary switch S during the second time period. a1 On, second auxiliary switch S a2 Turn off (i.e., the second auxiliary switch S) a2 (parasitic diode conduction) and the second main switch S m2 Turn off so that via the first main switch S m1 The current (i.e., the instantaneous current) decreases to a predetermined value, and the first conduction path is opened, i.e., through the resonant inductor L. r First auxiliary switch S a1 The conduction channel, the second auxiliary switch S a2 The parasitic diode, the second split capacitor C2, and the power supply voltage V in The path to the negative terminal, and the second conduction path, i.e., via the resonant inductor L. r First auxiliary switch S a1 The conduction channel, the second auxiliary switch S a2 The parasitic diode, the first split capacitor C1, and the output voltage Vout The path to the positive terminal. The predetermined value can be 0. Furthermore, it should be noted that the devices through which current flows in the second time period mentioned above also involve the power supply voltage V. in Filter inductor L F Output voltage regulator capacitor C F and output load resistance R F Etc. To facilitate understanding, the following will be combined with... Figure 1E , Figure 1F and Figure 1G Explain the current flow direction and conduction path of the device in the second time period. Figure 1E A schematic diagram of the current flow of the device during a second time period according to an embodiment of this application is shown. Figure 1F A schematic diagram of the first conduction path during the second time period according to an embodiment of this application is shown. Figure 1G A schematic diagram of a second conduction path during a second time period according to an embodiment of this application is shown. Figure 1E , Figure 1F and Figure 1G As shown, Figure 1E The red arrows indicate the direction of current flow in the device, the red lines indicate the devices through which current flows, and the black lines indicate that no current flows. Figure 1F and Figure 1G The above-mentioned conduction path is highlighted, the red arrows indicate the direction of current flow in the devices, and the red lines indicate the devices through which current flows along the above-mentioned conduction path. It should be noted that... Figure 1E The devices indicated by the red arrows and red lines also include power supply voltages V not covered in the aforementioned conduction paths. in Filter inductor L F Output voltage regulator capacitor C F and output load resistance R F . Figure 1F The devices indicated by the red arrows and red lines also include power supply voltage V not covered in the first conduction path described above. in and filter inductor L F . Figure 1G The devices indicated by the red arrows and red lines also include power supply voltage V not covered in the second conduction path described above. in Filter inductor L F and output voltage regulator capacitor C F Let's continue with the following... Figure 2 illustrate.

[0050] For the second time period (i.e., t1~t2), in t1, the external input PWM_IN requires the second main switch S. m2 When the circuit is turned on, it responds to the second main switch S. m2 Before conducting, first turn on the first auxiliary switch S. a1 This causes the current (i.e., the first main switch S) to flow.m1 The load current flows from the first main switch transistor S. m1 Gradually converted to flow to the first auxiliary switch S a1 That is, via the first main switch S m1 instantaneous current i sm1 Reduced to a predetermined value, and conduction is achieved through the resonant inductor L. r First auxiliary switch S a1 The conduction channel, the second auxiliary switch S a2 The parasitic diode, the second split capacitor C2, and the power supply voltage V in The path to the negative terminal, and via the resonant inductor and the first auxiliary switch S. a1 The conduction channel, the second auxiliary switch S a2 The parasitic diode, the first split capacitor C1, and the output voltage V out The positive path is thus established, thereby realizing the first main switch S. m1 Zero-current turn-off and the second main switch S m2 Zero-voltage turn-on.

[0051] According to embodiments of this application, by turning on the first auxiliary switch before turning on the second main switch, the current is guided to the first auxiliary switch. The resonant inductor's suppression of the current change rate reduces the current change rate during the turn-off of the first main switch, thus reducing the turn-off losses of the first main switch. With the current flowing through the first main switch completely guided to the first auxiliary switch, the resonant effect of the resonant inductor and the parasitic capacitance of the second main switch reduces the voltage across the parasitic capacitance of the second main switch in advance. This reduces the overlap area of ​​voltage and current during the turn-on process of the second main switch, thereby reducing its turn-on losses. This, in turn, reduces electromagnetic interference in the auxiliary resonant commutator inverter unit and improves its electromagnetic compatibility. Thus, turn-on protection for both the first and second main switches is achieved, reducing their heat generation. This effectively extends the service life of both main switches, improves the overall voltage output efficiency and power density of the auxiliary resonant commutator inverter unit, and enhances its reliability.

[0052] As one implementation method, such as Figure 1A As shown, the control module can also control the second auxiliary switch S during the third time period. a2 On, and the second main switch S m2 and the first auxiliary switch S a1 Turn off to enable the first conduction path, i.e., through the second split capacitor C2, to flow to the second auxiliary switch S. a2 The conduction channel, the first auxiliary switch S a1Parasitic diode, first main switch S m1 Parasitic diode and output voltage V out The positive terminal path. In addition, a second conduction path can be established, that is, flow through the first split capacitor C1 to the second auxiliary switch S. a2 The conduction channel, the first auxiliary switch S a1 The parasitic diode and the first main switch S m1 The parasitic diode returns to the path of the first split capacitor C1. Furthermore, it should be noted that the devices through which current flows in the third time period also involve the power supply voltage V. in Filter inductor L F Resonant inductor L r Output voltage regulator capacitor C F and output load resistance R F Etc. To facilitate understanding, the following will be combined with... Figure 1H , Figure 1I and Figure 1J Explain the current flow direction and conduction path of the device in the third time period. Figure 1H A schematic diagram of the current flow direction of the device during a third time period according to an embodiment of this application is shown. Figure 1I A schematic diagram of the first conduction path during the third time period according to an embodiment of this application is shown. Figure 1J A schematic diagram of the second conduction path during the third time period according to an embodiment of this application is shown. Figure 1H , Figure 1I and Figure 1J As shown, Figure 1H The red arrows indicate the direction of current flow in the device, the red lines indicate the devices through which current flows, and the black lines indicate that no current flows. Figure 1I and Figure 1J The above-mentioned conduction path is highlighted, the red arrows indicate the direction of current flow in the devices, and the red lines indicate the devices through which current flows along the above-mentioned conduction path. It should be noted that... Figure 1H The devices indicated by the red arrows and red lines also include power supply voltages V not covered in the aforementioned conduction paths. in Filter inductor L F Resonant inductor L r Output voltage regulator capacitor C F and output load resistance R F . Figure 1I The devices indicated by the red arrows and red lines also include the resonant inductor L, which is not covered in the first conduction path described above. r and output voltage regulator capacitor C F . Figure 1J The devices indicated by the red arrows and red lines also include the resonant inductor L, which is not covered in the second conduction path described above. r Let's continue with the following... Figure 2 illustrate.

[0053] like Figure 2 As shown, in the third time period (i.e., t7~t8), at t7, the control module can control the second main switch S. m2 Turn off, turn off the second main switch transistor S m2 The turn-off current (i.e.) With filter inductor L F Current I F The sum of these values ​​is greater than the filter inductance L. F Current I F Therefore, it can be seen that in the third time period, compensating for the voltage deviation generated by the first split capacitor C1 and the second split capacitor C2 during the operation of the auxiliary resonant commutator inverter unit is to improve the voltage of the second main switch S. m2 This is at the cost of turn-off losses. In the second main switch S... m2 When the circuit is off, the resonant inductor L r The voltage across the terminals is the output voltage V of the auxiliary resonant commutator inverter unit during the first time period. out Half of the resonant inductance L r The voltage across the terminals is V out / 2. Resonant inductor L r instantaneous current i r The linear decrease to t8 disappears. During the above process, the first split capacitor C1 is still in a charging state, and the second split capacitor C2 is still in a discharging state. At the resonant inductor L... r instantaneous current i r When the value drops to 0, that is, during the time period t8~t9, the second auxiliary switch S a2 Zero-current shutdown was achieved.

[0054] According to embodiments of this application, in order to reduce the losses caused by the instantaneous current when the second auxiliary switch is turned off, it is necessary to control the second main switch to adjust the voltage across the resonant inductor, thereby reducing the instantaneous current flowing through the resonant inductor and consequently reducing the current flowing through the second auxiliary switch. During the decrease in the instantaneous current flowing through the resonant inductor, the voltage deviation generated by the first and second split capacitors during the operation of the auxiliary resonant commutation inverter unit can be compensated, further achieving voltage equalization between the voltages across the first and second split capacitors in the operating mode of the auxiliary resonant commutation inverter unit, thus improving the stability of the voltage output of the auxiliary resonant commutation inverter unit. Furthermore, zero-current turn-off of the second auxiliary switch is achieved, reducing the turn-off losses of the second auxiliary switch under turn-off conditions and extending the service life of the second auxiliary switch.

[0055] As one implementation method, such as Figure 1A As shown, the control module can also control the second main switch S in the fourth time period.m2 Second auxiliary switch S a2 Turn off, and the first auxiliary switch S a1 Turn on so that the first main switch S can be activated. m1 Parasitic capacitance and resonant inductance L r First auxiliary switch S a1 The conduction channel, the second auxiliary switch S a2 The path between the parasitic diode and the first split capacitor C1 forms a resonant current, thus creating the first conduction path in the fourth time period. Furthermore, it should be noted that the devices through which the current flows in the fourth time period also involve the power supply voltage V. in Filter inductor L F Output voltage regulator capacitor C F and output load resistance R F Etc. To facilitate understanding, the following will be combined with... Figure 1K and Figure 1L Explain the current flow direction and first conduction path of the device in the fourth time period. Figure 1K A schematic diagram of the current flow direction of the device during the fourth time period according to an embodiment of this application is shown. Figure 1L A schematic diagram of the first conduction path in the fourth time period according to an embodiment of this application is shown. Figure 1K and Figure 1L As shown, Figure 1K The red arrows indicate the direction of current flow in the device, the red lines indicate the devices through which current flows, and the black lines indicate that no current flows. Figure 1L The first conduction path is highlighted, the red arrows indicate the direction of current flow in the devices, and the red lines indicate the devices through which current flows in the first conduction path. It should be noted that... Figure 1K The devices indicated by the red arrows and red lines also include power supply voltages V not covered in the first conduction path described above and the second conduction path described below. in Filter inductor L F Output voltage regulator capacitor C F and output load resistance R F Let's continue with the following... Figure 2 illustrate.

[0056] like Figure 2 As shown, in the fourth time period (i.e., t2~t4), at t2, the resonant inductor L flows... r instantaneous current i r Greater than the current flowing through the filter inductor L F Current I F (i.e., load current), first main switch S m1 Parasitic capacitance and resonant inductance L r Resonance occurs, and after half the resonance period, at t4, the first main switch S is controlled. m1The voltage rises to V out Resonant inductance L r instantaneous current i r At t3, the forward current peak is reached and is increased to the level of the filter inductor L. F Current I F The sum of the resonant currents generated by the parasitic capacitance of the main switching transistor, I rmax .

[0057] As one implementation method, the resonant inductance L in the fourth time period r Peak forward current I rmax It satisfies the following formula (2).

[0058] (2)

[0059] in, The resonant inductance L represents the fourth time period. r The peak value of the forward current. The filter inductance L represents the second time period. F The current. This represents the output voltage of the auxiliary resonant commutator inverter unit during the second time period. Indicates the first main switch transistor S m1 Parasitic capacitance or second main switch S m2 Parasitic capacitance. Represents the resonant inductance L r The inductance.

[0060] The above resonant inductor L r The inductance will directly affect the first auxiliary switch S a1 Second auxiliary switch S a2 The operating time and losses. In the resonant inductor L... r When operating at low frequencies, a larger inductance will cause the resonant inductance L to... r instantaneous current i r The rise is relatively slow, therefore, the impact on the operating state of the auxiliary resonant commutator inverter unit is relatively small. Conversely, the lower resonant inductance L... r The rate of change of current is beneficial to the first auxiliary switch S a1 Second auxiliary switch S a2 Zero-current turn-on. Furthermore, according to formula (2), a larger resonant inductance L... r The inductance can reduce the peak forward current of the resonant current, as well as the additional losses caused by the resonant current. Therefore, the limiting factor for the resonant inductance L is... r Factors affecting inductance may include inductance loss due to resonant current, and resonant inductance L. rThe saturation current and the volume required for the integration of the auxiliary resonant commutator inverter unit. The first auxiliary switch S... a1 Turn on to the second main switch S m2 The time between switching on and off can include the resonant inductance L r The linear rise time of the current and the duration corresponding to half the resonant period. The resonant inductor L mentioned above... r It features low loss, small size and easy integration.

[0061] As one implementation method, the resonant inductor L r The linear rise time of the current can satisfy the following formula (3).

[0062] (3)

[0063] in, Represents the resonant inductance L r The linear rise time of the current. This represents the output voltage of the auxiliary resonant commutator inverter unit. Represents the resonant inductance L r The inductance. Indicates the filter inductance L F The current.

[0064] As one implementation method, the duration corresponding to half of the resonance period satisfies the following formula (4).

[0065] (4)

[0066] in, This indicates the duration corresponding to half of the resonance period. Represents the resonant inductance L r The inductance. Indicates the first main switch transistor S m1 Parasitic capacitance or second main switch S m2 Parasitic capacitance.

[0067] Because the main switching transistor selected in the relevant technology has a large parasitic capacitance, therefore, the first main switching transistor S m1 Second main switch S m2 It has high switching losses and large parasitic capacitance, which leads to high switching losses in the first main switch S m1 Second main switch S m2 During hard turn-on, more charge flows through the switch, increasing turn-on losses. In the first main switch S... m1 Second main switch S m2 Under zero-voltage turn-on conditions (due to the first main switch transistor S) m1(Since the parasitic diode is conducting, it must be zero-voltage turn-on.) A large parasitic capacitance will not cause the first main switch S to conduct. m1 Second main switch S m2 This results in higher turn-on losses and reduces the first main switch S. m1 Second main switch S m2 The voltage rise rate during the turn-off process reduces the voltage of the first main switch S to some extent. m1 Second main switch S m2 The shutdown loss.

[0068] As one implementation method, such as Figure 1A As shown, the control module can also control the second main switch S in the fourth time period. m2 Second auxiliary switch S a2 Turn off, and the first auxiliary switch S a1 Turn on so that the second main switch S can be activated. m2 Parasitic capacitance and resonant inductance L r First auxiliary switch S a1 The conduction channel, the second auxiliary switch S a2 The parasitic diode and the path of the second split capacitor C2 form a resonant current, which constitutes the second conduction path in the fourth time period. For ease of understanding, the following will combine... Figure 1M Explain the second conduction path. Figure 1M A schematic diagram of the second conduction path during the fourth time period according to an embodiment of this application is shown. Figure 1M As shown, Figure 1M The second conduction path is highlighted above, with red arrows indicating the direction of current flow in the devices, and red lines indicating the devices through which current flows in the second conduction path. The following continues in conjunction with... Figure 2 illustrate.

[0069] like Figure 2 As shown, in the fourth time period (i.e., t2~t4), at t2, the resonant inductor L flows... r instantaneous current i r Greater than the current flowing through the filter inductor L F Current I F (i.e., load current), second main switch S m2 Parasitic capacitance and resonant inductance L r Resonance occurs, and after half the resonance period, at t4, the second main switch S is controlled. m2 The voltage drops to zero.

[0070] According to embodiments of this application, by forming a resonant current through the parasitic capacitance of the second main switch, the resonant inductance, the conduction channel of the first auxiliary switch, the parasitic diode of the second auxiliary switch, and the path of the second split capacitor, the turn-on loss of the second main switch can be reduced, the voltage output efficiency of the auxiliary resonant commutator inverter unit can be improved, the voltage and current stress distribution can be optimized, and the electromagnetic interference experienced by the auxiliary resonant commutator inverter unit can be reduced.

[0071] In addition, such as Figure 1A and Figure 2 As shown, at t4, the second main switch S m2 When the voltage drops to zero, it is necessary to precisely turn on the second main switch S. m2 This effectively avoids missing the switching timing and causing the second main switch transistor S to fail. m2 The voltage recovers. In practical design, a very small first base voltage is introduced as a soft-switching condition, and the second main switch S... m2 The second main switch S can be turned on when the voltage across its terminals drops below the first base voltage. m2 In the second main switch S m2 The resonant inductor L is conducting and during the fifth time period (t5~t6). r instantaneous current i r Disappears at t5, resonant inductance L r The instantaneous current disappears, and the second auxiliary switch S... a2 The parasitic diode stops conducting, and the second auxiliary switch S... a2 The voltage across the parasitic diode rises. After t5, that is, after the second auxiliary switch S... a2 When the voltage is not zero, the first auxiliary switch S a1 It can then be turned off, thus, in the second main switch S m2 Turn off the first auxiliary switch S before turning off. a1 That's it. Therefore, we can deduce that the second main switch transistor S... m2 Zero-voltage turn-on can be achieved. The first auxiliary switch S... a1 It achieves zero-current soft turn-on and zero-current soft turn-off.

[0072] As one implementation method, the auxiliary resonant commutator inverter unit can also include a detection module. The following section will discuss this further. Figure 1A and Figure 3 illustrate. Figure 3 A schematic diagram of another auxiliary resonant commutator inverter unit according to an embodiment of this application is shown. Figure 3 and Figure 1A The difference is that, Figure 3 A detection module has been added.

[0073] like Figure 1A and Figure 3 As shown, the auxiliary resonant commutator inverter unit may further include a detection module. The first output terminal of the detection module can be electrically connected to the first input terminal of the control module. The second output terminal of the detection module can be electrically connected to the second input terminal of the control module. The third input terminal of the control module can be electrically connected to the external input PWM_IN. The fourth input terminal of the control module can be connected to the first base voltage V. ref_ZVS Electrical connection.

[0074] The detection module can be based on the second main switch S m2 The first detection voltage is obtained by the voltage between the first and second electrodes. The detection module can send the first detection voltage to the control module via the first output terminal of the detection module and the first input terminal of the control module. Optionally, the detection module can determine the first detection voltage based on the voltage between the second auxiliary switch S. a2 The voltage between the first and second electrodes is used to obtain the second detection voltage. The detection module can send the second detection voltage to the control module via the second output terminal of the detection module and the second input terminal of the control module.

[0075] In the second or fourth time period, when the external input PWM_IN is high, the first detection voltage is greater than the first base voltage, and the second detection voltage is less than the first base voltage, the control module can output a low level at its first control terminal, a high level at its second control terminal, and a low level at its third control terminal, so that the first auxiliary switch S... a1 On, and the second auxiliary switch S a2 Second main switch S m2 Turn off.

[0076] The fact that the first detection voltage is greater than the first base voltage indicates that the second main switch S m2 If the voltage exceeds the predetermined voltage range, it can easily cause turn-on losses. Therefore, measures need to be taken to reduce the voltage of the second main switch transistor S. m2 This results in turn-on losses. To address this, the control module outputs a low level at its first control terminal, a high level at its second control terminal, and a low level at its third control terminal, so that the first auxiliary switch S... a1 On, and the second auxiliary switch S a2 Second main switch S m2 Turning off, thus allowing current to flow to the first auxiliary switch S. a1 To protect the second main switch transistor S m2 .

[0077] According to an embodiment of this application, the need for protection of the second main switch is determined based on the first detection voltage. This allows for timely blocking of current flowing to the second main switch, thereby protecting it, reducing turn-on losses, and extending its service life.

[0078] As one implementation method, such as Figure 1A and Figure 3 As shown, the auxiliary resonant commutator inverter unit may also include a detection module.

[0079] The third output terminal of the detection module can be electrically connected to the sixth input terminal of the control module. The fourth output terminal of the detection module can be electrically connected to the fifth input terminal of the control module. The seventh input terminal of the control module can be connected to the second base voltage V. ref_cap Electrical connection.

[0080] The detection module can obtain a third detection voltage based on the voltage between the first and second terminals of the first split capacitor C1. Optionally, the detection module can obtain a fourth detection voltage based on the voltage between the first and second terminals of the second split capacitor C2.

[0081] The aforementioned second base voltage, third detection voltage, fourth detection voltage, first base voltage, first detection voltage, and second detection voltage have all undergone additional isolation processing and have been converted to the same reference potential to facilitate subsequent calculations.

[0082] The control module can also, in the first time period, respond to the external input PWM_IN being low and the fourth detection voltage being greater than the third detection voltage, control the first control terminal of the control module to output a high level, the second control terminal to output a low level, and the third control terminal to output a high level, so that the second main switch S m2 Second auxiliary switch S a2 The first auxiliary switch S is turned on. a1 Turn off.

[0083] If the fourth detection voltage is greater than the third detection voltage, it indicates that there is a voltage difference between the first split capacitor C1 and the second split capacitor C2. This voltage difference is greater than the second base voltage V. ref_cap In this case, it is necessary to compensate for the voltage deviation generated by the first split capacitor C1 and the second split capacitor C2 during the operation of the auxiliary resonant commutator inverter unit. For this purpose, it is necessary to output a high level at the first control terminal of the control module, a low level at the second control terminal, and a high level at the third control terminal, so that the second main switch S... m2 Second auxiliary switch S a2 The first auxiliary switch S is turned on. a1When the circuit is turned off, the voltages of the first split capacitor C1 and the second split capacitor C2 become equal, or the voltage across the first split capacitor C1 is slightly higher than the voltage across the second split capacitor C2, allowing the circuit to operate normally.

[0084] According to an embodiment of this application, the need to compensate for the voltage deviation generated by the first and second split capacitors during the operation of the auxiliary resonant commutator inverter unit is determined based on the magnitude between the third and fourth detection voltages. This allows for timely detection of the neutral point potential change during the operation of the auxiliary resonant commutator inverter unit, thereby ensuring the unit is in a voltage equalization state and improving the stability and reliability of the voltage output.

[0085] As one implementation method, such as Figure 1A , Figure 2 and Figure 3 As shown, the control module can also, in the third time period, respond to the external input PWM_IN being low, control the first control terminal of the control module to output a low level, the second control terminal of the control module to output a low level, and the third control terminal of the control module to output a high level, so that the second auxiliary switch S a2 On, and the second main switch S m2 and the first auxiliary switch S a1 Turn off.

[0086] During the first time period (t6~t7), while the first split capacitor C1 is continuously charging and the second split capacitor C2 is continuously discharging, the current flowing through the resonant inductor L... r instantaneous current i r The current increases linearly, reaching a negative peak at t7. Therefore, in the third time period (t7~t8), the resonant inductor L needs to be adjusted. r instantaneous current i r The linear decrease until it disappears is achieved to realize the second auxiliary switch S. a2 Zero-current shutdown.

[0087] According to an embodiment of this application, when the parasitic diode of the second auxiliary switch ends its conduction, the parasitic diode of the second auxiliary switch withstands a reverse voltage, achieving zero-current turn-off of the first auxiliary switch. This reduces the turn-off loss of the first auxiliary switch when it is off.

[0088] It should be noted that, since the external input PWM_IN is the externally expected second main switch S... m2 The drive is based on the first main switch S in the half-bridge circuit. m1 Second main switch S m2 The principle that they will not be activated simultaneously is based on the assumption that during the aforementioned time periods, the first main switch S...m1 The conduction channel is not conductive. Therefore, the first main switch S... m1 The conduction channel needs to be turned off in the second time period. In the off state, the first main switch S... m1 The parasitic diode is still conducting current. If the first main switch transistor S... m1 If it is an insulated-gate bipolar transistor, then in boost mode, the first main switch S m1 It can be used as a diode, but is not turned on. In this case, it is connected via the resonant inductor L. r The current is diverted and flows through the first main switch transistor S. m1 The conduction current of the parasitic diode gradually decreases to zero.

[0089] To facilitate understanding, the following will be combined with... Figure 4 The control module described in the embodiments of this application will be used for illustration.

[0090] Figure 4 A schematic diagram of the control module according to an embodiment of this application is shown.

[0091] like Figure 4 As shown, according to the timing requirements of the control scheme proposed in the embodiments of this application, it is divided into controlling the first auxiliary switch S. a1 The first logic unit of the state and the second main switch S in the control compensation behavior m2 Second auxiliary switch S a2 The second logic unit. Therefore, the control module may include a first logic unit and a second logic unit.

[0092] The first logic unit may include a first AND gate AND1, a second AND gate AND2, a NOT gate NOT, a first comparator Q1, a first delay DLAY1, a first OR gate OR1, and a second comparator Q2.

[0093] The second logic unit may include a subtractor OPA, a third comparator Q3, a second OR gate OR2, a third AND gate AND3, a third OR gate OR3, a second delay DLAY2, an XOR gate XOR, a third delay DLAY3, and a fourth AND gate AND4.

[0094] The first delay unit DLAY1, the second delay unit DLAY2, and the third delay unit DLAY3 can be shutdown delay units. The second delay unit DLAY2 can generate the first shutdown delay signal, the third delay unit DLAY3 can generate the second shutdown delay signal, and the first delay unit DLAY1 can generate the third shutdown delay signal.

[0095] PWM_IN is an external input. CE_Sm2_clamp For the second main switch S m2 The first detection voltage (i.e., v)CE_Sm2_clamp For the second main switch S m2 (Voltage clamping detection signal). v DS_Sa2_clamp For the second auxiliary switch S a2 The second detection voltage (i.e., v) DS_Sa2_clamp For the second auxiliary switch S a2 (The voltage clamping detection signal). It should be noted that, in Figure 4 In the embodiment shown, the first detection voltage and the second detection voltage are subjected to v CE and v DS The reason for the distinction is that: v indicates that the voltage is a changing quantity, and the first main switch S m1 Second main switch S m2 Using IGBT, the first main switch transistor S m1 Second main switch S m2 The first electrode is the collector (C), and the second electrode is the emitter (E). The first auxiliary switch S... a1 Second auxiliary switch S a2 Using MOSFETs, the first auxiliary switch S a1 Second auxiliary switch S a2 The first electrode is the drain (D), and the second electrode is the source (S). V ref_ZVS This is the first base voltage. V ref_cap This is the second base voltage. C1 This is the third detection voltage (i.e., the voltage between the first and second terminals of the first split capacitor C1). C2 This is the fourth detection voltage (i.e., the voltage between the first and second terminals of the second split capacitor C2). PWM_S a2 For the second auxiliary switch S a2 The controller pole drives the PWM. PWM_S a1 The first auxiliary switch S a1 The controller pole drives the PWM. PWM_S m2 For the second main switch S m2 The control electrode drives the PWM.

[0096] The first input terminal of the first AND gate can be electrically connected to an external input. The first input terminal of the second AND gate can be electrically connected to an external input. The output terminal of the second AND gate can be electrically connected to the control electrode of the first auxiliary switch.

[0097] The output of the NOT gate can be electrically connected to the second input of the first AND gate. The positive input of the first comparator can be electrically connected to the first output of the detection module. The negative input of the first comparator can be electrically connected to the first base voltage. The output of the first comparator can be electrically connected to the input of the NOT gate.

[0098] The input terminal of the first delay unit can be electrically connected to the output terminal of the first comparator.

[0099] The first input terminal of the first OR gate can be electrically connected to the output terminal of the first delay unit. The output terminal of the first OR gate can be electrically connected to the second input terminal of the second AND gate.

[0100] The positive input of the second comparator can be electrically connected to the first base voltage. The negative input of the second comparator can be electrically connected to the second output of the detection module. The output of the second comparator can be electrically connected to the second input of the first OR gate.

[0101] The non-inverting input of the subtractor can be connected to the fourth detection voltage. The negative-inverting input of the subtractor can be electrically connected to the third detection voltage.

[0102] The positive input of the third comparator can be electrically connected to the output of the subtractor. The negative input of the third comparator can be electrically connected to the second base voltage.

[0103] The first input terminal of the second OR gate can be electrically connected to the output terminal of the third comparator. The second input terminal of the second OR gate can be electrically connected to the control electrode of the second auxiliary switch.

[0104] The first input terminal of the third AND gate can be electrically connected to the output terminal of the second OR gate. The first input terminal of the third OR gate can be electrically connected to the output terminal of the third AND gate. The second input terminal of the third OR gate can be electrically connected to the output terminal of the first AND gate. The output terminal of the third OR gate can be electrically connected to the control electrode of the second main switch.

[0105] The input of the second delay unit can be electrically connected to an external input. The output of the second delay unit can be electrically connected to the second input of the third AND gate.

[0106] The first input of the XOR gate can be electrically connected to the output of the second delay. The second input of the XOR gate can be electrically connected to an external input.

[0107] The input of the third delay unit can be electrically connected to the output of the XOR gate.

[0108] The first input terminal of the fourth AND gate can be electrically connected to the output terminal of the second OR gate and the first input terminal of the third AND gate. The second input terminal of the fourth AND gate can be electrically connected to the output terminal of the third delay unit. The output terminal of the fourth AND gate can be electrically connected to the control electrode of the second auxiliary switch.

[0109] The control logic of the embodiments of this application will be described in general below. A zero-voltage turn-on auxiliary function is provided to accommodate the operation of the main phase arm by only providing a zero-voltage turn-on auxiliary function when a hard switch is performed on the corresponding main switch (e.g., the second main switch). If the main phase arm can achieve zero-voltage turn-on on its own, for example, in the case of boundary mode turn-on, the auxiliary switch (e.g., the first or second auxiliary switch) will remain in standby mode. If the zero-voltage turn-on auxiliary function is determined, the control logic can provide appropriate drive outputs not only to the auxiliary switch but also to the main switch. This is because the turn-on time of the main switch should be delayed until the auxiliary switch completes the ZVS process. In summary, the embodiments of this application address the first auxiliary switch S... a1 The control logic of the first logic unit is as follows: the control module controls the external input PWM_IN and the second auxiliary switch S. a2 The voltage between the first and second terminals and the second main switch S m2 The voltage between the first and second terminals is processed logically, and the first auxiliary switch S is controlled based on the processing result. a1 The state of the second main switch S in this embodiment. m2 With the second auxiliary switch S a2 The control logic of the second logic unit is as follows: The control module controls the external input PWM_IN, the voltage across the first split capacitor C1, the voltage across the second split capacitor C2, and the second auxiliary switch S. a2 The control input and the output of the first AND gate in the first logic unit are processed logically, and the second main switch S is controlled based on the processing result. m2 Second auxiliary switch S a2 The state.

[0110] Table 1 shows the truth table of some devices in the first logic unit according to an embodiment of this application. T represents true, and F represents false. For ease of writing, the influence of the first delay is ignored in this table; only the scheme using the second comparator is considered. The duration of the first delay can be considered as 0.

[0111] Table 1

[0112] The first input terminal of the first AND gate The output of the first comparator The output of the second comparator The output of the first AND gate The output of the second AND gate T T T F T T T F F T T F T T T T F F T F F T T F F F T F F F F F T F F F F F F F

[0113] Table 2 shows the truth tables of some devices in the first and second logic units according to embodiments of this application. Wherein, T represents true, and F represents false.

[0114] Table 2

[0115] The output of the third comparator The second input of the second OR gate The second input terminal of the third AND gate The output of the first AND gate The output of the third OR gate T T T T T T T T F T T T F T T T T F F F T F T T T T F T F T T F F T T T F F F F F T T T T F T T F T F T F T T F T F F F F F T T T F F T F F F F F T T F F F F F

[0116] As shown in Tables 1 and 2, during the first time period, when the second input terminal of the first AND gate, the output terminal of the second comparator, the output terminal of the third comparator, the second input terminal of the second OR gate, the second input terminal of the third AND gate, the second input terminal of the fourth AND gate, and the output terminal of the third AND gate are all at high levels, and the first input terminal and the output terminal of the first AND gate are both at low levels, the output terminal of the third OR gate outputs a high level, the output terminal of the fourth AND gate outputs a high level, and the output terminal of the second AND gate outputs a low level. Thus, the output terminal of the third OR gate controls the second main switch to turn on, the output terminal of the fourth AND gate controls the second auxiliary switch to turn on, and the output terminal of the second AND gate controls the first auxiliary switch to turn off.

[0117] During the second time period, when both the first input of the first AND gate and the output of the first comparator are at high levels, and the output of the first AND gate is at a low level, the output of the second AND gate, the output of the second comparator, the output of the first OR gate, and the output of the second AND gate are all at high levels. Therefore, the output of the second AND gate controls the first auxiliary switch to turn on.

[0118] During the third time period, when the output of the first comparator is high and the first input of the first AND gate is low, the output of the first AND gate is low, the output of the fourth AND gate is high, and the outputs of the third OR gate and the second AND gate are both low. Thus, the output of the fourth AND gate controls the second auxiliary switch to turn on, the output of the third OR gate controls the second main switch to turn off, and the output of the second AND gate controls the first auxiliary switch to turn off.

[0119] In the fourth time period, assuming the voltage distribution of the split capacitors is uniform, and approaching t4 (before the first detected voltage is less than the first base voltage), the output of the third comparator is low, and the second input of the second OR gate is also low. When the first input of the first AND gate, the output of the first comparator, the output of the second comparator, and the output of the first OR gate are all high, and the second input and output of the first AND gate are both low, the outputs of the third OR gate and the fourth AND gate are both low, and the output of the second AND gate is high. Therefore, the output of the third OR gate controls the second main switch to turn off, the output of the fourth AND gate controls the second auxiliary switch to turn off, and the output of the second AND gate controls the first auxiliary switch to turn on.

[0120] The voltage between the first and second terminals of the main switch (e.g., the voltage between the first and second terminals of the second main switch) is used as an independent condition to determine whether the second main switch in the auxiliary resonant commutation inverter unit has reached the soft-switching condition. The first delay after the first comparator ensures that the auxiliary switch (e.g., the first auxiliary switch) is turned off after the main switch is turned on and the instantaneous current of the resonant inductor disappears, eliminating the influence of the switching time of different devices and reducing the loss of the first auxiliary switch.

[0121] When the output of the third comparator is high, the auxiliary resonant commutator inverter unit reaches the uneven voltage condition. Under this condition, regardless of whether the second input of the second OR gate is high or low, the output of the second OR gate will always be high. The second delay circuit generates a first turn-off delay signal, which adds a turn-off delay to the external input PWM_IN signal. The pulse width of the first turn-off delay signal is greater than that of the external input PWM_IN signal. However, the pulse width of the output signal of the first AND gate is always less than that of the external input PWM_IN signal. Therefore, the pulse width of the first turn-off delay signal is greater than that of the output signal of the first AND gate. That is, under normal operating conditions, if the first turn-off delay signal is low, the first AND gate will always output a low level; if the first AND gate always outputs a high level, the first turn-off delay signal will always output a high level. Therefore, under normal operating conditions, the situation in Table 2 where the second input of the third AND gate is low and the output of the first AND gate is high does not exist. This situation is only used to improve fault analysis. Therefore, when the output of the second OR gate is high, the output waveform of the third OR gate is the same as the first turn-off delay signal waveform, regardless of the output of the first AND gate. This method avoids the problem that it is difficult to achieve soft switching conditions through resonance under uneven voltage conditions, thus preventing the first AND gate from always outputting a low level and making it difficult to turn on the second main switch.

[0122] If the output of the third comparator is low, that is, the first input of the second OR gate is low, then when the second auxiliary switch is not turned on (that is, the output of the fourth AND gate is low, that is, the second input of the second OR gate is low), both the first and second inputs of the second OR gate are low, and the output of the second OR gate is low.

[0123] In the above situation, when the output of the third AND gate is low, the first input of the fourth AND gate is also low, thus causing the output of the fourth AND gate to be low, and therefore the second auxiliary switch does not operate.

[0124] If the output of the third comparator is low, then with the second auxiliary switch already turned on, the output of the second OR gate will be high. This is the same as the output of the third comparator being high, maintaining the drive of the second auxiliary switch (i.e., the output of the fourth AND gate is high). The above application scenario ensures that after resolving the voltage equalization issue during compensation, the second auxiliary switch remains active until the end of the current compensation process (i.e., the moment the second delay signal generated by the third delay unit is low). The second delay signal is a fixed-width drive signal generated by an external input PWM_IN, and its pulse width is the sum of the delays of the second and third delay units. Figure 2 The sum of the first and third time periods (i.e., t6~t8) is used to avoid modal confusion.

[0125] According to embodiments of this application, the second auxiliary switch, the first auxiliary switch, and the second main switch are controlled by the first and second logic units of the control module. This allows for precise control of the operation of the auxiliary resonant commutator inverter unit, reduces the switching losses of the second main switch, and improves the voltage equalization adjustment accuracy of the first and second split capacitors, thereby increasing the operating efficiency of the auxiliary resonant commutator inverter unit.

[0126] By using the voltage detection of the second auxiliary switch (i.e. signal one) and whether the second main switch has reached the soft-switching condition (i.e. signal two), the two signals are ORed as the switching condition of the first auxiliary switch, so as to realize that the first auxiliary switch is turned off after the instantaneous current of the resonant inductor has disappeared.

[0127] When the instantaneous current of the resonant inductor is present, the voltage of the second auxiliary switch is 0, and the output of the second comparator is high. At the moment the instantaneous current of the resonant inductor disappears (i.e.,...) Figure 2 (t5), the output of the second comparator is low. This allows for precise turn-off of the first auxiliary switch. To eliminate potential additional problems such as parameter design issues, premature turn-off, or device failure, a second main switch S is used. m2 Voltage clamping detection signal v CE_Sm2_clamp (i.e., the second main switch S) m2 The first detection voltage v CE_Sm2_clamp When the voltage of the second main switch is 0, the output of the first comparator is low, and after passing through the first delay, it is transmitted to the first OR gate.

[0128] The output signal of the first OR gate represents the signal that goes low later (i.e., has a longer pulse width) of the two signals. Therefore, its function can be: if the set delay is short (e.g., ...), Figure 2 (t4~t5), then through the second auxiliary switch Sa2 Voltage detection enables precise turn-on. If the set delay allows the signal to be maintained at... Figure 2 If t5~t6 are still at a high level, then this signal determines the turn-off time of the first auxiliary switch. The two signals mentioned above serve as mutual protection.

[0129] Setting the input of the compensation logic control unit (i.e., the second auxiliary switch) to the external input PWM_IN instead of the output of the first AND gate is intended to address the situation where, due to uneven voltage distribution in the auxiliary resonant commutator inverter unit and excessively high voltage across the second split capacitor, the minimum voltage of the second main switch is difficult to achieve during the resonance process to meet the soft-switching condition. In such cases, the output of the first AND gate remains low, making it difficult to turn on the second main switch and trigger compensation behavior to resolve the voltage distribution problem. Consequently, the voltage across the second split capacitor becomes too high, the second main switch does not conduct, and the auxiliary resonant commutator inverter unit cannot operate normally.

[0130] Each input to PWM_IN generates a signal carrying a turn-off delay. If there is no voltage imbalance in the auxiliary resonant commutator inverter unit, the voltage imbalance signal, i.e., the output of the third comparator, will be low. In this case, if PWM_S a2 A low output indicates that the second auxiliary switch is not turned on, meaning the second input of the second OR gate is low. Therefore, the second OR gate outputs a low level. A third AND gate performs an AND operation on the signal carrying the turn-off delay (the first delay signal) and the output signal of the second OR gate, resulting in a low output from the third AND gate. The output waveform of the third OR gate is the same as that of the first AND gate. In the case of uneven voltage signals in the auxiliary resonant commutator inverter unit, the output signal of the third AND gate is the same as the waveform of PWM_IN with an added turn-off delay, exhibiting the following characteristics: Figure 2 The signal is high during times t1~t6 and low at other times. This signal, after being ORed, is output as the output signal of the third OR gate to the second main switch S. m2 Therefore, it is possible to force the second main switch to turn on regardless of whether voltage equalization is achieved or even if the soft-switching condition is not met. The second auxiliary switch functions similarly, enabling compensation actions without considering whether the second main switch has met the soft-switching condition in the case of voltage unequalization.

[0131] In addition, such as Figures 1A to 1M and Figure 3 As shown, the aforementioned auxiliary resonant commutator inverter unit may further include an output voltage regulator capacitor C. F and output load resistance R F .

[0132] Output voltage regulator capacitor C FThe first terminal is electrically connected to the first terminal of the first split capacitor C1 and the second terminal of the second split capacitor C2. The output load resistor R... F The first terminal is connected to the output voltage regulator capacitor C. F The first terminal is electrically connected to the output load resistor R. F The second terminal is connected to the output voltage regulator capacitor C. F The second end is electrically connected.

[0133] It should be noted that the output voltage V of the auxiliary resonant commutator inverter unit in this embodiment is... out For the output voltage regulator capacitor C F With output load resistor R F The voltage across the terminals. Output voltage regulator capacitor C. F Large capacitance value, output voltage V out Basically unchanged. Output load resistance R F It can be used for other types of power loads. Output load resistance R F The voltage and current remain constant, and the output power remains constant. This is in addition to maintaining the output load resistance R. F Besides the current generated in the output power, the current flow direction generated in the second, third, and fourth time periods is all related to the output voltage regulator capacitor C. F related.

[0134] The technical effects of the auxiliary resonant commutator inverter unit provided in the embodiments of this application will be described in general below.

[0135] The auxiliary resonant commutator inverter unit of this application is based on the voltage equalization method of high-frequency transformer, which solves the problem of uneven capacitor voltage in DC-DC operation mode. As a result, it not only improves the reliability of the auxiliary resonant commutator inverter unit, but also reduces the dependence on external components, thereby reducing cost and size.

[0136] The auxiliary resonant commutator inverter unit in this application embodiment achieves precise control of the soft-switching process based on an adaptive control strategy using logic device combinations. By employing adaptive dead-time adjustment or intelligent compensation current injection, the challenge of maintaining soft-switching characteristics within a wide load range for the auxiliary resonant commutator inverter unit is solved.

[0137] The auxiliary resonant commutator inverter unit of this application integrates the entire soft-switching topology into a compact control unit, which improves practicality and portability. The above-mentioned modular design makes the auxiliary resonant commutator inverter unit provided in this application easy to apply to various power conversion scenarios.

[0138] The following is combined with Figure 5 Table 3 illustrates the simulation experiment of the auxiliary resonant commutator inverter unit.

[0139] Table 3 shows the device selection table for simulation tests according to embodiments of this application.

[0140] Table 3

[0141] parameter Selection <![CDATA[V in ]]> 100V <![CDATA[V out ]]> 200V <![CDATA[L r ]]> 3.3μH <![CDATA[C r ]]> 1nF <![CDATA[L F ]]> 1mH <![CDATA[C F ]]> 30μF <![CDATA[I F ]]> 20A <![CDATA[C1、C2]]> 30μF

[0142] Figure 5 The simulation waveform of an auxiliary resonant commutator inverter unit according to an embodiment of this application is shown.

[0143] like Figure 5 As shown, when the energy of a single-cycle compensation action of the auxiliary resonant commutator inverter unit is greater than the unbalanced energy of the resonant process, the compensation action will be performed once every fixed interval to correct the voltage across the first and second split capacitors back to the normal value.

[0144] The following is combined with Figures 6-8 The operation experiment of the auxiliary resonant commutator inverter unit is described. Specifically, oscilloscope waveforms are shown.

[0145] Figure 6 A schematic diagram showing the experimental results of an auxiliary resonant commutator inverter unit according to an embodiment of this application is provided.

[0146] like Figure 6 As shown, under the operating conditions of an output voltage of 30V, an output power of 20W, a soft-switching threshold voltage of 10V, and a voltage equalization threshold of 2.5V, the auxiliary resonant commutator inverter unit can normally achieve soft switching. Figure 6 In the diagram, 25V / div indicates 25V per cell on the oscilloscope. 5V / div indicates 5V per cell on the oscilloscope. 0.5A / div indicates 0.5A per cell on the oscilloscope. A cell represents the interval between the two white dashed lines. Therefore, because... Figure 6 The second main switch S is characterized in the middle. m2 Each cell of the yellow curve representing the voltage across the two terminals is 25V, and the second main switch transistor S... m2 The switching voltage occupies approximately 1.2 cells; therefore, the second main switch S... m2 The voltage across its two ends is 30V. Figure 6 The green curve representing the voltage across the second split capacitor C2 has the same reference potential as the yellow curve, and the indicated voltage is approximately half that of the yellow curve. Therefore, the voltage across the second split capacitor C2 is 15V. This demonstrates that the voltage equalization effect of the auxiliary resonant commutator inverter unit can be achieved.

[0147] Figure 7 A schematic diagram of the operational experimental results of another auxiliary resonant commutator inverter unit according to an embodiment of this application is shown.

[0148] like Figure 7As shown, when the voltage across the second split capacitor C2 is greater than the voltage equalization threshold (i.e.) Figure 7 The green curve shows upward fluctuations, but due to the relatively small second base voltage setting and high voltage equalization, the voltage imbalance is not obvious. The auxiliary resonant commutator inverter unit will initiate compensation, and the compensation action will occur in the resonant inductor L. r A negative current is generated, and during the period when the absolute value of the negative current increases, it passes through the second main switch S. m2 In the second main switch S m2 When turned off, the negative current disappears slowly. After the compensation operation of the auxiliary resonant commutator inverter unit, the voltage across the second split capacitor C2 decreases, and the positive resonant current generated during the turn-on process of the auxiliary resonant commutator inverter unit increases significantly. Other similar explanations can be found in [reference needed]. Figure 6 This will not be elaborated upon here.

[0149] exist Figure 7 On this basis, Figure 8 An embodiment according to this application is shown. Figure 7 A magnified schematic diagram of the experimental results of the auxiliary resonant commutator inverter unit.

[0150] like Figure 8 As shown, Figure 8 for Figure 7 Enlarged views of some of the experimental results. (Targeting...) Figure 8 For further explanation, please refer to Figure 7 This will not be elaborated upon here.

[0151] The embodiments of this application also provide an auxiliary resonant commutator inverter method that can be applied to an auxiliary resonant commutator inverter unit.

[0152] The auxiliary resonant commutator inverter method can include the following operations.

[0153] During the first time period, the second main switch and the second auxiliary switch are turned on, and the first auxiliary switch is turned off, so as to conduct the path through the second split capacitor, the conduction channel of the second auxiliary switch, the parasitic diode of the first auxiliary switch, the resonant inductor, the conduction channel of the second main switch, and back to the second split capacitor, as well as the path through the positive terminal of the output voltage to the first split capacitor, the conduction channel of the second auxiliary switch, the parasitic diode of the first auxiliary switch, the conduction channel of the second main switch, and the negative terminal of the output voltage.

[0154] For a description of the auxiliary resonant commutator inverter method, please refer to the description of the auxiliary resonant commutator inverter unit in the embodiments of this application above, which will not be repeated here.

[0155] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0156] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. An auxiliary resonant commutator inverter unit, characterized in that, include: First auxiliary switch transistor; A resonant inductor, wherein the first end of the resonant inductor is electrically connected to the first electrode of the first auxiliary switch transistor; A filter inductor, wherein the first terminal of the filter inductor is electrically connected to the positive terminal of the power supply voltage, and the second terminal of the filter inductor is electrically connected to the second terminal of the resonant inductor; The second terminal of the first main switch is electrically connected to the second terminal of the resonant inductor and the second terminal of the filter inductor. The second main switch transistor has its first terminal electrically connected to the second terminal of the resonant inductor, the second terminal of the filter inductor, and the second terminal of the first main switch transistor. The second terminal of the second main switch transistor is electrically connected to the negative terminal of the power supply voltage. The first split capacitor has its first terminal electrically connected to the first terminal of the first main switch and the positive terminal of the output voltage. The second auxiliary switch has its first terminal electrically connected to the second terminal of the first split capacitor, and its second terminal electrically connected to the second terminal of the first switch. The second split capacitor has its first terminal electrically connected to the second terminal of the first split capacitor and the first electrode of the second auxiliary switch, and its second terminal electrically connected to the second electrode of the second main switch, the negative electrode of the power supply voltage, and the negative electrode of the output voltage. as well as The control module has a first control terminal electrically connected to the control electrode of the second main switch, a second control terminal electrically connected to the control electrode of the first auxiliary switch, and a third control terminal electrically connected to the control electrode of the second auxiliary switch. It is configured to control the second main switch and the second auxiliary switch to be turned on and the first auxiliary switch to be turned off during a first time period. This is to enable the conduction of a path through the second split capacitor, the conduction channel of the second auxiliary switch, the parasitic diode of the first auxiliary switch, the resonant inductor, and the conduction channel of the second main switch, returning to the second split capacitor, and a path through the positive terminal of the output voltage to the first split capacitor, the conduction channel of the second auxiliary switch, the parasitic diode of the first auxiliary switch, the conduction channel of the second main switch, and the negative terminal of the output voltage.

2. The auxiliary resonant commutator inverter unit according to claim 1, characterized in that, The control module is further configured to control the first auxiliary switch to be turned on, the second auxiliary switch to be turned off, and the second main switch to be turned off during a second time period, so that the current through the first main switch is reduced to a predetermined value, and the path through the resonant inductor, the conduction channel of the first auxiliary switch, the parasitic diode of the second auxiliary switch, the second split capacitor, and the negative terminal of the power supply voltage, as well as the path through the resonant inductor, the conduction channel of the first auxiliary switch, the parasitic diode of the second auxiliary switch, the first split capacitor, and the positive terminal of the output voltage are turned on.

3. The auxiliary resonant commutator inverter unit according to claim 1 or 2, characterized in that, The control module is further configured to control the second auxiliary switch to be turned on and the second main switch and the first auxiliary switch to be turned off during a third time period, so as to open the path through the second split capacitor to the conduction channel of the second auxiliary switch, the parasitic diode of the first auxiliary switch, the parasitic diode of the first main switch and the positive terminal of the output voltage, and to open the path through the first split capacitor to the conduction channel of the second auxiliary switch, the parasitic diode of the first auxiliary switch and the parasitic diode of the first main switch, and back to the first split capacitor.

4. The auxiliary resonant commutator inverter unit according to claim 1 or 2, characterized in that, The control module is further configured to control the second main switch and the second auxiliary switch to turn off and the first auxiliary switch to turn on during a fourth time period, so as to form a resonant current through the path of the parasitic capacitance of the first main switch, the resonant inductance, the conduction channel of the first auxiliary switch, the parasitic diode of the second auxiliary switch, and the first split capacitor.

5. The auxiliary resonant commutator inverter unit according to claim 1 or 2, characterized in that, The control module is further configured to control the second main switch and the second auxiliary switch to turn off and the first auxiliary switch to turn on during a fourth time period, so as to form a resonant current through the path of the parasitic capacitance of the second main switch, the resonant inductance, the conduction channel of the first auxiliary switch, the parasitic diode of the second auxiliary switch, and the second split capacitor.

6. The auxiliary resonant commutator inverter unit according to claim 1 or 2, characterized in that, The auxiliary resonant commutator inverter unit further includes: The detection module has a first output terminal electrically connected to the first input terminal of the control module and a second output terminal electrically connected to the second input terminal of the control module. It is configured to obtain a first detection voltage based on the voltage between the first and second terminals of the second main switch transistor; and / or, to obtain a second detection voltage based on the voltage between the first and second terminals of the second auxiliary switch transistor. The control module, wherein its third input terminal is electrically connected to an external input and its fourth input terminal is electrically connected to a first base voltage, is further configured to, in a second or fourth time period, respond to the external input being high, the first detected voltage being greater than the first base voltage, and the second detected voltage being less than the first base voltage, control the first control terminal of the control module to output a low level, the second control terminal of the control module to output a high level, and the third control terminal of the control module to output a low level, so that the first auxiliary switch is turned on and the second auxiliary switch and the second main switch are turned off.

7. The auxiliary resonant commutator inverter unit according to claim 6, characterized in that, The detection module has its third output terminal electrically connected to the sixth input terminal of the control module, and its fourth output terminal electrically connected to the fifth input terminal of the control module. It is configured to obtain a third detection voltage based on the voltage between the first and second terminals of the first split capacitor; and / or, to obtain a fourth detection voltage based on the voltage between the first and second terminals of the second split capacitor. The control module, wherein its seventh input terminal is electrically connected to the second base voltage, is further configured to, during the first time period, in response to the external input being low and the fourth detection voltage being greater than the third detection voltage, control the first control terminal of the control module to output a high level, the second control terminal of the control module to output a low level, and the third control terminal of the control module to output a high level, so that the second main switch and the second auxiliary switch are turned on and the first auxiliary switch is turned off.

8. The auxiliary resonant commutator inverter unit according to claim 1 or 2, characterized in that, The control module is further configured to, in a third time period, in response to an external input being low, control the first control terminal of the control module to output a low level, the second control terminal of the control module to output a low level, and the third control terminal of the control module to output a high level, so that the second auxiliary switch is turned on and the second main switch and the first auxiliary switch are turned off.

9. The auxiliary resonant commutator inverter unit according to claim 7, characterized in that, The control module includes: The first AND gate, wherein the first input terminal of the first AND gate is electrically connected to an external input; The second AND gate has a first input terminal electrically connected to the external input, and an output terminal electrically connected to the control electrode of the first auxiliary switch. A NOT gate, wherein the output terminal of the NOT gate is electrically connected to the second input terminal of the first AND gate; The first comparator has its non-inverting input terminal electrically connected to the first output terminal of the detection module, its negative input terminal electrically connected to the first base voltage, and its output terminal electrically connected to the input terminal of the NOT gate. The first delay unit has its input terminal electrically connected to the output terminal of the first comparator; A first OR gate, wherein the first input terminal of the first OR gate is electrically connected to the output terminal of the first delay, and the output terminal of the first OR gate is electrically connected to the second input terminal of the second AND gate; The second comparator has its positive input terminal electrically connected to the first base voltage, its negative input terminal electrically connected to the second output terminal of the detection module, and its output terminal electrically connected to the second input terminal of the first OR gate. A subtractor, wherein the positive input terminal of the subtractor is electrically connected to the fourth detection voltage, and the negative input terminal of the subtractor is electrically connected to the third detection voltage; The third comparator has its positive input terminal electrically connected to the output terminal of the subtractor, and its negative input terminal electrically connected to the second base voltage. The second OR gate has its first input terminal electrically connected to the output terminal of the third comparator, and its second input terminal electrically connected to the control electrode of the second auxiliary switch. A third AND gate, wherein the first input terminal of the third AND gate is electrically connected to the output terminal of the second OR gate; The third OR gate has its first input terminal electrically connected to the output terminal of the third AND gate, its second input terminal electrically connected to the output terminal of the first AND gate, and its output terminal electrically connected to the control electrode of the second main switch. The second delay unit has its input terminal electrically connected to the external input, and its output terminal electrically connected to the second input terminal of the third AND gate. An XOR gate, wherein the first input terminal of the XOR gate is electrically connected to the output terminal of the second delay, and the second input terminal of the XOR gate is electrically connected to the external input; The third delay unit, the input of which is electrically connected to the output of the XOR gate; The fourth AND gate has its first input terminal electrically connected to the first input terminal of the third AND gate and the output terminal of the second OR gate, its second input terminal electrically connected to the output terminal of the third delay unit, and its output terminal electrically connected to the control electrode of the second auxiliary switch.

10. A method for auxiliary resonant commutator inverter, characterized in that, The auxiliary resonant commutator inverter unit, applied to any one of claims 1 to 9, comprises: During a first time period, the second main switch and the second auxiliary switch are controlled to be turned on, and the first auxiliary switch is turned off, so as to conduct the path through the second split capacitor, the conduction channel of the second auxiliary switch, the parasitic diode of the first auxiliary switch, the resonant inductor, the conduction channel of the second main switch, and back to the second split capacitor, as well as the path through the positive terminal of the output voltage to the first split capacitor, the conduction channel of the second auxiliary switch, the parasitic diode of the first auxiliary switch, the conduction channel of the second main switch, and the negative terminal of the output voltage.

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