Power supply circuit based on twelve-pulse rectification and NPC three-level inversion and control method

Abstract

The invention relates to the technical field of power supply circuits, in particular to a power supply circuit based on twelve-pulse rectification and NPC three-level inversion and a control method. Comprising a first transformer, a second transformer, a switch tube Q1, a switch tube Q2, a switch tube Q3, a switch tube Q4, a switch tube Q5, a switch tube Q6, a switch tube Q7, a switch tube Q8, a switch tube Q9, a switch tube Q10, a switch tube Q11, a switch tube Q12, a capacitor C1, a capacitor C2, an inversion module and a midpoint wire. The first transformer comprises a first A-phase output end, a first B-phase output end and a first C-phase output end; the second transformer comprises a second A-phase output end, a second B-phase output end and a second C-phase output end. The three-level inverter circuit solves the problems that a traditional three-level inverter circuit is complex in neutral-point voltage unbalance control, large in capacitance value and high in cost and size, and has the advantages of being simple in control logic, high in reliability, small in common-mode interference and optimized in cost and size.

Description

Technical Field

[0001] This invention relates to the field of power supply circuit technology, specifically to a power supply circuit and control method based on twelve-pulse rectification and NPC three-level inversion. Background Technology

[0002] In the field of power electronics, the NPC three-level inverter circuit is widely used in small and medium power converters due to its advantages such as good output waveform quality and low switching losses. Its core topology feature is that the midpoint is constructed by two series capacitors (C1, C2) on the DC side, which provides the basis for multi-level output of the inverter module. However, this structure also has the inherent technical problem of unbalanced midpoint voltage.

[0003] Specifically, the causes of midpoint voltage imbalance mainly include three aspects: First, slight differences in device parameters. Even power devices from the same batch may exhibit variations in parameters such as on-state voltage drop and switching speed, leading to uneven current distribution. Second, the delay effect of PWM modulation pulses. Timing deviations in the switching signals can cause asynchronous charging and discharging rhythms of the capacitors. Third, dynamic changes in load current. Fluctuations in the direction and amplitude of the load current directly affect the average current flowing through the midpoint, resulting in a non-zero current. These factors combined cause the charging and discharging quantities of capacitors C1 and C2 to be unable to perfectly match, thus triggering a midpoint potential shift. If this shift continues to accumulate, it will accelerate capacitor aging, shorten device lifespan, and even cause inverter output waveform distortion, severely impacting power supply quality.

[0004] To address the aforementioned issues, existing technologies typically employ two approaches: First, introducing complex modulation strategies (such as SVPWM or carrier PWM with a specific vector sequence) to achieve dynamic balance by actively controlling the direction and magnitude of the midpoint current. However, this approach significantly increases the complexity of the control algorithm and is highly coupled with the drive control of the inverter module, increasing the difficulty of topology implementation. Second, increasing the capacitance values ​​of DC-side capacitors C1 and C2 to suppress bus voltage fluctuations. However, increasing the capacitance values ​​not only leads to increased capacitor size and cost but also requires the addition of a pre-charging circuit to reduce the inrush current during startup, further exacerbating the complexity of the circuit structure.

[0005] Furthermore, traditional midpoint balancing algorithms must simultaneously address both slowly accumulating potential shifts and instantaneous charge imbalances. This dual task results in high algorithmic adjustment pressure and low control margin, making it difficult to balance stability and response speed. Therefore, simplifying control logic and optimizing circuit size and cost while ensuring midpoint voltage balance has become a pressing technical challenge for the application and promotion of three-level inverter circuits. Summary of the Invention

[0006] The purpose of this invention is to address the aforementioned shortcomings in the prior art by providing a power supply circuit and control method based on twelve-pulse rectification and NPC three-level inverter.

[0007] The objective of this invention is achieved through the following technical solution: a power supply circuit based on twelve-pulse rectification and NPC three-level inverter, comprising a first transformer, a second transformer, switching transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, capacitors C1 and C2, an inverter module, and a midpoint wire; The first transformer includes a first A-phase output terminal, a first B-phase output terminal, and a first C-phase output terminal; the second transformer includes a second A-phase output terminal, a second B-phase output terminal, and a second C-phase output terminal. One end of each of the three switching transistors Q1, Q2, and Q3 is connected to one end of capacitor C1; one end of each of the three switching transistors Q4, Q5, and Q6 is connected to one end of the midpoint wire; the other end of the midpoint wire is connected to the other end of capacitor C1; the other ends of both the switching transistors Q1 and Q4 are connected to the first phase A output terminal; the other ends of both the switching transistors Q2 and Q5 are connected to the first phase B output terminal; and the other ends of both the switching transistors Q3 and Q6 are connected to the first phase C output terminal. One end of each of the switching transistors Q7, Q8, and Q9 is connected to one end of the midpoint conductor; one end of each of the switching transistors Q10, Q11, and Q12 is connected to one end of capacitor C2; the other end of capacitor C2 is connected to the other end of capacitor C1; the other ends of both the switching transistors Q7 and Q10 are connected to the output terminal of the second phase A; the other ends of both the switching transistors Q8 and Q11 are connected to the output terminal of the second phase B; the other ends of both the switching transistors Q9 and Q12 are connected to the output terminal of the second phase C; and one end of each of the capacitors C1 and C2 is connected to the inverter module.

[0008] The present invention is further configured such that the power supply circuit based on twelve-pulse rectification and NPC three-level inverter also includes an input power supply; the first transformer and the second transformer are respectively connected to the input power supply; the first transformer is a delta transformer; and the second transformer is a star transformer.

[0009] The present invention is further configured such that the switching transistors Q1, Q2, Q3, Q4, Q5 and Q6 are all thyristors; The cathodes of switching transistors Q1, Q2, and Q3 are each connected to one end of capacitor C1; the anodes of switching transistors Q4, Q5, and Q6 are each connected to one end of the midpoint conductor; the anode of switching transistor Q1 and the cathode of switching transistor Q4 are both connected to the first phase A output terminal; the anode of switching transistor Q2 and the cathode of switching transistor Q5 are both connected to the first phase B output terminal; and the anode of switching transistor Q3 and the cathode of switching transistor Q6 are both connected to the first phase C output terminal.

[0010] The present invention is further configured such that the switching transistors Q7, Q8, Q9, Q10, Q11 and Q12 are all thyristors; The cathodes of switching transistors Q7, Q8, and Q9 are each connected to one end of the midpoint conductor; the anodes of switching transistors Q10, Q11, and Q12 are each connected to one end of capacitor C2; the anodes of switching transistors Q7 and Q10 are both connected to the output terminal of the second phase A; the anodes of switching transistors Q8 and Q11 are both connected to the output terminal of the second phase B; and the anodes of switching transistors Q9 and Q12 are both connected to the output terminal of the second phase C.

[0011] The present invention is further configured such that the power supply circuit based on twelve-pulse rectification and NPC three-level inversion also includes resistor R1 and resistor R2; resistor R1 is connected in parallel with capacitor C1; resistor R2 is connected in parallel with capacitor C2.

[0012] The present invention is further configured such that the inverter module includes MOSFETs D1, D2, D3, D4, D5, D6, D13, D14, D15, D16, D17, D18, diodes D7, D8, D9, D10, D11, and D12; The drains of MOSFETs D1, D2, and D3 are connected to one end of capacitor C1; the sources of MOSFETs D1, D2, and D3 are connected to the drains of MOSFETs D4, D5, and D6, respectively; the anodes of diodes D7, D8, and D9 are connected to the other end of the midpoint wire; the cathodes of diodes D7, D8, and D9 are connected to the sources of MOSFETs D1, D2, and D3, respectively; and the sources of MOSFETs D4, D5, and D6 are connected to the drains of MOSFETs D13, D14, and D15, respectively. The sources of MOSFETs D16, D17, and D18 are connected to one end of capacitor C2, respectively. The drains of MOSFETs D16, D17, and D18 are connected to the sources of MOSFETs D13, D14, and D15, respectively. The cathodes of diodes D10, D11, and D12 are connected to the other end of the midpoint wire, respectively. The anodes of diodes D10, D11, and D12 are connected to the drains of MOSFETs D16, D17, and D18, respectively.

[0013] The present invention is further configured such that a first current collector is connected between the source of MOSFET D4 and the drain of MOSFET D13; a second current collector is connected between the source of MOSFET D5 and the drain of MOSFET D14; and a third current collector is connected between the source of MOSFET D6 and the drain of MOSFET D15.

[0014] The present invention is further configured such that the midpoint conductor is equipped with a midpoint current collector.

[0015] A control method for a power supply circuit based on twelve-pulse rectification and NPC three-level inverter includes the following steps: S1. Real-time acquisition of the three-phase input voltage of the input power supply, the voltage VC1 of capacitor C1, the voltage VC2 of capacitor C2, the three-phase input current of the input power supply, the load current of the inverter module, and the midpoint current of the midpoint conductor. S2. Based on the collected three-phase input current and DC bus total voltage of the input power supply, the DC bus total voltage is stabilized and the three-phase input current of the input power supply is kept constant through the main control loop; the DC bus total voltage is the sum of the voltage of capacitor C1 and the voltage of capacitor C2. S3. Calculate the voltage deviation ∆VC between capacitors C1 and C2 = VC1 - VC2, and input the voltage deviation ∆VC into the low-bandwidth PI controller to generate zero-sequence voltage modulation or power distribution command. S4. According to the zero-sequence voltage modulation amount or power distribution command, adjust the firing angle of each switching transistor to control the rectified output voltage V1 of the first transformer and the rectified output voltage V2 of the second transformer to tend to balance, and correct the slowly accumulated midpoint voltage deviation. S5. Run the midpoint balancing algorithm in the inverter module, and process the instantaneous midpoint charge balance in each switching cycle based on the collected load current of the inverter module and the midpoint current of the midpoint conductor.

[0016] The present invention is further configured such that, based on the zero-crossing point of the three-phase input voltage of the input power supply, the trigger angle is adjusted by changing the trigger signal delay time of each switching transistor; the smaller the trigger angle, the longer the conduction time of the corresponding switching transistor and the higher the output voltage amplitude; the larger the trigger angle, the shorter the conduction time of the corresponding switching transistor and the lower the output voltage amplitude. By independently adjusting the firing angles of switching transistors Q1, Q2, Q3, Q4, Q5, and Q6, as well as the firing angles of switching transistors Q7, Q8, Q9, Q10, Q11, and Q12, the amplitudes of the rectified output voltage V1 of the first transformer and the rectified output voltage V2 of the second transformer are matched respectively, so that the deviation ∆VC between the voltage VC1 of capacitor C1 and the voltage VC2 of capacitor C2 is maintained within a preset range.

[0017] The beneficial effects of this invention are as follows: This invention constructs an active voltage equalization path through a midpoint conductor, combined with slow loop correction and fast loop instantaneous correction, resulting in high midpoint voltage balance accuracy and low output waveform distortion. Furthermore, the pre-stage trigger angle adjustment shares the voltage equalization task, simplifying control logic, reducing algorithm and drive coupling, and improving system reliability. Additionally, no additional capacitance is required, eliminating the need for a pre-charging circuit, significantly optimizing hardware cost and size. Moreover, the twelve-pulse rectification suppresses grid-side harmonics, and the constant grid-side current reduces grid impact, providing strong anti-interference capabilities. Furthermore, the switching transistors support multiple replacement types, adapting to different power scenarios and offering a wide range of applications. Finally, voltage balance reduces device losses, extends the lifespan of capacitors and power devices, and lowers long-term operating costs. Attached Figure Description

[0018] The invention will be further illustrated with reference to the accompanying drawings, but the embodiments in the drawings do not constitute any limitation on the invention. For those skilled in the art, other drawings can be obtained based on the following drawings without any creative effort.

[0019] Figure 1 This is the circuit schematic diagram of the present invention; Wherein: 1. First transformer; 11. First A-phase output terminal; 12. First B-phase output terminal; 13. First C-phase output terminal; 2. Second transformer; 21. Second A-phase output terminal; 22. Second B-phase output terminal; 23. Second C-phase output terminal; 3. Midpoint conductor; 31. Midpoint current collector; 4. Input power supply; 51. First current collector; 52. Second current collector; 53. Third current collector. Detailed Implementation

[0020] The present invention will be further described in conjunction with the following embodiments.

[0021] Depend on Figure 1 As can be seen, a power supply circuit based on twelve-pulse rectification and NPC three-level inverter in this embodiment includes a first transformer 1, a second transformer 2, switching transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, capacitors C1 and C2, an inverter module, and a midpoint wire 3; The first transformer 1 includes a first A-phase output terminal 11, a first B-phase output terminal 12, and a first C-phase output terminal 13; the second transformer 2 includes a second A-phase output terminal 21, a second B-phase output terminal 22, and a second C-phase output terminal 23. One end of each of the switching transistors Q1, Q2, and Q3 is connected to one end of the capacitor C1; one end of each of the switching transistors Q4, Q5, and Q6 is connected to one end of the midpoint wire 3; the other end of the midpoint wire 3 is connected to the other end of the capacitor C1; the other ends of the switching transistors Q1 and Q4 are both connected to the first phase A output terminal 11; the other ends of the switching transistors Q2 and Q5 are both connected to the first phase B output terminal 12; and the other ends of the switching transistors Q3 and Q6 are both connected to the first phase C output terminal 13. One end of each of the switching transistors Q7, Q8, and Q9 is connected to one end of the midpoint conductor 3; one end of each of the switching transistors Q10, Q11, and Q12 is connected to one end of capacitor C2; the other end of capacitor C2 is connected to the other end of capacitor C1; the other ends of both the switching transistors Q7 and Q10 are connected to the second phase A output terminal 21; the other ends of both the switching transistors Q8 and Q11 are connected to the second phase B output terminal 22; the other ends of both the switching transistors Q9 and Q12 are connected to the second phase C output terminal 23; and one end of each of the capacitors C1 and C2 is connected to the inverter module.

[0022] In this embodiment, two sets of switching transistors are connected to the three-phase output terminals of the first transformer 1 and the second transformer 2, forming a symmetrical rectification path. Capacitors C1 and C2 are connected in series to form a DC-side energy storage unit. The midpoint wire 3 directly connects the series connection point of the two sets of switching transistors to the common midpoint between capacitors C1 and C2. The inverter module is connected to both ends of capacitors C1 and C2, constructing a complete link of rectification-energy storage-inversion. In this embodiment, the two sets of switching transistors and the two transformers work together to form a twelve-pulse rectification foundation. The directional connection of the midpoint wire 3 provides a physical path for actively adjusting the voltage balance of capacitors C1 and C2. The direct connection of the inverter module to capacitors C1 and C2 ensures efficient power transmission, reduces the risk of midpoint voltage deviation from the topology level, and provides a stable hardware carrier for subsequent control algorithms.

[0023] This embodiment provides a power supply circuit based on twelve-pulse rectification and NPC three-level inversion. The power supply circuit also includes an input power supply 4. A first transformer 1 and a second transformer 2 are respectively connected to the input power supply 4. The first transformer 1 is a delta transformer, and the second transformer 2 is a star transformer. The input power supply 4 provides three-phase AC input to the first transformer 1 and the second transformer 2. The first transformer 1 is delta-connected, and the second transformer 2 is star-connected. Their output voltages naturally form a 30° phase difference, which, combined with two sets of rectifier switches, enables twelve-pulse rectification.

[0024] This embodiment provides a power supply circuit based on twelve-pulse rectification and NPC three-level inversion, wherein the switching transistors Q1, Q2, Q3, Q4, Q5, and Q6 are all thyristors. The cathodes of switching transistors Q1, Q2, and Q3 are each connected to one end of capacitor C1; the anodes of switching transistors Q4, Q5, and Q6 are each connected to one end of the midpoint conductor 3; the anode of switching transistor Q1 and the cathode of switching transistor Q4 are both connected to the first A-phase output terminal 11; the anode of switching transistor Q2 and the cathode of switching transistor Q5 are both connected to the first B-phase output terminal 12; and the anode of switching transistor Q3 and the cathode of switching transistor Q6 are both connected to the first C-phase output terminal 13.

[0025] Specifically, thyristors are selected as switching transistors Q1-Q6. The cathodes of switching transistors Q1-Q3 are connected to capacitor C1, and the anodes of switching transistors Q1-Q3 are connected to the output terminal of the first transformer 1. When conducting, they charge capacitor C1. The anodes of switching transistors Q4-Q6 are connected to the midpoint wire 3, and the cathodes of switching transistors Q4-Q6 are connected to the output terminal of the first transformer 1. When conducting, they provide a current path for the midpoint wire 3. Through the triggering and conduction characteristics of the thyristors, the current flow to capacitor C1 or the midpoint can be precisely controlled.

[0026] In this embodiment, a power supply circuit based on twelve-pulse rectification and NPC three-level inverter is provided, wherein the switching transistors Q7, Q8, Q9, Q10, Q11 and Q12 are all thyristors. The cathodes of switching transistors Q7, Q8, and Q9 are each connected to one end of the midpoint conductor 3; the anodes of switching transistors Q10, Q11, and Q12 are each connected to one end of capacitor C2; the anodes of switching transistors Q7 and Q10 are both connected to the second phase A output terminal 21; the anodes of switching transistors Q8 and Q11 are both connected to the second phase B output terminal 22; and the anodes of switching transistors Q9 and Q12 are both connected to the second phase C output terminal 23.

[0027] Specifically, switching transistors Q7-Q12 are also thyristors. The cathodes of switching transistors Q7-Q9 are connected to the midpoint wire 3, and the anodes of switching transistors Q7-Q9 are connected to the output terminal of the second transformer 2. When conducting, current flows into the midpoint wire 3. The anodes of switching transistors Q10-Q12 are connected to capacitor C2, and the cathodes of switching transistors Q10-Q12 are connected to the output terminal of the second transformer 2. When conducting, capacitor C2 is charged. The connection logic is symmetrical with that of switching transistors Q1-Q6, forming a regulating path for the rectified output voltage V2 on the side of the second transformer 2.

[0028] This embodiment presents a power supply circuit based on twelve-pulse rectification and NPC three-level inversion. The power supply circuit further includes resistors R1 and R2; resistor R1 is connected in parallel with capacitor C1; and resistor R2 is connected in parallel with capacitor C2. The parallel connections of resistors R1 and C1, and resistors R2 and C2, form a passive voltage equalization circuit. Utilizing the voltage dividing characteristics of the resistors, excess charge across the capacitors is shunted during initial circuit startup or under light load, preventing imbalance caused by inconsistent initial voltages or slight leakage.

[0029] This embodiment provides a power supply circuit based on twelve-pulse rectification and NPC three-level inverter. The inverter module includes MOSFETs D1, D2, D3, D4, D5, D6, D13, D14, D15, D16, D17, D18, diodes D7, D8, D9, D10, D11, and D12. The drains of MOSFETs D1, D2, and D3 are connected to one end of capacitor C1; the sources of MOSFETs D1, D2, and D3 are connected to the drains of MOSFETs D4, D5, and D6, respectively; the anodes of diodes D7, D8, and D9 are connected to the other end of the midpoint wire 3; the cathodes of diodes D7, D8, and D9 are connected to the sources of MOSFETs D1, D2, and D3, respectively; and the sources of MOSFETs D4, D5, and D6 are connected to the drains of MOSFETs D13, D14, and D15, respectively. The sources of MOSFETs D16, D17, and D18 are connected to one end of capacitor C2, respectively; the drains of MOSFETs D16, D17, and D18 are connected to the sources of MOSFETs D13, D14, and D15, respectively; the cathodes of diodes D10, D11, and D12 are connected to the other end of the midpoint wire 3, respectively; and the anodes of diodes D10, D11, and D12 are connected to the drains of MOSFETs D16, D17, and D18, respectively.

[0030] Specifically, the inverter module is symmetrically composed of 12 MOSFETs and 6 diodes. The MOSFETs are arranged in two layers to form a three-level output structure. Diodes D7-D9 and D10-D12 are respectively connected to the connection point of the midpoint wire 3 and the MOSFET, realizing voltage clamping and bidirectional current flow, ensuring the stability of the midpoint potential during the inverter process. The three-level inverter structure reduces the switching loss and voltage stress of the MOSFETs and improves the inverter efficiency. The clamping effect of the diodes limits the peak voltage across the MOSFETs and avoids device breakdown. The connection between the midpoint wire 3 and the diodes provides a discharge path for the instantaneous midpoint current. Combined with the fast switching characteristics of the MOSFETs, it can respond to midpoint voltage fluctuations in real time, providing hardware support for the inner fast loop control and ensuring low output waveform distortion.

[0031] This embodiment provides a power supply circuit based on twelve-pulse rectification and NPC three-level inverter. A first current collector 51 is connected between the source of MOSFET D4 and the drain of MOSFET D13; a second current collector 52 is connected between the source of MOSFET D5 and the drain of MOSFET D14; and a third current collector 53 is connected between the source of MOSFET D6 and the drain of MOSFET D15. The above configuration is used to collect the load current of the three phases of the inverter module.

[0032] This embodiment provides a power supply circuit based on twelve-pulse rectification and NPC three-level inverter. The midpoint conductor 3 is equipped with a midpoint current collector 31; the midpoint current of the midpoint conductor 3 is collected through the above-mentioned setup.

[0033] This embodiment provides a control method for a power supply circuit based on a twelve-pulse rectification and NPC three-level inverter, comprising the following steps: S1. Real-time acquisition of the three-phase input voltage of input power supply 4, voltage VC1 of capacitor C1, voltage VC2 of capacitor C2, three-phase input current of input power supply 4, load current of inverter module and midpoint current of midpoint conductor 3. S2. Based on the collected three-phase input current and DC bus total voltage of the input power supply 4, the DC bus total voltage is stabilized and the three-phase input current of the input power supply 4 is kept constant through the main control loop; the DC bus total voltage is the sum of the voltage of capacitor C1 and the voltage of capacitor C2. S3. Calculate the voltage deviation ∆VC between capacitors C1 and C2 = VC1 - VC2, and input the voltage deviation ∆VC into the low-bandwidth PI controller to generate zero-sequence voltage modulation or power distribution command. S4. According to the zero-sequence voltage modulation amount or power distribution command, adjust the firing angle of each switch tube to control the rectified output voltage V1 of the first transformer 1 and the rectified output voltage V2 of the second transformer 2 to tend to balance, and correct the slowly accumulated midpoint voltage deviation. S5. Run the midpoint balancing algorithm in the inverter module. Based on the collected load current of the inverter module and the midpoint current of the midpoint conductor 3, process the instantaneous midpoint charge balance in each switching cycle.

[0034] Specifically, this embodiment constructs a full-link feedback system from input to energy storage to output to midpoint through multi-dimensional signal acquisition, providing accurate data support for the control algorithm; it adopts a dual-loop main control logic with an outer voltage loop and an inner current loop, taking the stability of the total DC bus voltage as the core objective and the constant grid-side current as the constraint, and achieves power balance through PI regulation; it calculates the deviation ∆VC between VC1 and VC2, and the low-bandwidth PI controller generates modulation commands to avoid frequency coupling with the inner fast loop; it converts the modulation commands into switching transistor trigger angle adjustment, and corrects the slowly accumulating midpoint offset from the source by matching the amplitudes of V1 and V2; relying on the midpoint balance algorithm, combined with the instantaneous values ​​of load current and midpoint current, it dynamically corrects the switching timing of the inverter module to offset the instantaneous charge imbalance in each switching cycle.

[0035] This embodiment uses full signal acquisition to ensure comprehensive control decisions and avoid adjustment deviations caused by missing information. The main control loop achieves steady-state power balance, ensuring stable input voltage of the inverter module. The low-bandwidth PI controller allows the outer layer adjustment to focus on slow offsets without interfering with the inner layer instantaneous correction. Precise matching of V1 and V2 significantly reduces the risk of midpoint voltage imbalance and reduces capacitor aging losses. Inner layer instantaneous balance processing avoids deviation accumulation and ensures low output waveform distortion. Overall, it forms a coordinated control of steady-state coarse adjustment and instantaneous fine adjustment, significantly simplifying the control logic and improving system reliability and power supply quality.

[0036] This embodiment describes a control method for a power supply circuit based on a twelve-pulse rectification and NPC three-level inverter. Taking the zero-crossing point of the three-phase input voltage of the input power supply 4 as a reference, the trigger angle is adjusted by changing the trigger signal delay time of each switch. The smaller the trigger angle, the longer the conduction time of the corresponding switch and the higher the output voltage amplitude; the larger the trigger angle, the shorter the conduction time of the corresponding switch and the lower the output voltage amplitude. By independently adjusting the firing angles of switching transistors Q1, Q2, Q3, Q4, Q5, and Q6, as well as the firing angles of switching transistors Q7, Q8, Q9, Q10, Q11, and Q12, the amplitudes of the rectified output voltage V1 of the first transformer 1 and the rectified output voltage V2 of the second transformer 2 are matched respectively, so that the deviation ∆VC between the voltage VC1 of capacitor C1 and the voltage VC2 of capacitor C2 is maintained within a preset range.

[0037] Specifically, in this embodiment, the zero-crossing reference ensures that the firing angle adjustment is synchronized with the grid voltage phase, avoiding rectified output distortion and improving power quality. The clear correlation between the firing angle and the output voltage makes the adjustment of V1 and V2 precise and controllable, and the operation logic is simple. The independent adjustment of the two sets of switching transistors achieves directional matching of V1 and V2, specifically corrects the voltage deviation between capacitors C1 and C2, and avoids balance lag. Ultimately, it stabilizes ∆VC within the preset range, providing better initial operating conditions for the inverter module, further reducing the adjustment pressure of the inner midpoint balancing algorithm, while reducing device losses caused by voltage imbalance and extending the circuit life.

[0038] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A power supply circuit based on twelve-pulse rectification and NPC three-level inversion, characterized in that: It includes a first transformer (1), a second transformer (2), switching transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, capacitors C1 and C2, an inverter module, and a midpoint wire (3); The first transformer (1) includes a first A-phase output terminal (11), a first B-phase output terminal (12), and a first C-phase output terminal (13); the second transformer (2) includes a second A-phase output terminal (21), a second B-phase output terminal (22), and a second C-phase output terminal (23); One end of each of the switching transistors Q1, Q2, and Q3 is connected to one end of the capacitor C1; one end of each of the switching transistors Q4, Q5, and Q6 is connected to one end of the midpoint wire (3); the other end of the midpoint wire (3) is connected to the other end of the capacitor C1; the other ends of the switching transistors Q1 and Q4 are both connected to the first A-phase output terminal (11); the other ends of the switching transistors Q2 and Q5 are both connected to the first B-phase output terminal (12); the other ends of the switching transistors Q3 and Q6 are both connected to the first C-phase output terminal (13). One end of each of the switching transistors Q7, Q8, and Q9 is connected to one end of the midpoint conductor (3); one end of each of the switching transistors Q10, Q11, and Q12 is connected to one end of capacitor C2; the other end of capacitor C2 is connected to the other end of capacitor C1; the other ends of both the switching transistors Q7 and Q10 are connected to the second phase A output terminal (21); the other ends of both the switching transistors Q8 and Q11 are connected to the second phase B output terminal (22); the other ends of both the switching transistors Q9 and Q12 are connected to the second phase C output terminal (23); one end of each of the capacitors C1 and C2 is connected to the inverter module.

2. A power supply circuit based on twelve-pulse rectification and NPC three-level inverter as described in claim 1, characterized in that: The power supply circuit based on twelve-pulse rectification and NPC three-level inverter also includes an input power supply (4); the first transformer (1) and the second transformer (2) are respectively connected to the input power supply (4); the first transformer (1) is a delta transformer; the second transformer (2) is a star transformer.

3. A power supply circuit based on twelve-pulse rectification and NPC three-level inversion as described in claim 1, characterized in that: The switching transistors Q1, Q2, Q3, Q4, Q5, and Q6 are all thyristors; The cathodes of the switching transistors Q1, Q2, and Q3 are respectively connected to one end of the capacitor C1; the anodes of the switching transistors Q4, Q5, and Q6 are respectively connected to one end of the midpoint conductor (3); the anode of the switching transistor Q1 and the cathode of the switching transistor Q4 are both connected to the first A-phase output terminal (11); the anode of the switching transistor Q2 and the cathode of the switching transistor Q5 are both connected to the first B-phase output terminal (12); the anode of the switching transistor Q3 and the cathode of the switching transistor Q6 are both connected to the first C-phase output terminal (13).

4. A power supply circuit based on twelve-pulse rectification and NPC three-level inverter as described in claim 1, characterized in that: The switching transistors Q7, Q8, Q9, Q10, Q11, and Q12 are all thyristors; The cathodes of the switching transistors Q7, Q8, and Q9 are respectively connected to one end of the midpoint conductor (3); the anodes of the switching transistors Q10, Q11, and Q12 are respectively connected to one end of the capacitor C2; the anodes of the switching transistors Q7 and Q10 are both connected to the second phase A output terminal (21); the anodes of the switching transistors Q8 and Q11 are both connected to the second phase B output terminal (22); and the anodes of the switching transistors Q9 and Q12 are both connected to the second phase C output terminal (23).

5. A power supply circuit based on twelve-pulse rectification and NPC three-level inverter as described in claim 1, characterized in that: The power supply circuit based on twelve-pulse rectification and NPC three-level inversion also includes resistor R1 and resistor R2; resistor R1 is connected in parallel with capacitor C1; resistor R2 is connected in parallel with capacitor C2.

6. A power supply circuit based on twelve-pulse rectification and NPC three-level inverter as described in claim 1, characterized in that: The inverter module includes MOSFETs D1, D2, D3, D4, D5, D6, D13, D14, D15, D16, D17, D18, diodes D7, D8, D9, D10, D11, and D12; The drains of MOSFETs D1, D2, and D3 are connected to one end of capacitor C1; the sources of MOSFETs D1, D2, and D3 are connected to the drains of MOSFETs D4, D5, and D6; the anodes of diodes D7, D8, and D9 are connected to the other end of the midpoint wire (3); the cathodes of diodes D7, D8, and D9 are connected to the sources of MOSFETs D1, D2, and D3; and the sources of MOSFETs D4, D5, and D6 are connected to the drains of MOSFETs D13, D14, and D15. The sources of MOS transistors D16, D17, and D18 are connected to one end of capacitor C2, respectively; the drains of MOS transistors D16, D17, and D18 are connected to the sources of MOS transistors D13, D14, and D15, respectively; the cathodes of diodes D10, D11, and D12 are connected to the other end of the midpoint wire (3), respectively; and the anodes of diodes D10, D11, and D12 are connected to the drains of MOS transistors D16, D17, and D18, respectively.

7. A power supply circuit based on twelve-pulse rectification and NPC three-level inverter as described in claim 6, characterized in that: A first current collector (51) is connected between the source of MOSFET D4 and the drain of MOSFET D13; a second current collector (52) is connected between the source of MOSFET D5 and the drain of MOSFET D14; and a third current collector (53) is connected between the source of MOSFET D6 and the drain of MOSFET D15.

8. A power supply circuit based on twelve-pulse rectification and NPC three-level inverter as described in claim 1, characterized in that: The midpoint conductor (3) is equipped with a midpoint current collector (31).

9. A control method for a power supply circuit based on a twelve-pulse rectification and NPC three-level inverter as described in any one of claims 1-8, characterized in that: Includes the following steps: S1. Real-time acquisition of the three-phase input voltage of the input power supply (4), the voltage VC1 of capacitor C1, the voltage VC2 of capacitor C2, the three-phase input current of the input power supply (4), the load current of the inverter module, and the midpoint current of the midpoint conductor (3). S2. Based on the three-phase input current and DC bus total voltage of the input power supply (4) collected, the DC bus total voltage is stabilized through the main control loop and the three-phase input current of the input power supply (4) is kept constant; the DC bus total voltage is the sum of the voltage of capacitor C1 and the voltage of capacitor C2. S3. Calculate the voltage deviation ∆VC between capacitors C1 and C2 = VC1 - VC2, and input the voltage deviation ∆VC into the low-bandwidth PI controller to generate zero-sequence voltage modulation or power distribution command. S4. According to the zero-sequence voltage modulation amount or power distribution command, adjust the firing angle of each switch tube, control the rectified output voltage V1 of the first transformer (1) and the rectified output voltage V2 of the second transformer (2) to tend to balance, and correct the slowly accumulated midpoint voltage deviation. S5. Run the midpoint balancing algorithm in the inverter module. Based on the collected load current of the inverter module and the midpoint current of the midpoint conductor (3), process the instantaneous midpoint charge balance in each switching cycle.

10. The control method according to claim 9, characterized in that: Based on the zero-crossing point of the three-phase input voltage of the input power supply (4), the trigger angle is adjusted by changing the trigger signal delay time of each switch. The smaller the trigger angle, the longer the conduction time of the corresponding switch and the higher the output voltage amplitude. The larger the trigger angle, the shorter the conduction time of the corresponding switch and the lower the output voltage amplitude. By independently adjusting the firing angles of switching transistors Q1, Q2, Q3, Q4, Q5, and Q6, as well as the firing angles of switching transistors Q7, Q8, Q9, Q10, Q11, and Q12, the amplitudes of the rectified output voltage V1 of the first transformer (1) and the rectified output voltage V2 of the second transformer (2) are matched respectively, so that the deviation ∆VC between the voltage VC1 of capacitor C1 and the voltage VC2 of capacitor C2 is maintained within a preset range.

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