Metastable state detection and correction in analog-to-digital signal converters

Abstract

The invention relates to metastable state detection and correction in analog-to-digital signal converters. Embodiments disclosed herein relate to detecting metastable states to reduce noise and improve performance of an analog-to-digital converter (ADC) (120). In an example, an ADC (120) is provided that includes comparator circuitry (comparator 215), synchronization circuitry (synchronizers 225 and 230), digital output circuitry (SAR circuitry 235), and stability check circuitry (digital stability checker circuitry 240). The comparator circuitry performs a comparison of an analog input signal and an analog feedback signal and outputs a result of the comparison. Synchronization circuitry samples the results of the comparison at different times, resulting in a first sampled value and a second sampled value. The digital output circuitry generates a digital output signal based on the first sampling value and outputs the digital output signal. Stability check circuitry determines whether a metastable condition occurs with respect to the analog-to-digital converter based on the first sampled value and the second sampled value, and outputs an indication of whether the metastable condition occurs.

Description

Metastability detection and correction in analog-to-digital signal converters Technical Field

[0001] This largely involves analog-to-digital signal processing devices and systems, and more specifically, metastability detection and mitigation. Background Technology

[0002] In electronic systems, digital signal processing components (e.g., analog-to-digital converters (ADCs)) sample analog signals and convert them into digital signals for use by various components of the electronic system. To operate the ADC, the electronic system supplies power and a clock signal to the component. The ADC receives an analog input signal, generates a voltage for comparison with the analog signal, and converts the analog input signal into a digital output signal based on the comparison. For example, the analog input signal may be converted to one (or zero) depending on whether it is greater than (or less than) the comparison voltage.

[0003] Some analog signals cannot be correctly resolved due to a condition called metastability. Metastability is a condition in which the ADC comparator fails to make a definite decision within the required time range. This can occur when the analog input signal is very close to the comparator's threshold, causing the comparator's output to be in an uncertain state for a short period of time. Furthermore, metastability can produce sparkle code, such as deviations from the expected output signal, which cannot be attributed to the ADC's effective Gaussian noise.

[0004] Existing solutions attempt to address the problems caused by metastable values ​​encountered during digital signal processing. One example is the use of multiple redundant components in the ADC architecture, such as multiple DACs or multiple comparators, which increase redundancy to ensure the capture of resolute or stable values ​​during the conversion process. However, this solution increases design area requirements and cost due to the use of repetitive components.

[0005] Another existing solution obtains and transforms multiple redundant samples of the analog input signal, determines the standard deviation of multiple converted digital output signals, and determines the average of multiple digital output signals to mitigate the effects of metastability. However, this solution reduces ADC throughput and increases the time required to convert the analog input signal to digital. Summary of the Invention

[0006] The various embodiments disclosed herein relate to enhanced detection and reduction of metastable conditions in analog-to-digital converters (ADCs). In various embodiments, an ADC is provided that is capable of detecting metastable conditions in a unique manner that allows for faster correction of metastable conditions than other methods. The ADC can then be controlled to reduce future metastable rates.

[0007] In an example embodiment, the ADC includes comparator circuitry capable of entering undesirable metastable states. The ADC also includes synchronization circuitry, digital output circuitry, and stability checking circuitry. The stability checking circuitry is capable of determining the metastable state of the comparator circuitry. One or both of the comparator circuitry and the synchronization circuitry can be directly or indirectly controlled by the ADC to reduce or otherwise mitigate the occurrence of the metastable state. In a hardware approach, other circuitry within the ADC can control trimming levels to mitigate metastability. In a software approach, the ADC can interrupt software on one or more processing cores in response to the occurrence of metastability. The software can then adjust trimming levels or other parameters to control the metastability.

[0008] In operation, the ADC's analog-to-digital circuitry converts the digital feedback signal (generated by the digital output circuitry) into an analog feedback signal. The comparator circuitry performs a comparison between the analog input signal and the analog feedback signal, and outputs the result of the comparison to the synchronization circuitry. The comparator circuitry performs the comparison based on trimming levels and / or other configurable parameters that may affect metastability.

[0009] The synchronization circuitry samples the comparison result at different times to generate a first sampled value and a second sampled value. The digital output circuitry generates and outputs a digital feedback signal and a digital output signal based on the comparison result. The stability check circuitry detects or otherwise determines the occurrence of the metastable condition based on the first and second sampled values. The metastable condition (or the fact that it has occurred) can then be used forward to control one or more of how the comparison circuitry performs signal comparisons and how the synchronization circuitry samples the comparison result.

[0010] This summary is provided to introduce, in a simplified form, a series of concepts further described below in the detailed description. It is to be understood that this summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Attached Figure Description

[0011] Figure 1 illustrates an example system in the implementation scheme.

[0012] Figure 2 illustrates an example analog-to-digital converter in the implementation scheme.

[0013] Figure 3A illustrates an example method in the implementation scheme.

[0014] Figure 3B illustrates an example method in the implementation scheme.

[0015] Figure 4 illustrates an example analog-to-digital converter in the implementation scheme.

[0016] Figure 5 illustrates an example timing diagram of the components corresponding to the analog-to-digital converter in the implementation scheme.

[0017] The drawings are not necessarily drawn to scale. In the drawings, similar reference numerals are used throughout several views to indicate corresponding parts. In some embodiments, components or operations may be separated into different blocks or combined into a single block. Detailed Implementation

[0018] This document discloses enhanced components, techniques, and systems related to analog-to-digital signal conversion, and particularly to the detection and reduction of metastable conditions in analog-to-digital signal converter devices. Embodiments of this disclosure are described in a specific context, such as in analog-to-digital signal conversion and digital-to-analog signal conversion, which can be performed using a successive approximation register (SAR) analog-to-digital converter (ADC). Some embodiments can be used in other applications, such as in analog sampling and signal conversion, sampling timing analog outputs (e.g., timing comparator outputs, operational amplifiers), and / or other applications using different types of converters and their components.

[0019] In digital signal processing systems, an ADC samples an analog input signal and converts it into a digital output signal for use by downstream components and the system. The exemplary ADCs disclosed herein include various components that not only perform signal conversion but also verify the accuracy of the conversion, such as components that detect and reduce metastability and its effects during the conversion of the analog input signal to the digital output signal.

[0020] In an exemplary embodiment, the analog logic subsystem of the ADC includes a digital-to-analog converter (DAC) circuit system and a comparator circuit system, which cooperate to process the analog input signal and output the result to the digital logic subsystem. The digital logic subsystem includes a synchronization circuit system, a digital output circuit system, and a stability check circuit system, which process the output from the analog logic subsystem to produce a digital signal that is a digital representation of the analog input signal.

[0021] More specifically, the analog logic subsystem is coupled to the digital logic subsystem via the output of the comparator circuitry system, which feeds the input to the synchronous circuitry system, and the output of the digital output circuitry system, which also feeds the input to the comparator circuitry system. The DAC circuitry system converts the digital feedback signal (generated by the digital output circuitry system) into an analog feedback signal. The comparator circuitry system performs a comparison between the analog input signal and the analog feedback signal, and outputs the comparison result to the synchronous circuitry system. The synchronous circuitry system samples the result at different times to produce a first sample value and a second sample value.

[0022] The first sampled value is provided as input to the digital output circuit system and the stability check circuit system. The digital output circuit system generates a digital feedback signal based on the first sampled value. The digital output circuit system then outputs the digital feedback signal to the DAC circuit system, as described above.

[0023] The second sampled value is also provided as input to the stability checking circuitry. Therefore, the stability checking circuitry receives both the first and second sampled values ​​as input. The stability checking circuitry processes the sampled values ​​to determine or otherwise detect metastable conditions typically associated with analog logic subsystems (and particularly comparators).

[0024] For illustrative purposes, a metastable state is assumed. One or more components of the ADC can be controlled to reduce metastability, including a comparator circuitry and a synchronization circuitry. Additionally, control can be provided directly and / or indirectly. For example, when a metastable state is detected, a stability check circuitry can output an indication of the state to software executing on the processing core of the entire system in which the ADC is deployed. The software can then determine to adjust the ADC's operating parameters to bring the system out of the metastable state. Alternatively or additionally, the output of the stability check circuitry can be used by other components of the ADC itself to directly adjust the ADC's operating parameters to mitigate the occurrence of metastability.

[0025] More specifically, the timing of the comparator circuit system outputting the result of a comparison between its analog input signal and the analog feedback signal, and the timing of the synchronization circuit system sampling the comparison result, are based on various clock signals fed to the corresponding components of the ADC. For example, the comparator circuit system operates according to a first clock signal, while the synchronization circuit system operates according to second and third clock signals delayed relative to the first clock signal to perform corresponding operations after the comparator circuit system. In various instances, the synchronization circuit system includes two synchronizers, each configured to sample the result output by the comparator circuit system. The first synchronizer is fed the result and performs the sampling operation based on the second clock signal. The second synchronizer is also fed the result and performs the sampling operation based on the third clock signal. The third clock signal is delayed more than the second clock signal relative to the first clock signal, and therefore, the second synchronizer samples the result slightly later than the first synchronizer to produce a second sampled value.

[0026] The problem is that when the time between the comparator circuitry performing a comparison and the synchronous circuitry sampling is very short (e.g., 1 to 2 ns), the resulting signal passed from the comparator circuitry to the digital logic subsystem may be metastable because the comparator circuitry may not have enough time to resolve the value of the resulting signal into a stable binary value (0, 1). When the digital output circuitry uses metastable values ​​to generate a digital output signal, noise is introduced into the digital output signal. This noise cannot be attributed to the effective Gaussian noise of the ADC because the metastable values ​​cause inaccuracies in the digital output signal.

[0027] As disclosed herein, the stability check circuitry detects metastability at the comparator circuitry output earlier than in other cases because the synchronizer circuitry captures sampled values ​​from the comparator circuitry output and provides these sampled values ​​to the stability check circuitry before generating feedback and digital output signals. The timing and sequence of operations allow the ADC to take corrective and / or preventative actions before the digital output signal is fully completed and / or output for downstream use. For example, corrective actions may include guiding the digital output circuitry to use different (e.g., approximate) values ​​to generate the digital output signal, guiding the comparator circuitry to use updated parameters (e.g., trimmed settings) for subsequent comparison operations, etc. Preventative actions may include prematurely terminating the conversion operation, discarding digital output bits generated up to or after a certain time, etc.

[0028] Advantageously, ADCs are able to generate and operate stable digital output signals regardless of potential metastable signals output by the components of the ADC during the sampling and conversion process, which in turn reduces noise in the digital output signal and improves the performance of the ADC.

[0029] Turning now to the accompanying drawings, Figure 1 illustrates an example system configured to convert analog input signals into digital output signals in an embodiment. Figure 1 shows a system 100 that includes a microcontroller unit (MCU) 105 and sensor peripherals 135. The MCU 105 may include one or more processing cores 110, memory 115, an analog-to-digital converter (ADC) 120, input / output (I / O) devices 125, I / O devices 126, and peripherals 130.

[0030] In various instances, system 100 represents a processing system capable of converting an analog input signal into a digital output signal via ADC 120 and providing the digital output signal to downstream systems and devices (e.g., peripheral device 130). System 100 may be embodied in a circuit system for, for example, an embedded system (e.g., an integrated circuit (IC), a system-on-a-chip (SoC)) for use with an MCU 105. The elements of system 100 include dedicated, fixed-purpose hardware components capable of performing sampling and conversion operations as well as metastable detection operations, such as methods 300 and 301 of Figures 3A and 3B, respectively.

[0031] Processing core 110 refers to one or more processing units, cores, devices, or systems capable of executing program instructions from a memory device (e.g., memory 115) and controlling the operation of ADC 120 based on the execution of program instructions. Examples of processing core 110 may include general-purpose processing units, central processing units (CPUs), digital signal processors (DSPs), field-programmable arrays (FPGAs), application-specific integrated circuits (ASICs), and combinations and variations thereof.

[0032] Memory 115 refers to one or more non-transitory computer-readable storage media capable of storing data and program instructions for execution by processing core 110. Examples of memory 115 include volatile memory devices such as random access memory (RAM), tightly coupled memory (TCM), etc. Examples of memory 115 also include non-volatile memory devices such as flash memory. In some instances, MCU 105 may include multiple memory devices integrated together or separately.

[0033] ADC 120 represents an analog-to-digital conversion circuit system, such as a successive approximation register (SAR) ADC. ADC 120 is configured to receive an analog input signal (e.g., from a sensor peripheral device 135), convert the analog input signal into a corresponding digital output signal, and output a digital output signal for use by one or more devices, including internal devices (e.g., processing core 110, peripheral device 130) and external devices (e.g., sensor peripheral device 135).

[0034] I / O devices 125 and 126 represent interface devices comprising pins, ports, pads, or nodes configured to couple to and interface with sensor peripheral device 135. I / O devices 125 and 126 provide both internal and external connections to components of MCU 105 (e.g., ADC 120), such that when sensor peripheral device 135 is coupled to MCU 105 at I / O device 125 or I / O device 126, sensor peripheral device 135 can provide analog input signals to ADC 120 via I / O device 125 and / or I / O device 126. Thus, sensor peripheral device 135 may be off-chip relative to components of MCU 105. In some instances, sensor peripheral device 135 is on MCU 105. Peripheral device 130 represents an analog circuit, digital circuit, or processing device capable of implementing its corresponding function using digital output signals provided by ADC 120. Similarly, sensor peripheral device 135 refers to an analog circuit, digital circuit, or processing device, such as a sensor, capable of acquiring analog signals and driving the analog signals as inputs to ADC 120 via I / O devices 125 and 126.

[0035] Figure 2 shows an example block diagram 200 illustrating the components of ADC 120. In block diagram 200, ADC 120 includes an analog subsystem 210 and a digital subsystem 220. Analog subsystem 210 includes a digital-to-analog converter (DAC) 212 and a comparator 215, and digital subsystem 220 includes a synchronizer 225, a synchronizer 230, a successive approximation register (SAR) circuit 235, and a digital stability checker circuit 240.

[0036] DAC 212 indicates a digital-to-analog converter circuit system capable of converting analog inputs to digital outputs for use by other components of the ADC 120. In some instances, DAC 212 indicates a capacitor-type digital-to-analog converter.

[0037] DAC 212 is coupled to receive an analog input signal 205 from one or more sensor peripherals (e.g., sensor peripheral 135) and a feedback signal 236 from SAR circuitry 235. The analog input signal 205 contains a set of analog values ​​that will be converted by ADC 120 during an analog-to-digital conversion cycle. The feedback signal 236 represents a set of digital bits generated by SAR circuitry 235 and used to determine digital output signal 237. More specifically, each feedback signal generated by SAR circuitry 235 may correspond to an analog value (e.g., analog value 206) of analog input signal 205 and may be used during an analog-to-digital conversion cycle to generate digital output signal 237 for the analog value. Based on a given feedback signal, DAC 212 generates a weighted voltage 214 (e.g., an analog voltage representation of the digital bits of the feedback signal) according to the feedback signal and the corresponding analog input value (e.g., analog value 206) of analog input signal 205. This may require converting the feedback signal to an analog voltage value. DAC 212 outputs the weighted voltage 214 to comparator 215.

[0038] A comparator 215 is included to perform bit decisions regarding the analog-to-digital conversion cycle. Comparator 215 is coupled to receive a weighted voltage 214 from DAC 212, an analog value 206 (e.g., a reference value), and a clock signal 223 from a clock generation circuit. In operation, comparator 215 performs a comparison between the weighted voltage 214 and the analog value 206 to generate a decision signal 217. Decision signal 217 contains a binary value (e.g., 0, 1) corresponding to the result of the comparison performed by comparator 215. For example, decision signal 217 contains the value 1 if the weighted voltage 214 is higher than the analog value 206, and contains the value 0 if the weighted voltage 214 is lower than the analog value 206. The timing of comparator 215 generating and outputting decision signal 217 is based on clock signal 223.

[0039] Synchronizers 225 and 230 are included in ADC 120 to store the value of decision signal 217 at different times. Specifically, synchronizer 225 includes one or more flip-flops coupled to receive decision signal 217 and clock signal 224, while synchronizer 230 includes one or more flip-flops coupled to receive decision signal 217 and clock signal 222. Synchronizer 225 stores the decision value 226 associated with decision signal 217 at a time based on clock signal 224. Synchronizer 230 stores the decision value 231 associated with decision signal 217 at a time based on clock signal 222.

[0040] Clock signal 222 comprises a clock cycle sequence having a clock cycle delay relative to clock signal 224. Therefore, the time when synchronizer 230 stores decision value 231 occurs after the time when synchronizer 225 stores decision value 226. Taking into account the delay in capturing the value of decision signal 217, decision value 226 and decision value 231 may contain different values ​​based on the digital stability of ADC 120. In this way, synchronizer 230 provides redundancy in ADC 120 to determine digital stability by capturing a second value of decision signal 217 at a second time. In some instances, synchronizers 225 and 230 are both single-stage synchronizer devices, and therefore, corresponding values ​​can be captured to determine digital stability within a single clock cycle.

[0041] Synchronizer 225 is coupled to provide decision value 226 to SAR circuit 235 and digital stability checker circuit 240. Synchronizer 230 is coupled to provide decision value 231 to digital stability checker circuit 240.

[0042] SAR circuit 235 represents a sampling and conversion circuit system capable of executing an algorithm during an analog-to-digital conversion cycle to produce a digital output signal 237 for use by downstream systems (e.g., peripheral device 130). For example, ADC 120 is a 12-bit ADC. In such an example, SAR circuit 235 determines 12 bits within 12 conversion cycles to produce the digital output signal 237.

[0043] During each conversion cycle, SAR circuit 235 receives a value (e.g., decision value 226) from comparator 215 via synchronizer 225 and generates digital bits of digital output signal 237 based on feedback signal 236 and decision value 226. More specifically, based on decision value 226 containing 0 (e.g., indicating that a given feedback signal is lower than the corresponding analog value of analog input signal 205), SAR circuit 235 generates digital bits corresponding to the digital bits of feedback signal 237. Based on decision value 226 containing 1 (e.g., indicating that a given feedback signal is higher than the corresponding analog value), SAR circuit 235 generates digital bits of feedback signal 237 having the inverse value of the corresponding bit of the given feedback signal. SAR circuit 235 then generates another feedback signal to determine subsequent bits of digital output signal 237 associated with subsequent analog values ​​of analog input signal 205. The timing of operation of SAR circuit 235 is based on clock signal 221.

[0044] Furthermore, during each conversion cycle, the digital stability checker circuit 240 receives decision values ​​226 and 231 from the synchronizer and generates a result signal 242 based on the decision values ​​226 and 231. The digital stability checker circuit 240 represents one or more components capable of comparing decision values ​​226 and 231 to determine the digital stability state within the ADC 120. A metastable state occurs when the comparator 215 has not resolved the value of the decision signal 217 into a binary value (e.g., 0, 1) within a certain time amount (e.g., based on the delay between clock signals 223 and 224). Therefore, the decision value 226 can be 0 or 1, and has no reliable relationship to the final state of the decision signal 217, or, by extension, no reliable relationship to the decision value 231 generated later in the same cycle. A digital stability state occurs when the decision values ​​226 and 231 contain the same value.

[0045] By way of example, the digital stability checker circuit 240 generates a result signal 242 indicating a metastable state based on decision values ​​226 and 231, which have different values. Specifically, synchronizer 225 stores decision value 226 at a first time, during which time decision signal 217 contains values ​​between 0 and 1 (i.e., not yet resolved to 0 or 1) (e.g., unstable values). Then, synchronizer 230 stores decision value 231 at a later second time, during which time decision signal 217 contains either 0 or 1 (e.g., stable values). The different values ​​of decision values ​​226 and 231 indicate that comparator 215 is metastable for at least a duration during operation. Based on the result signal 242 indicating a metastable state output by digital stability checker circuit 240, the operation of SAR circuit 235 can be controlled to avoid generating erroneous digital bits in digital output signal 237 (e.g., output containing spark code).

[0046] Based on the result signal 242 indicating digital stability (e.g., decision values ​​226 and 231 are the same), the SAR circuit 235 operates as described above to generate a digital output signal 237. However, based on the result signal 242 indicating metastability within the ADC 120 (e.g., decision values ​​226 and 231 are different), the SAR circuit 235 may terminate the conversion cycle earlier (e.g., by approximating the digital output signal 237 using previously captured bits instead of one or more metastable bits), or generate the digital output signal 237 based on decision value 231. Examples of operations performed by components of the ADC 120 to detect metastability are shown and described below in methods 300 and 301 of Figures 3A and 3B.

[0047] Referring now to Figures 3A and 3B, methods 300 and 301 can be implemented logically within the context of the hardware elements of an analog-to-digital converter (e.g., ADC 120). When executed by ADC 120, the logic directs its components to operate as follows, referring to the elements of system 200 of Figure 2. In particular, method 300 relates to operations performed by the analog subsystem 210 of ADC 120, while method 301 relates to operations performed by the digital subsystem 220 of ADC 120.

[0048] To initiate method 300, in operation 305, DAC 212 of ADC 120 receives an analog input signal 205 from a device (e.g., a sensor peripheral device) to convert it into a digital output signal 237. To begin converting the analog input signal, DAC 212 receives an analog value of the analog input signal and a feedback signal 236 from SAR circuitry 235. During the first conversion cycle, the feedback signal 236 may contain an initial value (e.g., a value containing the most significant bit set to 1 and all other bits set to 0) to initialize the conversion cycle. Based on the feedback signal 236, DAC 212 generates a weighted voltage 214 that varies with the feedback signal 236, based on converting the feedback signal 236 into an analog voltage. For a given value (e.g., analog value 206), DAC 212 outputs the weighted voltage 214 and the analog value 206 to comparator 215.

[0049] Comparator 215 compares the weighted voltage 214 with the analog value 206 to determine whether the weighted voltage 214 is higher or lower than the analog value 206. After comparing the values, in operation 310, comparator 215 generates a decision signal 217 with a binary value (e.g., 0, 1) indicating the comparison result. For example, decision signal 217 contains the value 1 based on the weighted voltage 214 being higher than the analog value 206, and contains the value 0 based on the weighted voltage 214 being lower than the analog value 206. In operation 315, comparator 215 outputs decision signal 217 to synchronizers 225 and 230 at a time based on clock signal 223.

[0050] Next, components of digital subsystem 220 receive decision signal 217 to begin method 301 of FIG3B. In operation 320, synchronizer 225 receives decision signal 217 and stores the value of decision signal (e.g., decision value 226) at a time based on clock signal 224, and synchronizer 230 receives decision signal 217 and stores the value of decision signal (e.g., decision value 231) at a time based on clock signal 222. In various instances, synchronizer 225 stores decision value 226 after comparator 215 outputs decision signal 217 but before synchronizer 230 stores decision value 217 based on the corresponding clock signal. In some such instances, decision value 226 differs from decision value 231 based on the delay in capturing the corresponding value of decision signal 216. For example, if comparator 215 cannot resolve the comparison within the duration based on clock signal 223, then the value of decision signal 217 may contain values ​​between 0 and 1 (e.g., not yet resolved, but, for example, metastable). However, when synchronizer 230 captures decision value 231, the value of decision signal 217 may contain 0 or 1.

[0051] Synchronizer 225 outputs a decision signal with decision value 226 to SAR circuit 235 and digital stability checker circuit 240. Synchronizer 230 outputs a decision signal with decision value 231 to digital stability checker circuit 240.

[0052] In operation 325, SAR circuit 235 identifies decision value 226 and generates digital output signal 237 and feedback signal 236 based on decision value 226. Generating digital output signal 237 may require executing one or more algorithms to determine the digital bit value of digital output signal 237 based on decision value 226. More specifically, SAR circuit 235 determines the digital bit value of digital output signal 237 based on previously output feedback signal and based on decision value 226. Then, SAR circuit 235 generates another feedback signal with a different bit combination than the previously provided feedback signal. SAR circuit 235 outputs feedback signal 236 to DAC 212 for further use during the conversion cycle (if not completed), and SAR circuit 235 outputs digital output signal 237 for use by downstream subsystems after the conversion cycle is completed.

[0053] During the conversion cycle, in operation 330, the digital stability checker circuit 240 compares decision values ​​226 and 231, captured by synchronizers 225 and 230 respectively, to determine the metastable state of the decision signal 217. Based on the identification that decision values ​​226 and 231 are the same, the digital stability checker circuit 240 determines that the decision signal 217 is a metastable signal, and therefore, the state of the ADC 120 corresponds to a digital stability state. Based on the identification that decision values ​​226 and 231 are different, the digital stability checker circuit 240 determines that the decision signal 217 contains metastable values, and therefore, the state of the ADC 120 corresponds to a metastable state at least for the duration of the operation.

[0054] In operation 335, the digital stability checker circuit 240 generates a result signal 242 based on the metastable state. The result signal 242 may contain a first value indicating the digital stability state or a second value indicating the metastable state. In operation 340, the digital stability checker circuit 240 outputs the result signal 242. In some instances, the digital stability checker circuit 240 provides the result signal 242 to one or more processing cores (e.g., processing core 110), the SAR circuit 235, and / or one or more downstream subsystems.

[0055] Figure 4 illustrates an example block diagram 400 of additional components of the ADC 120 in the implementation scheme. Block diagram 400 includes a processing core 110 and an ADC 120. In block diagram 400, the ADC 120 includes various components categorized and arranged within the analog subsystem 210 and the digital subsystem 220.

[0056] Analog subsystem 210 includes circuitry for ADC 120 configured to perform analog logic operations related to analog-to-digital conversion. Digital subsystem 220 includes circuitry for ADC 120 configured to perform digital logic operations related to analog-to-digital conversion. Analog logic operations refer to operations performed by components of ADC 120 on analog signals, while digital logic operations refer to operations performed by components of ADC 120 on digital signals. Some components may perform operations on both types of signals.

[0057] As shown in block diagram 400, analog subsystem 410 includes digital-to-analog converter (DAC) 212, comparator 215, delay module 420, and delay module 425. Digital subsystem 220 includes synchronizer 225, synchronizer 230, digital stability checker circuit 240, inverting module 435, feedback signal calculation module 440, flip-flop 445, result circuit system 450, finite state machine (FSM) 455, and digital stability counter circuit 460.

[0058] DAC 212 includes an array of electrical components (e.g., resistors, capacitors) having an input coupled to receive analog input signal 205, an input coupled to receive feedback signal 236 from feedback signal calculation module 440, and an output coupled to comparator 215. For each feedback signal received by DAC 212, DAC 212 generates a corresponding weighted voltage (e.g., an analog representation of the digital bits of the feedback signal) and outputs the weighted voltage to comparator 215. DAC 212 also outputs an analog value of analog input signal 205 to comparator 215. In the example shown in block diagram 400, DAC 212 receives feedback signal 236 and generates a weighted voltage 214 based on feedback signal 236. DAC 212 outputs the weighted voltage and the corresponding analog value 206 of analog input signal 205 to comparator 215.

[0059] Comparator 215 includes amplifier 416 and latch 417 to perform a comparison operation with respect to an analog value and a weighted voltage and generate a decision signal 217. For example, amplifier 416 receives a weighted voltage 214 and an analog value 206 as inputs, amplifies the voltage inputs, and outputs the amplified weighted voltage and analog value to latch 417. Latch 417 receives the amplified versions of the weighted voltage 214 and the analog value 206 and stores a binary value (e.g., 0, 1) based on a comparison of the values ​​at a time based on clock signal 407 (e.g., at the rising edge of a clock cycle of clock signal 407). More specifically, latch 417 may store a value of 1 based on the weighted voltage 214 being higher than the analog value 206, and a value of 0 based on the weighted voltage 214 being lower than the analog value 206. The latch 417 then outputs a decision signal 217, which includes an indication of the comparison result based on the clock signal 407 (e.g., at the rising edge of the clock cycle of the clock signal 407).

[0060] Synchronizers 225 and 230 are coupled to receive a decision signal 217 from latch 417. Synchronizers 225 and 230 are further coupled to receive clock signals 408 and 406, respectively. Synchronizer 225 stores the value of decision signal 217 (e.g., decision value 226) (e.g., 0, 1) at a time based on clock signal 408, while synchronizer 230 stores the value of decision signal 217 (e.g., decision value 231) (e.g., 0, 1) at a different time based on clock signal 406. Synchronizer 225 outputs decision value 226 to feedback signal calculation module 440, trigger 445, and digital stability checker circuit 240. Synchronizer 230 outputs decision value 231 to digital stability checker circuit 240.

[0061] The feedback signal calculation module 440 represents one or more elements of a successive approximation register (SAR) circuitry (e.g., SAR circuit 235) capable of generating a feedback signal 236 based on the decision value 226. Specifically, the feedback signal calculation module 440 identifies the decision value 226 and determines a new combination of digital bits (relative to a previously output bit combination) based on the decision value 226. For example, the first feedback signal comprises a first bit sequence containing a - (1) for the first bit (e.g., the most significant bit) and zeros (0) for the remaining bits. Based on the decision value 226, the feedback signal calculation module 440 generates a second feedback signal comprising a second bit sequence containing a - (1) for the second bit and zeros (0) for the remaining bits. Each bit combination can be used to determine a digital bit of the digital output signal 237 corresponding to the analog value of the analog input signal 205. The feedback signal calculation module 440 outputs the second feedback signal to the DAC 212 to repeat the conversion process described above.

[0062] Trigger 445 and result circuit system 450 are also included in the SAR circuit system. Trigger 445 stores decision value 226 and outputs decision value 226 to result circuit system 450. Result circuit system 450 generates digital output signal 237 based on decision value 226 and feedback signal 236. For example, for a first digital bit, after determining that decision value 226 is a value indicating that weighted voltage 214 is higher than analog value 206 (e.g., 1), result circuit system 450 determines a value opposite to the value of the first feedback signal output by feedback signal calculation module 440. Similarly, for a first digital bit, after determining that decision value 226 is a value indicating that weighted voltage 214 is lower than analog value 206 (e.g., 0), result circuit system 450 determines the first digital bit based on the corresponding value of the first feedback signal. After determining all digital bits of digital output signal 237, result circuit system 450 outputs digital output signal 237.

[0063] The FSM 455 is also included in the SAR circuitry to control the operation of the result circuitry 450. Specifically, the FSM 455 operates based on a clock signal 405 to determine the start and end of each conversion cycle of the analog-to-digital conversion period. Based on determining the end of the last conversion cycle, the FSM 455 outputs an End-of-Conversion (EOC) signal 456 (e.g., a signal indicating the last conversion cycle in the conversion period) to the result circuitry 450. Upon receiving the EOC signal 456, the result circuitry 450 generates the last bit of the digital output signal 237 and outputs the digital output signal 237. The FSM 455 also outputs the EOC signal 456 to other components (e.g., peripheral device 130) to provide an indication of the end of the conversion cycle.

[0064] During the conversion cycle, digital stability checker circuit 240 compares decision values ​​226 and 231, captured by synchronizers 225 and 230 respectively, to determine the metastable state of decision signal 217. In various instances, synchronizer 225 stores decision value 226 before synchronizer 230 stores decision value 231 based on the delay between clock signals 406 and 408. In some instances, decision value 226 may differ from decision value 231. Decision value 226 may contain a value between 0 and 1 (e.g., a metastable value) because latch 417 failed to resolve the comparison between weighted voltage 214 and analog value 206 within the time period based on clock signals 407 and 408. If latch 417 resolves the comparison within the time period based on clock signals 407 and 409, then synchronizer 230 stores decision value 231 containing either 0 or 1, and therefore, decision values ​​226 and 231 have different values.

[0065] Based on the fact that decision values ​​226 and 231 are the same, the digital stability checker circuit 240 determines that decision signal 217 is a metastable signal, and therefore, the state of ADC 120 corresponds to a digital stability state. However, based on the fact that decision values ​​226 and 231 are different, the digital stability checker circuit 240 determines that decision signal 217 contains metastable values, and therefore, the state of ADC 120 corresponds to a digital instability state. The digital stability checker circuit 240 generates a result signal 242 indicating the metastable state and outputs the result signal 242 to the result circuit system 450, FSM 455, processing core 110, and digital stability control circuit 460.

[0066] Upon receiving the result signal 242 indicating digital instability (metastability), the FSM 455 controls the operation of the result circuit system 450. For example, the FSM 455 may provide the EOC signal 456 to the result circuit system 450 before the end of the conversion cycle to prematurely terminate its operation. In such an example, the result circuit system 450 may output a digital output signal 237 (an approximation) based on the final result of the digital signal calculated using bits captured before metastability was detected and zeros (0) for lower-order bits (e.g., least significant bits). Alternatively, the FSM 455 may instruct the result circuit system 450 to use decision value 231 instead of decision value 226 to generate specific digital bits of the digital output signal 237. In this way, if decision value 226 contains a metastable value but decision value 231 contains a stable value, the result circuit system 450 may generate a digital output signal 237 with one or more stable values ​​to avoid generating noisy or erroneous digital bits.

[0067] A digital stability counter circuit 460 is included in the ADC 120 to maintain the counter values ​​and control parameters of the components of the analog subsystem 210. Specifically, the digital stability counter circuit 460 includes a counter and increments the counter value based on a result signal 242 indicating metastability within the ADC 120. When the counter value exceeds a threshold counter value, the digital stability counter circuit 460 outputs an interrupt signal 461 to the processing core 110, a delay signal 462 to the delay module 420, a trim signal 463 to the comparator 215, and a delay signal 464 to the delay module 425.

[0068] Interrupt signal 461 indicates that the counter value of digital stability counter circuit 460 exceeds a threshold counter value. In response to receiving interrupt signal 461, processing core 110 can be configured to use decision value 231 to determine and replace the digital bits of digital output signal 237. By way of yet another example, processing core 110 may not use digital output signal 237 based on metastability detection.

[0069] Delay signal 462, trimming signal 463, and delay signal 464 indicate parameters that components of analog subsystem 210 can implement to update their operation or timing. More specifically, trimming signal 463 may contain trimming parameters (e.g., input reference voltage) implemented by comparator 215 to configure operating settings for a current or upcoming comparison operation. Delay signal 462 may contain delay parameters indicating the amount of delay added to or removed from clock signal 407 by delay module 420. Similarly, delay signal 464 may contain delay parameters indicating the amount of delay added to or removed from clock signal 408 by delay module 425. Clock signals 407 and 408 contain two of the clock signals used by ADC 120 to time the operation of components of ADC 120.

[0070] Referring more specifically to the clock signal shown in block diagram 400, the components of ADC 120 operate based on clock signal 405 and its variations as discussed above. Clock signal 405 represents a first clock signal provided to inverting module 435 and FSM 455 of digital subsystem 220. Clock signal 405 contains a first clock cycle sequence for coordinating the operation of the components. Inverting module 435 inverts the first clock cycle sequence to generate clock signal 406. Therefore, clock signal 406 contains a second clock cycle sequence inverted relative to the first clock cycle sequence. In some instances, inverting module 435 inverts the first clock cycle sequence such that the second clock cycle sequence is 180 degrees out of phase with respect to the first clock cycle sequence. Inverting module 435 provides clock signal 406 to synchronizer 230 and delay module 420.

[0071] Delay module 420 first inverts the second clock cycle sequence (e.g., by 180 degrees) to generate a third clock cycle sequence that is in phase with the first clock cycle sequence relative to clock signal 405. Next, delay module 420 delays the third clock cycle sequence by an offset to generate a clock signal 407 having a third clock cycle sequence that transitions between logic states (e.g., 0 to 1, 1 to 0) at a later time relative to the clock cycles of clock signals 405 and 406. Delay module 420 outputs clock signal 407 to latch 417 of comparator 215 and delay module 425.

[0072] The delay module 425 further delays the third clock cycle sequence to generate a fourth clock signal, namely clock signal 408, which includes a fourth clock signal sequence. Therefore, the transitions between logic states in the fourth clock cycle sequence are later than the clock cycles of clock signals 405, 406, and 407. The delay module 425 outputs clock signal 408 to synchronizer 225. Thus, comparator 215 operates based on clock signal 407 before synchronizers 225 and 230 (e.g., compares and outputs decision signal 217), and synchronizer 225 operates before synchronizer 230 operates (e.g., stores decision value 231) (e.g., stores decision value 226).

[0073] The delay between the operations of each component is based on the offset added to the corresponding clock cycle. Therefore, based on the delayed signals 462 and 464 output by the digital stability counter circuit 460, the operation of the synchronizer 225 can be delayed relative to the operation of the comparator 215, allowing more time before the synchronizer 225 captures the decision value 217. This further increases the amount of time the comparator 215 must spend resolving the value of the decision signal 217. In this way, the digital stability counter circuit 460 can reduce the likelihood of metastability in the ADC 120.

[0074] The timing diagram 500 in Figure 5 illustrates the visual representation of the clock signal. Timing diagram 500 shows instance logic state values ​​output by components of the system (e.g., ADC 120) at different times during sampling and conversion operations. The state values ​​shown by timing diagram 500 are described as logic high ("1" or "on") and logic low ("0" or "off") depending on the state of the corresponding signal.

[0075] The sampling enable signal 501 represents a signal that controls the sampling operation of the ADC 120. When in a logic high state, the sampling enable signal 501 enables the ADC 120 to perform a sampling operation on the analog input signal 205, and when in a logic low state, the sampling enable signal 501 enables the ADC 120 to maintain the sampled voltage value by providing a corresponding analog signal with the sampled voltage value for conversion. In various instances, the processing core 110 provides the sampling enable signal 501 to the ADC 120, and the ADC 120 performs the sampling operation when the sampling enable signal 501 indicates a logic high state.

[0076] Clock signal 405 is a first clock signal provided to ADC 120. Clock signal 405 includes a first clock cycle sequence that transitions multiple times between a low logic state and a high logic state starting at time 512 based on the conversion cycle of ADC 120.

[0077] Clock signals 406, 407, and 408 are clock signals generated based on clock signal 405. Clock signal 406 includes a second clock cycle sequence that is out of phase (e.g., 180 degrees) with respect to a first clock cycle sequence. For example, when the first clock cycle sequence of clock signal 405 transitions from a high logic state to a low logic state, the second clock cycle sequence transitions from a low logic state to a high logic state. Clock signal 407 includes a third clock cycle sequence that is in phase with respect to the first clock cycle sequence but offset by a delay. Therefore, the third clock cycle sequence transitions between logic states later than the clock cycles of clock signals 405 and 406. Clock signal 408 includes a fourth clock signal sequence that is in phase with respect to the first and third sets of clock cycles but offset by another delay. Therefore, the fourth clock cycle sequence transitions between logic states later than the clock cycles of clock signals 405, 406, and 407.

[0078] The metastability check enable signal 502 represents a signal that controls the operation of the digital stability checker circuit 240 during the transition cycle. More specifically, when the metastability check enable signal 502 is in a high logic state, the digital stability checker circuit 240 is enabled to perform a comparison between the values ​​provided to the digital stability checker circuit 240 by synchronizers 225 and 230, and outputs a result signal 242 based on the comparison. The metastability check enable signal 502 may transition to a high logic state based on the clock signal 408 and may remain in a high logic state until the transition cycle is complete.

[0079] Decision signal value capture phases 503 and 504 refer to sub-loops during the transition period, during which synchronizers 225 and 230 store decision values ​​226 and 231, respectively. Decision signal value capture phase 503 is based on clock signal 408, while decision signal value capture phase 504 is based on clock signal 406. More specifically, the capture operation performed by synchronizer 225 during decision signal value capture phase 503 occurs based on the transition of clock signal 408 from a logic low state to a logic high state (e.g., at time 516). The capture operation performed by synchronizer 230 during decision signal value capture phase 504 occurs based on the transition of clock signal 406 from a logic low state to a logic high state (e.g., at time 517).

[0080] Comparison phase 505 refers to a sub-loop during the transition period, during which the digital stability checker circuit 240 compares decision values ​​226 and 231 during decision signal value capture phases 503 and 504. Comparison phase 505 is based on clock signal 407. More specifically, the comparison operation performed by the digital stability checker circuit 240 occurs based on the transition of clock signal 407 from a logic high state to a logic low state after decision signal value capture phases 503 and 504 (e.g., at time 519).

[0081] The conversion end signal 456 indicates that the FSM 455 outputs the signal at the end of the conversion cycle as its indication. In the example where ADC120 represents a 12-bit ADC, the FSM 455 outputs the conversion end signal 456 at the transition of the last clock cycle of clock signal 405 (e.g., the 14th clock cycle). When the conversion end signal 456 transitions from a logic high state to a logic low state (e.g., at time 523), the digital output signal 506 (e.g., digital output signal 237) can be latched by the ADC 120 and output to downstream devices and systems.

[0082] More specifically referring to a particular time point in timing diagram 500, at time 510, the sampling enable signal 501 transitions from a logic low state to a logic high state to begin the sampling period. From time 510 until time 511, the ADC 120 samples the analog input signal 205 before beginning the conversion period. At time 511, the sampling enable signal 501 transitions from a logic high state to a logic low state, ending the sampling period. From time 511 to time 512, while the clock signal remains at a logic low state, the DAC 212 of the ADC 120 holds the sampled value of the analog input signal 205. During this hold state beginning at time 511, the DAC 212 generates a weighted voltage based on the feedback signal 236 for comparison with the analog input signal 205.

[0083] At time 512, clock signal 405 transitions from a logic low state to a logic high state and continues to transition between each state with a given duty cycle. At time 513, clock signal 405 transitions from a logic high state to a logic low state, and clock signal 406 transitions from a logic low state to a logic high state, and continues to transition between each state with a given duty cycle, such that clock signals 405 and 406 transition between opposite states relative to each other until the end of the transition cycle.

[0084] Additionally, at time 513, the amplifier 416 of comparator 215 receives a weighted voltage (e.g., weighted voltage 214) corresponding to the first bit used for conversion (e.g., analog value 206), and amplifies the voltage to a higher level for use by the latch 417 of comparator 215. At time 514, clock signal 405 transitions from a logic low state to a logic high state, and therefore, clock signal 406 transitions from a logic high state to a logic low state. At this time, latch 417 generates decision signal 217 based on the weighted voltage and the corresponding analog value.

[0085] At time 515, clock signal 407 transitions from a logic low state to a logic high state. As clock signal 407 transitions to logic high, latch 417 outputs decision signal 217 to synchronizers 225 and 230. Shortly thereafter, at time 516, clock signal 408 transitions from a logic low state to a logic high state. As clock signal 408 transitions to logic high, metastability check enable signal 502 also transitions to logic high to enable metastability detection and initiate the decision signal value capture phase 503. During the decision signal value capture phase 503, synchronizer 225 obtains the decision signal 217 from latch 417 and stores a first value associated with decision signal 217 (e.g., decision value 226) at time 516 (represented by "comp0" in the decision signal value capture phase 503 of timing diagram 500).

[0086] Between 516 and 517, the feedback signal calculation module 440 obtains the decision value 226 stored by the synchronizer 225, generates a feedback signal 236 based on the decision value 226, and outputs the feedback signal 236 to the DAC 212.

[0087] At time 517, clock signal 405 transitions from a logic high state to a logic low state, and clock signal 406 transitions from a logic low state to a logic high state. As clock signal 406 transitions to a logic high state, and the metastability check enable signal 502 is in a logic high state, decision signal value capture phase 504 is initiated. During this period, synchronizer 230 obtains decision signal 217 from latch 417 and stores a second value (e.g., decision value 231) associated with decision signal 217 at time 517 (represented by "comp0" in decision signal value capture phase 504 in timing diagram 500).

[0088] In various instances, the duration between 515 and 516 when comparator 215 generates and outputs decision signal 217 and synchronizer 225 captures decision value 226 is shorter than the duration between 515 and 517 when comparator 215 generates and outputs decision signal 217 and synchronizer 230 captures decision value 231. In some such instances, decision value 226 differs from decision value 231 because latch 417 may not have resolved the value of decision signal 217 before time 516 when synchronizer 225 stores decision value 226. In such instances, decision signal 217 is referred to as metastable. However, based on the longer duration from time 515 to time 517, latch 417 may have resolved the value of decision signal 217 by the time synchronizer 230 stores decision value 231 at time 517, and therefore, decision signal 217 may not have been in a metastable state before time 517.

[0089] Furthermore, at time 517, amplifier 416 can obtain a weighted voltage corresponding to the second bit (e.g., bit 1) used for conversion based on feedback signal 236. Amplifier 416 amplifies the voltage to a higher voltage signal for use by latch 417 to repeat the above process. At time 418, clock signal 405 transitions from logic low to logic high, and clock signal 406 transitions from logic high to logic low. At this time, latch 417 receives the weighted voltage and the corresponding analog value and generates a decision signal 217 with a value based on the weighted voltage and the analog value.

[0090] At time 519, clock signal 407 transitions from logic low to logic high, and therefore, latch 417 outputs decision signal 217 to synchronizers 225 and 230. Shortly thereafter, at time 520, clock signal 408 transitions from logic low to logic high. During these times, metastability check enable signal 502 remains in the logic high state, thus initiating the second capture phase of decision signal value capture phase 503. During the second capture phase of decision signal value capture phase 503, synchronizer 225 obtains decision signal 217 from latch 417 and stores the value associated with decision signal 217 at time 520 (represented by "comp1" in decision signal value capture phase 503 in timing diagram 500).

[0091] Furthermore, at time 519, a comparison phase 505 occurs, during which the digital stability checker circuit 240 obtains decision values ​​226 and 231 and performs a comparison between the two values. The digital stability checker circuit 240 generates a result signal 242 that indicates the metastable state, including the decision signal 217. If the two values ​​are the same, the digital stability checker circuit 240 outputs an indication of digital stability; if the two values ​​are different, the digital stability checker circuit 240 outputs an indication of digital instability or metastability. In various instances, the transition cycle may continue or may terminate based on the metastable state.

[0092] Following an instance where the conversion cycle continues, the ADC 120 can use various clock signals and repeat the above operations based on their rising and falling edges. For example, during a continued conversion cycle, at time 521, clock signal 405 transitions from a logic high state to a logic low state, and clock signal 406 transitions from a logic low state to a logic high state. As clock signal 406 transitions to a logic high state, and based on the metastability check enable signal 502 being in a logic high state, a decision signal value capture stage 504 can be enabled, during which synchronizer 230 obtains decision signal 217 from latch 417 and stores the value associated with decision signal 217 at time 521 (represented by "comp1" in the decision signal value capture stage 504 in timing diagram 500). Again, after the ADC 120 generates the second bit of the digital output signal, a second iteration of comparison stage 505 can occur to determine the metastability state. The conversion cycle can continue or terminate after the second iteration of comparison stage 505 based on the metastability state determined by digital stability checker circuit 240.

[0093] Following the above example, the ADC 120 can continue the conversion cycle until a digital output signal is generated based on the analog input signal 205 at time 522. At time 522, a conversion end signal 456 can be output by the FSM 455, indicating the end of the conversion cycle. When the conversion end signal 456 transitions from a logic high state to a logic low state at time 523, the ADC 120 outputs the digital output signal 506. The sampling and conversion cycle can start again with different analog input data after the same or similar process as shown in timing diagram 500.

[0094] In some instances, the conversion cycle can be terminated early based on a metastable state. For example, after the first, second, or another stage of the comparison stage 505, based on the digital stability checker circuit 240 determining that the decision signal 217 is in a metastable state, the FSM 455 can control the result circuit system 450 to end the conversion cycle by providing a conversion end signal 456 to the result circuit system 450 before time 522. In some such instances, the result circuit system 450 uses less than 12 bits of data to generate the digital output signal. In some such instances, the result circuit system 450 can use values ​​stored by synchronizer 225 and / or synchronizer 230, or combinations or variations thereof, to generate the digital output signal.

[0095] While some of the examples provided herein are described in the context of digital signal processing systems, sampling and conversion circuit systems, power circuit systems, clock generation circuit systems, metastability detection circuit systems, counter circuit systems, logic circuit systems, embedded systems or systems-on-a-chip, subcircuits, systems, subsystems, components, devices, architectures, or environments, it should be understood that the circuits, devices, logic elements, and other components, systems, and methods described herein are not limited to such embodiments and can be applied to a wide variety of other processes, systems, applications, devices, etc., such as other circuits, logic devices, transistors, etc., in the context of, for example, sampling and conversion functions. Therefore, aspects of the invention can be embodied in other systems, methods, and other configurable systems.

[0096] Unless the context clearly requires otherwise, throughout the specification and claims, the terms “comprise,” “comprising,” etc., shall be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense; that is, in the sense of “including but not limited to.” As used herein, the terms “connection,” “coupling,” or any variation thereof mean any direct or indirect connection or coupling between two or more elements; the coupling or connection between elements may be physical, logical, or a combination thereof. Additionally, when used in this application, the terms “this article,” “above,” “below,” and similar terms refer to the entire application and not any particular part of it. Where the context permits, the singular or plural terms used in the above specific embodiments may also include either the plural or the singular, respectively. The term “or” relating to a list of two or more items covers all of the following interpretations of the term: any one of the items in the list, all the items in the list, and any combination of the items in the list.

[0097] The phrases “in some embodiments,” “according to some embodiments,” “in the illustrated embodiments,” “in other embodiments,” etc., generally mean that the specific feature, structure, or characteristic following the phrase is included in at least one embodiment of the invention, and may be included in more than one embodiment. Furthermore, such phrases do not necessarily refer to the same embodiment or different embodiments.

[0098] The specific embodiments of the technology described above are not intended to be exhaustive or to limit the technology to the exact forms disclosed above. While specific examples of the technology have been described above for illustrative purposes, those skilled in the art will recognize that various equivalent modifications can be made within the scope of the technology. For example, although processes or blocks are presented in a given order, alternative implementations may execute routines with steps or employ systems with blocks in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified to provide alternatives or sub-combinations. Each of these processes or blocks can be implemented in many different ways. Furthermore, while processes or blocks are sometimes presented as being executed sequentially, these processes or blocks may be changed to be executed or implemented in parallel, or may be executed at different times. Additionally, any specific numbers mentioned herein are merely examples; alternative implementations may employ different values ​​or ranges.

[0099] The teachings of the techniques provided herein can be applied to other systems, not necessarily those described above. The elements and actions of the various examples described above can be combined to provide further implementations of the techniques. Some alternative implementations of the techniques may include not only the additional elements of those implementations mentioned above, but also fewer elements.

[0100] These and other changes can be made to the technology according to the specific embodiments described above. While the above descriptions depict certain instances of the technology and describe the best mode contemplated, the technology can be practiced in many ways, however detailed the descriptions may be. The details of the system can vary significantly in its particular implementation, while still being covered by the technology disclosed herein. As noted above, specific terms used in describing certain features or aspects of the technology should not be construed as implying that such terms are redefined herein as limited to any particular characteristic, feature, or aspect of the technology associated with those terms. Generally, unless such terms are explicitly defined in the above detailed description sections, the terms used in the appended claims should not be construed as limiting the technology to the specific instances disclosed in the specification. Therefore, the actual scope of the technology covers not only the disclosed instances but also all equivalent ways of practicing or implementing the technology in the claims.

[0101] To reduce the number of claims, certain aspects of the technology are presented below in certain claim forms, but the applicant may consider aspects of the technology in any number of claim forms. For example, while only one aspect of the technology may be described as a computer-readable media claim, other aspects may also be embodied as a computer-readable media claim, or in other forms, such as a means plus function claim. Any claim intended to be treated under 35 USC § 112(f) will begin with the phrase “means for…”, but the use of the term “for” in any other context is not intended to invoke treatment under 35 USC § 112(f). Therefore, the applicant reserves the right to seek appended claims after the filing of this application, in order to seek such appended claim forms in this application or a continuing application.

Claims

1. An analog-to-digital converter, comprising: A comparator circuit system configured to perform a comparison between an analog input signal and an analog feedback signal, and output the result of the comparison; A synchronous circuit system configured to sample the result of the comparison at different times to generate a first sample value and a second sample value; A digital output circuit system configured to generate a digital output signal based on the first sampled value and output the digital output signal; and a stability checking circuit system configured to determine whether a metastable condition has occurred in the analog-to-digital converter based on the first sampled value and the second sampled value, and output an indication of whether the metastable condition has occurred.

2. The analog-to-digital converter of claim 1, wherein, in order to detect whether the metastable condition has occurred, the stability checking circuit system is configured to perform a sample comparison between the first sample value and the second sample value, thereby generating a sample comparison result.

3. The analog-to-digital converter of claim 2, wherein the stability checking circuitry is configured to determine that the metastable state has occurred when the result of the sample comparison indicates that the first sample value is different from the second sample value.

4. The analog-to-digital converter of claim 1, further comprising a stability counter circuit system configured to: increment a counter based on an indication indicating the occurrence of the metastable condition output by the stability check circuit system; and output one or more trimmed values ​​associated with the comparator circuit system in response to the counter exceeding a threshold.

5. The analog-to-digital converter of claim 1, further comprising a stability counter circuit system configured to: increment a counter based on an indication indicating the occurrence of the metastable condition output by the stability check circuit system; and, in response to the counter exceeding a threshold, output an interrupt to one or more processing cores.

6. The analog-to-digital converter of claim 5, wherein the one or more processing cores are configured to adjust one or more trim values ​​associated with the comparator circuitry based on the interrupt.

7. The analog-to-digital converter of claim 1, wherein the digital output circuit system is further configured to generate a digital feedback signal based on the first sampled value and to output the digital feedback signal.

8. The analog-to-digital converter of claim 7, further comprising a digital-to-analog converter circuit system configured to convert the digital feedback signal into the analog feedback signal.

9. A system comprising: One or more processing cores; And an analog-to-digital converter, comprising: a comparator circuit system configured to perform a comparison of an analog input signal with an analog feedback signal and output the result of the comparison; a synchronization circuit system configured to sample the result of the comparison at different times to generate a first sample value and a second sample value; a digital output circuit system configured to generate a digital output signal based on the first sample value and output the digital output signal to one or more processing cores; and a stability check circuit system configured to detect a metastable state of the comparator circuit system based on the first sample value and the second sample value and output an indication of whether the metastable state has occurred.

10. The system of claim 9, wherein, in order to detect the metastable state, the stability checking circuit system is configured to perform a sample comparison between the first sample value and the second sample value, thereby generating a sample comparison result.

11. The system of claim 10, wherein the stability checking circuitry is configured to determine that the metastable state exists when the result of the sample comparison indicates that the first sample value is different from the second sample value.

12. The system of claim 9, further comprising a stability counter circuit system configured to: increment a counter whenever the stability check circuit system outputs an indication indicating that the metastable condition has occurred; and output one or more trimmed values ​​associated with the comparator circuit system in response to the counter exceeding a threshold.

13. The system of claim 9, further comprising a stability counter circuit system configured to: increment a counter whenever the stability check circuit system outputs an indication indicating that the metastable condition has occurred; and, in response to the counter exceeding a threshold, output an interrupt to the one or more processing cores.

14. The system of claim 13, wherein the one or more processing cores are configured to adjust one or more trim values ​​associated with the comparator circuitry based on the interrupt.

15. The system of claim 9, wherein the digital output circuit system is further configured to generate a digital feedback signal based on the first sampled value and to output the digital feedback signal.

16. The system of claim 15, further comprising a digital-to-analog converter circuitry configured to convert the digital feedback signal into the analog feedback signal.

17. A method for controlling metastability in an analog-to-digital converter (ADC) device, the method comprising performing the following operations via a circuit system of the ADC device: performing a comparison of an analog input signal with an analog feedback signal and outputting a result of the comparison; sampling the result of the comparison at different times to generate a first sampled value and a second sampled value; generating a digital output signal based on the first sampled value and outputting the digital output signal; and determining whether a metastability condition exists based on the first sampled value and the second sampled value, and outputting an indication of whether the metastability condition exists.

18. The method of claim 17, further comprising performing the following operations via the circuit system: generating a digital feedback signal based on the first sampled value; and converting the digital feedback signal into the analog feedback signal.

19. The method of claim 17, further comprising performing the following operations via the circuit system: incrementing a counter based on the occurrence of the metastable state; and adjusting one or more trim values ​​associated with the circuit system in response to the counter exceeding a threshold.

20. The method of claim 17, further comprising, via the circuitry, incrementing a counter based on the occurrence of the metastable condition; and, in response to the counter exceeding a threshold, providing an interrupt to one or more processing cores with an indication of the metastable condition.

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