Receiver, phase detection device and method for detecting phase

Abstract

The invention discloses a receiver, a phase detection apparatus and a phase detection method. The receiver includes: an analog front end configured to receive a data input / output signal, and amplify the data input / output signal, and generate a processed signal; a time interleaved analog-to-digital converter (TI ADC) configured to sample the processing signal and generate a plurality of digital data signals; a Mueller-Muller phase detector configured to receive the digital data signals, and to drive at least one of the plurality of calculators based on a transition between two digital data signals; a monitoring circuit configured to receive the digital data signal, receive the multi-level signal transmitted from the transmitter, and generate a monitoring output signal based on the digital data signal and the multi-level signal; and a control logic circuit configured to receive the output monitoring output signal and generate a plurality of calculator selection signals for driving the calculator based on the monitoring output signal.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0150932, filed on October 30, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a receiver, a phase detection device, and a method for detecting phase. Background Technology

[0003] Although electronic devices operate internally through digital signal processing, their interfaces with external devices primarily rely on analog signal transmission. As the performance of electronic devices improves, communication frequencies are becoming increasingly higher, and with these higher frequencies, jitter in the signals received from external devices becomes more pronounced. When the receiver digitally samples the analog signal, jitter can cause timing mismatches. Timing instability can lead to bit errors and sampling distortion during signal transitions. Therefore, the integrity of the analog signal received by the receiver from the external device can be compromised. Summary of the Invention

[0004] In general, this disclosure relates to a phase detection device and a phase detection method that can be driven by low electrical power.

[0005] According to some embodiments, this disclosure relates to a phase detection apparatus and a phase detection method capable of accurately detecting the phase difference between a data signal and a clock signal.

[0006] According to some embodiments, this disclosure relates to a receiver comprising: an analog front end configured to receive data input / output signals and amplify the data input / output signals to generate a processing signal; a time-interleaved analog-to-digital converter (TI ADC) configured to sample the processing signal based on a plurality of clock signals and generate a plurality of digital data signals; a Mueller-Muller phase detector configured to receive digital data signals from the TI ADC and drive at least one of a plurality of calculators based on a transition between two sequentially received digital data signals; a monitoring circuit configured to receive digital data signals from the TI ADC, receive a multi-level signal transmitted from a transmitter, and generate a monitoring output signal based on the digital data signals and the multi-level signal; and control logic configured to receive the monitoring output signal output from the monitoring circuit and generate a plurality of calculator selection signals for driving the calculators based on the monitoring output signal.

[0007] According to some embodiments, this disclosure relates to a phase detection device, the phase detection device comprising: a plurality of calculators configured to output a plurality of sampling control signals, the plurality of sampling control signals corresponding to the transition of two adjacent digital data signals and controlling a sampling timing sequence for sampling the signals; a monitoring circuit configured to acquire the digital data signals, receive from a transmitter a multi-level signal having one of N signal levels (N being a positive number) of signal levels, and generate a monitoring output signal using the digital data signals and the multi-level signals; control logic configured to compare the monitoring output signal with a first reference value and generate a plurality of calculator selection signals driving the calculators; and a plurality of switches configured to transmit a driving voltage from a voltage source to the calculators based on the calculator selection signals.

[0008] According to some embodiments, this disclosure relates to a phase detection method, the phase detection method comprising: calculating a bit error rate based on a multi-level signal having one of N (N is a positive number) signal levels received from a transmitter and a digital data signal obtained from a time-interleaved analog-to-digital converter; comparing the calculated bit error rate with a first reference value, and generating a plurality of calculator selection signals for turning on or off a plurality of switches respectively connected between a plurality of calculators and a voltage source based on the comparison result; and supplying the calculator selection signals to the switches and a multiplexer, the multiplexer receiving a sampling control signal output from the calculator. Attached Figure Description

[0009] The exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 A block diagram of an example memory system according to some implementations is shown.

[0011] Figure 2 A block diagram illustrating an example of a memory device according to some embodiments is shown.

[0012] Figure 3 and Figure 4 A block diagram is shown illustrating examples of transmitters and receivers included in each of a memory controller and a memory device according to some embodiments.

[0013] Figure 5 A block diagram illustrating an example of a data transmission / reception system according to some implementations is shown.

[0014] Figure 6 A graph illustrating an example of a processed signal according to some implementations is shown.

[0015] Figure 7A circuit diagram of an example of a time-interleaved analog-to-digital converter (or time-interleaved analog-to-digital converter) according to some implementations is shown.

[0016] Figure 8 A graph is shown illustrating an example of processing that converts a processed signal into digital data via an analog-to-digital converter, according to some embodiments.

[0017] Figure 9 A block diagram is shown illustrating a portion of the configuration of a Mueller-Muller phase detector according to some implementations.

[0018] Figure 10 A flowchart illustrating an example of processing of an arithmetic unit and a multiplexer driven by an operator selection signal, according to some implementations, is shown.

[0019] Figure 11 A table is shown illustrating examples of the gain and current consumption generated in a Mueller-Muller phase detector based on digital data transformations according to some implementations.

[0020] Figure 12 An example block diagram illustrating a computer device according to some implementations is shown. Detailed Implementation

[0021] The present disclosure will be described more fully below with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. As those skilled in the art will recognize, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure.

[0022] Therefore, the accompanying drawings and descriptions are to be considered illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals denote the same elements. In the flowcharts described with reference to the drawings, the order of operations may be changed, some operations may be combined, some operations may be split, and certain operations may be omitted.

[0023] Furthermore, unless explicitly stated as “a” or “single,” a statement written in the singular may be interpreted as either singular or plural. Terms including ordinal numbers such as first, second, etc., will only be used to describe various components and will not be construed as limiting those components. These terms may be used for the purpose of distinguishing one constituent element from other constituent elements.

[0024] The present disclosure will be described in more detail below with examples. These examples are for illustrative purposes only, and the scope of protection of the present disclosure is not limited by these examples.

[0025] Figure 1 A block diagram illustrating an example of a memory system according to some implementations is shown. Figure 1 In this system, memory system 100 may include memory device 110 and memory controller 120. In some embodiments, memory device 110 and memory controller 120 may be connected via a memory interface to send and receive signals through the memory interface.

[0026] Memory device 110 includes a memory cell array 111 and data input / output (I / O) circuitry 112. The memory cell array 111 includes a plurality of memory cells connected to multiple rows and multiple columns. In some embodiments, rows may be defined by word lines, and columns may be defined by bit lines. The data I / O circuitry 112 may store data transferred from an external source in the memory cell array 111, or may output data stored in the memory cell array 111 to an external location (i.e., a memory controller 120, etc.) of the memory device 110.

[0027] Data I / O circuitry 112 may include a transmitter 113 and a receiver 114. Transmitter 113 may receive data DATA from memory cell array 111, encode the data DATA, and output a data input / output signal DQ based on the encoded signal. In some embodiments, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicating between memory controller 120 and memory device 110. Examples of multi-symbol modulation schemes include, but are not limited to, pulse amplitude modulation (PAM), quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), etc. A multi-symbol signal may be a signal modulated by encoding more than one bit of information using a modulation scheme comprising at least three levels. Multi-symbol modulation schemes and symbols may optionally be referred to as non-binary, multi-bit, or higher-order modulation schemes and symbols. For example, transmitter 113 may generate and output a data input / output signal (DQ) capable of expressing 2a (=n) data values, comprising symbols comprising multiple bits, according to n-level pulse amplitude modulation (PAM-n). Transmitter 113 can generate and output a data input / output signal (DQ) consisting of 2 bits representing four data values ​​(00, 01, 10, and 11) according to PAM-4. In the following text, it is assumed that data I / O circuit 112 uses the PAM-4 scheme.

[0028] Receiver 114 can receive data input / output signals (DQ) supplied from memory controller 120 and can decode the received DQ to generate PAM-4 data. PAM-4 data may include digital data that can represent four data values ​​(00, 01, 10, and 11). The operation of receiver 114 will be described in detail below.

[0029] Memory controller 120 controls memory operations of memory device 110 by providing signals to memory device 110. These signals may include command CMD and address ADDR. In some embodiments, memory controller 120 may provide command CMD and address ADDR to memory device 110 to access memory cell array 111 and control memory operations (such as read or write). According to a read operation, data input / output signals (DQ) may be transmitted from memory cell array 111 to memory controller 120, and according to a write operation, data input / output signals (DQ) may be transmitted from memory controller 120 to memory cell array 111.

[0030] Memory device 110 and memory controller 120 can send and receive data input / output (DQ) signals to each other via a serial interface. Memory controller 120 can access memory device 110 upon request from a host outside memory system 100. Memory controller 120 can communicate with the host using various protocols. For example, memory controller 120 can communicate with the external host via a parallel interface. In some embodiments, memory controller 120 can communicate with the host via a serial interface.

[0031] The CMD command may include activation commands, read / write commands, and refresh commands. An activation command may be a command used to switch a target row of memory cell array 111 to an active state in order to write data to or read data from memory cell array 111. The memory cells of the target row may be activated (e.g., driven) in response to the activation command. A read / write command may be a command used to perform a read or write operation on the target memory cell of the row that has been switched to the active state. A refresh command may be a command used to perform a refresh operation in memory cell array 111.

[0032] When the command CMD is a read command, the transmitter 113 can receive data DATA from the memory cell array 111. The transmitter 113 can encode the data DATA based on PAM-4 and can output the encoded signal as a data input / output signal (DQ).

[0033] The data I / O circuit 121 of the memory controller 120 can output data as a data input / output signal (DQ) to the memory device 110, or can receive data input / output signals (DQ) output from the memory device 110. The data I / O circuit 121 may include a transmitter 122 and a receiver 123. The transmitter 122 can send data provided from an external host to the memory device 110. The transmitter 122 and receiver 123 of the memory controller 120 may be substantially the same as the transmitter 113 and receiver 114 of the memory device 110, therefore, reference is made to the above description of the transmitter 113 and receiver 114 of the memory device 110.

[0034] Memory device 110 may be a semiconductor-based memory device. In some embodiments, memory device 110 may include a dynamic random access memory (DRAM) device. In some embodiments, memory device 110 may include another volatile or non-volatile memory device in which a transmitter 113 or a receiver 114 is used.

[0035] Figure 2 A block diagram illustrating an example of a memory device according to some embodiments is shown. Figure 2 In the memory device 200, there may be a memory cell array 210, a sense amplifier 211, a control logic circuit 220, an address buffer 230, a row decoder 250, a column decoder 260, an I / O gating circuit 270, and a data I / O circuit 295.

[0036] The memory cell array 210 may include a plurality of memory cells MC. In some embodiments, the memory cell array 210 may include a plurality of memory banks 210a to 210h. Although eight memory banks BANK0 to BANKh (210a to 210h) are shown in Figure 2 However, the number of memory banks is not limited to this. Each of the memory banks 210a to 210h may include multiple rows, multiple columns, and multiple memory cells MC arranged at the intersections of the rows and columns. In some embodiments, rows may be defined by multiple word lines WL, and columns may be defined by multiple bit lines BL.

[0037] Control logic circuitry 220 can control the operation of memory device 200. For example, control logic circuitry 220 can generate control signals causing memory device 200 to perform read operations, write operations, offset calibration operations, etc. In some embodiments, control logic circuitry 220 may include command decoder 221. Command decoder 221 can control the operation of memory device 200 by controlling the operation of a slave memory controller (e.g., ...). Figure 1 The command CMD received by (120) is decoded to generate control signals.

[0038] Address buffer 230 receives address ADDR provided from memory controller 120. Address ADDR includes a row address RA indicating a row of memory cell array 210 and a column address CA indicating a column of memory cell array 210. Row address RA is provided to row decoder 250, and column address CA is provided to column decoder 260. In some embodiments, memory device 200 may further include row address multiplexer 251. Row address RA may be provided to row decoder 250 via row address multiplexer 251. In some embodiments, address ADDR may further include bank address BA indicating a bank of memory. Bank address BA may be provided to bank control logic 240.

[0039] In some embodiments, the memory device 200 may further include memory control logic 240 that generates a memory control signal in response to a memory address BA. The memory control logic 240 may activate, in response to the memory control signal, the row decoder 250 corresponding to the memory address BA among a plurality of row decoders 250, and may activate the column decoder 260 corresponding to the memory address BA among a plurality of column decoders 260.

[0040] The row decoder 250 selects the row to be activated from among a plurality of rows of the memory cell array 210 based on the row address. To do this, the row decoder 250 may apply a drive voltage to the word line corresponding to the row to be activated. In some embodiments, row decoders 250a to 250h corresponding to the respective memory banks 210a to 210h may be provided.

[0041] The column decoder 260 selects the column to be activated from among a plurality of columns of the memory cell array 210 based on the column address. For this purpose, the column decoder 260 can activate the sense amplifier 211 corresponding to the column address CA via the I / O gating circuit 270. In some embodiments, column decoders 260a to 260h corresponding to the respective memory banks 210a to 210h may be provided. In some embodiments, the I / O gating circuit 270 may gate input / output data and may include a data latch for storing data read from the memory cell array 210 and a write driver for writing data to the memory cell array 210. The data read from the memory cell array 210 may be sensed by the sense amplifier 211 and may be stored in the I / O gating circuit 270 (e.g., the data latch). In some embodiments, a plurality of sense amplifiers 211a to 211h corresponding to the respective memory banks 210a to 210h may be provided.

[0042] In some implementations, data read from memory cell array 210 (e.g., data stored in a data latch) can be provided to memory controller 120 via data I / O circuitry 295. Data to be written to memory cell array 210 can be provided from memory controller 120 to data I / O circuitry 295, and data provided to data I / O circuitry 295 can be provided to I / O gate circuitry 270.

[0043] Data I / O circuit 295 can output or receive data input / output signals (DQ). Data I / O circuit 295 may include a TX circuit (hereinafter referred to as a "transmitter") 2951 and an RX circuit (hereinafter referred to as a "receiver") 2952. Transmitter 2951 can encode data DATA transmitted from I / O gate circuit 270 based on PAM-4 to output data DATA as a data input / output signal (DQ). Receiver 2952 can decode the received data input / output signal (DQ), restoring the data input / output signal (DQ) to a PAM-4 signal, and can transmit data DATA based on the restored signal to I / O gate circuit 270.

[0044] Figure 3 and Figure 4 A block diagram illustrating examples of transmitters and receivers included in each of a memory controller and a memory device according to some embodiments is shown. Figure 3 and Figure 4 In the memory system 100 (in Figure 1 The (middle) may include a semiconductor memory device 310, a memory controller 320, and multiple channels 315a, 315b, and 315c.

[0045] Semiconductor memory device 310 may include multiple transmitters 311a, 311b, and 311c, multiple receivers 312a, 312b, and 312c, and multiple data input / output pads 313a, 313b, and 313c. Memory controller 320 may include multiple transmitters 321a, 321b, and 321c, multiple receivers 322a, 322b, and 322c, and multiple data input / output pads 323a, 323b, and 323c.

[0046] Each of transmitters 311a, 311b, 311c, 321a, 321b, and 321c can generate a data input / output signal (DQ) as a multi-level data signal. Each of receivers 312a, 312b, 312c, 322a, 322b, and 322c can receive the data input / output signal (DQ). Transmitters 311a, 311b, 311c, 321a, 321b, and 321c and receivers 312a, 312b, 312c, 322a, 322b, and 322c can transmit the data input / output signal (DQ) through multiple channels 315a, 315b, and 315c.

[0047] Each of the data input / output pads 313a, 313b, 313c, 323a, 323b, and 323c can be connected to one of the transmitters 311a, 311b, 311c, 321a, 321b, and 321c, and one of the receivers 312a, 312b, 312c, 322a, 322b, and 322c.

[0048] Channels 315a, 315b, and 315c can connect the memory controller 320 and the semiconductor memory device 310. Each of channels 315a, 315b, and 315c can be connected to one of the transmitters 321a, 321b, and 321c and one of the receivers 322a, 322b, and 322c via one of the data input / output pads 323a, 323b, and 323c. Each of channels 315a, 315b, and 315c can be connected to one of the transmitters 311a, 311b, and 311c and one of the receivers 312a, 312b, and 312c via one of the data input / output pads 313a, 313b, and 313c. Data input / output signals (DQ) can be transmitted through each of channels 315a, 315b, and 315c.

[0049] Figure 3 The operation of transmitting data from memory controller 320 to semiconductor memory device 310 is illustrated. For example, transmitter 321a can generate a data input / output signal DQ1 as a multi-level data signal based on input data DATA1. The data input / output signal DQ1 can be transmitted from memory controller 320 to semiconductor memory device 310 via channel 315a. Receiver 312a can receive data input / output signal DQ1 to obtain target data DX1 corresponding to input data DATA1.

[0050] Similarly, transmitter 321b can generate a data input / output signal DQ2 as a multi-level data signal based on input data DATA2. Data input / output signal DQ2 can be transmitted to semiconductor memory device 310 via channel 315b. Receiver 312b can receive data input / output signal DQ2 to obtain target data DX2 corresponding to input data DATA2.

[0051] Similarly, transmitter 321c can generate a data input / output signal DQ3 as a multi-level data signal based on the input data DATAN. ​​The data input / output signal DQ3 can be sent to the semiconductor memory device 310 through channel 315c. Receiver 312c can receive the data input / output signal DQ3 to obtain the target data DXN corresponding to the input data DATAN.

[0052] Figure 4 The operation of transmitting data from a semiconductor memory device 410 to a memory controller 420 is illustrated. The semiconductor memory device 410 may include multiple transmitters 411a, 411b, and 411c, multiple receivers 412a, 412b, and 412c, and multiple data input / output pads 413a, 413b, and 413c. The memory controller 420 may include multiple transmitters 421a, 421b, and 421c, multiple receivers 422a, 422b, and 422c, and multiple data input / output pads 423a, 423b, and 423c. Similarly, transmitter 411a may generate a data input / output signal DQ1 as a multi-level data signal based on input data DATA1. The data input / output signal DQ1 may be transmitted from the semiconductor memory device 410 to the memory controller 420 via channel 415a. Receiver 422a may receive the data input / output signal DQ1 to obtain target data DX1 corresponding to the input data DATA1.

[0053] Similarly, transmitter 411b can generate a data input / output signal DQ2 as a multi-level data signal based on input data DATA2. Data input / output signal DQ2 can be sent to memory controller 420 via channel 415b. Receiver 422b can receive data input / output signal DQ2 to obtain target data DX2 corresponding to input data DATA2. Similarly, transmitter 411c can generate a data input / output signal DQ3 as a multi-level data signal based on input data DATAN. ​​Data input / output signal DQ3 can be sent to memory controller 420 via channel 415c. Receiver 422c can receive data input / output signal DQ3 to obtain target data DXN corresponding to input data DATAN. ​​In this case, input data DATA1, DATA2, and DATAN can be read data read from semiconductor memory device 410.

[0054] In the following text, for better understanding and ease of description, the operation of the transmitters 321a, 321b and 321c of the memory controller 320 and the receivers 312a, 312b and 312c of the semiconductor memory device 310 when transmitting data from the memory controller 320 to the semiconductor memory device 310 will be described.

[0055] Figure 5 A block diagram illustrating an example of a data transmission / reception system according to some implementations is shown. Figure 5 In this system, a data transmission / reception system may include a data transmitter TX and a data receiver RX. The data transmitter TX generates a multi-level signal MS from user data UD in digital signal form. Furthermore, the data transmitter TX converts the multi-level signal MS into an analog signal to be transmitted to the data receiver RX. For better understanding and ease of description, it will be assumed that the data transmitter TX is a memory controller 320 (in... Figure 3 Transmitters 321a, 321b and 321c (in) Figure 3 (in the middle), and the data receiver RX is a semiconductor memory device 310 (in Figure 3 Receivers 312a, 312b and 312c (in) Figure 3 middle).

[0056] The transmitter TX may include a multilevel signal generator 501, a digital-to-analog converter (DAC) 502, and a driver 503. The multilevel signal generator 501 receives user data UD from an external host. The multilevel signal generator 501 generates a multilevel signal MS from the user data UD. The multilevel signal MS may have any of N (N is a positive integer) signal levels. For example, the multilevel signal generator 501 may encode the user data UD based on PAM-4 to output one of four multilevel signals MS. The multilevel signal generator 501 may send the multilevel signal MS to the DAC 502.

[0057] The digital-to-analog converter 502 converts the multi-level signal MS into an analog signal. The driver 503 receives the analog signal from the multi-level signal MS after conversion by the digital-to-analog converter 502. The driver 503 performs the necessary tasks to transmit the analog signal of the multi-level signal MS to the receiver RX. The driver 503 generates a data input / output signal DQ from the analog signal of the multi-level signal MS. The driver 503 transmits the data input / output signal DQ to the receiver RX as a serial signal.

[0058] The receiver RX may include an analog front-end (AFE) circuit 510, a time-interleaved (TI) analog-to-digital converter (ADC) 520, a Mueller-Muller phase detector (MMPD) 530, a loop filter 540, a clock generator 550, a switch control signal generator (SSC) 560, a monitoring circuit 570, and control logic (or control logic circuitry) 580.

[0059] The analog front-end circuit 510 can be a circuit located at the input terminal of the receiver RX for processing analog signals and converting them into digital signals. The analog front-end circuit 510 can amplify fine analog signals to enhance them to a level suitable for digitization. Furthermore, the analog front-end circuit 510 can remove noise or unwanted frequency components included in the analog signal through filtering. In this case, the analog front-end circuit 510 can use a low-pass filter or a band-pass filter to retain only the desired frequency band and can re-fine the analog signal for digital signal processing before transmission.

[0060] For example, analog front-end circuitry 510 can receive a data input / output signal DQ from transmitter TX. Analog front-end circuitry 510 can amplify the data input / output signal DQ to a level suitable for digitization. Analog front-end circuitry 510 can remove noise or unwanted frequency components included in the data input / output signal DQ by using a low-pass filter. Analog front-end circuitry 510 can amplify the data input / output signal DQ and remove noise to generate a processed signal DQE. Analog front-end circuitry 510 can send the processed signal DQE to time-interleaved analog-to-digital converter 520.

[0061] Figure 6 A graph illustrating an example of the processing signal DQE according to some implementations is shown. Figure 6 In this process, the voltage V of the processing signal DQE can vary with time t from t1 to t32. For example, from 0 to t1, the voltage V of the processing signal DQE can increase from 0V to V1V. From t1 to t2, the voltage V of the processing signal DQE can increase from V1V to V4V. From t2 to t3, the voltage V of the processing signal DQE can decrease from V4V to V2V. From t3 to t4, the voltage V of the processing signal DQE can increase from V2V to V3V.

[0062] exist Figure 5In this embodiment, the time-interleaved analog-to-digital converter 520 may include multiple analog-to-digital converters (hereinafter referred to as "ADCs") arranged in parallel for digitizing high-speed analog signals. Each of the ADCs generates a digital signal by sampling the input analog signal at specific time intervals. With a single ADC, the input analog signal is sampled sequentially, but with multiple ADCs, the input analog signal can be sampled together at specific time intervals. Therefore, as the number of ADCs increases, the sampling rate of the input analog signal can be improved.

[0063] For example, the time-interleaved analog-to-digital converter 520 may include 32 ADCs. The time-interleaved analog-to-digital converter 520 may receive a processed signal DQE from the analog front-end circuit 510. The time-interleaved analog-to-digital converter 520 can generate a digital signal by sampling the processed signal DQE at 32 different time intervals.

[0064] The time-interleaved analog-to-digital converter 520 can receive multiple clock signals CK from the clock generator 550. The time-interleaved analog-to-digital converter 520 can sample the processed signal DQE based on the clock signals CK. The time-interleaved analog-to-digital converter 520 can convert the processed signal DQE into a digital data signal (or digital data) DO. The time-interleaved analog-to-digital converter 520 can send the digital data signal DO to the Mueller-Muller phase detector 530. The time-interleaved analog-to-digital converter 520 can send the digital data signal DO to the monitoring circuit 570.

[0065] Figure 7 A circuit diagram of an example time-interleaved analog-to-digital converter according to some implementations is shown.

[0066] Time-interleaved analog-to-digital converter 520 (in) Figure 5 The system may include 32 ADCs (ADC1, ADC2, ADC3, ..., and ADC32), and each of the ADCs (ADC1, ADC2, ADC3, ..., and ADC32) can sample the processed signal DQE at 32 different time intervals using switches SW1, SW2, SW3, ..., and SW32. In this case, switches SW1, SW2, SW3, ..., and SW32 can be connected between the input terminal 521 to which the DQE signal 600 is input and the ADCs (ADC1, ADC2, ADC3, ..., and ADC32). Each of switches SW1, SW2, SW3, ..., and SW32 can be controlled from a switch control signal generator 560 (in... Figure 5 (in the middle) receives switch control signals SC1, SC2, SC3, ... and SC32, and can be turned on (closed) or off (opened) based on switch control signals SC1, SC2, SC3, ... and SC32.

[0067] Switches SW1, SW2, SW3, ..., and SW32 can be switched on sequentially in two different time sequences. For example, during time period t0 to t1, only the first switch SW1 can be switched on, and during time period t1 to t2, only the second switch SW2 can be switched on. Similarly, during time period t2 to t3, only the third switch SW3 can be switched on, and during time period t31 to t32, only the thirty-second switch SW32 can be switched on.

[0068] During time period 0 to t1, the processing signal DQE can be sent to the first ADC ADC1 via the activated first switch SW1. The first ADC ADC1 samples the processing signal DQE at the rising edge of the first clock CK1 and converts the processing signal DQE into first digital data DO1. During time period t1 to t2, the processing signal DQE can be sent to the second ADC ADC2 via the activated second switch SW2. The second ADC ADC2 samples the processing signal DQE at the rising edge of the second clock CK2 and converts the processing signal DQE into second digital data DO2. During time period t2 to t3, the processing signal DQE can be sent to the third ADC ADC3 via the activated third switch SW3. The third ADC ADC3 samples the processing signal DQE at the rising edge of the third clock CK3 and converts the processing signal DQE into third digital data DO3. Similarly, during time period t31 to t32, the processing signal DQE can be sent to the thirty-second ADC ADC32 via the activated thirty-second switch SW32. The 32nd ADC, ADC32, can sample the processing signal DQE on the rising edge of the 32nd clock CK32 and convert the processing signal DQE into 32nd digital data DO32. In this case, the first clock CK1 to the 32nd clock CK32 can be obtained from the clock generator 550 by the time-interleaved analog-to-digital converter 520. Figure 5 (in the middle) received. The first digital data DO1 to the thirty-second digital data DO32 converted by the ADCs (ADC1, ADC2, ADC3, ... and ADC32) can be sent to the Mueller-Muller phase detector 530 (in Figure 5 (in the middle). The first digital data DO1 to the thirty-second digital data DO32 converted by the ADCs (ADC1, ADC2, ADC3, ... and ADC32) can be sent to the monitoring circuit 570 (in the middle). Figure 5 middle).

[0069] Figure 8 A graph is shown illustrating an example of processing that converts a processed signal into digital data via an analog-to-digital converter, according to some embodiments.

[0070] ADC ( Figure 7 The ADCs 1, ADC2, ADC3, ..., ADC32 in the above can convert the processed signal DQE (e.g., DQE signal 800) into a digital data signal DO based on a first reference voltage VREF1, a second reference voltage VREF2, and a third reference voltage VREF3. For example, if the voltage of the processed signal DQE is less than the first reference voltage VREF1, the processed signal DQE can be converted to 00 as a digital data signal DO (2). If the voltage of the processed signal DQE is greater than or equal to the first reference voltage VREF1 and less than the second reference voltage VREF2, the processed signal DQE can be converted to 01 as a digital data signal DO (2). If the voltage of the processed signal DQE is greater than or equal to the second reference voltage VREF2 and less than the third reference voltage VREF3, the processed signal DQE can be converted to 10 as a digital data signal DO (2). If the voltage of the processed signal DQE is greater than or equal to the third reference voltage VREF3, the processed signal DQE can be converted to 11 as a digital data signal DO (2).

[0071] For example, the voltage V1 of the processing signal DQE at t1 is less than the first reference voltage VREF1. Therefore, the processing signal DQE from 0 to t1 can be converted into 00 as the digital data signal DO (2). The voltage V4 of the processing signal DQE at t2 is greater than or equal to the second reference voltage VREF2 and less than the third reference voltage VREF3. Therefore, the processing signal DQE from t1 to t2 can be converted into 10 as the digital data signal DO (2). The voltage V2 of the processing signal DQE at t3 is greater than or equal to the first reference voltage VREF1 and less than the second reference voltage VREF2. Therefore, the processing signal DQE from t2 to t3 can be converted into 01 as the digital data signal DO (2). The voltage V3 of the processing signal DQE at t4 is greater than or equal to the second reference voltage VREF2 and less than the third reference voltage VREF3. Therefore, the processing signal DQE from t3 to t4 can be converted into 10 as the digital data signal DO (2). Therefore, the first ADC ADC1 can output 00(2) as the first digital data DO1, and the second ADC ADC2 can output 10(2) as the second digital data DO2. The third ADC ADC3 can output 01(2) as the third digital data DO3, and the fourth ADC ADC4 can output 10(2) as the fourth digital data DO4. In the same manner as above, the remaining ADCs ADC5 to ADC32 can also output digital data DO5 to DO32.

[0072] exist Figure 5In this circuit, the Mueller-Muller phase detector 530 detects sampling timing errors in the digital data signal DO. The Mueller-Muller phase detector 530 receives continuous digital data signals DO from the time-interleaved analog-to-digital converter 520. The Mueller-Muller phase detector 530 detects sampling timing errors by calculating the differences between successive digital data signals DO. The Mueller-Muller phase detector 530 sends a sampling control signal DX to the loop filter 540; the sampling control signal DX is a control signal used to correct errors in the sampling timing.

[0073] In some implementations, the Mueller-Muller phase detector 530 can receive a digital data signal DO and determine whether the digital data signal DO is phase-delayed or phase-advanced. The Mueller-Muller phase detector 530 can determine whether the digital data signal DO is phase-delayed or phase-advanced based on two digital data signals DO. For example, the Mueller-Muller phase detector 530 can determine whether the digital data signal DO is phase-delayed or phase-advanced based on digital data signals DO that transition at adjacent timing points. The Mueller-Muller phase detector 530 can also detect sampling timing errors based on whether the digital data signal DO is phase-delayed or phase-advanced.

[0074] A loop filter 540 (e.g., a digital loop filter) integrates the sampling control signal DX, which is the output of the Mueller-Muller phase detector 530. The loop filter 540 generates a phase adjustment signal DY by integrating the sampling control signal DX. The loop filter 540 then sends the phase adjustment signal DY to a clock generator 550.

[0075] Clock generator 550 outputs a clock signal CK whose frequency and phase are adjusted based on a phase adjustment signal DY, which is the output of a loop filter. Clock generator 550 can send the clock signal CK to time-interleaved analog-to-digital converter 520 and switch control signal generator 560.

[0076] The switch control signal generator 560 can generate a switch control signal SC based on the clock signal CK. The switch control signal generator 560 can send the switch control signal SC to the time-interleaved analog-to-digital converter 520.

[0077] Monitoring circuit 570 receives digital data signal DO from time-interleaved analog-to-digital converter 520. Monitoring circuit 570 receives multi-level signal MS from multi-level signal generator 501. Monitoring circuit 570 generates monitoring output signal MV based on the difference between digital data signal DO and multi-level signal MS. Monitoring circuit 570 sends monitoring output signal MV to control logic 580.

[0078] Monitoring circuit 570 calculates the bit error rate (BER) based on the digital data signal DO and the multi-level signal MS. Monitoring circuit 570 calculates the BER based on the total number of transmission bits of the multi-level signal MS transmitted from transmitter TX and the number of error bits between the multi-level signal MS and the digital data signal DO. Monitoring circuit 570 sends the calculated BER as a monitoring output signal MV to control logic 580.

[0079] The monitoring circuit 570 can calculate the signal-to-noise ratio (SNR) based on the digital data signal DO and the multi-level signal MS. The monitoring circuit 570 can calculate the SNR based on the signal power of the multi-level signal MS, the signal power of the digital data signal DO, and the noise power.

[0080] The monitoring circuit 570 can use the signal power of the digital data signal DO or the signal power of the multi-level signal MS when calculating the signal-to-noise ratio (SNR). Since the multi-level signal MS and the digital data signal DO, as PAM-4 signals, can have four types of voltage levels, the signal power can be calculated by averaging the squares of each voltage level.

[0081] Noise power may include power losses due to power line interference occurring along the transmission path. Noise power may also include power losses due to thermal noise and white noise occurring in the transmission path.

[0082] The monitoring circuit 570 can send the calculated signal-to-noise ratio (SNR) as a monitoring output signal MV to the control logic 580. For example, if the average power of the multi-level signal MS is 100W and the power loss is 1W, then the SNR can be 100. The monitoring circuit 570 can send an SNR of 100 as a monitoring output signal MV to the control logic 580. If the average power of the digital data signal DO is 500W and the power loss is 1W, then the SNR can be 50. The monitoring circuit 570 can send a calculated SNR of 50 as a monitoring output signal MV to the control logic 580.

[0083] Control logic 580 can receive a monitoring output signal MV from monitoring circuit 570. Control logic 580 can generate an arithmetic unit selection signal (or calculator selection signal) CAL_EN based on the monitoring output signal MV. Control logic 580 can send the arithmetic unit selection signal CAL_EN to Mueller-Muller phase detector 530.

[0084] Figure 9 A block diagram is shown illustrating a portion of the configuration of a Mueller-Muller phase detector according to some implementations.

[0085] The Mueller-Muller phase detector 530 may include a phase decision decoder (or phase decision decoder circuit) 910, multiple arithmetic units (or calculators) 911a, 912a, ... and 913a, and multiple multiplexers 911b, 912b, ... and 913b.

[0086] Phase decision decoder 910 can be obtained from time interleaved analog-to-digital converter 520 (in Figure 5 The digital data signal DO is received from the input digital data signal DO. The phase decision decoder 910 can generate transition information of the digital data signal DO based on the continuously input digital data signals DO (e.g., digital data signals DO(N-1) and DO(N)), and can determine whether the phase of the digital data signal DO is leading or lagging.

[0087] The phase decision decoder 910 can select one of a plurality of calculators 911a, 912a, ..., and 913a based on the transition information of the digital data signal DO. The phase decision decoder 910 can output phase decision signals DC1, DC2, ..., and DC16 to the selected calculator 911a, 912a, ..., and 913a. The phase decision signals DC1, DC2, ..., and DC16 can include the value of each of the continuously input digital data signals DO(N-1) and DO(N) and phase information.

[0088] For example, if the digital data signal DO(N-1) is 11(2) and the digital data signal DO(N) is 11(2) and the same as the digital data signal DO(N-1), then the phase decision decoder 910 may select the first calculator 911a. If the digital data signal (DO(N-1)) is 10(2) and the digital data signal (DO(N)) is 11(2), then the phase decision decoder 910 may select the second calculator 912a. If the digital data signal (DO(N-1)) is 00(2) and the digital data signal (DO(N)) is 00(2), then the phase decision decoder 910 may select the sixteenth calculator 913a. However, this disclosure is not limited to this example.

[0089] The phase decision decoder 910 can select one of the calculators 911a, 912a, ..., 913a by considering the transition information and phase information of the digital data signal DO. For example, if the digital data signal DO is phase-advanced relative to the clock signal CK and the digital data signal DO transitions from 11(2) to 11(2), then the phase decision decoder 910 can output the phase decision signal DC1 to the first calculator 911a (in... Figure 9 If the digital data signal DO is phase-advanced relative to the clock signal CK and the digital data signal D0 changes from 10(2) to 11(2), then the phase decision decoder 910 can output the phase decision signal DC2 to the second calculator 912a (in Figure 9 If the digital data signal DO is phase-advanced relative to the clock signal CK and the digital data signal DO changes from 00(2) to 00(2), then the phase decision decoder 910 can output the phase decision signal DC16 to the sixteenth calculator 913a (in Figure 9 If the digital data signal DO is phase-delayed relative to the clock signal CK and transitions from 00(2) to 00(2), the phase decision decoder 910 can output the phase decision signal DC1 to the first calculator 911a. If the digital data signal DO is phase-delayed relative to the clock signal CK and transitions from 10(2) to 11(2), the phase decision decoder 910 can output the phase decision signal DC2 to the second calculator 912a. If the digital data signal DO is phase-delayed relative to the clock signal CK and transitions from 11(2) to 11(2), the phase decision decoder 910 can output the phase decision signal DC16 to the sixteenth calculator 913a. The method by which the phase decision decoder 910 outputs the phase decision signals DC1 to DC16 to calculators 911a, 912a, ... and 913a based on phase information and transition information is not limited to this.

[0090] Each of calculators 911a, 912a, ..., and 913a can perform an operation corresponding to a different transition among multiple transitions that can occur between digital data signal DO(N) and digital data signal DO(N-1). Calculators 911a, 912a, ..., and 913a can receive phase decision signals DC1, DC2, ..., and DC16, and can generate sampling control signals DX1, DX2, ..., and DX16 based on the phase decision signals DC1, DC2, ..., and DC16 to control the timing of multiple clock signals. Therefore, interference between calculators 911a, 912a, ..., and 913a can be minimized, and computational processing speed can be improved.

[0091] Each of calculators 911a, 912a, ..., and 913a can receive a drive voltage from a separate voltage source VDD. Switches SX1, SX2, ..., and SX16 can be connected between calculators 911a, 912a, ..., and 913a and the voltage source VDD. Each of calculators 911a, 912a, ..., and 913a can receive a drive voltage from the voltage source VDD while switches SX1, SX2, ..., and SX16 are closed.

[0092] Each of the switches SX1, SX2, ..., and SX16 receives a calculator selection signal CAL_EN from control logic 580. Switches SX1, SX2, ..., and SX16 can be turned on or off based on the calculator selection signal CAL_EN. For example, the first switch SX1 can be turned on or off based on the first calculator selection signal CAL_EN1. The second switch SX2 can be turned on or off based on the second calculator selection signal CAL_EN2. The sixteenth switch SX16 can be turned on or off based on the sixteenth calculator selection signal CAL_EN16. As the number of calculators 911a, 912a, ..., and 913a that are driven by the applied drive voltage decreases, the Mueller-Muller phase detector 530 (in...) Figure 5 The power consumption generated in the middle can be reduced.

[0093] The calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16 can be generated by control logic 580. Control logic 580 generates calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16, which control switches SX1, SX2, ..., and SX16 connected to calculators 911a, 912a, ..., and 913a, determined based on the transition information of the digital data signal DO.

[0094] Control logic 580 can generate calculator selection signals CAL_EN1, CAL_EN2, ..., CAL_EN16 based on the monitored output signal MV, which will turn switches SX1, SX2, ..., and SX16 on or off. Control logic 580 can send calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16 to switches SX1, SX2, ..., and SX16. Switches SX1, SX2, ..., and SX16 can be turned on or off based on calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16. Control logic 580 can control whether switches SX1, SX2, ..., and SX16 can be enabled based on the monitored output signal MV. For example, control logic 580 can enable the required number of switches to meet a reference value and disable the remaining switches based on the monitored output signal MV. For example, control logic 580 can enable six of the 16 switches SX1, SX2, ..., and SX16 and disable ten of these switches. Control logic 580 can generate calculator selection signals CAL_EN1, CAL_EN2, ..., CAL_EN16 based on monitoring output signals MV that do not meet reference values ​​to enable seven switches and disable nine switches. In some embodiments, control logic 580 can generate calculator selection signals CAL_EN1, CAL_EN2, ..., CAL_EN16 based on monitoring output signals MV that meet reference values ​​to enable five switches and disable eleven switches.

[0095] When the bit error rate (BER) between the digital data signal DO and the multi-level signal MS is equal to or greater than the first reference value, the control logic 580 can generate calculator selection signals CAL_EN1, CAL_EN2, ... and CAL_EN16, which will turn on the switches SX1, SX2, ... and SX16 of the calculators 911a, 912a, ... and 913a determined based on the transition information of the digital data signal DO. When the bit error rate (BER) between the digital data signal DO and the multi-level signal MS is less than a first reference value, the control logic 580 generates calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16. These calculator selection signals disconnect switches SX1, SX2, ..., and SX16 connected to calculators 911a, 912a, ..., and 913a, determined based on the transition information of the digital data signal DO. In this case, the value corresponding to the first reference value can be stored in a separate storage device within the control logic.

[0096] For example, when the bit error rate (BER) between the digital data signal DO and the multilevel signal MS is 10-4 And the first reference value is 5 -4 When the control logic 580 generates calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16, these signals will disconnect switches SX1, SX2, ..., and SX1 connected to calculators 911a, 912a, ..., and 913a, determined based on the transition information of the digital data signal DO. When the bit error rate (BER) between the digital data signal DO and the multi-level signal MS is 3... -4 And the first reference value is 5 -4 At that time, control logic 580 can generate calculator selection signals CAL_EN1, CAL_EN2, ... and CAL_EN16, which will turn on the switches SX1, SX2, ... and SX16 of calculators 911a, 912a, ... and 913a determined based on the transition information of digital data signal DO.

[0097] When the signal-to-noise ratio (SNR) of the digital data signal DO or the multi-level signal MS is less than a first reference value, control logic 580 generates calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16. These calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16 will turn on the switches SX1, SX2, ..., and SX16 connected to calculators 911a, 912a, ..., and 913a, determined based on the transition information of the digital data signal DO. When the SNR of the digital data signal DO and the multi-level signal MS is greater than or equal to the first reference value, control logic 580 generates calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16. These calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16 will disconnect the switches SX1, SX2, ..., and SX16 connected to calculators 911a, 912a, ..., and 913a, determined based on the transition information of the digital data signal DO.

[0098] For example, when the signal-to-noise ratio (SNR) is 100 and the first reference value is 50, the control logic 580 can generate calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16, which disconnect the switches SX1, SX2, ..., and SX16 connected to calculators 911a, 912a, ..., and 913a determined based on the transition information of the digital data signal DO. When the SNR is 40 and the first reference value is 50, the control logic 580 can generate calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16, which turn on the switches SX1, SX2, ..., and SX16 connected to calculators 911a, 912a, ..., and 913a determined based on the transition information of the digital data signal DO.

[0099] The sampling control signals DX1, DX2, ..., DX16, which are the calculated values ​​output from the corresponding calculators 911a, 912a, ..., 913a, can be input to multiplexers 911b, 912b, ..., 913b (in... Figure 9 (In the middle). Control logic 580 can send the first calculator selection signal CAL_EN1, the second calculator selection signal CAL_EN2, and the sixteenth calculator selection signal CAL_EN16 to the first multiplexer 911b, the second multiplexer 912b, and the sixteenth multiplexer 913b, respectively. Multiplexers 911b, 912b, ..., 913b can receive the corresponding calculator selection signal CAL_EN from control logic 580, and can determine the processing of the sampling control signals DX1, DX2, ..., DX16 based on the corresponding calculator selection signal CAL_EN.

[0100] Multiplexers 911b, 912b, ..., and 913b can receive sampling control signals DX1, DX2, ..., and DX16 from calculators 911a, 912a, ..., and 913a, and can selectively output sampling control signals DX1, DX2, ..., and DX16. Multiplexers 911b, 912b, ..., and 913b can receive the sampling control signals DX1, DX2, ..., and DX16 received from calculators 911a, 912a, ..., and 913a based on the calculator selection signal CAL_EN, and send them as is to the loop filter 540 (in...). Figure 5 (In the middle). Multiplexers 911b, 912b, ... and 913b can select the calculator signal CAL_EN without sending the sampling control signals DX1, DX2, ... and DX16 to the loop filter 540.

[0101] When switches SX1, SX2, ..., and SX16 connected to one of calculators 911a, 912a, ..., 913a are turned on based on the calculator selection signal CAL_EN, one of the multiplexers 911b, 912b, ..., and 913b that receive the outputs of calculators 911a, 912a, ..., and 913a can transmit the sampling control signals DX1, DX2, ..., and DX16 received from calculators 911a, 912a, ..., and 913a to the loop filter 540 (in... Figure 5 middle).

[0102] When switches SX1, SX2, ..., and SX16 connected to one of calculators 911a, 912a, ..., and 913a are disconnected based on the calculator selection signal CAL_EN, one of the multiplexers 911b, 912b, ..., and 913b that receive the outputs of calculators 911a, 912a, ..., and 913a may not transmit the sampling control signals DX1, DX2, ..., and DX16 received from calculators 911a, 912a, ..., and 913a to the loop filter 540.

[0103] For example, control logic 580 can send a first calculator selection signal CAL_EN1, a second calculator selection signal CAL_EN2, and a sixteenth calculator selection signal CAL_EN16, used to activate the first calculator 911a, the second calculator 912a, and the sixteenth calculator 913a, to a first multiplexer 911b, a second multiplexer 912b, and a sixteenth multiplexer 913b. The first multiplexer 911b, the second multiplexer 912b, and the sixteenth multiplexer 913b can receive sampling control signals DX1, DX2, and DX16 from the first calculator 911a, the second calculator 912a, and the sixteenth calculator 913a, respectively. The first multiplexer 911b, the second multiplexer 912b, and the sixteenth multiplexer 913b can each transmit the sampling control signals DX1, DX2, and DX16 to a loop filter 540. The remaining multiplexers, except for the first multiplexer 911b, the second multiplexer 912b, and the sixteenth multiplexer 913b, may not transmit the received sampling control signal DX to the loop filter 540.

[0104] The phase decision decoder 910 can output phase decision signals DC1, DC2, ..., and DC16 to selected calculators 911a, 912a, ..., and 913a. The phase decision decoder 910 can generate transition information for two digital data DO(N) and DO(N-1), and can determine the phase information for the sampling timing of the two digital data DO(N) and DO(N-1). The phase decision decoder 910 can generate phase decision signals DC1, DC2, ..., and DC16 including phase information (in... Figure 9 middle).

[0105] The phase decision decoder 910 can output phase decision signals DC1, DC2, ..., DC16 to calculators 911a, 912a, ..., and 913a based on the transition information and phase information between digital data signal DO(N) and digital data signal DO(N-1).

[0106] For example, if the digital data signal DO is phase-advanced relative to the clock signal CK and the digital data signal DO changes from 11(2) to 11(2), then the phase decision decoder 910 can output the phase decision signal DC1 to the first calculator 911a. If the digital data signal DO is phase-advanced relative to the clock signal CK and the digital data signal DO changes from 10(2) to 11(2), then the phase decision decoder 910 can output the phase decision signal DC2 to the second calculator 912a. If the digital data signal DO is phase-advanced relative to the clock signal CK and the digital data signal DO changes from 00(2) to 00(2), then the phase decision decoder 910 can output the phase decision signal DC16 to the sixteenth calculator 913a. If the digital data signal DO is phase-delayed relative to the clock signal CK and changes from 00(2) to 00(2), then the phase decision decoder 910 can output the phase decision signal DC1 to the first calculator 911a. If the digital data signal DO is phase-delayed relative to the clock signal CK and transitions from 10(2) to 11(2), the phase decision decoder 910 can output the phase decision signal DC2 to the second calculator 912a. If the digital data signal DO is phase-delayed relative to the clock signal CK and transitions from 11(2) to 11(2), the phase decision decoder 910 can output the phase decision signal DC16 to the sixteenth calculator 913a. However, the method by which the phase decision decoder 910 outputs the phase decision signals DC1 to DC16 to calculators 911a, 912a, ... and 913a based on phase information and transition information is not limited to this.

[0107] Figure 10 A flowchart illustrating an example of processing involving an arithmetic unit and a multiplexer driven by an arithmetic unit selection signal according to some embodiments is shown. In step S1010, the receiver RX (in Figure 5 (in) can be based on the transmitter TX (in) Figure 5 The multi-level signal MS received by (in) Figure 5 (in) and from the time-interleaved analog-to-digital converter 520 (in) Figure 5 The digital data signal DO obtained from (in) Figure 5The receiver RX calculates the bit error rate (BER) based on the total number of transmitted bits of the multilevel signal MS from the transmitter TX and the number of erroneous bits between the multilevel signal MS and the digital data signal DO. The number of erroneous bits refers to the number of bits that differ between the multilevel signal MS and the digital data signal DO. For example, when the total number of transmitted bits of the multilevel signal MS is 10... 4 Furthermore, when the number of erroneous bits is 1, the bit error rate (BER) is 10. -4 .

[0108] In step (S1020), the receiver RX can generate a calculator selection signal CAL_EN based on the calculated bit error rate (BER). Figure 9 (In the middle). The receiver RX can obtain a first reference value (i.e., a first threshold) from a separate storage device included in the receiver RX for comparison of the bit error rate (BER). When the bit error rate (BER) is greater than or equal to the first threshold, the receiver RX can generate calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16, which will turn on the switches SX1, SX2, ..., and SX16 of calculators 911a, 912a, ..., and 913a determined based on the transition information of the digital data signal DO. When the bit error rate (BER) is less than the first threshold, the receiver RX can generate calculator selection signals CAL_EN1, CAL_EN2, ..., and CAL_EN16, which will turn on the switches SX1, SX2, ..., and SX16 of calculators 911a, 912a, ..., and 913a determined based on the transition information of the digital data signal DO. Figure 9 Switches SX1, SX2, ... and SX16 in the middle are disconnected.

[0109] In step (S1030), calculators 911a, 912a, ... and 913a and multiplexers 911b, 912b, ..., 913b (in... Figure 9The calculators 911a, 912a, ..., 913a can be driven based on calculator selection signals CAL_EN1, CAL_EN2, ..., CAL_EN16. Switches SX1, SX2, ..., SX16 can be turned on based on calculator selection signals CAL_EN1, CAL_EN2, ..., CAL_EN16 that turn on switches SX1, SX2, ..., SX16. Drive voltages can be applied to calculators 911a, 912a, ..., 913a. Multiplexers 911b, 912b, ..., 913b can receive sampling control signals DX1, DX2, ..., DX16 as calculated values ​​from each output of calculators 911a, 912a, ..., 913a. Multiplexers 911b, 912b, ..., 913b can receive sampling control signals DX1, DX2, ..., DX16 and can transmit them as is to loop filter 540 (in... Figure 5 middle).

[0110] Switches SX1, SX2, ..., SX16 can be disconnected based on calculator selection signals CAL_EN1, CAL_EN2, ..., CAL_EN16 that disconnect switches SX1, SX2, ..., SX16. Drive voltages may not be applied to calculators 911a, 912a, ..., 913a. Multiplexers 911b, 912b, ..., 913b may not transmit sampling control signals DX1, DX2, ..., DX16, which are the calculated values ​​from each output of calculators 911a, 912a, ..., 913a, to loop filter 540.

[0111] Figure 11 Table (1100) illustrates examples of gain and current consumption generated in a Mueller-Muller phase detector based on digital data transformations according to some embodiments. Figure 11 In the middle, the gain can be indicated according to the input to the Mueller-Muller phase detector 530 (in Figure 5 The variability of the output value of the phase difference between the digital data signal DO and the clock signal CK (in the image) is considered. As the gain increases, the variability of the output value increases, making it easier to adjust the phase of the clock signal CK to accurately capture the digital data signal DO. Furthermore, as the gain increases, the gain-to-noise ratio (GNR) improves, thus eliminating distortion caused by noise in the digital data signal DO and the clock signal CK.

[0112] The gain can vary based on the voltage level difference between two successively input digital data signals (DO). For example, the gain of the Mueller-Muller phase detector 530 during the transition from +3V to +3V can be 0.2255V / rad, the gain during the transition from +3V to +1V can be 0.3393V / rad, and the gain during the transition from +3V to -1V can be 0.3447V / rad. The gain during the transition from +3V to -3V can be 0.448V / rad, the gain during the transition from +1V to +1V can be 0.0789V / rad, and the gain during the transition from +1V to -1V can be 0.1713V / rad. The Mueller-Muller phase detector 530 can have a gain of 0.3446 V / rad at the transition from +1V to -3V; a gain of 0.0823 V / rad at the transition from -1V to -1V; a gain of 0.3485 V / rad at the transition from -1V to -3V; and a gain of 0.2347 V / rad at the transition from -3V to -3V.

[0113] If the Mueller-Muller phase detector 530 detects all transitions occurring in the digital data signal DO, the gain can be increased, but the current consumption can also increase. The current consumption generated by the Mueller-Muller phase detector 530 for detecting all transitions can be 52.3µA each.

[0114] The Mueller-Muller phase detector 530 can select at least one type of transition and can detect only the selected transition in the digital data signal DO. The calculators 911a, 912a, ..., and 913a (in...) correspond to transitions not selected by the Mueller-Muller phase detector 530. Figure 9 (In the middle) because switches SX1, SX2, ... and SX16 are open, the voltage source VDD (in) can be bypassed. Figure 9(In the middle) receives the drive voltage. Calculators 911a, 912a, ..., and 913a are not driven, therefore, the current consumption generated in the Mueller-Muller phase detector 530 can be reduced. Therefore, the fewer transitions selected by the Mueller-Muller phase detector 530, the fewer calculators 911a, 912a, ..., and 913a need to be driven, thus allowing the Mueller-Muller phase detector 530 to be driven with lower power.

[0115] Figure 12 Example block diagrams illustrating examples of computer devices (or computing devices) according to some embodiments are shown. Figure 12 In this computing device 1200, there are a processor 1210, a memory 1220, a memory controller 1230, a storage device 1240, a communication interface 1250, and a bus 1260. The computing device 1200 may also include other general-purpose components.

[0116] Processor 1210 controls the overall operation of each component of computing device 1200. Processor 1210 may be implemented as at least one of various processors, such as central processing unit (CPU), application processor (AP), and graphics processing unit (GPU).

[0117] Processor 1210 can be based on ( Figure 5 The processor 1210 obtains transition information from the two digital data signals DO and can determine whether the digital data signal DO is phase-delayed or phase-advanced. The processor 1210 can detect sampling timing errors of the digital data signal DO based on the transition information and phase information.

[0118] Processor 1210 can calculate bit error rate (BER). Processor 1210 can calculate based on multi-level signal MS (in Figure 5 The processor 1210 calculates the bit error rate (BER) using the digital data signal DO and the input (in the middle) signal. The processor 1210 can compare the calculated BER with a first reference value and can generate values ​​for calculators 911a, 912a, ..., and 913a (in... Figure 9 (in) and multiplexers 911b, 912b, ... and 913b (in) Figure 9 The calculator selection signals CAL_EN1, CAL_EN2, ... and CAL_EN16 (in the middle) are used to drive the calculator selection signals. Figure 9 middle).

[0119] Memory 1220 stores various data and commands. Memory 1220 can be implemented as a reference. Figures 1 to 11The memory device described. Memory controller 1230 controls the transfer of data or commands to and from memory 1220. In some embodiments, memory controller 1230 may be provided as a separate chip from processor 1210. In some embodiments, memory controller 1230 may be provided as an internal component of processor 1210.

[0120] Storage device 1240 stores programs and data non-temporarily. In some embodiments, storage device 1240 may be implemented as non-volatile memory. Communication interface 1250 supports wired and wireless Internet communication of computing device 1200. Furthermore, communication interface 1250 may support various communication methods other than Internet communication. Bus 1260 provides communication functionality between components of computing device 1200. Bus 1260 may include at least one type of bus depending on the communication protocol between components.

[0121] While this disclosure contains numerous details of specific implementations, these details should not be construed as limiting the scope of the claims, their equivalents, and the appended claims. Certain features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, in some cases one or more features from the combination may be removed from that combination, and the combination may involve sub-combinations or variations thereof.

Claims

1. A receiver, comprising: The analog front-end circuit is configured to receive data input / output signals and amplify the data input / output signals to generate processing signals. A time-interleaved analog-to-digital converter is configured to sample the processed signal based on multiple clock signals and generate multiple digital data signals. The Mueller-Muller phase detector is configured to receive the plurality of digital data signals from a time-interleaved analog-to-digital converter and drive at least one of the plurality of calculators based on the transition between two sequentially received digital data signals among the plurality of digital data signals. The monitoring circuit is configured to: receive the plurality of digital data signals from a time-interleaved analog-to-digital converter, receive a multi-level signal transmitted from a transmitter, and generate a monitoring output signal based on the plurality of digital data signals and the multi-level signal; as well as The control logic circuit is configured to receive a monitoring output signal from the monitoring circuit and generate a plurality of calculator selection signals based on the monitoring output signal, the plurality of calculator selection signals being configured to drive the plurality of calculators.

2. The receiver according to claim 1, wherein, The Mueller-Muller phase detector includes: The phase decision decoder circuit is configured to: generate transition information between the two digital data signals, determine phase information for a clock signal used to sample the two digital data signals, and output a phase decision signal including the phase information. The plurality of calculators are configured to: receive a phase decision signal and generate a plurality of sampling control signals based on the phase decision signal, wherein the plurality of sampling control signals are used to control the timing of a clock signal; Multiple switches are configured to connect the multiple calculators and voltage sources; and Multiple multiplexers are configured to receive sampling control signals from the multiple calculators and selectively output sampling control signals.

3. The receiver according to claim 2, in, The phase decision decoder circuit is configured to: select a first calculator from the plurality of calculators based on the transition information, and output a phase decision signal to the first calculator. The multiple switches are configured to be turned on or off based on a calculator selection signal.

4. The receiver according to claim 3, wherein, The monitoring circuit is configured as follows: The signal-to-noise ratio (SNR) is calculated based on signal power and noise power. Signal power is measured as the squared average of the voltage levels of the two digital data signals or the squared average of the voltage levels of a multi-level signal. Noise power includes power loss occurring during the signal transmission path. The signal-to-noise ratio is generated as the monitoring output signal.

5. The receiver according to claim 4, in, The first of the plurality of switches is connected to the first calculator and is configured to disconnect based on a calculator selection signal generated according to a monitored output signal being greater than or equal to a first reference value. The first multiplexer among the plurality of multiplexers is connected to the first calculator and is configured to: based on a calculator selection signal generated according to the monitoring output signal being greater than or equal to a first reference value, not send the sampling control signal of the first calculator among the plurality of sampling control signals to the loop filter.

6. The receiver according to claim 4, in, The first of the plurality of switches is connected to the first calculator and is configured to be turned on based on a calculator selection signal generated according to a monitored output signal being less than a first reference value. The first multiplexer among the plurality of multiplexers is connected to the first calculator and is configured to output the sampling control signal of the first calculator among the plurality of sampling control signals to the loop filter based on a calculator selection signal generated according to the monitoring output signal being less than a first reference value.

7. The receiver according to claim 3, wherein, The monitoring circuit is configured as follows: The bit error rate is calculated based on the total number of transmitted bits of the multi-level signal and the number of erroneous bits between the multi-level signal and the two digital data signals; and The bit error rate is generated as a monitoring output signal.

8. The receiver according to claim 7, in, The first of the plurality of switches is connected to the first calculator and is configured to disconnect based on a calculator selection signal generated according to a monitored output signal being less than a first reference value. The first multiplexer among the plurality of multiplexers is connected to the first calculator and is configured to: based on a calculator selection signal generated according to the monitoring output signal being less than a first reference value, not send the sampling control signal of the first calculator among the plurality of sampling control signals to the loop filter.

9. The receiver according to claim 7, in, The first switch of the plurality of switches is connected to the first calculator and is configured to be turned on based on a calculator selection signal generated according to a monitored output signal being greater than or equal to a first reference value, and The first multiplexer among the plurality of multiplexers is connected to the first calculator and is configured to: generate a calculator selection signal based on the monitoring output signal being greater than or equal to a first reference value, and output the sampling control signal of the first calculator among the plurality of sampling control signals to a loop filter.

10. The receiver according to claim 3, wherein, Phase decision signals include: The transformation information; and The values ​​of the two digital data signals.

11. A phase detection device, comprising: Multiple calculators, each configured to: output multiple sampling control signals corresponding to the transition of two adjacent digital data signals among multiple digital data signals, and control the sampling timing for sampling the digital data signals; The monitoring circuit is configured to: acquire the plurality of digital data signals, receive a multi-level signal having one of N signal levels from the transmitter, and generate a monitoring output signal using the plurality of digital data signals and the multi-level signal, wherein N is a positive integer; The control logic circuit is configured to: compare a monitored output signal with a first reference value and generate a plurality of calculator selection signals configured to drive the plurality of calculators; and Multiple switches are configured to transmit drive voltage from a voltage source to the multiple calculators based on the multiple calculator selection signals.

12. The phase detection device according to claim 11, further comprising: Multiple multiplexers are configured to selectively output the multiple sampling control signals based on the multiple calculator selection signals.

13. The phase detection device according to claim 12, wherein, The monitored output signal includes a signal representing the signal-to-noise ratio, which is based on the signal power of the multi-level signal, the signal power of the digital data signal among the plurality of digital data signals, and the noise power including power loss that occurs in the signal transmission path.

14. The phase detection device according to claim 13, in, The control logic circuit is configured to generate calculator selection signals, based on a monitoring output signal less than a first reference value, to drive m calculators among the plurality of calculators, where m is a positive integer. Among these, a group of switches connected to the m calculators is configured to be turned on based on a calculator selection signal, and Among them, a group of multiplexers connected to the m calculators is configured to output a sampled control signal from the m calculators based on the calculator selection signal.

15. The phase detection device according to claim 14, in, The control logic circuit is configured to generate calculator selection signals, based on a monitoring output signal that is greater than or equal to a first reference value, to drive n calculators among the plurality of calculators, where n is a positive integer. <m, Among these, another set of switches connected to the n calculators is configured to disconnect upon receiving a calculator selection signal, and Among them, another set of multiplexers connected to the n calculators is configured not to transmit the sampling control signals output from the n calculators to the loop filter.

16. The phase detection device according to claim 12, wherein, The monitored output signal includes a signal representing the bit error rate, which is determined based on the number of bit errors between the multi-level signal and the plurality of digital data signals.

17. The phase detection device according to claim 13, in, The control logic circuit is configured to generate calculator selection signals, based on a monitoring output signal that is greater than or equal to a first reference value, to drive m calculators among the plurality of calculators, where m is a positive integer. Among these, a group of switches connected to the m calculators is configured to be turned on based on a calculator selection signal, and One group of multiplexers connected to the m calculators is configured to output a sampled control signal from the m calculators based on a calculator selection signal.

18. The phase detection device according to claim 17, in, The control logic circuit is configured to: generate calculator selection signals, based on a monitoring output signal less than a first reference value, to drive n calculators among the plurality of calculators, where n is a positive integer. <m, Among these, another set of switches connected to the n calculators is configured to disconnect upon receiving a calculator selection signal, and Among them, another set of multiplexers connected to the n calculators is configured not to transmit the sampling control signals output from the n calculators to the loop filter.

19. A phase detection method, comprising: The bit error rate is calculated based on a multi-level signal with one of N signal levels received from the transmitter and a digital data signal obtained from a time-interleaved analog-to-digital converter, where N is a positive integer; Compare the bit error rate with a first reference value; Based on the comparison results, multiple calculator selection signals are generated, which are used to turn on or off multiple switches respectively connected between multiple calculators and a voltage source; and The plurality of calculator selection signals are supplied to the plurality of switches and the plurality of multiplexers, the plurality of multiplexers being configured to receive sampled control signals output from the plurality of calculators.

20. The phase detection method according to claim 19, wherein, The steps for generating the plurality of calculator selection signals include: Based on a bit error rate equal to or greater than a first reference value, generate the plurality of calculator selection signals for turning on the plurality of switches; and Based on a bit error rate less than a first reference value, the plurality of calculator selection signals are generated to disconnect the plurality of switches.

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