Electronic device, communication system, communication method, computer device, and medium

Abstract

The invention provides electronic equipment, a communication system, a communication method, computer equipment and a medium. An electronic device according to an embodiment includes a serial bus including a clock signal line and a data signal line, and a conversion structure including: a signal modulation circuit that modulates a received first signal with a first data signal from the data signal line to generate a first modulated signal, the first signal comprises clock information of a first clock signal from a clock signal line; the photoelectric and electro-optical conversion circuit is used for converting the first modulation signal into an optical signal output by the electronic equipment based on the control information of the control circuit, and converting the received optical signal into an electric signal based on the control information of the control circuit; and the signal separation circuit separates the electric signal into a second clock signal transmitted to the clock signal line and a second data signal transmitted to the data signal line. According to the electronic equipment disclosed by the embodiment of the invention, two-way transmission of two signals can be realized on one optical fiber.

Description

Technical Field

[0001] This disclosure relates to the field of communications. More specifically, it relates to an electronic device, a communication system, a communication method, a computer device, and a computer-readable storage medium. Background Technology

[0002] To facilitate long-distance transmission of HDMI signals, HDMI fiber optic cables are generally used, especially in large conference rooms where the distance from the control panel to the large screen display can exceed 20 meters. Currently, HDMI fiber optic cables on the market do not achieve fiber optic transmission of all signals. Only high-speed video signals such as TMDS are converted into optical signals through an electro-optical conversion chip, while low-speed signals such as I2C, CEC, and ARC still use copper wire connections.

[0003] However, long-distance copper wires attenuate frequency signals, and this attenuation becomes more pronounced with increasing distance, causing the receiver to fail to correctly identify the signal and thus preventing the display of the image. Summary of the Invention

[0004] A first aspect of this disclosure provides an electronic device, including: a serial bus and a conversion structure electrically connected to the serial bus, the serial bus including clock signal lines and data signal lines, and the conversion structure including: a signal modulation circuit, a photoelectric and electro-optic conversion circuit, a signal separation circuit, and a control circuit; A signal modulation circuit is used to modulate a first data signal from a data signal line onto a received first signal to generate a first modulated signal, wherein the first signal includes clock information from a first clock signal from a clock signal line. The photoelectric and electro-optical conversion circuit is used to convert a first modulation signal into an optical signal for output by an electronic device based on control information from a control circuit, and to convert the received optical signal into an electrical signal based on control information from a control circuit. A signal separation circuit is used to separate an electrical signal into a second clock signal that is transmitted to a clock signal line and a second data signal that is transmitted to a data signal line.

[0005] Optionally, the control circuit further includes a memory, which includes an address register, a first data register, and a second data register; wherein the address memory is used to store a first set or a second set of data from the data signal line, and the first data memory is used to store subsequent data from the data signal line; or, the address memory is used to store a first set or a second set of data from the second data signal, and the second data memory is used to store subsequent data from the second data signal.

[0006] Optionally, the signal separation circuit includes: a high-pass filter circuit, a latch and frequency reduction circuit, and an envelope detection circuit. The high-pass filter circuit is used to perform high-pass filtering on the electrical signal to generate a second signal, the second signal including clock information. The latching and down-frequency circuit is used to down-frequency the second signal to generate a second clock signal and generate an interrupt signal output to the control circuit based on the comparison of the duration of adjacent high levels of the second clock signal. An envelope detection circuit is used to filter out high-frequency components in a second signal and form a second data signal with an envelope waveform of the second signal.

[0007] Optionally, the conversion structure further includes a frequency multiplier circuit, wherein the control circuit generates a third clock signal based on the first clock signal line, and the frequency multiplier circuit is used to multiply the third clock signal to generate the first signal.

[0008] Optionally, the high-pass filter cutoff frequency of the high-pass filter circuit is greater than or equal to 1 / 5 of the frequency of the second signal.

[0009] Optionally, the photoelectric and electro-optical conversion circuit includes: an electro-optical conversion sub-circuit and a photoelectric conversion sub-circuit; The electro-optical conversion sub-circuit includes a light-emitting device. When the electro-optical conversion sub-circuit is turned on based on the control signal of the control circuit, the light-emitting device emits light based on the control of the received first modulation signal to generate an optical signal. The photoelectric conversion sub-circuit includes photoelectric devices. When the photoelectric conversion sub-circuit is turned on based on the control signal of the control circuit, it generates an electrical signal based on the optical signal received by the photoelectric devices. When the first modulation signal is high, the light-emitting device emits light, and when the photoelectric device receives the light signal, the electrical signal is high; or, when the first modulation signal is low, the light-emitting device emits light, and when the photoelectric device receives the light signal, the electrical signal is low.

[0010] A second aspect of this disclosure provides a communication system comprising at least two electronic devices, the electronic devices being those described above, the at least two electronic devices including at least one master device and at least one slave device, the output of the conversion structure of the master device and the output of the conversion structure of the slave device communicating therewith being connected and communicating via an optical fiber.

[0011] A third aspect of this disclosure provides a communication method applied to a master device, the master device being an electronic device according to the above description, comprising: Obtain the serial communication start flag from the serial bus; In response to the serial communication start flag, the conversion structure generates a third clock signal as an optical communication start flag signal and turns off the signal modulation circuit, converts the third clock signal into an optical signal and sends it to the slave device; The first or second set of data from the data signal line is stored in the address register. The conversion structure turns on the signal modulation circuit and sends the generated optical signal to the slave device using the first or second set of data as the first data signal. In response to the first level of the flag bit in the address register, the conversion structure stores the subsequent data of the data signal line into the first data register, and uses the signal read from the first data register as the first data signal to send the generated optical signal to the slave device.

[0012] Optionally, the communication method further includes: in response to the flag bit in the address register being at the second level, the conversion structure acquires the optical signal from the slave device and generates a second data signal, and stores the second data signal in the second data register.

[0013] Optionally, after the conversion structure stores subsequent data of the data signal line into the first data register in response to the flag bit in the address register being at the first level, and sends the generated optical signal to the slave device as the first data signal using the signal read from the first data register, the method further includes: Obtain the serial communication end marker from the serial bus; In response to the serial communication end flag, the conversion structure generates a third clock signal representing the optical communication end flag signal and shuts down the signal modulation circuit, converts the third clock signal representing the optical communication end flag signal into an optical signal and sends it to the slave device.

[0014] Optionally, after the conversion structure acquires the optical signal from the slave device and generates a second data signal in response to the flag bit in the address register being at the second level, and stores the second data signal in the second data register, the method further includes: The conversion structure calculates the time difference between two adjacent high levels in the second clock signal; In response to a positive time difference between the preceding and following high levels, the conversion structure sends a serial communication end flag to the data signal line.

[0015] Optionally, the optical communication start signal is a sequence of square wave signals with successively increasing high-level time lengths, and the optical communication end signal is a sequence of square wave signals with successively decreasing high-level time lengths.

[0016] Optionally, the first set of data from the data signal line is the device address of the slave device. The conversion structure sends the first set of data as the first data signal to the slave device to generate the optical signal, and stores the second set of data from the data signal line into the address register. In response to the flag bit in the address register being at a first level, the conversion structure stores subsequent data from the data signal line into the first data register, and uses the signal read from the first data register as the first data signal to send the generated optical signal to the slave device, further comprising: In response to the first level of the flag bit in the address register, the conversion structure stores the second set of data on the data signal line into the first data register, and uses the signal read from the first data register as the first data signal to send the generated optical signal to the slave device. In response to the acknowledgment signal from the slave device, the conversion structure shuts down the signal modulation circuit, converts multiple clock signals from the clock signal line into optical signals as optical communication indication signals, and sends them to the slave device. In response to an acknowledgment signal from the slave device, the conversion structure stores subsequent data from the data signal line into the first data register, and uses the signal read from the first data register as the first data signal to send the generated optical signal to the slave device.

[0017] A fourth aspect of this disclosure provides a communication method applied to a slave device, the slave device being an electronic device according to the above description, comprising: The conversion structure generates a second clock signal representing the start of optical communication based on the acquired optical signal from the master device; The conversion structure generates a second clock signal and a first set of second data signals based on the optical signal acquired from the master device, and stores the first set or the second set of second data signals into the address register; In response to the first level of the flag bit in the address register, the conversion structure stores the subsequent second data signal into the second data register.

[0018] Optionally, the communication method further includes: in response to the flag bit in the address register being at a second level, the conversion structure stores the data signal in the second data register into the first data register, and sends the generated optical signal to the master device as the signal read from the first data register as the first data signal.

[0019] Optionally, the first set of data from the data signal line is the device address of the slave device. The conversion structure sends the first set of data as the first data signal to the slave device to generate the optical signal, and stores the second set of data from the data signal line into the address register. In response to the flag bit in the address register being at the second level, the conversion structure stores the data signal in the second data register into the first data register, and uses the signal read from the first data register as the first data signal to send the generated optical signal to the master device, further comprising: In response to the optical signal from the master device, a first set of second data signals is generated and matched with the device address of one of the multiple devices in the slave device to obtain the device address; The conversion structure then generates a second clock signal representing the start of optical communication based on the acquired optical signal from the master device, and sends an acknowledgment signal to the master device. In response to the flag bit in the address register of the device corresponding to the device address being at the second level, the conversion structure stores the data signal in the second data register of the corresponding device into the first data register, and uses the signal read from the first data register as the first data signal to send the generated optical signal to the master device.

[0020] The fifth aspect of this disclosure provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the communication method described in the third aspect above, or the processor executes the program to implement the communication method described in the fourth aspect above.

[0021] The fifth aspect of this disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein a processor executes the program to implement the communication method described in the third aspect above, or the processor executes the program to implement the communication method described in the fourth aspect above.

[0022] The beneficial effects of this disclosure are as follows: The electronic devices, communication systems, communication methods, computer equipment, and media described in this disclosure provide a conversion structure electrically connected to a serial bus. This conversion structure includes a signal modulation circuit, a photoelectric and electro-optical conversion circuit, a signal separation circuit, and a control circuit. The signal modulation circuit modulates a first signal (including clock information) using a first data signal and converts it into an optical signal for propagation. The received optical signal is then converted into an electrical signal and separated into a second data signal and a second clock signal. This single conversion structure enables two-line transmission of serial bus signals over a single optical fiber, solving the integrity problem after long-distance wire communication. It facilitates communication between the main control device and controlled devices such as large screens, ensuring normal display and demonstrating broad application prospects. Attached Figure Description

[0023] The specific embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0024] Figure 1 The waveform at the receiving end of an electronic device in the related technology after long-distance communication via copper wires is shown. Figure 2 A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown; Figure 3 A schematic diagram of an electronic device according to another embodiment of the present disclosure is shown; Figure 4 A waveform diagram of a third clock signal SDL_3 and a first signal A generated by an electronic device according to an embodiment of the present disclosure is shown. Figure 5A waveform diagram of a first clock signal SDL_1, a first signal A, and a first modulation signal B generated by an electronic device according to an embodiment of the present disclosure is shown. Figure 6 A schematic diagram of an electro-optical conversion sub-circuit of an electronic device according to an embodiment of the present disclosure is shown. Figure 7 A schematic diagram of a photoelectric conversion sub-circuit of an electronic device according to an embodiment of the present disclosure is shown. Figure 8 A schematic diagram of an electronic device according to another embodiment of the present disclosure is shown; Figure 9 A schematic waveform diagram of an optical communication start-signal signal according to an embodiment of the present disclosure is shown; Figure 10 A schematic waveform diagram of an optical communication end-of-communication signal according to an embodiment of the present disclosure is shown; Figure 11 A schematic diagram of an envelope detection circuit of an electronic device according to an embodiment of the present disclosure is shown. Figure 12 A schematic diagram of a communication system according to an embodiment of the present disclosure is shown. Figure 13 A schematic flowchart of a communication method according to an embodiment of the present disclosure is shown; Figure 14 A memory schematic diagram of a control circuit according to an embodiment of the present disclosure is shown; Figure 15 A schematic flowchart illustrating a communication method according to another embodiment of the present disclosure is shown; Figure 16 A schematic diagram of a computer device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0025] To more clearly illustrate this disclosure, the following description, in conjunction with embodiments and accompanying drawings, provides further insight. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.

[0026] Reference Figure 1 As shown, Figure 1The diagram illustrates the signal waveform received by an oscilloscope at the receiving end when transmitting I2C bus frequency signals over a 20-meter long copper wire in a related technology. The upper waveform represents the data signal line, and the lower waveform represents the clock signal line. As can be seen from the diagram, after long-distance transmission, due to the attenuation effect of the copper wire on the frequency signal, the square wave waveform at the transmitting end is severely distorted, with a significant decrease in amplitude. At the receiving end, it can no longer be recognized as a square wave signal, and the effective duration of high and low level signals cannot be received. This means that communication between the receiving large-screen device and the transmitting device cannot be completed, resulting in the controlled large screen failing to display correctly.

[0027] Because optical communication is unidirectional, while serial buses such as I2C are typically bidirectional, current solutions to address signal attenuation and communication failures involve replacing the two copper wires in an HDMI cable with two optical fibers. This involves converting the clock and data signal lines of a serial bus, such as I2C, into optical signals to achieve long-distance transmission. However, this requires two separate photoelectric conversion circuits for signal conversion, which hinders interface miniaturization.

[0028] Therefore, there is a need to provide a solution for addressing the integrity issues of long-distance communication in a miniaturized manner.

[0029] In view of the above, one embodiment of this disclosure provides an electronic device, including: A serial bus and a conversion structure electrically connected to the serial bus, the serial bus including clock signal lines and data signal lines. The conversion structure includes: signal modulation circuit, photoelectric and electro-optic conversion circuit, signal separation circuit, and control circuit. A signal modulation circuit is used to modulate a first data signal from a data signal line onto a received first signal to generate a first modulated signal, wherein the first signal includes clock information from a first clock signal from a clock signal line. The photoelectric and electro-optical conversion circuit is used to convert a first modulation signal into an optical signal for output by an electronic device based on control information from a control circuit, and to convert the received optical signal into an electrical signal based on control information from a control circuit. A signal separation circuit is used to separate an electrical signal into a second clock signal that is transmitted to a clock signal line and a second data signal that is transmitted to a data signal line.

[0030] In this embodiment, a conversion structure electrically connected to a serial bus is provided. The conversion structure includes a signal modulation circuit, a photoelectric and electro-optic conversion circuit, a signal separation circuit, and a control circuit. The signal modulation circuit uses a first data signal to modulate a first signal including clock information and converts it into an optical signal for propagation. The received optical signal is converted into an electrical signal and then separated into a second data signal and a second clock signal. Thus, a single conversion structure is used to achieve two-line transmission of serial bus signals on a single optical fiber, solving the integrity problem after long-distance wire communication, enabling communication between the main control device and controlled devices such as large screens, and ensuring normal display.

[0031] The structure and function of the electronic device according to the present disclosure will be described in detail below with reference to specific embodiments.

[0032] Reference Figure 2 As shown, the electronic device of this embodiment includes a serial bus and a conversion structure 1 electrically connected to the serial bus. The serial bus includes a clock signal line SDL and a data signal line SDA.

[0033] Optionally, the conversion structure 1 can be electrically connected to the clock signal line SDL and data signal line SDA in the serial bus via a connector, or it can be directly electrically connected on the circuit board. The specific electrical connection method is not limited in this article.

[0034] It should be noted that the serial bus in this disclosure includes, but is not limited to, the I2C bus. Any serial bus that requires clock signal lines and data signal lines for signal transmission during communication is covered by this disclosure. For example, serial buses include, but are not limited to, the I2C bus, the SPI bus, and other similar buses.

[0035] The conversion structure 1 includes: a signal modulation circuit 10, a photoelectric and electro-optic conversion circuit 20, a signal separation circuit 30, and a control circuit 40.

[0036] The signal modulation circuit 10 is used to modulate the received first signal A by the first data signal SDA_1 from the data signal line SDA to generate a first modulated signal B. The first signal A includes clock information from the first clock signal SDL_1 from the clock signal line SDL.

[0037] The photoelectric and electro-optical conversion circuit 20 is used to convert the first modulation signal B into an optical signal C for output by the electronic device based on the control information of the control circuit 40, and to convert the received optical signal C into an electrical signal D based on the control information of the control circuit 40. It should be noted that, in this document, the process of converting the first modulation signal B into the optical signal C for output by the electronic device is called the electro-optical conversion process, and the process of converting the optical signal C received by the electronic device into the electrical signal D is called the electro-optical conversion process. These two processes represent two conversion paths, and the optical signal C in both paths only indicates signals of the same nature being transmitted and received, not the same signal.

[0038] The signal separation circuit 30 is used to separate the electrical signal D into a second clock signal SDL_2 transmitted to the clock signal line SDL and a second data signal SDA_2 transmitted to the data signal line SDA.

[0039] The control circuit 40 is used to send control signals to the signal modulation circuit 10 and the photoelectric and electro-optical conversion circuit 20 based on the received signals from the clock signal line SDL and the data signal line SDA, or to provide feedback information, clock signals or data signals to the clock signal line SDL and the data signal line SDA in response to the second clock signal and the second data signal from the signal separation circuit 30.

[0040] Optionally, refer to Figure 3 As shown, the electronic device also includes a frequency multiplier circuit 50. The control circuit 40 generates a third clock signal SDL_3 based on the first clock signal. The frequency multiplier circuit 50 multiplies the frequency of the third clock signal SDL_3 to generate the first signal A. For example, if the frequency of the first clock signal SDL_1 is f0, the frequency of the multiplied signal (i.e., the first signal A) is f0. N is a positive integer. Figure 4 The waveform of the third clock signal SDL_3 and the waveform of the first signal A generated by multiplying the frequency of the third clock signal SDL_3 are illustrated.

[0041] For example, the I2C protocol supports several fixed clock rates: 100kHz, 400kHz, 1MHz, and 3.4MHz. Even after multiplying the frequency by 10, the maximum frequency is only 34MHz, which is relatively easy to implement. Of course, those skilled in the art should understand that the specific clock frequency and multiplication factor can be selected according to the specific protocol type of the serial bus and the required hardware specifications, and this disclosure does not impose any special limitations.

[0042] It should be understood that, when the frequency multiplier circuit 50 is included, the first signal A embodies the clock information of the first clock signal SDL_1, which is N times the frequency of the first clock signal SDL_1, in the form of a signal frequency that is N times the frequency of the first clock signal SDL_1.

[0043] Figure 5 An exemplary diagram shows the signal waveforms of the first data signal SDA_1, the first signal A, and the first modulation signal B from the data signal line SDA. Figure 5 As can be seen, the first signal A is used as a carrier signal. After the first signal A is modulated by the first data signal SDA_1, the generated first modulated signal B simultaneously reflects the clock information from the first clock signal SDL_1 and the data information from the first data signal SDA_1. In other words, it realizes the transmission of two kinds of information with one signal.

[0044] It is worth mentioning that by multiplying the signal frequency through the frequency multiplier circuit 50 before the third clock signal SDL_3 enters the modulation circuit 10, when the first signal A is modulated by the first data signal SDA_1, the first modulation signal B can represent the data information with more high-frequency signals during the high-level period corresponding to the first data signal SDA_1, which facilitates accurate signal transmission.

[0045] In an optional embodiment, the electro-optical and photoelectric conversion circuit 20 includes an electro-optical conversion sub-circuit that converts an electrical signal into an optical signal and a photoelectric conversion sub-circuit that converts an optical signal into an electrical signal.

[0046] The electro-optical conversion sub-circuit includes a light-emitting device. When the electro-optical conversion sub-circuit is turned on based on the control signal of the control circuit, the light-emitting device emits light based on the control of the received first modulation signal to generate an optical signal. The photoelectric conversion sub-circuit includes a photoelectric device. When the photoelectric conversion sub-circuit is turned on based on the control signal of the control circuit, it generates an electrical signal based on the optical signal received by the photoelectric device.

[0047] For example, Figure 6 The circuit diagram of an electro-optical conversion sub-circuit is shown. Figure 6 As can be seen, the circuit includes an NPN transistor Q1 connected in series between the power supply terminal VCC and the ground terminal, and a light-emitting device. When the base of the NPN transistor Q1 receives a high level of the first modulation signal B, the NPN transistor Q1 is turned on, and the cathode of the light-emitting device is electrically connected to the ground terminal, thereby driving the light-emitting device to emit light. When the first modulation signal B is high, the light-emitting device lights up; when it is low, the light-emitting device is off, thus forming a light pulse within one high-frequency clock cycle. The modulated signal is converted into a light pulse, which can be transmitted to the other end of the transmission line via an optical fiber connected to the electronic device.

[0048] For example, Figure 7 The circuit diagram of a photoelectric conversion sub-circuit is shown. Figure 7 As can be seen, the circuit includes: a photodiode, a first resistor R1, a second resistor R2, and an NPN transistor Q2.

[0049] Specifically, the first terminal of the first resistor R1 is electrically connected to the power supply terminal VCC, and the second terminal is electrically connected to the anode of the photodiode. The base of the NPN transistor Q2 is electrically connected to the anode of the photodiode, and the cathode of the photodiode is electrically connected to ground. The first terminal of the second resistor R2 is electrically connected to the power supply terminal VCC, and the second terminal is electrically connected to the collector of the NPN transistor. The emitter of the NPN transistor is electrically connected to ground. When the photodiode receives the light signal C, it conducts, causing the base of the NPN transistor Q2 to be connected to a low level and turned off, thus generating a high-level electrical signal. Conversely, when the photodiode does not receive the light signal C, it is turned off, causing the base of the NPN transistor Q2 to be connected to a high level and turned on, generating a low-level electrical signal D. In this way, one light pulse is converted into one periodic electrical signal.

[0050] It should be noted that, although Figure 6 and Figure 7 Each of the above presents a circuit diagram for implementing an electro-optical conversion sub-circuit and a photoelectric conversion sub-circuit, but this disclosure is not intended to be limited thereto. That is, the embodiments of this disclosure are not intended to limit the specific circuit form and connection method of the electro-optical conversion sub-circuit and the photoelectric conversion sub-circuit.

[0051] However, it should be noted that, considering the communication characteristics of the serial bus, the electronic devices communicating with each other should be configured with the conversion structure of the present disclosure embodiment, and the conversion logic between the electro-optical conversion sub-circuit and the photoelectric conversion sub-circuit of the corresponding electronic devices should be consistent.

[0052] For example, if the electro-optical conversion sub-circuit of electronic device 1 outputs the light signal C corresponding to the light emission of the light-emitting device based on the high level of the first modulation signal B, the electrical signal D converted by the photoelectric conversion sub-circuit of electronic device 2 based on the received light signal C should also be at a high level. Conversely, if the electrical signal D converted by the photoelectric conversion sub-circuit of electronic device 1 based on the received light signal C is at a high level, the electro-optical conversion sub-circuit of electronic device 2 should also cause the light-emitting device to emit light based on the high level of the first modulation signal B. In other words, the logic of an electrical signal of one level being converted by the electro-optical conversion sub-circuit at the transmitting end and then converted back by the optoelectronic circuit at the receiving end should be consistent.

[0053] Optionally, considering manufacturing costs, when the first modulation signal is high, the light-emitting device emits light, and when the photoelectric device receives the light signal, the electrical signal is high; or, when the first modulation signal is low, the light-emitting device emits light, and when the photoelectric device receives the light signal, the electrical signal is low.

[0054] This scheme sets the photoelectric and photoelectric conversion logic within the electro-optical and photoelectric conversion circuits to be consistent, which is beneficial for mass production. This eliminates the need to install electro-optical and photoelectric conversion sub-circuits with different logics according to the configuration of electronic devices during the production stage.

[0055] In an optional embodiment, refer to Figure 8 As shown, the signal separation circuit 30 includes: a high-pass filter circuit 31, a latch and frequency reduction circuit 32, and an envelope detector circuit 33.

[0056] The high-pass filter circuit 31 is used to perform high-pass filtering on the electrical signal to generate a second signal E, which includes clock information.

[0057] It can be understood that the electrical signal D generated by the photoelectric conversion sub-circuit after photoelectric conversion of the optical signal is actually a restored first modulation signal from another electronic device. After the electrical signal D is high-pass filtered by the high-pass filter circuit 31, the high-frequency clock signal in the received modulation signal is filtered out. Specifically, the frequency of the second signal E can be the clock frequency after frequency multiplication. .

[0058] Considering that the high-pass filter circuit 31 is intended to filter out the DC component and low-frequency component in the signal waveform of the electrical signal D and to obtain the frequency-multiplied clock signal, it should ensure that the frequency-multiplied clock signal passes through completely.

[0059] Optionally, the high-pass filter cutoff frequency of the high-pass filter circuit is greater than or equal to 1 / 5 of the frequency of the second signal, that is, the cutoff frequency of the high-pass filter circuit is greater than or equal to... .

[0060] This setting ensures that both DC and low-frequency components are filtered out, while also ensuring that the clock signal waveform after frequency multiplication is fully transmitted.

[0061] Continue to refer to Figure 8 As shown, the latching and down-frequency circuit 32 is used to down-frequency the second signal E to generate the second clock signal SDL_2 and generate an interrupt signal INT to be output to the control circuit based on the comparison of the duration of adjacent high levels of the second clock signal SDL_2.

[0062] Specifically, by setting up the latch and down-frequency circuit 32, frequency locking can be achieved by outputting an interrupt signal INT to the control circuit 40 based on the comparison result of the adjacent high-level durations of the second clock signal.

[0063] Optionally, the control circuit 40, based on the serial bus protocol, generates a third clock signal SDL_3 as a start-of-communication signal according to the flags indicating the start and end of communication in the serial bus. Alternatively, after receiving the aforementioned start-of-communication flag and generating the third clock signal SDL_3, the control circuit 40 uses the same clock signal as the first clock signal SDL_1 from the clock signal line SDL as its generated third clock signal SDL_3. It should be noted that when the conversion structure transmits the third clock signal SDL_3 as both the start-of-communication signal and the end-of-communication signal, the control circuit 40 shuts down the frequency multiplier circuit 50 and the signal modulation circuit 10, allowing the waveform of the third clock signal SDL_3 to be directly converted into an optical signal output through electro-optical conversion without any change.

[0064] Therefore, when the electronic device receives the optical signal, the second signal E obtained after high-pass filtering has three waveforms: the optical communication start signal, the frequency-doubled clock signal, and the third clock signal SDL_3, which is the optical communication end signal.

[0065] For example, refer to Figure 9 and 10 As shown, Figure 9 The waveforms of the third clock signal SDL_3, which serves as the start signal and the end signal for optical communication, are shown. Using the latch and down-conversion circuit 32, an interrupt signal INT is output to the control circuit 40 based on a comparison of the durations of adjacent high levels of the second clock signal SDL_2. If the comparison result is that the duration of the preceding high level is shorter than the duration of the following high level (i.e., the difference is negative), it indicates the start of optical communication. Therefore, the durations of adjacent high levels of the subsequently generated second clock signal SDL_2 should be equal. Locking the second clock signal SDL_2 and generating the interrupt signal INT enables normal communication. Conversely, if the comparison result is that the duration of the preceding high level is longer than the duration of the following high level (i.e., the difference is positive), it indicates the end of optical communication.

[0066] In addition, for the second clock signal SDL_2, which represents the clock signal of the normal communication process, when the comparison result is that the duration of adjacent high levels is equal, the latch and down-frequency circuit 32 down-frequencys the second clock signal SDL_2, thereby obtaining a clock signal with a frequency of f0.

[0067] Continue to refer to Figure 8 As shown, the envelope detection circuit 33 is used to filter out high-frequency components in the second signal E and form a second data signal SDA_2 having the envelope waveform of the second signal E. For example, refer to... Figure 11As shown, the envelope detection circuit 33 may include an RC filter circuit composed of a third resistor R3 and a first capacitor C1. By setting the resistance value of the third resistor R3 and the capacitance value of the first capacitor C1, the envelope detection capability is achieved, thereby reflecting the envelope outline of the second signal E input to the envelope detection circuit 33 in the generated second data signal SDA_2, so that the second data signal SDA_2 has the envelope waveform of the second signal E.

[0068] At this point, the control circuit 40 receives the second clock signal SDA_2, the interrupt signal INT, and the second data signal SDA_2 from the signal separation circuit 30, and provides the first data signal SDA_1 and the first clock signal SDL_1 to the data signal line SDA according to the received signals. Figure 2 , Figure 3 and Figure 8 As shown, the data signal line SDA and the clock signal line SDL can output signals to the control circuit 40 and receive signals from the control circuit 40. Therefore, the signals in this path are represented as the first data signal SDA_1 and the first clock signal SDL_1.

[0069] In an optional embodiment, considering that bidirectional communication is achieved via a single optical fiber, the electronic devices at both ends of the communication cannot directly determine the change in their receiving and sending identities, the control circuit 40 also includes a memory comprising an address register, a first data register, and a second data register. The first data register is also referred to as the "transmit data register," and the second data register is also referred to as the "receive data register."

[0070] The address memory is used to store the first or second set of data from the data signal line SDA, and the first data memory is used to store subsequent data from the data signal line SDA. Alternatively, the address memory is used to store the first or second set of data from the second data signal SDA_2, and the second data memory is used to store subsequent data from the second data signal SDA_2. The above-described structure and function of the memory will be described in detail in the specific communication implementation below.

[0071] It should be noted that although the above description, in conjunction with the accompanying drawings, illustrates the implementation of the hardware circuit architecture of at least the signal modulation circuit 10, the high-pass filter circuit 31, the latch and down-conversion circuit 32, and the envelope detection circuit 33 in the conversion structure of the electronic device, this disclosure is not limited thereto. At least a portion of these circuits can be integrated with the control circuit 40 in a system-on-a-chip (SoC), FPGA, microcontroller (MCU), etc., as plug-ins, firmware, software, etc.

[0072] In practical implementation, regardless of whether the circuits are included in the hardware or software communication architecture, they can all be encapsulated on the port circuit board of the HDMI fiber optic cable. The HDMI source outputs I2C signals, which first go to the HDMI connector and then to conversion structure 1. After being converted into optical pulse signals, these signals are transmitted through a single optical fiber to the conversion structure of the receiving electronic device. The resulting electrical signals (e.g., SDA_2, SDL_2, and INT) enter the control circuit, where the data is reorganized before being output to the HDMI connector and then to the controlled devices such as the HDMI display device. Because this circuit has bidirectional communication capabilities, the I2C signal returned by the HDMI display device is transmitted back to the HDMI source through the reverse process described above, thus completing the I2C communication via a single optical fiber.

[0073] The electronic device described in the above embodiments can be implemented as a communication system, which includes at least one master device and at least one slave device, as shown below. Figure 12 The diagram illustrates the relationship between a master device and a slave device. The output of the master device's conversion structure 1_1 and the output of the slave device's conversion structure 1_2, which communicates with it, are connected and communicate via an optical fiber. Each of the master and slave devices is an electronic device as described above.

[0074] By providing a communication system composed of the aforementioned electronic devices, a conversion structure is used to realize the two-line transmission of serial bus signals on a single optical fiber, solving the integrity problem after long-distance wire communication, realizing communication between the main control device and controlled devices such as large screens, and ensuring normal display.

[0075] The following describes a communication method provided by another aspect of this disclosure, in conjunction with the electronic devices and the device relationships between slave and master devices constituted by the electronic devices in the above embodiments. Those skilled in the art should understand that the specific implementation process of the communication method described below will utilize the cooperation of the various functional circuits of the electronic devices described in the above embodiments. For ease of distinction, the following description will be combined with... Figure 12 The master device's conversion structure is represented as "1_1", and the slave device's conversion structure is represented as "1_2". For ease of description, the following process uses the I2C serial bus as an example.

[0076] Reference Figure 13 As shown, in step S1, the serial communication start flag from the serial bus is obtained.

[0077] The master device is the initiator and controller of the entire communication process. During communication, the master device issues a serial communication start flag. Specifically, the I2C protocol stipulates that when the clock signal line is high, the data signal line changes from high to indicate the start of communication. When the control circuit 40 of the conversion module 1_1 receives a high level on the clock signal line SDL and a low level on the clock signal line SDA, it obtains the serial communication start flag of the serial bus.

[0078] In step S2, in response to the serial communication start flag, the conversion structure generates a third clock signal as the optical communication start flag signal and turns off the signal modulation circuit, converts the third clock signal into an optical signal and sends it to the slave device.

[0079] For example, when the control circuit 40 receives the serial communication start flag from the serial bus, it generates a third clock signal SDL_3 as the optical communication start flag signal based on the first clock signal SDL_1 of the clock signal line SDL being high and the first data signal SDA of the data signal line SDA changing from high to low. Specifically, after recognizing the serial communication start flag of the I2C serial bus, the control circuit 40 first turns off the frequency multiplier circuit 50 and the signal modulation circuit 10, receives the first clock signal SDL_1, calculates the frequency of the clock signal, denoted as f0, and outputs the signal as shown in the figure. Figure 9 The image shows the third clock signal SDL_3, which represents the start signal for optical communication. (See reference...) Figure 9 As shown, the third clock signal SDL_3, which indicates the start of optical communication, consists of three high-level square waves. The first high level lasts for 1 / f0, the low level lasts for 2 / f0, the second high level lasts for 3 / f0, the low level lasts for 4 / f0, and the third high level lasts for 5 / f0.

[0080] It should be understood that the waveform of the third clock signal SDL_3, which indicates the start of optical communication, is not limited to... Figure 9 As shown, in an optional embodiment, it can be any sequence of square wave signals with sequentially increasing high-level time lengths.

[0081] Specifically, because the control circuit 40 shuts down the frequency multiplier circuit 50 and the signal modulation circuit 10, the third clock signal SDL_3 passes directly through and is converted into an optical signal by the electro-optical conversion sub-circuit in the photoelectric and electro-optical conversion circuit 20 and sent to the slave device.

[0082] Correspondingly, the conversion structure 1_2 of the device receives the data from... Figure 9The signal shown is converted into an optical signal, which is then photoelectrically converted and high-pass filtered. The latch and frequency reduction circuit 33 determines that the duration of the first high level is longer than the duration of the second high level, i.e., the difference is positive, thus confirming that this is an optical communication start signal.

[0083] By setting an optical communication start flag, the problem of misalignment between clock and data signals after processing can be solved when a single optical fiber performs bidirectional data transmission. By using the control circuit to generate an optical communication start flag based on the I2C bus communication start protocol, the alignment signal of the dual signal lines can be converted into another judgment method, providing basic support for bidirectional data transmission of a single optical fiber.

[0084] In step S3, the first or second set of data from the data signal line is stored in the address register, the conversion structure turns on the signal modulation circuit and sends the generated optical signal to the slave device as the first data signal using the first or second set of data.

[0085] For example, the control circuit 40 of conversion structure 1_1 starts data reception after receiving the communication start flag from the I2C bus of the electronic device's master control terminal. The first set of data from the data signal line SDA, for example, the first 8 bits, is stored in the address register. Figure 14 An exemplary memory structure diagram of the control circuit 40 is shown. The first group of 8 bits of data includes a flag bit W / R. For example, if the flag bit W / R is "0", it means writing data to the slave device, and if it is "1", it means reading data from the slave device.

[0086] Additionally, the control circuit 40 activates the frequency multiplier circuit 50 and the signal modulation circuit 10. The frequency multiplier circuit 50 multiplies the third clock signal SDL_3 to generate a first signal A. The first signal A is then modulated using the third clock signal SDA_3 corresponding to the first set of data to generate a first modulated signal B. The first modulated signal B is then electro-optically converted using the electro-optical conversion sub-circuit of the photoelectric and electro-optical conversion circuit 20 to generate an optical signal C. After completing this process, the control circuit 40 sends control information to the photoelectric and electro-optical conversion circuit 20, closing the electro-optical conversion sub-circuit and opening the photoelectric conversion sub-circuit, awaiting a response from the slave device.

[0087] Correspondingly, upon receiving the optical signal from the conversion structure 1_2 of the device, the second data signal SDA_2, corresponding to the first set of data, is generated and sent to its control circuit 40 via its photoelectric and electro-optical conversion circuit 20 and signal separation circuit 30. The control circuit 40 receives the second data signal SDA_2 and writes it into its address register. After confirming receipt of the first set of 8-bit data, the control circuit 40 shuts down the photoelectric conversion sub-circuit and turns on the electro-optical conversion sub-circuit, sending an acknowledgment signal to the master device. This acknowledgment signal is sent in the form of a data signal, for example, a 1-bit data acknowledgment signal to the master device.

[0088] This completes one data transmission and acknowledgment cycle, and the master and slave devices can then proceed with the transmission of the next set of 8-bit data. However, it should be noted that which end of the master and slave devices is the transmitting end and which end is the receiving end depends on the level of the W / R flag bit written into their respective address registers in the first set mentioned above.

[0089] Optionally, if the slave device is a large screen under control, the master device usually sends the screen data corresponding to the display screen to the slave device first, and then the master device continues to send data to the slave device as the sending end.

[0090] In step S4, in response to the first level of the flag bit in the address register, the conversion structure stores the subsequent data of the data signal line into the first data register, and uses the signal read from the first data register as the first data signal to send the generated optical signal to the slave device.

[0091] For example, the first level can be a level indicating writing data to the slave device, such as "0". Thus, the master device's conversion structure stores subsequent data that is not in the first group of data into the first data register, and sequentially reads the data stored in the first data register as the first data signal. The master device then uses the first data signal SDA_1 to modulate the frequency-multiplied third clock signal SDL_3, i.e., the first signal A, to generate the first modulation signal B. After electro-optic conversion, the signal is converted into an optical signal and then transmitted to the slave device via light.

[0092] Correspondingly, the conversion structure 1_2 of the slave device processes the received optical signal through photoelectric conversion, high-pass filtering, envelope detection, latching, and frequency reduction to generate a second data signal SDA_2 corresponding to the data sent by the master device. Its control circuit 40 stores the received second data signal SDA_2 into a second data register, i.e., a receive data register, for transmission to the slave device's data signal line for large-screen display. Upon successful reception, the slave device sends a 1-bit acknowledgment signal to the master device.

[0093] It should be understood that the master device's conversion structure 1_1 sends a control message to the photoelectric and electro-optical conversion circuit 20 once for each set of data sent, in order to close the electro-optical conversion sub-circuit and open the photoelectric conversion sub-circuit, in order to wait for the response signal from the slave device. If no response signal is received from the slave device within one response cycle, it means that the data transmission was unsuccessful, and the master device will resend the data to be sent last time.

[0094] After step S4, refer to Figure 15 As shown, the reference communication method further includes: step S51, obtaining a serial communication end flag from the serial bus; step S52, in response to the serial communication end flag, the conversion structure shuts down the signal modulation circuit, converts multiple clock signals from the clock signal line into optical signals as optical communication end flag signals, and sends them to the slave device.

[0095] For example, when the control circuit 40 receives the serial communication end flag from the serial bus, it generates a third clock signal SDL_3 as the optical communication end flag signal based on the first clock signal SDL_1 on the clock signal line SDL being high and the first data signal SDA on the data signal line SDA changing from low to high. Specifically, after recognizing the serial communication end flag of the I2C serial bus, the control circuit 40 first turns off the frequency multiplier circuit 50 and the signal modulation circuit 10, receives the first clock signal SDL_1, and outputs... Figure 10 The third clock signal SDL_3, shown, represents the end-of-optical-communication marker. (Refer to...) Figure 10 As shown, the third clock signal SDL_3, which indicates the start of optical communication, is a square wave with three high levels. The first high level lasts for 5 / f0 and the low level lasts for 4 / f0. The second high level lasts for 3 / f0 and the low level lasts for 2 / f0. The third high level lasts for 1 / f0.

[0096] It should be understood that the waveform of the third clock signal SDL_3, which represents the end-of-optical-communication flag, is not limited to... Figure 10 As shown, in an optional embodiment, it can be any sequence of square wave signals with sequentially increasing high-level time lengths.

[0097] Specifically, because the control circuit 40 shuts down the frequency multiplier circuit 50 and the signal modulation circuit 10, the third clock signal SDL_3 passes directly through and is converted into an optical signal by the electro-optical conversion sub-circuit in the photoelectric and electro-optical conversion circuit 20 and sent to the slave device.

[0098] Correspondingly, the conversion structure 1_2 of the device receives the data from... Figure 10The signal shown is converted into an optical signal, which undergoes photoelectric conversion, high-pass filtering, and then, via latching and frequency reduction circuit 33, determines whether the duration of the previous high level is less than the duration of the next high level (i.e., the difference is positive), thus identifying it as an optical communication end-of-communication signal. After recognizing the optical communication end-of-communication signal, the control circuit 40 of the slave device's conversion structure 1_2 outputs a termination signal on the I2C bus, thus completing the optical communication write operation on the slave device.

[0099] It should be noted that although the above example shows that the optical communication start signal is a signal with a high level duration that increases sequentially and the optical communication end signal is a signal with a high level duration that decreases sequentially, this disclosure is not intended to be limited to this. As long as the optical communication start signal is a signal with a high level duration that decreases sequentially and the optical communication end signal is a signal with a high level duration that increases sequentially, it is sufficient as long as the start and end of the optical communication process of the switching structure can be indicated by the corresponding duration changes. This will not be elaborated further.

[0100] On the other hand, after the communication process reaches step S3, if the flag bit in the address register is at the second level, which is different from the first level mentioned above, it indicates the level at which the slave device receives data. Then, the conversion structure acquires the optical signal from the slave device and generates a second data signal, and stores the second data signal in the second data register.

[0101] In other words, if the flag in the address register indicates the level of data received from the device, for example, if the flag bit is "1", then the master device performs an optical communication data read operation.

[0102] When the master device performs a read data operation, there are two possible implementation methods.

[0103] In one possible implementation, only one device is associated with an I2C serial bus, meaning the master device does not need to distinguish the data source from which it needs to read data. In this case, during communication, the first set of 8 bits of data is sent to the slave device as described in the example above. After receiving a response from the slave device, the slave device stores the first set of data in its address register, sends a response message to the master device, and then writes the data to be sent to the master device into its first data register. The master device then generates a first modulated signal through its signal modulation circuit, and finally sends it to the master device as an optical signal after electro-optical conversion.

[0104] Upon receiving the optical signal, the master device generates a second data signal SDA_2, a second clock signal SDL_2, and an interrupt signal INT corresponding to the data to be received after high-pass filtering, envelope detection, latching, and frequency reduction. The received data is then stored in the second data register. The control circuit 40 transmits the second data signal SDA_2 as the first data signal SDA_1 to the data signal line SDA. After receiving the second data signal SDA_2, the control circuit 40 sends an acknowledgment signal to the slave device, and transmission continues. The slave device continues to receive data from other slave devices and then continues to send data to the master device.

[0105] Subsequently, in step S1, if the control circuit 40 of the master device receives a serial communication end flag from the serial bus, then in step S52, in response to the serial communication end flag, the conversion structure shuts down the signal modulation circuit, converts multiple clock signals from the clock signal line into optical signals as optical communication end flag signals, and sends them to the slave device.

[0106] In another possible implementation, multiple devices in the slave device are associated with an I2C serial bus, meaning that the master device needs to distinguish the specific data source when reading data.

[0107] In this embodiment, the difference from the communication process described above is that the master device needs to inform the slave device of the specific device address for communication.

[0108] The specific difference in this implementation is that, in step S3, the second set of data from the data signal line is stored in the address register, the conversion structure activates the signal modulation circuit, and the second set of data is used as the first data signal to send the generated optical signal to the slave device. The first set of data is then broadcast as the slave device's device address to all devices associated with an I2C serial bus within the slave device.

[0109] Specifically, the control circuit 40 of the slave device monitors the second data signal SDA_2 corresponding to the optical signal from the master device in real time. If the slave device determines that the first set of second data signals SDA_2 matches the device address of a certain device, such as the device address of sensor 1, it means that the master device is sending or receiving data corresponding to that device.

[0110] Subsequently, the master device's control circuit 40 stores the second set of data from the data signal line into the address register, the conversion structure activates the frequency multiplication circuit and the signal modulation circuit, and sends the generated optical signal to the slave device using the second set of data as the first data signal.

[0111] Correspondingly, when the conversion structure 1_2 of the device receives the optical signal, it performs photoelectric conversion, high-pass filtering, envelope detection, latching and frequency reduction to generate the second data signal SDA_2, the second clock signal SDA_2 and the interrupt signal INT corresponding to the second set of data. The control circuit 40 of the conversion structure 1_2 stores the second data signal SDA_2 into the second data register corresponding to the device address of the sensor 1.

[0112] On the other hand, if the master device needs to read data from one of the multiple devices of the slave device, such as sensor 1, then in step S3, the second set of data from the data signal line is stored in the address register, the conversion structure turns on the signal modulation circuit and sends the generated optical signal to the slave device using the second set of data as the first data signal. This process is the same as the data transmission process and will not be described in detail here.

[0113] Then, step S4 further includes: In response to the first level of the flag bit in the address register, the conversion structure stores the second set of data on the data signal line into the first data register, and uses the signal read from the first data register as the first data signal to send the generated optical signal to the slave device. In response to the acknowledgment signal from the slave device, the conversion structure shuts down the signal modulation circuit, converts multiple clock signals from the clock signal line into optical signals as optical communication indication signals, and sends them to the slave device. In response to an acknowledgment signal from the slave device, the conversion structure stores subsequent data from the data signal line into the first data register, and uses the signal read from the first data register as the first data signal to send the generated optical signal to the slave device.

[0114] In other words, after the master device finishes sending the second 8-bit data as the register address and receives the acknowledgment signal from the slave device, the master device will receive an I2C restart signal, i.e., a start signal. The control circuit 40 further generates an optical communication indication signal based on this signal. This optical communication indication signal can be the same signal as the optical communication start flag signal. This signal is sent directly to the slave device as the third clock signal SDL_3 without frequency multiplication and signal modulation, so as to inform the slave device to start the data transmission.

[0115] By configuring the above settings, including an address memory, a first data memory, and a second data memory in the control circuit 40, and by generating optical communication start and end signals based on communication flags from the serial bus, bidirectional communication using a single optical fiber is possible. In other words, by combining the above communication method with the conversion structure, only one conversion structure and one optical fiber are needed to achieve bidirectional serial communication, thus solving the problem of low-frequency signal transmission failure at a lower cost.

[0116] Based on the same concept, this disclosure also provides a communication method applied to a slave device, wherein the slave device is the electronic device described in the above embodiments, and the method includes: The conversion structure generates a second clock signal representing the start of optical communication based on the acquired optical signal from the master device; The conversion structure generates a second clock signal and a first set of second data signals based on the optical signal acquired from the master device, and stores the first set or the second set of second data signals into the address register; In response to the flag bit in the address register being at the first level, the conversion structure stores the subsequent second data signal into the second data register.

[0117] By utilizing the above method and the cooperation between the slave and master devices through the conversion structure, bidirectional serial communication is achieved with only one conversion structure and one optical fiber, thus solving the problem of low-frequency signals not being able to be transmitted normally at a lower cost.

[0118] Optionally, the communication method applied to the slave device further includes: in response to the flag bit in the address register being at a second level, the conversion structure stores the data signal in the second data register into the first data register, and sends the generated optical signal to the master device as the first data signal using the signal read from the first data register.

[0119] This step enables the use of a conversion structure to send data from the device to the master device.

[0120] Optionally, the first set of data from the data signal line is the device address of the slave device. The conversion structure sends the first set of data as a first data signal to the slave device to generate an optical signal, and stores the second set of data from the data signal line into an address register. In response to a flag bit in the address register being at a second level, the conversion structure stores the data signal from the second data register into a first data register. Sending the generated optical signal to the master device using the signal read from the first data register as the first data signal further includes: In response to the optical signal from the master device, a first set of second data signals is generated and matched with the device address of one of the multiple devices in the slave device to obtain the device address; The conversion structure then generates a second clock signal representing the start of optical communication based on the acquired optical signal from the master device; In response to the flag bit in the address register of the device corresponding to the device address being at the second level, the conversion structure stores the data signal in the second data register of the corresponding device into the first data register, and uses the signal read from the first data register as the first data signal to send the optical signal generated by the master device.

[0121] This configuration allows a slave device to read and write data from multiple devices connected to the same serial bus by monitoring the data corresponding to the first set of optical signals from the master device. It determines which specific device among the multiple devices the second data signal generated based on that set of optical signals corresponds to, and thus determines the address register of the device to which the second data signal generated from the subsequent received second set of optical signals will be written. This configuration enables a master device to read and write data from multiple devices associated with a single serial bus using only one optical fiber.

[0122] It should be noted that the specific implementation of the data sending and reading process of the above-mentioned slave device has been described in detail in the process of describing the communication method of the master device, and will not be repeated here.

[0123] Another embodiment of this application provides a computer-readable storage medium having a computer program stored thereon, which is implemented when executed by a processor: Obtain the serial communication start flag from the serial bus; In response to the serial communication start flag, the conversion structure generates a third clock signal as an optical communication start flag signal and shuts down the signal modulation circuit. The third clock signal is converted into an optical signal and sent to the slave device. The first or second set of data from the data signal line is stored in the address register. The conversion structure enables the signal modulation circuit and sends the generated optical signal to the slave device using the first or second set of data as the first data signal. In response to the flag bit in the address register being at a first level, the conversion structure stores the subsequent data of the data signal line into a first data register, and uses the signal read from the first data register as the first data signal to send the optical signal generated by the slave device.

[0124] Another embodiment of this application provides a computer-readable storage medium having a computer program stored thereon, which is implemented when executed by a processor: The conversion structure generates a second clock signal representing the start of optical communication based on the acquired optical signal from the master device; The conversion structure generates a second clock signal and a first set of second data signals based on the optical signal acquired from the master device, and stores the first set or the second set of second data signals into the address register; In response to the flag bit in the address register being at the first level, the conversion structure stores the subsequent second data signal into the second data register.

[0125] In practical applications, the computer-readable storage medium can be any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0126] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0127] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0128] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0129] like Figure 16 As shown, another embodiment of this application provides a structural schematic diagram of a computer device. Figure 16 The computer device 102 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0130] like Figure 16 As shown, the computer device 102 is presented in the form of a general-purpose computing device. The components of the computer device 102 may include, but are not limited to: one or more processors or processing units 106, system memory 208, and bus 108 connecting different system components (including system memory 208 and processing unit 106).

[0131] Bus 108 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. Examples of these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0132] Computer device 102 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by computer device 102, including volatile and non-volatile media, removable and non-removable media.

[0133] System memory 208 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 300 and / or cache memory 302. Computer device 102 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 304 may be used to read and write non-removable, non-volatile magnetic media (…). Figure 16 Not shown; usually referred to as a "hard drive"). Although Figure 16 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 108 via one or more data media interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of this application.

[0134] A program / utility 400 having a set (at least one) of program modules 402 may be stored, for example, in memory 208. Such program modules 402 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 402 typically perform the functions and / or methods described in the embodiments of this application.

[0135] Computer device 102 can also communicate with one or more external devices 104 (e.g., keyboard, pointing device, display 204, etc.), and with one or more devices that enable a user to interact with the computer device 102, and / or with any device that enables the computer device 102 to communicate with one or more other computing devices (e.g., network interface card, modem, etc.). This communication can be performed through input / output (I / O) interface 202. Furthermore, computer device 102 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 200. Figure 16 As shown, network adapter 200 communicates with other modules of computer device 102 via bus 108. It should be understood that, although... Figure 16 As not shown, other hardware and / or software modules may be used in conjunction with computer device 102, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0136] The processor unit 106 executes various functional applications and data processing by running programs stored in the system memory 208, such as implementing a communication method described in the above embodiments provided in this application.

[0137] In the description of this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0138] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. An electronic device, characterized in that, include: A serial bus and a conversion structure electrically connected to the serial bus, the serial bus including clock signal lines and data signal lines. The conversion structure includes: a signal modulation circuit, a photoelectric and electro-optic conversion circuit, a signal separation circuit, and a control circuit. The signal modulation circuit is used to modulate the received first signal with the first data signal from the data signal line to generate a first modulated signal, wherein the first signal includes clock information from the first clock signal from the clock signal line. The photoelectric and electro-optical conversion circuit is used to convert the first modulation signal into an optical signal for output by the electronic device based on the control information of the control circuit, and to convert the received optical signal into an electrical signal based on the control information of the control circuit. The signal separation circuit is used to separate the electrical signal into a second clock signal transmitted to the clock signal line and a second data signal transmitted to the data signal line.

2. The electronic device according to claim 1, characterized in that, The control circuit also includes a memory, which comprises an address register, a first data register, and a second data register. The address memory is used to store a first or second set of data from the data signal line, and the first data memory is used to store subsequent data from the data signal line, or The address memory is used to store the first or second set of data of the second data signal, and the second data memory is used to store subsequent data of the second data signal.

3. The electronic device according to claim 1, characterized in that, The signal separation circuit includes: a high-pass filter circuit, a latch and frequency reduction circuit, and an envelope detector circuit. The high-pass filter circuit is used to perform high-pass filtering on the electrical signal to generate a second signal, the second signal including clock information; The latch circuit is used to down-frequency the second signal to generate the second clock signal and to generate an interrupt signal output to the control circuit based on a comparison of the duration of adjacent high levels of the second clock signal. The envelope detection circuit is used to filter out high-frequency components in the second signal and form the second data signal having the envelope waveform of the second signal.

4. The electronic device according to claim 1, characterized in that, The conversion structure also includes a frequency multiplier circuit. The control circuit generates a third clock signal based on the first clock signal, and the frequency multiplier circuit is used to multiply the third clock signal to generate the first signal.

5. The electronic device according to claim 3, characterized in that, The high-pass filter cutoff frequency of the high-pass filter circuit is greater than or equal to 1 / 5 of the frequency of the second signal.

6. The electronic device according to claim 1, characterized in that, The photoelectric and electro-optical conversion circuit includes: an electro-optical conversion sub-circuit and a photoelectric conversion sub-circuit. The electro-optic conversion sub-circuit includes a light-emitting device. When the electro-optic conversion sub-circuit is turned on based on the control signal from the control circuit, the light-emitting device emits light under the control of the received first modulation signal to generate an optical signal. The photoelectric conversion sub-circuit includes photoelectric devices. When the photoelectric conversion sub-circuit is activated based on the control signal from the control circuit, it generates the electrical signal based on the optical signal received by the photoelectric devices. When the first modulation signal is high, the light-emitting device emits light, and when the photoelectric device receives the light signal, the electrical signal is high; or, when the first modulation signal is low, the light-emitting device emits light, and when the photoelectric device receives the light signal, the electrical signal is low.

7. A communication system, characterized in that, It includes at least two electronic devices, wherein the electronic devices are those according to any one of claims 1-6. The at least two electronic devices include at least one master device and at least one slave device, wherein the output terminal of the conversion structure of the master device and the output terminal of the conversion structure of the slave device that communicates with it are connected and communicate via an optical fiber.

8. A communication method applied to a master device, said master device being an electronic device according to any one of claims 1-6, characterized in that, include: Obtain the serial communication start flag from the serial bus; In response to the serial communication start flag, the conversion structure generates a third clock signal as an optical communication start flag signal and shuts down the signal modulation circuit, converts the third clock signal into an optical signal and sends it to the slave device; The first or second set of data from the data signal line is stored in the address register. The conversion structure enables the signal modulation circuit and sends the generated optical signal to the slave device using the first or second set of data as the first data signal. In response to the flag bit in the address register being at a first level, the conversion structure stores the subsequent data of the data signal line into a first data register, and uses the signal read from the first data register as the first data signal to send the optical signal generated by the slave device.

9. The communication method according to claim 8, characterized in that, In response to the flag bit in the address register being at the second level, the conversion structure acquires the optical signal from the slave device and generates the second data signal, and stores the second data signal in the second data register.

10. The communication method according to claim 8, characterized in that, After the conversion structure stores subsequent data of the data signal line into a first data register in response to a first level flag bit in the address register, and sends the generated optical signal to the slave device as the first data signal using the signal read from the first data register, the method further includes: Obtain the serial communication end flag from the serial bus; In response to the serial communication end flag, the conversion structure generates a third clock signal representing the optical communication end flag signal and shuts down the signal modulation circuit, converts the third clock signal representing the optical communication end flag signal into an optical signal and sends it to the slave device.

11. The communication method according to claim 9, characterized in that, After the conversion structure acquires the optical signal from the slave device and generates the second data signal in response to the flag bit in the address register being at the second level, and stores the second data signal in the second data register, the method further includes: The conversion structure calculates the time length difference between two adjacent high levels in the second clock signal; In response to a positive time difference between the preceding and following high levels, the conversion structure sends a serial communication end flag to the data signal line.

12. The communication method according to claim 10, characterized in that, The optical communication start signal is a sequence of square wave signals with successively increasing high-level time lengths, and the optical communication end signal is a sequence of square wave signals with successively decreasing high-level time lengths.

13. The communication method according to claim 8, characterized in that, The first set of data from the data signal line is the device address of the slave device. The conversion structure sends the first set of data as a first data signal to the slave device to generate its optical signal, and stores the second set of data from the data signal line into the address register. The step of responding to a first level in the address register, wherein the conversion structure stores subsequent data of the data signal line into a first data register, and sends the generated optical signal to the slave device as the first data signal using the signal read from the first data register, further includes: In response to the flag bit in the address register being at a first level, the conversion structure stores the second set of data from the data signal line into the first data register, and uses the signal read from the first data register as the first data signal to send the optical signal generated by the slave device. In response to an acknowledgment signal from the slave device, the conversion structure shuts down the signal modulation circuit, converts multiple clock signals from the clock signal line as optical communication indication signals into optical signals, and sends them to the slave device. In response to an acknowledgment signal from the slave device, the conversion structure stores subsequent data of the data signal line into a first data register, and uses the signal read from the first data register as the first data signal to send the optical signal generated by the slave device.

14. A communication method applied to a slave device, said slave device being an electronic device according to any one of claims 1-6, characterized in that, include: The conversion structure generates a second clock signal representing the start of optical communication based on the acquired optical signal from the master device; The conversion structure generates a second clock signal and a first set of second data signals based on the optical signal acquired from the master device, and stores the first set or the second set of second data signals into the address register; In response to the flag bit in the address register being at the first level, the conversion structure stores the subsequent second data signal into the second data register.

15. The communication method according to claim 14, characterized in that, Also includes: In response to the flag bit in the address register being at the second level, the conversion structure stores the data signal in the second data register into the first data register, and uses the signal read from the first data register as the first data signal to send the generated optical signal to the master device.

16. The communication method according to claim 15, characterized in that, The first set of data from the data signal line is the device address of the slave device. The conversion structure sends the first set of data as a first data signal to the slave device to generate its optical signal, and stores the second set of data from the data signal line into the address register. The step of responding to the flag bit in the address register being at a second level, and the conversion structure storing the data signal in the second data register into the first data register, and using the signal read from the first data register as the first data signal to send the generated optical signal to the master device, further includes: In response to the optical signal from the master device, a first set of second data signals is generated and matched with the device address of one of the multiple devices in the slave device to obtain the device address; The conversion structure then generates a second clock signal representing the start of optical communication based on the acquired optical signal from the master device; In response to the flag bit in the address register of the device corresponding to the device address being at the second level, the conversion structure stores the data signal in the second data register of the corresponding device into the first data register, and uses the signal read from the first data register as the first data signal to send the optical signal generated by the master device.

17. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the communication method as described in any one of claims 8-13, or When the processor executes the program, it implements the communication method as described in any one of claims 14-16.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the processor executes the program, it implements the communication method as described in any one of claims 8-13, or When the processor executes the program, it implements the communication method as described in any one of claims 14-16.

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